Changeset 69 for trunk/fw_g473rct/Core/Src/main.c
- Timestamp:
- Apr 10, 2026, 10:32:16 AM (4 weeks ago)
- File:
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- 1 edited
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trunk/fw_g473rct/Core/Src/main.c (modified) (7 diffs)
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trunk/fw_g473rct/Core/Src/main.c
r65 r69 57 57 #include "ltc_current.h" 58 58 #include "usbd_cdc_if.h" 59 #include "ring.h" 59 60 60 61 /* USER CODE END Includes */ … … 100 101 static volatile uint32_t newADC5Data = 0; 101 102 103 ring_buffer_t usb_in_buff __attribute__((section(".CCM_RAM1_CRC"))); 104 ring_buffer_t usb_out_buff __attribute__((section(".CCM_RAM1_CRC"))); 105 102 106 /* USER CODE END PV */ 103 107 … … 105 109 void SystemClock_Config(void); 106 110 /* USER CODE BEGIN PFP */ 111 107 112 bool SetFlashReadProtection(bool state); 108 113 uint8_t printprotectionstate(void); … … 113 118 void CheckRAMHWParity(void); 114 119 void DoNothing(void){}; 120 void processUSB(ring_buffer_t* const ring_in_buff, ring_buffer_t* const ring_out_buff); 121 115 122 /* USER CODE END PFP */ 116 123 … … 463 470 } 464 471 472 if (rb_available(&usb_in_buff) > 8) // 8 minimum packet size in Modbus RTU RHR/WHR 473 { // Theres something in our USB buffer. We need to process it 474 processUSB(&usb_in_buff, &usb_out_buff); 475 } 465 476 466 477 } … … 526 537 527 538 /* USER CODE BEGIN 4 */ 539 540 void processUSB(ring_buffer_t* const ring_in_buff, ring_buffer_t* const ring_out_buff) 541 { 542 const uint32_t MAX_DELAY_ms = 1000U; 543 static uint32_t lastTime; 544 static int stage; 545 uint8_t adr, data; 546 547 switch (stage) 548 { 549 case 0: // Initial stage. We are waiting for our slave address 550 while (rb_peek(ring_in_buff, &adr) && adr != sys_data.s.parameter.slave_address) // Removing elements from ring buffer, till we get a byte with our salve address 551 rb_pop(ring_in_buff, &data); 552 553 uint8_t fc; 554 bool r = rb_peek_at(ring_in_buff, 1U, &fc); // Testing function code, if present 555 if (r == false) 556 { 557 lastTime = HAL_GetTick(); // Saving time of arrival of last byte 558 ++stage; 559 return; 560 } 561 562 switch (fc) 563 { 564 case FC_READ_HOLDING_REGISTERS: { 565 uint8_t start_addr_hi; 566 r = rb_peek_at(ring_in_buff, 3U, &start_addr_hi); 567 if (r == false) 568 { 569 lastTime = HAL_GetTick(); // Saving time of arrival of last byte 570 ++stage; 571 return; 572 } 573 574 uint8_t start_addr_lo; 575 r = rb_peek_at(ring_in_buff, 2U, &start_addr_lo); 576 if (r == false) 577 { 578 lastTime = HAL_GetTick(); // Saving time of arrival of last byte 579 ++stage; 580 return; 581 } 582 583 uint16_t start_addr = (((uint16_t)start_addr_hi) << 8U) | ((uint16_t)start_addr_lo); // Modbus register start address 584 585 uint8_t reg_num_hi; 586 r = rb_peek_at(ring_in_buff, 5U, ®_num_hi); 587 if (r == false) 588 { 589 lastTime = HAL_GetTick(); // Saving time of arrival of last byte 590 ++stage; 591 return; 592 } 593 594 uint8_t reg_num_lo; 595 r = rb_peek_at(ring_in_buff, 4U, ®_num_lo); 596 if (r == false) 597 { 598 lastTime = HAL_GetTick(); // Saving time of arrival of last byte 599 ++stage; 600 return; 601 } 602 603 uint16_t reg_num = (((uint16_t)reg_num_hi) << 8U) | ((uint16_t)reg_num_lo); // Modbus Quantity of Registers 604 605 606 } 607 break; 608 609 case FC_WRITE_SINGLE_REGISTER: 610 break; 611 612 case FC_WRITE_MULTIPLE_REGISTER: 613 break; 614 615 case FC_READ_COILS: 616 default: 617 break; 618 } 619 break; 620 621 case 1: 622 break; 623 624 case 2: 625 break; 626 } 627 } 628 629 //------------------------------------------------------------------------------ 630 528 631 void LoadBackupRegister(void) 529 632 { … … 754 857 ; 755 858 } 859 else 860 { 861 #ifdef DEBUG 862 printf("RAM Parity check was activated\n"); 863 #endif 864 } 756 865 } 757 866
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