Changeset 23 for trunk/firmware/App
- Timestamp:
- Oct 5, 2026, 8:38:52 AM (4 weeks ago)
- Location:
- trunk/firmware/App
- Files:
-
- 3 edited
- 1 moved
-
CubeMX/Appli/Core/Src/main.c (modified) (3 diffs)
-
CubeMX/blto2_App.ioc (modified) (4 diffs)
-
SES/Output/Debug/Exe/blto_App.bin (modified) ( previous)
-
SES/blto2_App.emProject (moved) (moved from trunk/firmware/App/SES/blto_App.emProject ) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/firmware/App/CubeMX/Appli/Core/Src/main.c
r21 r23 48 48 49 49 /* Private function prototypes -----------------------------------------------*/ 50 static void MPU_Config(void); 50 51 /* USER CODE BEGIN PFP */ 51 52 … … 66 67 /* USER CODE BEGIN 1 */ 67 68 69 /* System clock already configured, simply SystemCoreClock init */ 70 SystemCoreClockUpdate(); 71 68 72 /* USER CODE END 1 */ 73 74 /* MPU Configuration--------------------------------------------------------*/ 75 MPU_Config(); 76 77 /* Enable the CPU Cache */ 78 79 /* Enable I-Cache---------------------------------------------------------*/ 80 SCB_EnableICache(); 81 82 /* Enable D-Cache---------------------------------------------------------*/ 83 SCB_EnableDCache(); 69 84 70 85 /* MCU Configuration--------------------------------------------------------*/ … … 100 115 /* USER CODE END 4 */ 101 116 117 /* MPU Configuration */ 118 119 void MPU_Config(void) 120 { 121 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 122 MPU_Attributes_InitTypeDef MPU_AttributesInit = {0}; 123 uint32_t primask_bit = __get_PRIMASK(); 124 __disable_irq(); 125 126 /* Disables the MPU */ 127 HAL_MPU_Disable(); 128 129 /** Initializes and configures the Region 0 and the memory to be protected 130 */ 131 MPU_InitStruct.Enable = MPU_REGION_ENABLE; 132 MPU_InitStruct.Number = MPU_REGION_NUMBER0; 133 MPU_InitStruct.BaseAddress = 0x38000000; 134 MPU_InitStruct.LimitAddress = 0x38000040; 135 MPU_InitStruct.AttributesIndex = MPU_ATTRIBUTES_NUMBER0; 136 MPU_InitStruct.AccessPermission = MPU_REGION_ALL_RW; 137 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; 138 MPU_InitStruct.DisablePrivExec = MPU_PRIV_INSTRUCTION_ACCESS_ENABLE; 139 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 140 141 HAL_MPU_ConfigRegion(&MPU_InitStruct); 142 143 /** Initializes and configures the Attribute 0 and the memory to be protected 144 */ 145 MPU_AttributesInit.Number = MPU_ATTRIBUTES_NUMBER0; 146 MPU_AttributesInit.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE); 147 148 HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit); 149 /* Enables the MPU */ 150 HAL_MPU_Enable(MPU_HFNMI_PRIVDEF); 151 152 /* Exit critical section to lock the system and avoid any issue around MPU mechanism */ 153 __set_PRIMASK(primask_bit); 154 155 } 156 102 157 /** 103 158 * @brief This function is executed in case of error occurrence. -
trunk/firmware/App/CubeMX/blto2_App.ioc
r21 r23 7 7 CORTEX_M55_FSBL.CPU_ICache=Enabled 8 8 CORTEX_M55_FSBL.IPParameters=CPU_ICache,CPU_DCache 9 CORTEX_M55_S.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ALL_RW 10 CORTEX_M55_S.Attributes0=MPU_ATTRIBUTES_NUMBER0 11 CORTEX_M55_S.AttributesIndex-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ATTRIBUTES_NUMBER0 12 CORTEX_M55_S.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0x38000000 13 CORTEX_M55_S.CPU_DCache=Enabled 14 CORTEX_M55_S.CPU_ICache=Enabled 15 CORTEX_M55_S.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE 16 CORTEX_M55_S.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,AttributesIndex-Cortex_Memory_Protection_Unit_Region0_Settings,Attributes0,BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings,LimitAddress-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings 17 CORTEX_M55_S.LimitAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0x38000040 18 CORTEX_M55_S.MPU_Control=MPU_HFNMI_PRIVDEF 9 19 ExtMemLoader.IPs=EXTMEM_LOADER,EXTMEM_MANAGER,RCC\:I,GPIO 10 FSBL.IPs=CORTEX_M55_FSBL,GPDMA1\:I,HDP,HPDMA1\:I,LINKEDLIST,RCC,GPIO\:I,NVIC\:I 20 FSBL.IPs=CORTEX_M55_FSBL,GPDMA1\:I,HDP,HPDMA1\:I,LINKEDLIST,RCC,GPIO\:I,NVIC\:I,MEMORYMAP 11 21 File.Version=6 12 22 GPIO.groupedBy= 13 23 KeepUserPlacement=false 24 MMTAppReg1.MEMORYMAP.AppRegionName=RAM 25 MMTAppReg1.MEMORYMAP.ContextName=FSBL 26 MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M55 27 MMTAppReg1.MEMORYMAP.DefaultDataRegion=true 28 MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name 29 MMTAppReg1.MEMORYMAP.Name=RAM 30 MMTAppReg1.MEMORYMAP.Size=262144 31 MMTAppReg1.MEMORYMAP.StartAddress=0x341C0000 32 MMTAppReg2.MEMORYMAP.AppRegionName=FLASH 33 MMTAppReg2.MEMORYMAP.ContextName=FSBL 34 MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M55 35 MMTAppReg2.MEMORYMAP.DefaultCodeRegion=true 36 MMTAppReg2.MEMORYMAP.DefaultDataRegion=false 37 MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,DefaultCodeRegion,ISRRegion,RootBootRegion 38 MMTAppReg2.MEMORYMAP.ISRRegion=true 39 MMTAppReg2.MEMORYMAP.Name=FLASH 40 MMTAppReg2.MEMORYMAP.RootBootRegion=true 41 MMTAppReg2.MEMORYMAP.Size=261120 42 MMTAppReg2.MEMORYMAP.StartAddress=0x34180400 43 MMTAppReg3.MEMORYMAP.AppRegionName=RAM 44 MMTAppReg3.MEMORYMAP.ContextName=Appli 45 MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M55 46 MMTAppReg3.MEMORYMAP.DefaultDataRegion=true 47 MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name 48 MMTAppReg3.MEMORYMAP.Name=RAM 49 MMTAppReg3.MEMORYMAP.Size=1572864 50 MMTAppReg3.MEMORYMAP.StartAddress=0x34080000 51 MMTAppReg4.MEMORYMAP.AppRegionName=FLASH 52 MMTAppReg4.MEMORYMAP.ContextName=Appli 53 MMTAppReg4.MEMORYMAP.CoreName=ARM Cortex-M55 54 MMTAppReg4.MEMORYMAP.DefaultCodeRegion=true 55 MMTAppReg4.MEMORYMAP.DefaultDataRegion=false 56 MMTAppReg4.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,DefaultCodeRegion,ISRRegion,RootBootRegion 57 MMTAppReg4.MEMORYMAP.ISRRegion=true 58 MMTAppReg4.MEMORYMAP.Name=FLASH 59 MMTAppReg4.MEMORYMAP.RootBootRegion=true 60 MMTAppReg4.MEMORYMAP.Size=523264 61 MMTAppReg4.MEMORYMAP.StartAddress=0x34000400 62 MMTAppRegionsCount=4 63 MMTConfigApplied=false 64 MMTSectionSuffix= 14 65 Mcu.CPN=STM32N657X0H3Q 15 66 Mcu.Context0=FSBL … … 21 72 Mcu.IP0=CORTEX_M55_FSBL 22 73 Mcu.IP1=CORTEX_M55_S 23 Mcu.IP2=NVIC1 24 Mcu.IP3=NVIC 25 Mcu.IP4=RCC 26 Mcu.IP5=RIF 27 Mcu.IPNb=6 74 Mcu.IP2=MEMORYMAP 75 Mcu.IP3=NVIC1 76 Mcu.IP4=NVIC 77 Mcu.IP5=RCC 78 Mcu.IP6=RIF 79 Mcu.IPNb=7 28 80 Mcu.Name=STM32N657X0HxQ 29 81 Mcu.Package=VFBGA264 30 82 Mcu.Pin0=VP_RIF_VS_RIF1 31 Mcu.PinsNb=1 83 Mcu.Pin1=VP_MEMORYMAP_VS_MEMORYMAP 84 Mcu.PinsNb=2 32 85 Mcu.ThirdPartyNb=0 33 86 Mcu.UserConstants= … … 108 161 ProjectManager.UAScriptBeforePath= 109 162 ProjectManager.UnderRoot=false 110 ProjectManager.functionlistsort=1-SystemClock_Config-RCC- false-HAL-false-FSBL,1-SystemIsolation_Config-RIF-false-HAL-true-Appli,0-MX_CORTEX_M55_FSBL_Init-CORTEX_M55_FSBL-false-HAL-true-FSBL,0-MX_CORTEX_M55_S_Init-CORTEX_M55_S-false-HAL-true-Appli163 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-true-HAL-false-FSBL,2-MX_GPIO_Init-GPIO-false-HAL-true-FSBL,1-MX_GPIO_Init-GPIO-false-HAL-true-Appli,2-SystemIsolation_Config-RIF-false-HAL-true-Appli,0-MX_CORTEX_M55_FSBL_Init-CORTEX_M55_FSBL-false-HAL-true-FSBL,0-MX_CORTEX_M55_S_Init-CORTEX_M55_S-false-HAL-true-Appli,1-MX_GPIO_Init-GPIO-false-HAL-true-ExtMemLoader 111 164 RCC.ADC12Freq_Value=200000000 112 165 RCC.ADFFreq_Value=200000000 … … 774 827 RIF.VENC_CID_RIMU=0 775 828 RIF.default_config=false 829 VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg 830 VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP 776 831 VP_RIF_VS_RIF1.Mode=RISUP 777 832 VP_RIF_VS_RIF1.Signal=RIF_VS_RIF1 -
trunk/firmware/App/SES/blto2_App.emProject
r22 r23 1 1 <!DOCTYPE CrossStudio_Project_File> 2 <solution Name="blto _App" target="8" version="2">2 <solution Name="blto2_App" target="8" version="2"> 3 3 <configuration 4 4 Name="Debug" … … 15 15 gcc_optimization_level="Level 2 balanced" 16 16 link_dedupe_code="Yes" /> 17 <project Name="blto _App">17 <project Name="blto2_App"> 18 18 <configuration 19 19 LIBRARY_IO_TYPE="RTT"
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