Index: /trunk/firmware/App/CubeMX/.mxproject =================================================================== --- /trunk/firmware/App/CubeMX/.mxproject (revision 21) +++ /trunk/firmware/App/CubeMX/.mxproject (revision 21) @@ -0,0 +1,84 @@ +[FSBL:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h; + +[FSBL:PreviousUsedMakefileFiles] +SourceFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Appli:PreviousLibFiles] +LibFiles=Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h; + +[Appli:PreviousUsedMakefileFiles] +SourceFiles=Appli\Core\Src\main.c;Appli\Core\Src\gpio.c;Appli\Core\Src\stm32n6xx_it.c;Appli\Core\Src\stm32n6xx_hal_msp.c;Appli\Core\Src\secure_nsc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include;Appli\Core\Inc;Secure_nsclib;Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[ExtMemLoader:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h; + +[ExtMemLoader:PreviousUsedMakefileFiles] +SourceFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousLibFiles] +LibFiles=Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h;Drivers\CMSIS\Include\m-profile\armv7m_cachel1.h;Drivers\CMSIS\Include\m-profile\armv7m_mpu.h;Drivers\CMSIS\Include\m-profile\armv81m_pac.h;Drivers\CMSIS\Include\m-profile\armv8m_mpu.h;Drivers\CMSIS\Include\m-profile\armv8m_pmu.h;Drivers\CMSIS\Include\m-profile\cmsis_armclang_m.h;Drivers\CMSIS\Include\m-profile\cmsis_clang_m.h;Drivers\CMSIS\Include\m-profile\cmsis_gcc_m.h;Drivers\CMSIS\Include\m-profile\cmsis_iccarm_m.h;Drivers\CMSIS\Include\m-profile\cmsis_tiarmclang_m.h;Drivers\CMSIS\Include\r-profile\cmsis_armclang_r.h;Drivers\CMSIS\Include\r-profile\cmsis_clang_r.h;Drivers\CMSIS\Include\r-profile\cmsis_gcc_r.h;Drivers\CMSIS\Include\r-profile\cmsis_iccarm_r.h; + +[PreviousUsedMakefileFiles] +SourceFiles=Appli\Core\Src\main.c;Appli\Core\Src\gpio.c;Appli\Core\Src\stm32n6xx_it.c;Appli\Core\Src\stm32n6xx_hal_msp.c;Appli\Core\Src\secure_nsc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Src\system_stm32n6xx_s.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Src\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;FSBL\Core\Src\;Appli\Core\Src\system_stm32n6xx_s.c;ExtMemLoader\Core\Src\;;; +HeaderPath=Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include;Drivers\CMSIS\Include\m-profile;Drivers\CMSIS\Include\r-profile;Appli\Core\Inc;Secure_nsclib; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[FSBL:PreviousGenFiles] +SourceFiles=; + +[Appli:PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=..\Appli\Core\Inc\gpio.h +HeaderFiles#1=..\Appli\Core\Inc\stm32n6xx_it.h +HeaderFiles#2=..\Appli\Core\Inc\stm32n6xx_hal_conf.h +HeaderFiles#3=..\Appli\Core\Inc\main.h +HeaderFiles#4=..\Appli\Core\Inc\partition_stm32n657xx.h +HeaderFiles#5=..\Secure_nsclib\secure_nsc.h +HeaderFolderListSize=2 +HeaderPath#0=..\Appli\Core\Inc +HeaderPath#1=..\Secure_nsclib +HeaderFiles=; +SourceFileListSize=5 +SourceFiles#0=..\Appli\Core\Src\gpio.c +SourceFiles#1=..\Appli\Core\Src\stm32n6xx_it.c +SourceFiles#2=..\Appli\Core\Src\stm32n6xx_hal_msp.c +SourceFiles#3=..\Appli\Core\Src\main.c +SourceFiles#4=..\Appli\Core\Src\secure_nsc.c +SourceFolderListSize=1 +SourcePath#0=..\Appli\Core\Src +SourceFiles=; + +[ExtMemLoader:PreviousGenFiles] +SourceFiles=; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=..\Appli\Core\Inc\gpio.h +HeaderFiles#1=..\Appli\Core\Inc\stm32n6xx_it.h +HeaderFiles#2=..\Appli\Core\Inc\stm32n6xx_hal_conf.h +HeaderFiles#3=..\Appli\Core\Inc\main.h +HeaderFiles#4=..\Appli\Core\Inc\partition_stm32n657xx.h +HeaderFiles#5=..\Secure_nsclib\secure_nsc.h +HeaderFolderListSize=2 +HeaderPath#0=..\Appli\Core\Inc +HeaderPath#1=..\Secure_nsclib +HeaderFiles=; +SourceFileListSize=5 +SourceFiles#0=..\Appli\Core\Src\gpio.c +SourceFiles#1=..\Appli\Core\Src\stm32n6xx_it.c +SourceFiles#2=..\Appli\Core\Src\stm32n6xx_hal_msp.c +SourceFiles#3=..\Appli\Core\Src\main.c +SourceFiles#4=..\Appli\Core\Src\secure_nsc.c +SourceFolderListSize=1 +SourcePath#0=..\Appli\Core\Src +SourceFiles=; + Index: /trunk/firmware/App/CubeMX/Appli/Core/Inc/gpio.h =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Inc/gpio.h (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Inc/gpio.h (revision 21) @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + Index: /trunk/firmware/App/CubeMX/Appli/Core/Inc/main.h =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Inc/main.h (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Inc/main.h (revision 21) @@ -0,0 +1,87 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined ( __ICCARM__ ) +# define CMSE_NS_CALL __cmse_nonsecure_call +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_CALL __attribute((cmse_nonsecure_call)) +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* Function pointer declaration in non-secure*/ +#if defined ( __ICCARM__ ) +typedef void (CMSE_NS_CALL *funcptr)(void); +#else +typedef void CMSE_NS_CALL (*funcptr)(void); +#endif + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS; + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Inc/partition_stm32n657xx.h =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Inc/partition_stm32n657xx.h (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Inc/partition_stm32n657xx.h (revision 21) @@ -0,0 +1,786 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file partition_stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* +* Copyright (c) 2009-2016 ARM Limited. All rights reserved. +* Portions Copyright (c) 2023 STMicroelectronics, all rights reserved +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ +/* USER CODE END Header */ + +#ifndef PARTITION_STM32N657XX_H +#define PARTITION_STM32N657XX_H +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ +/* USER CODE BEGIN 0 */ +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 +/* USER CODE END 0 */ +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ +/* USER CODE BEGIN 1 */ +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ +/* USER CODE END 1 */ +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 +/* +// Interrupts 0..31 +// PVD_PVM_IRQn <0=> Secure state +// Reserved <0=> Secure state +// DTS_IRQn <0=> Secure state +// RCC_IRQn <0=> Secure state +// LOCKUP_IRQn <0=> Secure state +// CACHE_ECC_IRQn <0=> Secure state +// TCM_ECC_IRQn <0=> Secure state +// BKP_ECC_IRQn <0=> Secure state +// FPU_IRQn <0=> Secure state +// Reserved <0=> Secure state +// RTC_S_IRQn <0=> Secure state +// TAMP_IRQn <0=> Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state +// IAC_IRQn <0=> Secure state +// RCC_S_IRQn <0=> Secure state +// Reserved <0=> Secure state +// RTC_IRQn <0=> Secure state +// Reserved <0=> Secure state +// IWDG_IRQn <0=> Secure state +// WWDG_IRQn <0=> Secure state +// EXTI0_IRQn <0=> Secure state +// EXTI1_IRQn <0=> Secure state +// EXTI2_IRQn <0=> Secure state +// EXTI3_IRQn <0=> Secure state +// EXTI4_IRQn <0=> Secure state +// EXTI5_IRQn <0=> Secure state +// EXTI6_IRQn <0=> Secure state +// EXTI7_IRQn <0=> Secure state +// EXTI8_IRQn <0=> Secure state +// EXTI9_IRQn <0=> Secure state +// EXTI10_IRQn <0=> Secure state +// EXTI11_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS0_VAL 0x00000000 +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +/ Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state +// EXTI13_IRQn <0=> Secure state +// EXTI14_IRQn <0=> Secure state +// EXTI15_IRQn <0=> Secure state +// SAES_IRQn <0=> Secure state +// CRYP_IRQn <0=> Secure state +// PKA_IRQn <0=> Secure state +// HASH_IRQn <0=> Secure state +// RNG_IRQn <0=> Secure state +// Reserved <0=> Secure state +// MCE1_IRQn <0=> Secure state +// MCE2_IRQn <0=> Secure state +// MCE3_IRQn <0=> Secure state +// MCE4_IRQn <0=> Secure state +// ADC1_2_IRQn <0=> Secure state +// CSI_IRQn <0=> Secure state +// DCMIPP_IRQn <0=> Secure state +// Reserved <0=> Secure state +// Reserved <0=> Secure state +// Reserved <0=> Secure state +// PAHB_ERR_IRQn <0=> Secure state +// NPU0_IRQn <0=> Secure state +// NPU1_IRQn <0=> Secure state +// NPU2_IRQn <0=> Secure state +// NPU3_IRQn <0=> Secure state +// CACHEAXI_IRQn <0=> Secure state +// LTDC_LO_IRQn <0=> Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state +// DMA2D_IRQn <0=> Secure state +// JPEG_IRQn <0=> Secure state +// VENC_IRQn <0=> Secure state +// GFXMMU_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state +// GPU2D_IRQn <0=> Secure state +// GPU2D_ER_IRQn <0=> Secure state +// ICACHE_IRQn <0=> Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state +// I2C1_EV_IRQn <0=> Secure state +// I2C1_ER_IRQn <0=> Secure state +// I2C2_EV_IRQn <0=> Secure state +// I2C2_ER_IRQn <0=> Secure state +// I2C3_EV_IRQn <0=> Secure state +// I2C3_ER_IRQn <0=> Secure state +// I2C4_EV_IRQn <0=> Secure state +// I2C4_ER_IRQn <0=> Secure state +// I3C1_EV_IRQn <0=> Secure state +// I3C1_ER_IRQn <0=> Secure state +// I3C2_EV_IRQn <0=> Secure state +// I3C2_ER_IRQn <0=> Secure state +// TIM1_BRK_IRQn <0=> Secure state +// TIM1_UP_IRQn <0=> Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state +// TIM1_CC_IRQn <0=> Secure state +// TIM2_IRQn <0=> Secure state +// TIM3_IRQn <0=> Secure state +// TIM4_IRQn <0=> Secure state +// TIM5_IRQn <0=> Secure state +// TIM6_IRQn <0=> Secure state +// TIM7_IRQn <0=> Secure state +// TIM8_BRK_IRQn <0=> Secure state +// TIM8_UP_IRQn <0=> Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state +// TIM8_CC_IRQn <0=> Secure state +// TIM9_IRQn <0=> Secure state +// TIM10_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state +// TIM12_IRQn <0=> Secure state +// TIM13_IRQn <0=> Secure state +// TIM14_IRQn <0=> Secure state +// TIM15_IRQn <0=> Secure state +// TIM16_IRQn <0=> Secure state +// TIM17_IRQn <0=> Secure state +// TIM18_IRQn <0=> Secure state +// LPTIM1_IRQn <0=> Secure state +// LPTIM2_IRQn <0=> Secure state +// LPTIM3_IRQn <0=> Secure state +// LPTIM4_IRQn <0=> Secure state +// LPTIM5_IRQn <0=> Secure state +// ADF1_FLT0_IRQn <0=> Secure state +// MDF1_FLT0_IRQn <0=> Secure state +// MDF1_FLT1_IRQn <0=> Secure state +// MDF1_FLT2_IRQn <0=> Secure state +// MDF1_FLT3_IRQn <0=> Secure state +// MDF1_FLT4_IRQn <0=> Secure state +// MDF1_FLT5_IRQn <0=> Secure state +// SAI1_A_IRQn <0=> Secure state +// SAI1_B_IRQn <0=> Secure state +// SAI2_A_IRQn <0=> Secure state +// SAI2_B_IRQn <0=> Secure state +// SPDIFRX1_IRQn <0=> Secure state +// SPI1_IRQn <0=> Secure state +// SPI2_IRQn <0=> Secure state +// SPI3_IRQn <0=> Secure state +// SPI4_IRQn <0=> Secure state +// SPI5_IRQn <0=> Secure state +// SPI6_IRQn <0=> Secure state +// USART1_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state +// USART3_IRQn <0=> Secure state +// UART4_IRQn <0=> Secure state +// UART5_IRQn <0=> Secure state +// USART6_IRQn <0=> Secure state +// UART7_IRQn <0=> Secure state +// UART8_IRQn <0=> Secure state +// UART9_IRQn <0=> Secure state +// USART10_IRQn <0=> Secure state +// LPUART1_IRQn <0=> Secure state +// XSPI1_IRQn <0=> Secure state +// XSPI2_IRQn <0=> Secure state +// XSPI3_IRQn <0=> Secure state +// FMC_IRQn <0=> Secure state +// SDMMC1_IRQn <0=> Secure state +// SDMMC2_IRQn <0=> Secure state +// UCPD1_IRQn <0=> Secure state +// USB1_OTG_HS_IRQn <0=> Secure state +// USB2_OTG_HS_IRQn <0=> Secure state +// ETH1_IRQn <0=> Secure state +// FDCAN1_IT0_IRQn <0=> Secure state +// FDCAN1_IT1_IRQn <0=> Secure state +// FDCAN2_IT0_IRQn <0=> Secure state +// FDCAN2_IT1_IRQn <0=> Secure state +// FDCAN3_IT0_IRQn <0=> Secure state +// FDCAN3_IT1_IRQn <0=> Secure state +// FDCAN_CU_IRQn <0=> Secure state +// MDIOS_IRQn <0=> Secure state +// DCMI_PSSI_IRQn <0=> Secure state +// WAKEUP_PIN_IRQn <0=> Secure state +// CTI_INT0_IRQn <0=> Secure state +// CTI_INT1_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 +/* +// Interrupts 192..223 +// USART2_IRQn <0=> Secure state +// USART3_IRQn <0=> Secure state +// UART4_IRQn <0=> Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* USER CODE BEGIN 2 */ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} +/* USER CODE END 2 */ +#endif /* PARTITION_STM32N657XX_H */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Inc/stm32n6xx_hal_conf.h =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Inc/stm32n6xx_hal_conf.h (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Inc/stm32n6xx_hal_conf.h (revision 21) @@ -0,0 +1,513 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CONF_H +#define STM32N6xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DCMIPP_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_ICACHE_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +/*#define HAL_RIF_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */ +/* The real value may vary depending on the variations in voltage and temperature.*/ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32n6xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ######################### */ + +#define USE_SDIO_TRANSCEIVER 0U +#define SDIO_MAX_IO_NUMBER 7U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32n6xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_RIF_MODULE_ENABLED +#include "stm32n6xx_hal_rif.h" +#endif /* HAL_RIF_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32n6xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CACHEAXI_MODULE_ENABLED +#include "stm32n6xx_hal_cacheaxi.h" +#endif /* HAL_CACHEAXI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32n6xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32n6xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32n6xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32n6xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32n6xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32n6xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32n6xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32n6xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32n6xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32n6xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32n6xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32n6xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32n6xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32n6xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32n6xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32n6xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32n6xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32n6xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32n6xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32n6xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32n6xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32n6xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32n6xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32n6xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32n6xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32n6xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32n6xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32n6xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED +#include "stm32n6xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32n6xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32n6xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32n6xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32n6xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32n6xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32n6xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32n6xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32n6xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32n6xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32n6xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32n6xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32n6xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32n6xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32n6xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32n6xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32n6xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32n6xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32n6xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32n6xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32n6xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CONF_H */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Inc/stm32n6xx_it.h =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Inc/stm32n6xx_it.h (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Inc/stm32n6xx_it.h (revision 21) @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32N6xx_IT_H +#define __STM32N6xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SecureFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32N6xx_IT_H */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Src/gpio.c =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Src/gpio.c (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Src/gpio.c (revision 21) @@ -0,0 +1,195 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOQ_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pins : PQ6 PQ3 PQ4 PQ5 + PQ2 PQ1 PQ0 PQ7 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOQ, &GPIO_InitStruct); + + /*Configure GPIO pins : PC10 PC1 PC4 PC11 + PC6 PC5 PC9 PC12 + PC7 PC0 PC8 PC2 + PC3 PC13 */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_11 + |GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_9|GPIO_PIN_12 + |GPIO_PIN_7|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_2 + |GPIO_PIN_3|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PE13 PE15 PE8 PE9 + PE14 PE12 PE7 PE10 + PE5 PE4 PE6 PE11 + PE3 PE2 PE0 PE1 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_14|GPIO_PIN_12|GPIO_PIN_7|GPIO_PIN_10 + |GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_11 + |GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pins : PD10 PD1 PD15 PD4 + PD2 PD12 PD14 PD13 + PD6 PD0 PD5 PD7 + PD3 PD8 PD11 PD9 */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_4 + |GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_14|GPIO_PIN_13 + |GPIO_PIN_6|GPIO_PIN_0|GPIO_PIN_5|GPIO_PIN_7 + |GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : PH3 PH6 PH8 PH7 + PH9 PH2 PH4 PH5 */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_7 + |GPIO_PIN_9|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : PB14 PB13 PB2 PB9 + PB8 PB15 PB0 PB7 + PB6 PB3 PB11 PB12 + PB1 PB4 PB10 PB5 */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_2|GPIO_PIN_9 + |GPIO_PIN_8|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_7 + |GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_10|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PP7 PP6 PP0 PP4 + PP1 PP15 PP5 PP12 + PP3 PP2 PP13 PP11 + PP8 PP14 PP9 PP10 */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_0|GPIO_PIN_4 + |GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_5|GPIO_PIN_12 + |GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_13|GPIO_PIN_11 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOP, &GPIO_InitStruct); + + /*Configure GPIO pins : PO5 PO1 PO2 PO3 + PO0 PO4 */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_0|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOO, &GPIO_InitStruct); + + /*Configure GPIO pins : PG7 PG6 PG5 PG4 + PG14 PG3 PG15 PG1 + PG0 PG12 PG10 PG2 + PG9 PG8 PG13 PG11 */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 + |GPIO_PIN_14|GPIO_PIN_3|GPIO_PIN_15|GPIO_PIN_1 + |GPIO_PIN_0|GPIO_PIN_12|GPIO_PIN_10|GPIO_PIN_2 + |GPIO_PIN_9|GPIO_PIN_8|GPIO_PIN_13|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PF4 PF10 PF6 PF7 + PF3 PF5 PF15 PF14 + PF8 PF2 PF9 PF11 + PF1 PF13 PF0 PF12 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_8|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_11 + |GPIO_PIN_1|GPIO_PIN_13|GPIO_PIN_0|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pins : PN4 PN12 PN6 PN8 + PN0 PN3 PN5 PN1 + PN9 PN7 PN2 PN10 + PN11 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_12|GPIO_PIN_6|GPIO_PIN_8 + |GPIO_PIN_0|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + |GPIO_PIN_9|GPIO_PIN_7|GPIO_PIN_2|GPIO_PIN_10 + |GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPION, &GPIO_InitStruct); + + /*Configure GPIO pins : PA9 PA6 PA1 PA15 + PA10 PA5 PA7 PA3 + PA14 PA11 PA2 PA13 + PA12 PA8 PA0 PA4 */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_6|GPIO_PIN_1|GPIO_PIN_15 + |GPIO_PIN_10|GPIO_PIN_5|GPIO_PIN_7|GPIO_PIN_3 + |GPIO_PIN_14|GPIO_PIN_11|GPIO_PIN_2|GPIO_PIN_13 + |GPIO_PIN_12|GPIO_PIN_8|GPIO_PIN_0|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Src/main.c =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Src/main.c (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Src/main.c (revision 21) @@ -0,0 +1,132 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Src/secure_nsc.c =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Src/secure_nsc.c (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Src/secure_nsc.c (revision 21) @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file Secure/Src/secure_nsc.c + * @author MCD Application Team + * @brief This file contains the non-secure callable APIs (secure world) + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* USER CODE BEGIN Non_Secure_CallLib */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "secure_nsc.h" +/** @addtogroup STM32N6xx_HAL_Examples + + * @{ + */ + +/** @addtogroup Templates + * @{ + */ + +/* Global variables ----------------------------------------------------------*/ +void *pSecureFaultCallback = NULL; /* Pointer to secure fault callback in Non-secure */ +void *pSecureErrorCallback = NULL; /* Pointer to secure error callback in Non-secure */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Secure registration of non-secure callback. + * @param CallbackId callback identifier + * @param func pointer to non-secure function + * @retval None + */ + CMSE_NS_ENTRY void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func) + { + if(func != NULL) + { + switch(CallbackId) + { + case SECURE_FAULT_CB_ID: /* SecureFault Interrupt occurred */ + pSecureFaultCallback = func; + break; + case IAC_ERROR_CB_ID: /* Illegal Access Interrupt occurred */ + pSecureErrorCallback = func; + break; + default: + /* unknown */ + break; + } + } + } + +/** + * @} + */ + +/** + * @} + */ +/* USER CODE END Non_Secure_CallLib */ + Index: /trunk/firmware/App/CubeMX/Appli/Core/Src/stm32n6xx_hal_msp.c =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Src/stm32n6xx_hal_msp.c (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Src/stm32n6xx_hal_msp.c (revision 21) @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Src/stm32n6xx_it.c =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Src/stm32n6xx_it.c (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Src/stm32n6xx_it.c (revision 21) @@ -0,0 +1,218 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32n6xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Secure fault. + */ +void SecureFault_Handler(void) +{ + /* USER CODE BEGIN SecureFault_IRQn 0 */ + + /* USER CODE END SecureFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_SecureFault_IRQn 0 */ + /* USER CODE END W1_SecureFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32N6xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32n6xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ Index: /trunk/firmware/App/CubeMX/Appli/Core/Src/system_stm32n6xx_s.c =================================================================== --- /trunk/firmware/App/CubeMX/Appli/Core/Src/system_stm32n6xx_s.c (revision 21) +++ /trunk/firmware/App/CubeMX/Appli/Core/Src/system_stm32n6xx_s.c (revision 21) @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file system_stm32n6xx_s.c + * @author MCD Application Team + * @brief CMSIS Cortex-M55 Device Peripheral Access Layer System Source File + * to be used in secure application. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32n6xx.s" file. + * + * - SystemCoreClock variable: Contains the CPU core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update + * the variable SystemCoreClock and return + * its value to the non-secure calling + * application. It must be called whenever + * the core clock is changed during program + * execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32n6xx.s" file, to + * configure the system before to branch to main program. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32N6xx_System + * @{ + */ + +/** @addtogroup STM32N6xx_System_Private_Includes + * @{ + */ + +#include "stm32n6xx.h" +#include "partition_stm32n6xx.h" /* Trustzone-M core secure attributes */ +#include + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_TypesDefinitions + * @{ + */ + +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the High-Speed External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000UL /*!< Minimum value of the Low-power Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +#if !defined (EXTERNAL_I2S_CLOCK_VALUE) + #define EXTERNAL_I2S_CLOCK_VALUE 12288000UL /*!< Value of the External clock for I2S_CKIN in Hz */ +#endif /* EXTERNAL_I2S_CLOCK_VALUE */ + + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in memory, else the vector table is kept at the automatic + selected boot address */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS SRAM1_AXI_BASE_S /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Functions + * @{ + */ + +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)&__vector_table) +#elif defined(__ARMCC_VERSION) +extern void *__Vectors; +#define INTVECT_START ((uint32_t)&__Vectors) +#elif defined(__GNUC__) +extern void *g_pfnVectors; +#define INTVECT_START ((uint32_t)&g_pfnVectors) +#endif + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#else + SCB->VTOR = INTVECT_START; +#endif /* USER_VECT_TAB_ADDRESS */ + + /* System configuration setup */ + RCC->APB4ENSR2 = RCC_APB4ENSR2_SYSCFGENS; + /* Delay after an RCC peripheral clock enabling */ + (void)RCC->APB4ENR2; + + /* Set default Vector Table location after system reset or return from Standby */ + SYSCFG->INITSVTORCR = SCB->VTOR; + /* Read back the value to make sure it is written before deactivating SYSCFG */ + (void) SYSCFG->INITSVTORCR; + /* Deactivate SYSCFG clock */ + RCC->APB4ENCR2 = RCC_APB4ENCR2_SYSCFGENC; + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + + SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif /* __FPU_PRESENT && __FPU_USED */ + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Depending on secure or non-secure compilation, the adequate RCC peripheral + * memory are is accessed thanks to RCC alias defined in stm32n6xxxx.h device file + * so either from RCC_S peripheral register mapped memory in secure or from + * RCC_NS peripheral register mapped memory in non-secure. + * + * @note Each time the CPU core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If CPUCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If CPUCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(**) + * + * - If CPUCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If CPUCLK source is IC1, SystemCoreClock will contain the HSI_VALUE(*) + * or MSI_VALUE(**) or HSE_VALUE(***) or EXTERNAL_I2S_CLOCK_VALUE (****) + * multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE default value is 64 MHz. + * With the HAL, HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file + * but the real value may vary depending on the variations in voltage and temperature. + * + * (**) MSI_VALUE default value is 4 MHz. + * With the HAL, MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file + * but the real value may vary depending on the variations in voltage and temperature. + * + * (***) HSE_VALUE default value is 30 MHz. + * With the HAL, HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file. + * User has to ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * (****) EXTERNAL_I2S_CLOCK_VALUE default value is 12.288 MHz. + * With the HAL, EXTERNAL_I2S_CLOCK_VALUE is a constant defined in stm32n6xx_hal_conf.h file. + * User has to ensure that EXTERNAL_I2S_CLOCK_VALUE is same as the real I2S_CKIN + * pin frequency. Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysclk = 0; + uint32_t pllm = 0; + uint32_t plln = 0; + uint32_t pllfracn = 0; + uint32_t pllp1 = 0; + uint32_t pllp2 = 0; + uint32_t pllcfgr, pllsource, pllbypass, ic_divider; + float_t pllvco; + + /* Get CPUCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_CPUSWS) + { + case 0: /* HSI used as system clock source (default after reset) */ + sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos); + break; + + case RCC_CFGR1_CPUSWS_0: /* MSI used as system clock source */ + if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) + { + sysclk = MSI_VALUE; + } + else + { + sysclk = 16000000UL; + } + break; + + case RCC_CFGR1_CPUSWS_1: /* HSE used as system clock source */ + sysclk = HSE_VALUE; + break; + + case (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0): /* IC1 used as system clock source */ + /* Get IC1 clock source parameters */ + switch (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL)) + { + case 0: /* PLL1 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL1CFGR1); + pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL; + pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; + plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL1CFGR3); + pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; + } + break; + case RCC_IC1CFGR_IC1SEL_0: /* PLL2 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL2CFGR1); + pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL; + pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos; + plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL2CFGR3); + pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos; + } + break; + + case RCC_IC1CFGR_IC1SEL_1: /* PLL3 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL3CFGR1); + pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL; + pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos; + plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL3CFGR3); + pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos; + } + break; + + default: /* RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0 */ /* PLL4 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL4CFGR1); + pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL; + pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; + plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL4CFGR3); + pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos; + } + break; + } + + /* Get oscillator frequency used as PLL clock source */ + switch (pllsource) + { + case 0: /* HSI selected as PLL clock source */ + sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos); + break; + case RCC_PLL1CFGR1_PLL1SEL_0: /* MSI selected as PLL clock source */ + if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) + { + sysclk = MSI_VALUE; + } + else + { + sysclk = 16000000UL; + } + break; + case RCC_PLL1CFGR1_PLL1SEL_1: /* HSE selected as PLL clock source */ + sysclk = HSE_VALUE; + break; + case (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0): /* I2S_CKIN selected as PLL clock source */ + sysclk = EXTERNAL_I2S_CLOCK_VALUE; + break; + default: + /* Nothing to do, should not occur */ + break; + } + + /* Check whether PLL is in bypass mode or not */ + if (pllbypass == 0U) + { + /* Compte PLL output frequency (Integer and fractional modes) */ + /* PLLVCO = (Freq * (DIVN + (FRACN / 0x1000000) / DIVM) / (DIVP1 * DIVP2)) */ + pllvco = ((float_t)sysclk * ((float_t)plln + ((float_t)pllfracn/(float_t)0x1000000UL))) / (float_t)pllm; + sysclk = (uint32_t)((float_t)(pllvco/(((float_t)pllp1) * ((float_t)pllp2)))); + } + /* Apply IC1 divider */ + ic_divider = (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL; + sysclk = sysclk / ic_divider; + break; + default: + /* Nothing to do, should not occur */ + break; + } + + /* Return system clock frequency (CPU frequency) */ + SystemCoreClock = sysclk; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the CPU core clock, it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + SystemCoreClockUpdate(); + + return SystemCoreClock; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: /trunk/firmware/App/CubeMX/blto2_App.ioc =================================================================== --- /trunk/firmware/App/CubeMX/blto2_App.ioc (revision 21) +++ /trunk/firmware/App/CubeMX/blto2_App.ioc (revision 21) @@ -0,0 +1,778 @@ +#MicroXplorer Configuration settings - do not modify +Appli.IPs=CORTEX_M55_S,GPDMA1,HPDMA1,LINKEDLIST,RCC,RIF,SAU,GPIO,NVIC1\:I +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M55_FSBL.CPU_DCache=Enabled +CORTEX_M55_FSBL.CPU_ICache=Enabled +CORTEX_M55_FSBL.IPParameters=CPU_ICache,CPU_DCache +ExtMemLoader.IPs=EXTMEM_LOADER,EXTMEM_MANAGER,RCC\:I,GPIO +FSBL.IPs=CORTEX_M55_FSBL,GPDMA1\:I,HDP,HPDMA1\:I,LINKEDLIST,RCC,GPIO\:I,NVIC\:I +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32N657X0H3Q +Mcu.Context0=FSBL +Mcu.Context1=Appli +Mcu.Context2=ExtMemLoader +Mcu.ContextNb=3 +Mcu.ContextProject=FullSecure +Mcu.Family=STM32N6 +Mcu.IP0=CORTEX_M55_FSBL +Mcu.IP1=CORTEX_M55_S +Mcu.IP2=NVIC1 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RIF +Mcu.IPNb=6 +Mcu.Name=STM32N657X0HxQ +Mcu.Package=VFBGA264 +Mcu.Pin0=VP_RIF_VS_RIF1 +Mcu.PinsNb=1 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32N657X0HxQ +MxCube.Version=6.18.1 +MxDb.Version=DB.6.0.181 +NVIC.BFHFNMINS=0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PRIS=0 +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.BFHFNMINS=0 +NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.ForceEnableDMAVector=true +NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PRIS=0 +NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PCC.Bar.Display=Horizontal Bar +PCC.Checker=false +PCC.Display=Plot\: All Steps +PCC.Line=STM32N6x7 +PCC.MCU=STM32N657X0HxQ +PCC.PartNumber=STM32N657X0HxQ +PCC.SequenceTime=1.0 ms +PCC.SequenceTime.Unit=ms +PCC.Series=STM32N6 +PCC.Temperature=25 +PCC.Vdd=1.8 +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32N657X0HxQ +ProjectManager.FirmwarePackage=STM32Cube FW_N6 V1.4.1 +ProjectManager.FreePins=true +ProjectManager.FreePinsContext=Appli +ProjectManager.HalAssertFull=true +ProjectManager.HeapSize=FSBL-0x200,Appli-0x200,ExtMemLoader-0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=blto2_App.ioc +ProjectManager.ProjectName=blto2_App +ProjectManager.ProjectStructure=FSBL\:FSBL\:false;Appli\:Appli\:true;ExtMemLoader\:ExtMemLoader\:false; +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=FSBL-0x800,Appli-0x800,ExtMemLoader-0x800 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-FSBL,1-SystemIsolation_Config-RIF-false-HAL-true-Appli,0-MX_CORTEX_M55_FSBL_Init-CORTEX_M55_FSBL-false-HAL-true-FSBL,0-MX_CORTEX_M55_S_Init-CORTEX_M55_S-false-HAL-true-Appli +RCC.ADC12Freq_Value=200000000 +RCC.ADFFreq_Value=200000000 +RCC.AHB1234Freq_Value=200000000 +RCC.AHBFreq_Value=75000000 +RCC.APB1Freq_Value=200000000 +RCC.APB2Freq_Value=200000000 +RCC.APB4Freq_Value=200000000 +RCC.APB5Freq_Value=200000000 +RCC.AXIClockFreq_Value=400000000 +RCC.CKPERFreq_Value=64000000 +RCC.CPUCLKSource=RCC_CPUCLKSOURCE_IC1 +RCC.CortexFreq_Value=75000000 +RCC.CpuClockFreq_Value=600000000 +RCC.DCMIPPFreq_Value=200000000 +RCC.ETH1Freq_Value=200000000 +RCC.FBDIV1=75 +RCC.FDCANFreq_Value=200000000 +RCC.FMCFreq_Value=200000000 +RCC.FOUTPOSTDIV1Freq_Value=1200000000 +RCC.FOUTPOSTDIV2Freq_Value=1600000000 +RCC.FOUTPOSTDIV3Freq_Value=1600000000 +RCC.FOUTPOSTDIV4Freq_Value=1600000000 +RCC.FREFDIV1=4 +RCC.FamilyName=M +RCC.HSE_VALUE=48000000 +RCC.HSI_VALUE=64000000 +RCC.I2C1Freq_Value=200000000 +RCC.I2C2Freq_Value=200000000 +RCC.I2C3Freq_Value=200000000 +RCC.I2C4Freq_Value=200000000 +RCC.I3C1Freq_Value=200000000 +RCC.I3C2Freq_Value=200000000 +RCC.IC10Freq_VALUE=1600000000 +RCC.IC11Freq_VALUE=300000000 +RCC.IC12Freq_VALUE=1600000000 +RCC.IC13Freq_VALUE=1600000000 +RCC.IC14Freq_VALUE=1600000000 +RCC.IC15Freq_VALUE=1600000000 +RCC.IC16Freq_VALUE=1600000000 +RCC.IC17Freq_VALUE=1600000000 +RCC.IC18Freq_VALUE=1600000000 +RCC.IC19Freq_VALUE=1600000000 +RCC.IC1Div=2 +RCC.IC1Freq_VALUE=600000000 +RCC.IC20Freq_VALUE=1600000000 +RCC.IC2Div=3 +RCC.IC2Freq_VALUE=400000000 +RCC.IC3Freq_VALUE=1200000000 +RCC.IC4Freq_VALUE=1200000000 +RCC.IC5Freq_VALUE=1200000000 +RCC.IC6Freq_VALUE=300000000 +RCC.IC7Freq_VALUE=1600000000 +RCC.IC8Freq_VALUE=1600000000 +RCC.IC9Freq_VALUE=1600000000 +RCC.IPParameters=ADC12Freq_Value,ADFFreq_Value,AHB1234Freq_Value,AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,CKPERFreq_Value,CPUCLKSource,CortexFreq_Value,CpuClockFreq_Value,DCMIPPFreq_Value,ETH1Freq_Value,FBDIV1,FDCANFreq_Value,FMCFreq_Value,FOUTPOSTDIV1Freq_Value,FOUTPOSTDIV2Freq_Value,FOUTPOSTDIV3Freq_Value,FOUTPOSTDIV4Freq_Value,FREFDIV1,FamilyName,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,I3C2Freq_Value,IC10Freq_VALUE,IC11Freq_VALUE,IC12Freq_VALUE,IC13Freq_VALUE,IC14Freq_VALUE,IC15Freq_VALUE,IC16Freq_VALUE,IC17Freq_VALUE,IC18Freq_VALUE,IC19Freq_VALUE,IC1Div,IC1Freq_VALUE,IC20Freq_VALUE,IC2Div,IC2Freq_VALUE,IC3Freq_VALUE,IC4Freq_VALUE,IC5Freq_VALUE,IC6Freq_VALUE,IC7Freq_VALUE,IC8Freq_VALUE,IC9Freq_VALUE,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPUART1Freq_Value,LSE_VALUE,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,MDFFreq_Value,MSI_VALUE,OTGHS1Freq_Value,OTGHS2Freq_Value,OTGPHY1Freq_Value,OTGPHY2Freq_Value,PSSIFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPDIFRX1Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSBCLKFreq_VALUE,SYSBCLKSource,SYSCCLKFreq_VALUE,SYSDCLKFreq_VALUE,TIMGFreq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,USART10Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCO4OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInput4Freq_Value,XSPI1Freq_Value,XSPI2Freq_Value,XSPI3Freq_Value +RCC.LPTIM1Freq_Value=200000000 +RCC.LPTIM2Freq_Value=200000000 +RCC.LPTIM3Freq_Value=200000000 +RCC.LPTIM4Freq_Value=200000000 +RCC.LPTIM5Freq_Value=200000000 +RCC.LPUART1Freq_Value=200000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.LTDCFreq_Value=200000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=64000000 +RCC.MDFFreq_Value=200000000 +RCC.MSI_VALUE=16000000 +RCC.OTGHS1Freq_Value=24000000 +RCC.OTGHS2Freq_Value=24000000 +RCC.OTGPHY1Freq_Value=24000000 +RCC.OTGPHY2Freq_Value=24000000 +RCC.PSSIFreq_Value=200000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=200000000 +RCC.SAI2Freq_Value=200000000 +RCC.SDMMC1Freq_Value=200000000 +RCC.SDMMC2Freq_Value=200000000 +RCC.SPDIFRX1Freq_Value=200000000 +RCC.SPI1Freq_Value=200000000 +RCC.SPI2Freq_Value=200000000 +RCC.SPI3Freq_Value=200000000 +RCC.SPI4Freq_Value=200000000 +RCC.SPI5Freq_Value=200000000 +RCC.SPI6Freq_Value=200000000 +RCC.SYSBCLKFreq_VALUE=400000000 +RCC.SYSBCLKSource=RCC_SYSCLKSOURCE_IC2_IC6_IC11 +RCC.SYSCCLKFreq_VALUE=300000000 +RCC.SYSDCLKFreq_VALUE=300000000 +RCC.TIMGFreq_Value=400000000 +RCC.UART4Freq_Value=200000000 +RCC.UART5Freq_Value=200000000 +RCC.UART7Freq_Value=200000000 +RCC.UART8Freq_Value=200000000 +RCC.UART9Freq_Value=200000000 +RCC.USART10Freq_Value=200000000 +RCC.USART1Freq_Value=200000000 +RCC.USART2Freq_Value=200000000 +RCC.USART3Freq_Value=200000000 +RCC.USART6Freq_Value=200000000 +RCC.VCO1OutputFreq_Value=1200000000 +RCC.VCO2OutputFreq_Value=1600000000 +RCC.VCO3OutputFreq_Value=1600000000 +RCC.VCO4OutputFreq_Value=1600000000 +RCC.VCOInput1Freq_Value=16000000 +RCC.VCOInput2Freq_Value=64000000 +RCC.VCOInput3Freq_Value=64000000 +RCC.VCOInput4Freq_Value=64000000 +RCC.XSPI1Freq_Value=200000000 +RCC.XSPI2Freq_Value=200000000 +RCC.XSPI3Freq_Value=200000000 +RIF.DCMIPP_CID_RIMU=0 +RIF.DMA2D_CID_RIMU=0 +RIF.ETH1_CID_RIMU=0 +RIF.ETR_CID_RIMU=0 +RIF.GPU_CID_RIMU=0 +RIF.IPParameters=ETR_CID_RIMU,SDMMC1_CID_RIMU,SDMMC2_CID_RIMU,OTG1_CID_RIMU,OTG2_CID_RIMU,ETH1_CID_RIMU,GPU_CID_RIMU,DMA2D_CID_RIMU,DCMIPP_CID_RIMU,VENC_CID_RIMU,LTDC_L1_CID_RIMU,LTDC_L2_CID_RIMU +RIF.LTDC_L1_CID_RIMU=0 +RIF.LTDC_L2_CID_RIMU=0 +RIF.OTG1_CID_RIMU=0 +RIF.OTG2_CID_RIMU=0 +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Secure=false +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Cid=- +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Secure=false +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Cid=- +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Secure=false +RIF.SDMMC1_CID_RIMU=0 +RIF.SDMMC2_CID_RIMU=0 +RIF.VENC_CID_RIMU=0 +RIF.default_config=false +VP_RIF_VS_RIF1.Mode=RISUP +VP_RIF_VS_RIF1.Signal=RIF_VS_RIF1 +board=custom