Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h (revision 16) @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h (revision 16) @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h (revision 16) @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h (revision 16) @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h (revision 16) @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h (revision 16) @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h (revision 16) @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_version.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_version.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/cmsis_version.h (revision 16) @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h (revision 16) @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h (revision 16) @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h (revision 16) @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm0.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm0.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm0.h (revision 16) @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h (revision 16) @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm1.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm1.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm1.h (revision 16) @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm23.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm23.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm23.h (revision 16) @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm3.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm3.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm3.h (revision 16) @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm33.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm33.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm33.h (revision 16) @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm35p.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm35p.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm35p.h (revision 16) @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm4.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm4.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm4.h (revision 16) @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm55.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm55.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm55.h (revision 16) @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm7.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm7.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm7.h (revision 16) @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm85.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm85.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_cm85.h (revision 16) @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_sc000.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_sc000.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_sc000.h (revision 16) @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_sc300.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_sc300.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_sc300.h (revision 16) @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_starmc1.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_starmc1.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/core_starmc1.h (revision 16) @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h (revision 16) @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h (revision 16) @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/pac_armv81.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/pac_armv81.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/pac_armv81.h (revision 16) @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h (revision 16) @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif Index: trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/tz_context.h =================================================================== --- trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/tz_context.h (revision 16) +++ trunk/firmware/FSBL/SES/CMSIS_5/CMSIS/Core/Include/tz_context.h (revision 16) @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H Index: trunk/firmware/FSBL/SES/Output/Debug/Exe/blto2_FSBL.htm =================================================================== --- trunk/firmware/FSBL/SES/Output/Debug/Exe/blto2_FSBL.htm (revision 16) +++ trunk/firmware/FSBL/SES/Output/Debug/Exe/blto2_FSBL.htm (revision 16) @@ -0,0 +1,29109 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ + +
+SEGGER ARM Linker 4.44.5 compiled Aug  7 2026 18:47:09
+Copyright (c) 2017-2026 SEGGER Microcontroller GmbH    www.segger.com
+
+ + +
+--add-region:ITCM_RAM=0x00010000@0x10000000
+--add-region:DTCM_RAM=0x00020000@0x30000000
+--add-region:FLEX_RAM=0x00064000@0x34000000
+--add-region:AXI_RAM1=0x0009c000@0x34064000
+--add-region:AXI_RAM2=0x0007fc00@0x34180400
+--add-region:AXI_RAM3=0x00070000@0x34200000
+--add-region:AXI_RAM4=0x00070000@0x34270000
+--add-region:AXI_RAM5=0x00070000@0x342e0000
+--add-region:AXI_RAM6=0x00070000@0x34350000
+--add-region:AXI_RAM7=0x00040000@0x343c0000
+--add-region:AXI_RAM8=0x00020000@0x34400000
+--add-region:AHB_RAM1=0x00004000@0x38000000
+--add-region:AHB_RAM2=0x00004000@0x38004000
+--add-region:BKP_RAM=0x00002000@0x3c000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Debug/Exe/blto2_FSBL.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=8.1-M.main
+--silent
+-TD:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf
+--defsym=__STACKSIZE__=16384
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=256
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_short_float_long_long
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Debug/Exe/blto2_FSBL.elf
+D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Debug/Obj/blto2_FSBL_lto.o
+Output/Debug/Obj/SEGGER_THUMB_Startup.o
+Output/Debug/Obj/stm32n657xx_Vectors.o
+Output/Debug/Obj/STM32N6xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/libc_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/prinops_rtt_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_disable_interrupts_locking_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/mbops_timeops_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf'

+ +
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32N6xx_RAM.icf
+Purpose : STM32N6xx linker script for application placement in RAM
+          (to be copied to RAM by bootloader or debugger)
+          for use with the SEGGER Linker.
+Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
+          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
+          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
+          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
+          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
+          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region RAM   = AXI_RAM2;
+
+//
+// Block definitions
+//
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { section .vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in RAMn
+//
+place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
+place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
+place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
+place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
+place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
+place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
+place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.*  };  // This region may be deactivated and not accessible
+place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
+place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
+place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
+
+//
+// RAM Placement
+//
+place at start of RAM                       { section .vectors };                                   // Vector table section
+place in RAM with minimum size order        { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x34180400

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x341804008441024stm32n657xx_Vectors.o
+

place at 0x34200000

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x341FC00016 3848[ Linker created ]
+

"<#14> at line 120, col 45": place in [0x34180400 to 0x341FFFFF] with maximum packing

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Symbol or [section] nameTypeAddressSizeAlignObject File
Error_HandlerCode0x3418074C44blto2_FSBL_lto.o
HAL_MspInitCode0x3418075084blto2_FSBL_lto.o
SysTick_HandlerCode0x3418075884blto2_FSBL_lto.o
SystemCoreClockUpdateCode0x341807608284blto2_FSBL_lto.o
HAL_InitCode0x34180A9C484blto2_FSBL_lto.o
HAL_GetTickCode0x34180ACC124blto2_FSBL_lto.o
__NVIC_SetPriorityGroupingCode0x34180AD8604blto2_FSBL_lto.o
HAL_NVIC_SetPriorityCode0x34180B141684blto2_FSBL_lto.o
__NVIC_GetPriorityGroupingCode0x34180BBC164blto2_FSBL_lto.o
NVIC_EncodePriorityCode0x34180BCC1004blto2_FSBL_lto.o
HAL_SYSTICK_ConfigCode0x34180C30164blto2_FSBL_lto.o
HAL_GPIO_InitCode0x34180C401 9284blto2_FSBL_lto.o
LL_RCC_HSI_SetDividerCode0x341813C8284blto2_FSBL_lto.o
LL_RCC_HSI_IsReadyCode0x341813E4164blto2_FSBL_lto.o
LL_RCC_GetCpuClkSourceCode0x341813F4164blto2_FSBL_lto.o
LL_RCC_GetSysClkSourceCode0x34181404164blto2_FSBL_lto.o
LL_RCC_PLL1_GetSourceCode0x34181414164blto2_FSBL_lto.o
LL_RCC_PLL2_GetSourceCode0x34181424164blto2_FSBL_lto.o
LL_RCC_PLL3_GetSourceCode0x34181434164blto2_FSBL_lto.o
LL_RCC_PLL4_GetSourceCode0x34181444164blto2_FSBL_lto.o
LL_RCC_MSI_SetFrequencyCode0x34181454284blto2_FSBL_lto.o
LL_RCC_MSI_IsReadyCode0x34181470164blto2_FSBL_lto.o
LL_RCC_LSI_IsReadyCode0x34181480164blto2_FSBL_lto.o
LL_RCC_LSE_IsReadyCode0x34181490164blto2_FSBL_lto.o
LL_RCC_PLL1_IsReadyCode0x341814A0164blto2_FSBL_lto.o
LL_RCC_IC1_GetSourceCode0x341814B0164blto2_FSBL_lto.o
LL_RCC_IC2_GetSourceCode0x341814C0164blto2_FSBL_lto.o
LL_RCC_IC6_GetSourceCode0x341814D0164blto2_FSBL_lto.o
LL_RCC_IC11_GetSourceCode0x341814E0164blto2_FSBL_lto.o
LL_RCC_PLL2_IsReadyCode0x341814F0164blto2_FSBL_lto.o
LL_RCC_PLL3_IsReadyCode0x34181500164blto2_FSBL_lto.o
LL_RCC_PLL4_IsReadyCode0x34181510164blto2_FSBL_lto.o
RCC_PLL_Source_IsReadyCode0x34181520844blto2_FSBL_lto.o
LL_RCC_HSE_IsReadyCode0x34181574164blto2_FSBL_lto.o
LL_RCC_HSI_GetDividerCode0x34181584164blto2_FSBL_lto.o
LL_RCC_PLL1_IsEnabledBypassCode0x34181594164blto2_FSBL_lto.o
LL_RCC_PLL2_IsEnabledBypassCode0x341815A4164blto2_FSBL_lto.o
LL_RCC_PLL3_IsEnabledBypassCode0x341815B4164blto2_FSBL_lto.o
LL_RCC_PLL4_IsEnabledBypassCode0x341815C4164blto2_FSBL_lto.o
HAL_RCC_GetClockConfigCode0x341815D42404blto2_FSBL_lto.o
LL_RCC_PLL4_IsReady.57Code0x341816C4164blto2_FSBL_lto.o
LL_RCC_PLL4P_IsEnabledCode0x341816D4164blto2_FSBL_lto.o
LL_RCC_PLL4_GetSource.58Code0x341816E4164blto2_FSBL_lto.o
RCCEx_GetPLLSourceFreqCode0x341816F41404blto2_FSBL_lto.o
LL_RCC_PLL4_GetMCode0x34181780164blto2_FSBL_lto.o
LL_RCC_PLL4_GetNCode0x34181790164blto2_FSBL_lto.o
LL_RCC_PLL4_GetFRACNCode0x341817A0164blto2_FSBL_lto.o
LL_RCC_PLL4_GetP1Code0x341817B0164blto2_FSBL_lto.o
LL_RCC_PLL4_GetP2Code0x341817C0164blto2_FSBL_lto.o
RCCEx_CalcPLLFreqCode0x341817D01364blto2_FSBL_lto.o
LL_RCC_PLL4_IsEnabledBypass.59Code0x34181858164blto2_FSBL_lto.o
LL_RCC_HSI_IsReady.60Code0x34181868164blto2_FSBL_lto.o
LL_RCC_HSI_GetDivider.61Code0x34181878164blto2_FSBL_lto.o
LL_RCC_MSI_IsReady.62Code0x34181888164blto2_FSBL_lto.o
LL_RCC_MSI_GetFrequencyCode0x34181898164blto2_FSBL_lto.o
LL_RCC_HSE_IsReady.63Code0x341818A8164blto2_FSBL_lto.o
LL_RCC_PLL3_IsReady.64Code0x341818B8164blto2_FSBL_lto.o
LL_RCC_PLL3P_IsEnabledCode0x341818C8164blto2_FSBL_lto.o
LL_RCC_PLL3_GetSource.65Code0x341818D8164blto2_FSBL_lto.o
LL_RCC_PLL3_GetMCode0x341818E8164blto2_FSBL_lto.o
LL_RCC_PLL3_GetNCode0x341818F8164blto2_FSBL_lto.o
LL_RCC_PLL3_GetFRACNCode0x34181908164blto2_FSBL_lto.o
LL_RCC_PLL3_GetP1Code0x34181918164blto2_FSBL_lto.o
LL_RCC_PLL3_GetP2Code0x34181928164blto2_FSBL_lto.o
LL_RCC_PLL3_IsEnabledBypass.66Code0x34181938164blto2_FSBL_lto.o
LL_RCC_PLL2_IsReady.67Code0x34181948164blto2_FSBL_lto.o
LL_RCC_PLL2P_IsEnabledCode0x34181958164blto2_FSBL_lto.o
LL_RCC_PLL2_GetSource.68Code0x34181968164blto2_FSBL_lto.o
LL_RCC_PLL2_GetMCode0x34181978164blto2_FSBL_lto.o
LL_RCC_PLL2_GetNCode0x34181988164blto2_FSBL_lto.o
LL_RCC_PLL2_GetFRACNCode0x34181998164blto2_FSBL_lto.o
LL_RCC_PLL2_GetP1Code0x341819A8164blto2_FSBL_lto.o
LL_RCC_PLL2_GetP2Code0x341819B8164blto2_FSBL_lto.o
LL_RCC_PLL2_IsEnabledBypass.69Code0x341819C8164blto2_FSBL_lto.o
LL_RCC_PLL1_IsReady.70Code0x341819D8164blto2_FSBL_lto.o
LL_RCC_PLL1P_IsEnabledCode0x341819E8164blto2_FSBL_lto.o
LL_RCC_PLL1_GetSource.71Code0x341819F8164blto2_FSBL_lto.o
LL_RCC_PLL1_GetMCode0x34181A08164blto2_FSBL_lto.o
LL_RCC_PLL1_GetNCode0x34181A18164blto2_FSBL_lto.o
LL_RCC_PLL1_GetFRACNCode0x34181A28164blto2_FSBL_lto.o
LL_RCC_PLL1_GetP1Code0x34181A38164blto2_FSBL_lto.o
LL_RCC_PLL1_GetP2Code0x34181A48164blto2_FSBL_lto.o
LL_RCC_PLL1_IsEnabledBypass.72Code0x34181A58164blto2_FSBL_lto.o
_startCode0x34181A68204SEGGER_THUMB_Startup.o
reset_handlerCode0x34181A7C444STM32N6xx_Startup.o
__aeabi_memclrCode0x34181AA81044strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
MX_GPIO_InitCode0x34181B104664blto2_FSBL_lto.o
PVD_PVM_IRQHandlerCode0x34181CE222stm32n657xx_Vectors.o
LL_AHB4_GRP1_EnableClockCode0x34181CE4344blto2_FSBL_lto.o
DTS_IRQHandlerCode0x34181D0622stm32n657xx_Vectors.o
mainCode0x34181D08664blto2_FSBL_lto.o
RCC_IRQHandlerCode0x34181D4A22stm32n657xx_Vectors.o
SystemClock_ConfigCode0x34181D4C2384blto2_FSBL_lto.o
LOCKUP_IRQHandlerCode0x34181E3A22stm32n657xx_Vectors.o
assert_failedCode0x34181E3C104blto2_FSBL_lto.o
CACHE_ECC_IRQHandlerCode0x34181E4622stm32n657xx_Vectors.o
NMI_HandlerCode0x34181E4824blto2_FSBL_lto.o
TCM_ECC_IRQHandlerCode0x34181E4A22stm32n657xx_Vectors.o
HardFault_HandlerCode0x34181E4C24blto2_FSBL_lto.o
BCK_ECC_IRQHandlerCode0x34181E4E22stm32n657xx_Vectors.o
MemManage_HandlerCode0x34181E5024blto2_FSBL_lto.o
FPU_IRQHandlerCode0x34181E5222stm32n657xx_Vectors.o
BusFault_HandlerCode0x34181E5424blto2_FSBL_lto.o
RTC_S_IRQHandlerCode0x34181E5622stm32n657xx_Vectors.o
UsageFault_HandlerCode0x34181E5824blto2_FSBL_lto.o
TAMP_IRQHandlerCode0x34181E5A22stm32n657xx_Vectors.o
SVC_HandlerCode0x34181E5C24blto2_FSBL_lto.o
RIFSC_TAMPER_IRQHandlerCode0x34181E5E22stm32n657xx_Vectors.o
DebugMon_HandlerCode0x34181E6024blto2_FSBL_lto.o
IAC_IRQHandlerCode0x34181E6222stm32n657xx_Vectors.o
PendSV_HandlerCode0x34181E6424blto2_FSBL_lto.o
RCC_S_IRQHandlerCode0x34181E6622stm32n657xx_Vectors.o
SystemInitCode0x34181E685104blto2_FSBL_lto.o
RTC_IRQHandlerCode0x3418206622stm32n657xx_Vectors.o
HAL_InitTickCode0x341820681264blto2_FSBL_lto.o
IWDG_IRQHandlerCode0x341820E622stm32n657xx_Vectors.o
HAL_IncTickCode0x341820E8264blto2_FSBL_lto.o
WWDG_IRQHandlerCode0x3418210222stm32n657xx_Vectors.o
HAL_DelayCode0x34182104584blto2_FSBL_lto.o
EXTI0_IRQHandlerCode0x3418213E22stm32n657xx_Vectors.o
HAL_NVIC_SetPriorityGroupingCode0x34182140624blto2_FSBL_lto.o
EXTI1_IRQHandlerCode0x3418217E22stm32n657xx_Vectors.o
__NVIC_SetPriorityCode0x34182180624blto2_FSBL_lto.o
EXTI2_IRQHandlerCode0x341821BE22stm32n657xx_Vectors.o
SysTick_ConfigCode0x341821C0784blto2_FSBL_lto.o
EXTI3_IRQHandlerCode0x3418220E22stm32n657xx_Vectors.o
HAL_GPIO_WritePinCode0x341822101024blto2_FSBL_lto.o
EXTI4_IRQHandlerCode0x3418227622stm32n657xx_Vectors.o
HAL_PWREx_ConfigSupplyCode0x341822781144blto2_FSBL_lto.o
EXTI5_IRQHandlerCode0x341822EA22stm32n657xx_Vectors.o
HAL_PWREx_ControlVoltageScalingCode0x341822EC1144blto2_FSBL_lto.o
EXTI6_IRQHandlerCode0x3418235E22stm32n657xx_Vectors.o
HAL_PWREx_EnableVddIO3Code0x34182360184blto2_FSBL_lto.o
EXTI7_IRQHandlerCode0x3418237222stm32n657xx_Vectors.o
LL_RCC_HSI_EnableCode0x34182374144blto2_FSBL_lto.o
EXTI8_IRQHandlerCode0x3418238222stm32n657xx_Vectors.o
HAL_RCC_OscConfigCode0x341823842 8104blto2_FSBL_lto.o
EXTI9_IRQHandlerCode0x34182E7E22stm32n657xx_Vectors.o
LL_RCC_HSI_SetCalibTrimmingCode0x34182E80304blto2_FSBL_lto.o
EXTI10_IRQHandlerCode0x34182E9E22stm32n657xx_Vectors.o
LL_RCC_HSI_DisableCode0x34182EA0144blto2_FSBL_lto.o
EXTI11_IRQHandlerCode0x34182EAE22stm32n657xx_Vectors.o
LL_RCC_MSI_SetCalibTrimmingCode0x34182EB0304blto2_FSBL_lto.o
EXTI12_IRQHandlerCode0x34182ECE22stm32n657xx_Vectors.o
LL_RCC_MSI_EnableCode0x34182ED0144blto2_FSBL_lto.o
EXTI13_IRQHandlerCode0x34182EDE22stm32n657xx_Vectors.o
LL_RCC_MSI_DisableCode0x34182EE0144blto2_FSBL_lto.o
EXTI14_IRQHandlerCode0x34182EEE22stm32n657xx_Vectors.o
LL_RCC_LSI_EnableCode0x34182EF0144blto2_FSBL_lto.o
EXTI15_IRQHandlerCode0x34182EFE22stm32n657xx_Vectors.o
LL_RCC_LSI_DisableCode0x34182F00144blto2_FSBL_lto.o
SAES_IRQHandlerCode0x34182F0E22stm32n657xx_Vectors.o
RCC_PLL_IsNewConfigCode0x34182F102184blto2_FSBL_lto.o
CRYP_IRQHandlerCode0x34182FEA22stm32n657xx_Vectors.o
RCC_PLL_ConfigCode0x34182FEC8464blto2_FSBL_lto.o
PKA_IRQHandlerCode0x3418333A22stm32n657xx_Vectors.o
RCC_PLL_EnableCode0x3418333C944blto2_FSBL_lto.o
HASH_IRQHandlerCode0x3418339A22stm32n657xx_Vectors.o
HAL_RCC_ClockConfigCode0x3418339C2 4984blto2_FSBL_lto.o
RNG_IRQHandlerCode0x34183D5E22stm32n657xx_Vectors.o
RCC_IC_CheckPLLSourcesCode0x34183D602344blto2_FSBL_lto.o
MCE1_IRQHandlerCode0x34183E4A22stm32n657xx_Vectors.o
LL_RCC_IC1_EnableCode0x34183E4C144blto2_FSBL_lto.o
MCE2_IRQHandlerCode0x34183E5A22stm32n657xx_Vectors.o
HAL_RCC_GetCpuClockFreqCode0x34183E5C2384blto2_FSBL_lto.o
MCE3_IRQHandlerCode0x34183F4A22stm32n657xx_Vectors.o
LL_RCC_IC1_GetDividerCode0x34183F4C224blto2_FSBL_lto.o
MCE4_IRQHandlerCode0x34183F6222stm32n657xx_Vectors.o
HAL_RCCEx_GetPLL1CLKFreqCode0x34183F641304blto2_FSBL_lto.o
ADC1_2_IRQHandlerCode0x34183FE622stm32n657xx_Vectors.o
HAL_RCCEx_GetPLL2CLKFreqCode0x34183FE81304blto2_FSBL_lto.o
CSI_IRQHandlerCode0x3418406A22stm32n657xx_Vectors.o
HAL_RCCEx_GetPLL3CLKFreqCode0x3418406C1304blto2_FSBL_lto.o
DCMIPP_IRQHandlerCode0x341840EE22stm32n657xx_Vectors.o
HAL_RCCEx_GetPLL4CLKFreqCode0x341840F01304blto2_FSBL_lto.o
PAHB_ERR_IRQHandlerCode0x3418417222stm32n657xx_Vectors.o
NPU0_IRQHandlerCode0x3418417422stm32n657xx_Vectors.o
NPU1_IRQHandlerCode0x3418417622stm32n657xx_Vectors.o
NPU2_IRQHandlerCode0x3418417822stm32n657xx_Vectors.o
NPU3_IRQHandlerCode0x3418417A22stm32n657xx_Vectors.o
CACHEAXI_IRQHandlerCode0x3418417C22stm32n657xx_Vectors.o
LTDC_LO_IRQHandlerCode0x3418417E22stm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandlerCode0x3418418022stm32n657xx_Vectors.o
DMA2D_IRQHandlerCode0x3418418222stm32n657xx_Vectors.o
JPEG_IRQHandlerCode0x3418418422stm32n657xx_Vectors.o
VENC_IRQHandlerCode0x3418418622stm32n657xx_Vectors.o
GFXMMU_IRQHandlerCode0x3418418822stm32n657xx_Vectors.o
GFXTIM_IRQHandlerCode0x3418418A22stm32n657xx_Vectors.o
GPU2D_IRQHandlerCode0x3418418C22stm32n657xx_Vectors.o
GPU2D_ER_IRQHandlerCode0x3418418E22stm32n657xx_Vectors.o
ICACHE_IRQHandlerCode0x3418419022stm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandlerCode0x3418419222stm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandlerCode0x3418419422stm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandlerCode0x3418419622stm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandlerCode0x3418419822stm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandlerCode0x3418419A22stm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandlerCode0x3418419C22stm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandlerCode0x3418419E22stm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandlerCode0x341841A022stm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandlerCode0x341841A222stm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandlerCode0x341841A422stm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandlerCode0x341841A622stm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandlerCode0x341841A822stm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandlerCode0x341841AA22stm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandlerCode0x341841AC22stm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandlerCode0x341841AE22stm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandlerCode0x341841B022stm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandlerCode0x341841B222stm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandlerCode0x341841B422stm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandlerCode0x341841B622stm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandlerCode0x341841B822stm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandlerCode0x341841BA22stm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandlerCode0x341841BC22stm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandlerCode0x341841BE22stm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandlerCode0x341841C022stm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandlerCode0x341841C222stm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandlerCode0x341841C422stm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandlerCode0x341841C622stm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandlerCode0x341841C822stm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandlerCode0x341841CA22stm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandlerCode0x341841CC22stm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandlerCode0x341841CE22stm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandlerCode0x341841D022stm32n657xx_Vectors.o
I2C1_EV_IRQHandlerCode0x341841D222stm32n657xx_Vectors.o
I2C1_ER_IRQHandlerCode0x341841D422stm32n657xx_Vectors.o
I2C2_EV_IRQHandlerCode0x341841D622stm32n657xx_Vectors.o
I2C2_ER_IRQHandlerCode0x341841D822stm32n657xx_Vectors.o
I2C3_EV_IRQHandlerCode0x341841DA22stm32n657xx_Vectors.o
I2C3_ER_IRQHandlerCode0x341841DC22stm32n657xx_Vectors.o
I2C4_EV_IRQHandlerCode0x341841DE22stm32n657xx_Vectors.o
I2C4_ER_IRQHandlerCode0x341841E022stm32n657xx_Vectors.o
I3C1_EV_IRQHandlerCode0x341841E222stm32n657xx_Vectors.o
I3C1_ER_IRQHandlerCode0x341841E422stm32n657xx_Vectors.o
I3C2_EV_IRQHandlerCode0x341841E622stm32n657xx_Vectors.o
I3C2_ER_IRQHandlerCode0x341841E822stm32n657xx_Vectors.o
TIM1_BRK_IRQHandlerCode0x341841EA22stm32n657xx_Vectors.o
TIM1_UP_IRQHandlerCode0x341841EC22stm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandlerCode0x341841EE22stm32n657xx_Vectors.o
TIM1_CC_IRQHandlerCode0x341841F022stm32n657xx_Vectors.o
TIM2_IRQHandlerCode0x341841F222stm32n657xx_Vectors.o
TIM3_IRQHandlerCode0x341841F422stm32n657xx_Vectors.o
TIM4_IRQHandlerCode0x341841F622stm32n657xx_Vectors.o
TIM5_IRQHandlerCode0x341841F822stm32n657xx_Vectors.o
TIM6_IRQHandlerCode0x341841FA22stm32n657xx_Vectors.o
TIM7_IRQHandlerCode0x341841FC22stm32n657xx_Vectors.o
TIM8_BRK_IRQHandlerCode0x341841FE22stm32n657xx_Vectors.o
TIM8_UP_IRQHandlerCode0x3418420022stm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandlerCode0x3418420222stm32n657xx_Vectors.o
TIM8_CC_IRQHandlerCode0x3418420422stm32n657xx_Vectors.o
TIM9_IRQHandlerCode0x3418420622stm32n657xx_Vectors.o
TIM10_IRQHandlerCode0x3418420822stm32n657xx_Vectors.o
TIM11_IRQHandlerCode0x3418420A22stm32n657xx_Vectors.o
TIM12_IRQHandlerCode0x3418420C22stm32n657xx_Vectors.o
TIM13_IRQHandlerCode0x3418420E22stm32n657xx_Vectors.o
TIM14_IRQHandlerCode0x3418421022stm32n657xx_Vectors.o
TIM15_IRQHandlerCode0x3418421222stm32n657xx_Vectors.o
TIM16_IRQHandlerCode0x3418421422stm32n657xx_Vectors.o
TIM17_IRQHandlerCode0x3418421622stm32n657xx_Vectors.o
TIM18_IRQHandlerCode0x3418421822stm32n657xx_Vectors.o
LPTIM1_IRQHandlerCode0x3418421A22stm32n657xx_Vectors.o
LPTIM2_IRQHandlerCode0x3418421C22stm32n657xx_Vectors.o
LPTIM3_IRQHandlerCode0x3418421E22stm32n657xx_Vectors.o
LPTIM4_IRQHandlerCode0x3418422022stm32n657xx_Vectors.o
LPTIM5_IRQHandlerCode0x3418422222stm32n657xx_Vectors.o
ADF1_FLT0_IRQHandlerCode0x3418422422stm32n657xx_Vectors.o
MDF1_FLT0_IRQHandlerCode0x3418422622stm32n657xx_Vectors.o
MDF1_FLT1_IRQHandlerCode0x3418422822stm32n657xx_Vectors.o
MDF1_FLT2_IRQHandlerCode0x3418422A22stm32n657xx_Vectors.o
MDF1_FLT3_IRQHandlerCode0x3418422C22stm32n657xx_Vectors.o
MDF1_FLT4_IRQHandlerCode0x3418422E22stm32n657xx_Vectors.o
MDF1_FLT5_IRQHandlerCode0x3418423022stm32n657xx_Vectors.o
SAI1_A_IRQHandlerCode0x3418423222stm32n657xx_Vectors.o
SAI1_B_IRQHandlerCode0x3418423422stm32n657xx_Vectors.o
SAI2_A_IRQHandlerCode0x3418423622stm32n657xx_Vectors.o
SAI2_B_IRQHandlerCode0x3418423822stm32n657xx_Vectors.o
SPDIFRX_IRQHandlerCode0x3418423A22stm32n657xx_Vectors.o
SPI1_IRQHandlerCode0x3418423C22stm32n657xx_Vectors.o
SPI2_IRQHandlerCode0x3418423E22stm32n657xx_Vectors.o
SPI3_IRQHandlerCode0x3418424022stm32n657xx_Vectors.o
SPI4_IRQHandlerCode0x3418424222stm32n657xx_Vectors.o
SPI5_IRQHandlerCode0x3418424422stm32n657xx_Vectors.o
SPI6_IRQHandlerCode0x3418424622stm32n657xx_Vectors.o
USART1_IRQHandlerCode0x3418424822stm32n657xx_Vectors.o
USART2_IRQHandlerCode0x3418424A22stm32n657xx_Vectors.o
USART3_IRQHandlerCode0x3418424C22stm32n657xx_Vectors.o
UART4_IRQHandlerCode0x3418424E22stm32n657xx_Vectors.o
UART5_IRQHandlerCode0x3418425022stm32n657xx_Vectors.o
USART6_IRQHandlerCode0x3418425222stm32n657xx_Vectors.o
UART7_IRQHandlerCode0x3418425422stm32n657xx_Vectors.o
UART8_IRQHandlerCode0x3418425622stm32n657xx_Vectors.o
UART9_IRQHandlerCode0x3418425822stm32n657xx_Vectors.o
USART10_IRQHandlerCode0x3418425A22stm32n657xx_Vectors.o
LPUART1_IRQHandlerCode0x3418425C22stm32n657xx_Vectors.o
XSPI1_IRQHandlerCode0x3418425E22stm32n657xx_Vectors.o
XSPI2_IRQHandlerCode0x3418426022stm32n657xx_Vectors.o
XSPI3_IRQHandlerCode0x3418426222stm32n657xx_Vectors.o
FMC_IRQHandlerCode0x3418426422stm32n657xx_Vectors.o
SDMMC1_IRQHandlerCode0x3418426622stm32n657xx_Vectors.o
SDMMC2_IRQHandlerCode0x3418426822stm32n657xx_Vectors.o
UCPD1_IRQHandlerCode0x3418426A22stm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandlerCode0x3418426C22stm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandlerCode0x3418426E22stm32n657xx_Vectors.o
ETH1_IRQHandlerCode0x3418427022stm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandlerCode0x3418427222stm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandlerCode0x3418427422stm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandlerCode0x3418427622stm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandlerCode0x3418427822stm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandlerCode0x3418427A22stm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandlerCode0x3418427C22stm32n657xx_Vectors.o
FDCAN_CU_IRQHandlerCode0x3418427E22stm32n657xx_Vectors.o
MDIOS_IRQHandlerCode0x3418428022stm32n657xx_Vectors.o
DCMI_PSSI_IRQHandlerCode0x3418428222stm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandlerCode0x3418428422stm32n657xx_Vectors.o
CTI_INT0_IRQHandlerCode0x3418428622stm32n657xx_Vectors.o
CTI_INT1_IRQHandlerCode0x3418428822stm32n657xx_Vectors.o
LTDC_UP_IRQHandlerCode0x3418428A22stm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandlerCode0x3418428C22stm32n657xx_Vectors.o
[.rodata..L.str.20]Cnst0x3418428E1061blto2_FSBL_lto.o
[.rodata..L.str.35]Cnst0x341842F81051blto2_FSBL_lto.o
[.rodata.block.tdata.copy]Cnst0x341843611[ Linker created ]
[.init_array]----0x3418436444STM32N6xx_Startup.o
[.rodata..L.str.10]Cnst0x341843681081blto2_FSBL_lto.o
[.rodata..L.str.28]Cnst0x341843D41081blto2_FSBL_lto.o
__SEGGER_init_ctorsCode0x3418444C364SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_table__Cnst0x34184470524[ Linker created ]
__SEGGER_init_data__Cnst0x341844A4124[ Linker created ]
__SEGGER_init_zeroCode0x341844B0182SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_copyCode0x341844C2202SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
+

"<#16> at line 128, col 45": place in [0x34180400 to 0x341FFFFF] with auto order

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
uwTickFreqInit0x3418436111blto2_FSBL_lto.o
[.bss.block.heap]None0x341843688[ Linker created ]
uwTickZero0x3418444044blto2_FSBL_lto.o
uwTickPrioInit0x3418444444blto2_FSBL_lto.o
SystemCoreClockInit0x3418444844blto2_FSBL_lto.o
[.bss.block.stack]None0x341FC00016 3848[ Linker created ]
+

"<#17> at line 132, col 45": place in [0x34180400 to 0x341FFFFF] with auto order

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x341843688[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
blto2_FSBL_lto.o14 63042794
SEGGER_THUMB_Startup.o20
stm32n657xx_Vectors.o1 216
STM32N6xx_Startup.o44
Subtotal (4 objects)15 91042794
SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a74
strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a104
Subtotal (2archives)178
Linker created (shared data, fills, blocks):6416 384
Total:16 088491916 388
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)74
strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)104
Subtotal (2 members from 2 archives)178
Objects (4 files)15 91042794
Linker created (shared data, fills, blocks):6416 384
Total:16 088491916 388
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table64
Memory for block 'stack'16 384
Subtotal (linker created):6416 384
Objects (4 files)15 91042794
Archives (2 files)178
Total:16 088491916 388
+

MODULE DETAIL

+

Module blto2_FSBL_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_RCC_OscConfig2 810
HAL_RCC_ClockConfig2 498
HAL_GPIO_Init1 928
RCC_PLL_Config846
SystemCoreClockUpdate828
SystemInit510
MX_GPIO_Init466
HAL_RCC_GetClockConfig240
SystemClock_Config238
HAL_RCC_GetCpuClockFreq238
RCC_IC_CheckPLLSources234
RCC_PLL_IsNewConfig218
HAL_NVIC_SetPriority168
RCCEx_GetPLLSourceFreq140
RCCEx_CalcPLLFreq136
HAL_RCCEx_GetPLL1CLKFreq130
HAL_RCCEx_GetPLL2CLKFreq130
HAL_RCCEx_GetPLL3CLKFreq130
HAL_RCCEx_GetPLL4CLKFreq130
HAL_InitTick126
HAL_PWREx_ConfigSupply114
HAL_PWREx_ControlVoltageScaling114
HAL_GPIO_WritePin102
NVIC_EncodePriority100
RCC_PLL_Enable94
RCC_PLL_Source_IsReady84
SysTick_Config78
main66
HAL_NVIC_SetPriorityGrouping62
__NVIC_SetPriority62
__NVIC_SetPriorityGrouping60
HAL_Delay58
HAL_Init48
LL_AHB4_GRP1_EnableClock34
LL_RCC_HSI_SetCalibTrimming30
LL_RCC_MSI_SetCalibTrimming30
LL_RCC_HSI_SetDivider28
LL_RCC_MSI_SetFrequency28
HAL_IncTick26
LL_RCC_IC1_GetDivider22
HAL_PWREx_EnableVddIO318
__NVIC_GetPriorityGrouping16
HAL_SYSTICK_Config16
LL_RCC_HSI_IsReady16
LL_RCC_GetCpuClkSource16
LL_RCC_GetSysClkSource16
LL_RCC_PLL1_GetSource16
LL_RCC_PLL2_GetSource16
LL_RCC_PLL3_GetSource16
LL_RCC_PLL4_GetSource16
LL_RCC_MSI_IsReady16
LL_RCC_LSI_IsReady16
LL_RCC_LSE_IsReady16
LL_RCC_PLL1_IsReady16
LL_RCC_IC1_GetSource16
LL_RCC_IC2_GetSource16
LL_RCC_IC6_GetSource16
LL_RCC_IC11_GetSource16
LL_RCC_PLL2_IsReady16
LL_RCC_PLL3_IsReady16
LL_RCC_PLL4_IsReady16
LL_RCC_HSE_IsReady16
LL_RCC_HSI_GetDivider16
LL_RCC_PLL1_IsEnabledBypass16
LL_RCC_PLL2_IsEnabledBypass16
LL_RCC_PLL3_IsEnabledBypass16
LL_RCC_PLL4_IsEnabledBypass16
LL_RCC_PLL4_IsReady.5716
LL_RCC_PLL4P_IsEnabled16
LL_RCC_PLL4_GetSource.5816
LL_RCC_PLL4_GetM16
LL_RCC_PLL4_GetN16
LL_RCC_PLL4_GetFRACN16
LL_RCC_PLL4_GetP116
LL_RCC_PLL4_GetP216
LL_RCC_PLL4_IsEnabledBypass.5916
LL_RCC_HSI_IsReady.6016
LL_RCC_HSI_GetDivider.6116
LL_RCC_MSI_IsReady.6216
LL_RCC_MSI_GetFrequency16
LL_RCC_HSE_IsReady.6316
LL_RCC_PLL3_IsReady.6416
LL_RCC_PLL3P_IsEnabled16
LL_RCC_PLL3_GetSource.6516
LL_RCC_PLL3_GetM16
LL_RCC_PLL3_GetN16
LL_RCC_PLL3_GetFRACN16
LL_RCC_PLL3_GetP116
LL_RCC_PLL3_GetP216
LL_RCC_PLL3_IsEnabledBypass.6616
LL_RCC_PLL2_IsReady.6716
LL_RCC_PLL2P_IsEnabled16
LL_RCC_PLL2_GetSource.6816
LL_RCC_PLL2_GetM16
LL_RCC_PLL2_GetN16
LL_RCC_PLL2_GetFRACN16
LL_RCC_PLL2_GetP116
LL_RCC_PLL2_GetP216
LL_RCC_PLL2_IsEnabledBypass.6916
LL_RCC_PLL1_IsReady.7016
LL_RCC_PLL1P_IsEnabled16
LL_RCC_PLL1_GetSource.7116
LL_RCC_PLL1_GetM16
LL_RCC_PLL1_GetN16
LL_RCC_PLL1_GetFRACN16
LL_RCC_PLL1_GetP116
LL_RCC_PLL1_GetP216
LL_RCC_PLL1_IsEnabledBypass.7216
LL_RCC_HSI_Enable14
LL_RCC_HSI_Disable14
LL_RCC_MSI_Enable14
LL_RCC_MSI_Disable14
LL_RCC_LSI_Enable14
LL_RCC_LSI_Disable14
LL_RCC_IC1_Enable14
HAL_GetTick12
assert_failed10
HAL_MspInit8
SysTick_Handler8
Error_Handler4
NMI_Handler2
HardFault_Handler2
MemManage_Handler2
BusFault_Handler2
UsageFault_Handler2
SVC_Handler2
DebugMon_Handler2
PendSV_Handler2
[.rodata..L.str.10]108
[.rodata..L.str.28]108
[.rodata..L.str.20]106
[.rodata..L.str.35]105
SystemCoreClock4
uwTickPrio4
uwTickFreq1
uwTick4
Total:14 63042794
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32n657xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors844
PVD_PVM_IRQHandler2
DTS_IRQHandler2
RCC_IRQHandler2
LOCKUP_IRQHandler2
CACHE_ECC_IRQHandler2
TCM_ECC_IRQHandler2
BCK_ECC_IRQHandler2
FPU_IRQHandler2
RTC_S_IRQHandler2
TAMP_IRQHandler2
RIFSC_TAMPER_IRQHandler2
IAC_IRQHandler2
RCC_S_IRQHandler2
RTC_IRQHandler2
IWDG_IRQHandler2
WWDG_IRQHandler2
EXTI0_IRQHandler2
EXTI1_IRQHandler2
EXTI2_IRQHandler2
EXTI3_IRQHandler2
EXTI4_IRQHandler2
EXTI5_IRQHandler2
EXTI6_IRQHandler2
EXTI7_IRQHandler2
EXTI8_IRQHandler2
EXTI9_IRQHandler2
EXTI10_IRQHandler2
EXTI11_IRQHandler2
EXTI12_IRQHandler2
EXTI13_IRQHandler2
EXTI14_IRQHandler2
EXTI15_IRQHandler2
SAES_IRQHandler2
CRYP_IRQHandler2
PKA_IRQHandler2
HASH_IRQHandler2
RNG_IRQHandler2
MCE1_IRQHandler2
MCE2_IRQHandler2
MCE3_IRQHandler2
MCE4_IRQHandler2
ADC1_2_IRQHandler2
CSI_IRQHandler2
DCMIPP_IRQHandler2
PAHB_ERR_IRQHandler2
NPU0_IRQHandler2
NPU1_IRQHandler2
NPU2_IRQHandler2
NPU3_IRQHandler2
CACHEAXI_IRQHandler2
LTDC_LO_IRQHandler2
LTDC_LO_ERR_IRQHandler2
DMA2D_IRQHandler2
JPEG_IRQHandler2
VENC_IRQHandler2
GFXMMU_IRQHandler2
GFXTIM_IRQHandler2
GPU2D_IRQHandler2
GPU2D_ER_IRQHandler2
ICACHE_IRQHandler2
HPDMA1_Channel0_IRQHandler2
HPDMA1_Channel1_IRQHandler2
HPDMA1_Channel2_IRQHandler2
HPDMA1_Channel3_IRQHandler2
HPDMA1_Channel4_IRQHandler2
HPDMA1_Channel5_IRQHandler2
HPDMA1_Channel6_IRQHandler2
HPDMA1_Channel7_IRQHandler2
HPDMA1_Channel8_IRQHandler2
HPDMA1_Channel9_IRQHandler2
HPDMA1_Channel10_IRQHandler2
HPDMA1_Channel11_IRQHandler2
HPDMA1_Channel12_IRQHandler2
HPDMA1_Channel13_IRQHandler2
HPDMA1_Channel14_IRQHandler2
HPDMA1_Channel15_IRQHandler2
GPDMA1_Channel0_IRQHandler2
GPDMA1_Channel1_IRQHandler2
GPDMA1_Channel2_IRQHandler2
GPDMA1_Channel3_IRQHandler2
GPDMA1_Channel4_IRQHandler2
GPDMA1_Channel5_IRQHandler2
GPDMA1_Channel6_IRQHandler2
GPDMA1_Channel7_IRQHandler2
GPDMA1_Channel8_IRQHandler2
GPDMA1_Channel9_IRQHandler2
GPDMA1_Channel10_IRQHandler2
GPDMA1_Channel11_IRQHandler2
GPDMA1_Channel12_IRQHandler2
GPDMA1_Channel13_IRQHandler2
GPDMA1_Channel14_IRQHandler2
GPDMA1_Channel15_IRQHandler2
I2C1_EV_IRQHandler2
I2C1_ER_IRQHandler2
I2C2_EV_IRQHandler2
I2C2_ER_IRQHandler2
I2C3_EV_IRQHandler2
I2C3_ER_IRQHandler2
I2C4_EV_IRQHandler2
I2C4_ER_IRQHandler2
I3C1_EV_IRQHandler2
I3C1_ER_IRQHandler2
I3C2_EV_IRQHandler2
I3C2_ER_IRQHandler2
TIM1_BRK_IRQHandler2
TIM1_UP_IRQHandler2
TIM1_TRG_CCU_IRQHandler2
TIM1_CC_IRQHandler2
TIM2_IRQHandler2
TIM3_IRQHandler2
TIM4_IRQHandler2
TIM5_IRQHandler2
TIM6_IRQHandler2
TIM7_IRQHandler2
TIM8_BRK_IRQHandler2
TIM8_UP_IRQHandler2
TIM8_TRG_CCU_IRQHandler2
TIM8_CC_IRQHandler2
TIM9_IRQHandler2
TIM10_IRQHandler2
TIM11_IRQHandler2
TIM12_IRQHandler2
TIM13_IRQHandler2
TIM14_IRQHandler2
TIM15_IRQHandler2
TIM16_IRQHandler2
TIM17_IRQHandler2
TIM18_IRQHandler2
LPTIM1_IRQHandler2
LPTIM2_IRQHandler2
LPTIM3_IRQHandler2
LPTIM4_IRQHandler2
LPTIM5_IRQHandler2
ADF1_FLT0_IRQHandler2
MDF1_FLT0_IRQHandler2
MDF1_FLT1_IRQHandler2
MDF1_FLT2_IRQHandler2
MDF1_FLT3_IRQHandler2
MDF1_FLT4_IRQHandler2
MDF1_FLT5_IRQHandler2
SAI1_A_IRQHandler2
SAI1_B_IRQHandler2
SAI2_A_IRQHandler2
SAI2_B_IRQHandler2
SPDIFRX_IRQHandler2
SPI1_IRQHandler2
SPI2_IRQHandler2
SPI3_IRQHandler2
SPI4_IRQHandler2
SPI5_IRQHandler2
SPI6_IRQHandler2
USART1_IRQHandler2
USART2_IRQHandler2
USART3_IRQHandler2
UART4_IRQHandler2
UART5_IRQHandler2
USART6_IRQHandler2
UART7_IRQHandler2
UART8_IRQHandler2
UART9_IRQHandler2
USART10_IRQHandler2
LPUART1_IRQHandler2
XSPI1_IRQHandler2
XSPI2_IRQHandler2
XSPI3_IRQHandler2
FMC_IRQHandler2
SDMMC1_IRQHandler2
SDMMC2_IRQHandler2
UCPD1_IRQHandler2
USB1_OTG_HS_IRQHandler2
USB2_OTG_HS_IRQHandler2
ETH1_IRQHandler2
FDCAN1_IT0_IRQHandler2
FDCAN1_IT1_IRQHandler2
FDCAN2_IT0_IRQHandler2
FDCAN2_IT1_IRQHandler2
FDCAN3_IT0_IRQHandler2
FDCAN3_IT1_IRQHandler2
FDCAN_CU_IRQHandler2
MDIOS_IRQHandler2
DCMI_PSSI_IRQHandler2
WAKEUP_PIN_IRQHandler2
CTI_INT0_IRQHandler2
CTI_INT1_IRQHandler2
LTDC_UP_IRQHandler2
LTDC_UP_ERR_IRQHandler2
Total:1 216
+

Module STM32N6xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler44
Total:44
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr104
Total:104
+

All modules

+ + + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:16 08842794
+

SECTION DETAIL

+

Sections by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSymbol or [section] NameSizeAlInitAcObject File
34180400-3418074B_vectors8441024CodeRXstm32n657xx_Vectors.o
3418074C-3418074FError_Handler44CodeRXblto2_FSBL_lto.o
34180750-34180757HAL_MspInit84CodeRXblto2_FSBL_lto.o
34180758-3418075FSysTick_Handler84CodeRXblto2_FSBL_lto.o
34180760-34180A9BSystemCoreClockUpdate8284CodeRXblto2_FSBL_lto.o
34180A9C-34180ACBHAL_Init484CodeRXblto2_FSBL_lto.o
34180ACC-34180AD7HAL_GetTick124CodeRXblto2_FSBL_lto.o
34180AD8-34180B13__NVIC_SetPriorityGrouping604CodeRXblto2_FSBL_lto.o
34180B14-34180BBBHAL_NVIC_SetPriority1684CodeRXblto2_FSBL_lto.o
34180BBC-34180BCB__NVIC_GetPriorityGrouping164CodeRXblto2_FSBL_lto.o
34180BCC-34180C2FNVIC_EncodePriority1004CodeRXblto2_FSBL_lto.o
34180C30-34180C3FHAL_SYSTICK_Config164CodeRXblto2_FSBL_lto.o
34180C40-341813C7HAL_GPIO_Init1 9284CodeRXblto2_FSBL_lto.o
341813C8-341813E3LL_RCC_HSI_SetDivider284CodeRXblto2_FSBL_lto.o
341813E4-341813F3LL_RCC_HSI_IsReady164CodeRXblto2_FSBL_lto.o
341813F4-34181403LL_RCC_GetCpuClkSource164CodeRXblto2_FSBL_lto.o
34181404-34181413LL_RCC_GetSysClkSource164CodeRXblto2_FSBL_lto.o
34181414-34181423LL_RCC_PLL1_GetSource164CodeRXblto2_FSBL_lto.o
34181424-34181433LL_RCC_PLL2_GetSource164CodeRXblto2_FSBL_lto.o
34181434-34181443LL_RCC_PLL3_GetSource164CodeRXblto2_FSBL_lto.o
34181444-34181453LL_RCC_PLL4_GetSource164CodeRXblto2_FSBL_lto.o
34181454-3418146FLL_RCC_MSI_SetFrequency284CodeRXblto2_FSBL_lto.o
34181470-3418147FLL_RCC_MSI_IsReady164CodeRXblto2_FSBL_lto.o
34181480-3418148FLL_RCC_LSI_IsReady164CodeRXblto2_FSBL_lto.o
34181490-3418149FLL_RCC_LSE_IsReady164CodeRXblto2_FSBL_lto.o
341814A0-341814AFLL_RCC_PLL1_IsReady164CodeRXblto2_FSBL_lto.o
341814B0-341814BFLL_RCC_IC1_GetSource164CodeRXblto2_FSBL_lto.o
341814C0-341814CFLL_RCC_IC2_GetSource164CodeRXblto2_FSBL_lto.o
341814D0-341814DFLL_RCC_IC6_GetSource164CodeRXblto2_FSBL_lto.o
341814E0-341814EFLL_RCC_IC11_GetSource164CodeRXblto2_FSBL_lto.o
341814F0-341814FFLL_RCC_PLL2_IsReady164CodeRXblto2_FSBL_lto.o
34181500-3418150FLL_RCC_PLL3_IsReady164CodeRXblto2_FSBL_lto.o
34181510-3418151FLL_RCC_PLL4_IsReady164CodeRXblto2_FSBL_lto.o
34181520-34181573RCC_PLL_Source_IsReady844CodeRXblto2_FSBL_lto.o
34181574-34181583LL_RCC_HSE_IsReady164CodeRXblto2_FSBL_lto.o
34181584-34181593LL_RCC_HSI_GetDivider164CodeRXblto2_FSBL_lto.o
34181594-341815A3LL_RCC_PLL1_IsEnabledBypass164CodeRXblto2_FSBL_lto.o
341815A4-341815B3LL_RCC_PLL2_IsEnabledBypass164CodeRXblto2_FSBL_lto.o
341815B4-341815C3LL_RCC_PLL3_IsEnabledBypass164CodeRXblto2_FSBL_lto.o
341815C4-341815D3LL_RCC_PLL4_IsEnabledBypass164CodeRXblto2_FSBL_lto.o
341815D4-341816C3HAL_RCC_GetClockConfig2404CodeRXblto2_FSBL_lto.o
341816C4-341816D3LL_RCC_PLL4_IsReady.57164CodeRXblto2_FSBL_lto.o
341816D4-341816E3LL_RCC_PLL4P_IsEnabled164CodeRXblto2_FSBL_lto.o
341816E4-341816F3LL_RCC_PLL4_GetSource.58164CodeRXblto2_FSBL_lto.o
341816F4-3418177FRCCEx_GetPLLSourceFreq1404CodeRXblto2_FSBL_lto.o
34181780-3418178FLL_RCC_PLL4_GetM164CodeRXblto2_FSBL_lto.o
34181790-3418179FLL_RCC_PLL4_GetN164CodeRXblto2_FSBL_lto.o
341817A0-341817AFLL_RCC_PLL4_GetFRACN164CodeRXblto2_FSBL_lto.o
341817B0-341817BFLL_RCC_PLL4_GetP1164CodeRXblto2_FSBL_lto.o
341817C0-341817CFLL_RCC_PLL4_GetP2164CodeRXblto2_FSBL_lto.o
341817D0-34181857RCCEx_CalcPLLFreq1364CodeRXblto2_FSBL_lto.o
34181858-34181867LL_RCC_PLL4_IsEnabledBypass.59164CodeRXblto2_FSBL_lto.o
34181868-34181877LL_RCC_HSI_IsReady.60164CodeRXblto2_FSBL_lto.o
34181878-34181887LL_RCC_HSI_GetDivider.61164CodeRXblto2_FSBL_lto.o
34181888-34181897LL_RCC_MSI_IsReady.62164CodeRXblto2_FSBL_lto.o
34181898-341818A7LL_RCC_MSI_GetFrequency164CodeRXblto2_FSBL_lto.o
341818A8-341818B7LL_RCC_HSE_IsReady.63164CodeRXblto2_FSBL_lto.o
341818B8-341818C7LL_RCC_PLL3_IsReady.64164CodeRXblto2_FSBL_lto.o
341818C8-341818D7LL_RCC_PLL3P_IsEnabled164CodeRXblto2_FSBL_lto.o
341818D8-341818E7LL_RCC_PLL3_GetSource.65164CodeRXblto2_FSBL_lto.o
341818E8-341818F7LL_RCC_PLL3_GetM164CodeRXblto2_FSBL_lto.o
341818F8-34181907LL_RCC_PLL3_GetN164CodeRXblto2_FSBL_lto.o
34181908-34181917LL_RCC_PLL3_GetFRACN164CodeRXblto2_FSBL_lto.o
34181918-34181927LL_RCC_PLL3_GetP1164CodeRXblto2_FSBL_lto.o
34181928-34181937LL_RCC_PLL3_GetP2164CodeRXblto2_FSBL_lto.o
34181938-34181947LL_RCC_PLL3_IsEnabledBypass.66164CodeRXblto2_FSBL_lto.o
34181948-34181957LL_RCC_PLL2_IsReady.67164CodeRXblto2_FSBL_lto.o
34181958-34181967LL_RCC_PLL2P_IsEnabled164CodeRXblto2_FSBL_lto.o
34181968-34181977LL_RCC_PLL2_GetSource.68164CodeRXblto2_FSBL_lto.o
34181978-34181987LL_RCC_PLL2_GetM164CodeRXblto2_FSBL_lto.o
34181988-34181997LL_RCC_PLL2_GetN164CodeRXblto2_FSBL_lto.o
34181998-341819A7LL_RCC_PLL2_GetFRACN164CodeRXblto2_FSBL_lto.o
341819A8-341819B7LL_RCC_PLL2_GetP1164CodeRXblto2_FSBL_lto.o
341819B8-341819C7LL_RCC_PLL2_GetP2164CodeRXblto2_FSBL_lto.o
341819C8-341819D7LL_RCC_PLL2_IsEnabledBypass.69164CodeRXblto2_FSBL_lto.o
341819D8-341819E7LL_RCC_PLL1_IsReady.70164CodeRXblto2_FSBL_lto.o
341819E8-341819F7LL_RCC_PLL1P_IsEnabled164CodeRXblto2_FSBL_lto.o
341819F8-34181A07LL_RCC_PLL1_GetSource.71164CodeRXblto2_FSBL_lto.o
34181A08-34181A17LL_RCC_PLL1_GetM164CodeRXblto2_FSBL_lto.o
34181A18-34181A27LL_RCC_PLL1_GetN164CodeRXblto2_FSBL_lto.o
34181A28-34181A37LL_RCC_PLL1_GetFRACN164CodeRXblto2_FSBL_lto.o
34181A38-34181A47LL_RCC_PLL1_GetP1164CodeRXblto2_FSBL_lto.o
34181A48-34181A57LL_RCC_PLL1_GetP2164CodeRXblto2_FSBL_lto.o
34181A58-34181A67LL_RCC_PLL1_IsEnabledBypass.72164CodeRXblto2_FSBL_lto.o
34181A68-34181A7B_start204CodeRXSEGGER_THUMB_Startup.o
34181A7C-34181AA7reset_handler444CodeRXSTM32N6xx_Startup.o
34181AA8-34181B0F__aeabi_memclr1044CodeRXstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
34181B10-34181CE1MX_GPIO_Init4664CodeRXblto2_FSBL_lto.o
34181CE2-34181CE3PVD_PVM_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181CE4-34181D05LL_AHB4_GRP1_EnableClock344CodeRXblto2_FSBL_lto.o
34181D06-34181D07DTS_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181D08-34181D49main664CodeRXblto2_FSBL_lto.o
34181D4A-34181D4BRCC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181D4C-34181E39SystemClock_Config2384CodeRXblto2_FSBL_lto.o
34181E3A-34181E3BLOCKUP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E3C-34181E45assert_failed104CodeRXblto2_FSBL_lto.o
34181E46-34181E47CACHE_ECC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E48-34181E49NMI_Handler24CodeRXblto2_FSBL_lto.o
34181E4A-34181E4BTCM_ECC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E4C-34181E4DHardFault_Handler24CodeRXblto2_FSBL_lto.o
34181E4E-34181E4FBCK_ECC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E50-34181E51MemManage_Handler24CodeRXblto2_FSBL_lto.o
34181E52-34181E53FPU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E54-34181E55BusFault_Handler24CodeRXblto2_FSBL_lto.o
34181E56-34181E57RTC_S_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E58-34181E59UsageFault_Handler24CodeRXblto2_FSBL_lto.o
34181E5A-34181E5BTAMP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E5C-34181E5DSVC_Handler24CodeRXblto2_FSBL_lto.o
34181E5E-34181E5FRIFSC_TAMPER_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E60-34181E61DebugMon_Handler24CodeRXblto2_FSBL_lto.o
34181E62-34181E63IAC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E64-34181E65PendSV_Handler24CodeRXblto2_FSBL_lto.o
34181E66-34181E67RCC_S_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181E68-34182065SystemInit5104CodeRXblto2_FSBL_lto.o
34182066-34182067RTC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182068-341820E5HAL_InitTick1264CodeRXblto2_FSBL_lto.o
341820E6-341820E7IWDG_IRQHandler22CodeRXstm32n657xx_Vectors.o
341820E8-34182101HAL_IncTick264CodeRXblto2_FSBL_lto.o
34182102-34182103WWDG_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182104-3418213DHAL_Delay584CodeRXblto2_FSBL_lto.o
3418213E-3418213FEXTI0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182140-3418217DHAL_NVIC_SetPriorityGrouping624CodeRXblto2_FSBL_lto.o
3418217E-3418217FEXTI1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182180-341821BD__NVIC_SetPriority624CodeRXblto2_FSBL_lto.o
341821BE-341821BFEXTI2_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821C0-3418220DSysTick_Config784CodeRXblto2_FSBL_lto.o
3418220E-3418220FEXTI3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182210-34182275HAL_GPIO_WritePin1024CodeRXblto2_FSBL_lto.o
34182276-34182277EXTI4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182278-341822E9HAL_PWREx_ConfigSupply1144CodeRXblto2_FSBL_lto.o
341822EA-341822EBEXTI5_IRQHandler22CodeRXstm32n657xx_Vectors.o
341822EC-3418235DHAL_PWREx_ControlVoltageScaling1144CodeRXblto2_FSBL_lto.o
3418235E-3418235FEXTI6_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182360-34182371HAL_PWREx_EnableVddIO3184CodeRXblto2_FSBL_lto.o
34182372-34182373EXTI7_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182374-34182381LL_RCC_HSI_Enable144CodeRXblto2_FSBL_lto.o
34182382-34182383EXTI8_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182384-34182E7DHAL_RCC_OscConfig2 8104CodeRXblto2_FSBL_lto.o
34182E7E-34182E7FEXTI9_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182E80-34182E9DLL_RCC_HSI_SetCalibTrimming304CodeRXblto2_FSBL_lto.o
34182E9E-34182E9FEXTI10_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182EA0-34182EADLL_RCC_HSI_Disable144CodeRXblto2_FSBL_lto.o
34182EAE-34182EAFEXTI11_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182EB0-34182ECDLL_RCC_MSI_SetCalibTrimming304CodeRXblto2_FSBL_lto.o
34182ECE-34182ECFEXTI12_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182ED0-34182EDDLL_RCC_MSI_Enable144CodeRXblto2_FSBL_lto.o
34182EDE-34182EDFEXTI13_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182EE0-34182EEDLL_RCC_MSI_Disable144CodeRXblto2_FSBL_lto.o
34182EEE-34182EEFEXTI14_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182EF0-34182EFDLL_RCC_LSI_Enable144CodeRXblto2_FSBL_lto.o
34182EFE-34182EFFEXTI15_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182F00-34182F0DLL_RCC_LSI_Disable144CodeRXblto2_FSBL_lto.o
34182F0E-34182F0FSAES_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182F10-34182FE9RCC_PLL_IsNewConfig2184CodeRXblto2_FSBL_lto.o
34182FEA-34182FEBCRYP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182FEC-34183339RCC_PLL_Config8464CodeRXblto2_FSBL_lto.o
3418333A-3418333BPKA_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418333C-34183399RCC_PLL_Enable944CodeRXblto2_FSBL_lto.o
3418339A-3418339BHASH_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418339C-34183D5DHAL_RCC_ClockConfig2 4984CodeRXblto2_FSBL_lto.o
34183D5E-34183D5FRNG_IRQHandler22CodeRXstm32n657xx_Vectors.o
34183D60-34183E49RCC_IC_CheckPLLSources2344CodeRXblto2_FSBL_lto.o
34183E4A-34183E4BMCE1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34183E4C-34183E59LL_RCC_IC1_Enable144CodeRXblto2_FSBL_lto.o
34183E5A-34183E5BMCE2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34183E5C-34183F49HAL_RCC_GetCpuClockFreq2384CodeRXblto2_FSBL_lto.o
34183F4A-34183F4BMCE3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34183F4C-34183F61LL_RCC_IC1_GetDivider224CodeRXblto2_FSBL_lto.o
34183F62-34183F63MCE4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34183F64-34183FE5HAL_RCCEx_GetPLL1CLKFreq1304CodeRXblto2_FSBL_lto.o
34183FE6-34183FE7ADC1_2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34183FE8-34184069HAL_RCCEx_GetPLL2CLKFreq1304CodeRXblto2_FSBL_lto.o
3418406A-3418406BCSI_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418406C-341840EDHAL_RCCEx_GetPLL3CLKFreq1304CodeRXblto2_FSBL_lto.o
341840EE-341840EFDCMIPP_IRQHandler22CodeRXstm32n657xx_Vectors.o
341840F0-34184171HAL_RCCEx_GetPLL4CLKFreq1304CodeRXblto2_FSBL_lto.o
34184172-34184173PAHB_ERR_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184174-34184175NPU0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184176-34184177NPU1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184178-34184179NPU2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418417A-3418417BNPU3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418417C-3418417DCACHEAXI_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418417E-3418417FLTDC_LO_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184180-34184181LTDC_LO_ERR_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184182-34184183DMA2D_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184184-34184185JPEG_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184186-34184187VENC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184188-34184189GFXMMU_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418418A-3418418BGFXTIM_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418418C-3418418DGPU2D_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418418E-3418418FGPU2D_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184190-34184191ICACHE_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184192-34184193HPDMA1_Channel0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184194-34184195HPDMA1_Channel1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184196-34184197HPDMA1_Channel2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184198-34184199HPDMA1_Channel3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418419A-3418419BHPDMA1_Channel4_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418419C-3418419DHPDMA1_Channel5_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418419E-3418419FHPDMA1_Channel6_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841A0-341841A1HPDMA1_Channel7_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841A2-341841A3HPDMA1_Channel8_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841A4-341841A5HPDMA1_Channel9_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841A6-341841A7HPDMA1_Channel10_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841A8-341841A9HPDMA1_Channel11_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841AA-341841ABHPDMA1_Channel12_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841AC-341841ADHPDMA1_Channel13_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841AE-341841AFHPDMA1_Channel14_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841B0-341841B1HPDMA1_Channel15_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841B2-341841B3GPDMA1_Channel0_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841B4-341841B5GPDMA1_Channel1_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841B6-341841B7GPDMA1_Channel2_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841B8-341841B9GPDMA1_Channel3_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841BA-341841BBGPDMA1_Channel4_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841BC-341841BDGPDMA1_Channel5_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841BE-341841BFGPDMA1_Channel6_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841C0-341841C1GPDMA1_Channel7_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841C2-341841C3GPDMA1_Channel8_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841C4-341841C5GPDMA1_Channel9_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841C6-341841C7GPDMA1_Channel10_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841C8-341841C9GPDMA1_Channel11_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841CA-341841CBGPDMA1_Channel12_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841CC-341841CDGPDMA1_Channel13_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841CE-341841CFGPDMA1_Channel14_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841D0-341841D1GPDMA1_Channel15_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841D2-341841D3I2C1_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841D4-341841D5I2C1_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841D6-341841D7I2C2_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841D8-341841D9I2C2_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841DA-341841DBI2C3_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841DC-341841DDI2C3_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841DE-341841DFI2C4_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841E0-341841E1I2C4_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841E2-341841E3I3C1_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841E4-341841E5I3C1_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841E6-341841E7I3C2_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841E8-341841E9I3C2_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841EA-341841EBTIM1_BRK_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841EC-341841EDTIM1_UP_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841EE-341841EFTIM1_TRG_CCU_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841F0-341841F1TIM1_CC_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841F2-341841F3TIM2_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841F4-341841F5TIM3_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841F6-341841F7TIM4_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841F8-341841F9TIM5_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841FA-341841FBTIM6_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841FC-341841FDTIM7_IRQHandler22CodeRXstm32n657xx_Vectors.o
341841FE-341841FFTIM8_BRK_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184200-34184201TIM8_UP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184202-34184203TIM8_TRG_CCU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184204-34184205TIM8_CC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184206-34184207TIM9_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184208-34184209TIM10_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418420A-3418420BTIM11_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418420C-3418420DTIM12_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418420E-3418420FTIM13_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184210-34184211TIM14_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184212-34184213TIM15_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184214-34184215TIM16_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184216-34184217TIM17_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184218-34184219TIM18_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418421A-3418421BLPTIM1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418421C-3418421DLPTIM2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418421E-3418421FLPTIM3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184220-34184221LPTIM4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184222-34184223LPTIM5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184224-34184225ADF1_FLT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184226-34184227MDF1_FLT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184228-34184229MDF1_FLT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418422A-3418422BMDF1_FLT2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418422C-3418422DMDF1_FLT3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418422E-3418422FMDF1_FLT4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184230-34184231MDF1_FLT5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184232-34184233SAI1_A_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184234-34184235SAI1_B_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184236-34184237SAI2_A_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184238-34184239SAI2_B_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418423A-3418423BSPDIFRX_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418423C-3418423DSPI1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418423E-3418423FSPI2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184240-34184241SPI3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184242-34184243SPI4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184244-34184245SPI5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184246-34184247SPI6_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184248-34184249USART1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418424A-3418424BUSART2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418424C-3418424DUSART3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418424E-3418424FUART4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184250-34184251UART5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184252-34184253USART6_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184254-34184255UART7_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184256-34184257UART8_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184258-34184259UART9_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418425A-3418425BUSART10_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418425C-3418425DLPUART1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418425E-3418425FXSPI1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184260-34184261XSPI2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184262-34184263XSPI3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184264-34184265FMC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184266-34184267SDMMC1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184268-34184269SDMMC2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418426A-3418426BUCPD1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418426C-3418426DUSB1_OTG_HS_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418426E-3418426FUSB2_OTG_HS_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184270-34184271ETH1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184272-34184273FDCAN1_IT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184274-34184275FDCAN1_IT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184276-34184277FDCAN2_IT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184278-34184279FDCAN2_IT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418427A-3418427BFDCAN3_IT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418427C-3418427DFDCAN3_IT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418427E-3418427FFDCAN_CU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184280-34184281MDIOS_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184282-34184283DCMI_PSSI_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184284-34184285WAKEUP_PIN_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184286-34184287CTI_INT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34184288-34184289CTI_INT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418428A-3418428BLTDC_UP_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418428C-3418428DLTDC_UP_ERR_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418428E-341842F7[.rodata..L.str.20]1061CnstROblto2_FSBL_lto.o
341842F8-34184360[.rodata..L.str.35]1051CnstROblto2_FSBL_lto.o
34184361-34184361uwTickFreq11InitRWblto2_FSBL_lto.o
34184362-34184363( UNUSED .=.+2 )2-------
34184364-34184367[.init_array]44------STM32N6xx_Startup.o
34184368-341843D3[.rodata..L.str.10]1081CnstROblto2_FSBL_lto.o
341843D4-3418443F[.rodata..L.str.28]1081CnstROblto2_FSBL_lto.o
34184440-34184443uwTick44ZeroZIblto2_FSBL_lto.o
34184444-34184447uwTickPrio44InitRWblto2_FSBL_lto.o
34184448-3418444BSystemCoreClock44InitRWblto2_FSBL_lto.o
3418444C-3418446F__SEGGER_init_ctors364CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
34184470-341844A3__SEGGER_init_table__524CnstRO[ Linker created ]
341844A4-341844AF__SEGGER_init_data__124CnstRO[ Linker created ]
341844B0-341844C1__SEGGER_init_zero182CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
341844C2-341844D5__SEGGER_init_copy202CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
341844D6-341FBFFF( UNUSED .=.+490282 )490 282-------
341FC000-341FFFFF[.bss.block.stack]16 3848NoneZI[ Linker created ]
+

UNUSED MEMORY SUMMARY

+

Detail

+ + + + + + + + + + + + + + + + + +
RangeSizeReason
34184362-341843632Unused memory between sections '.data.uwTickFreq' and '.init_array'
341844D6-341FBFFF490 282Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.block.stack'
+

INITIALIZATION TABLE

+

Constructor list

+ + + + + + + + + + + + +
Table
Address		Called
Address		Called
Symbol or [section] name
0x341843640x34180761SystemCoreClockUpdate
+

Initialize by zero

+ + + + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+ +
RangeSizeSymbol or [section] name
34184440-341844434uwTick
34184440-341844434Total (1 sections)
+ + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+ +
RangeSizeSymbol or [section] name
34184361-341843611uwTickFreq
34184361-341843611Total (1 sections)
+ + + + + + + + + + + + + + + + + + + + + +

Summary

+ +
RangeSizeSymbol or [section] name
34184444-341844474uwTickPrio
34184448-3418444B4SystemCoreClock
34184444-3418444B8Total (2 sections)
+ + + + + + + + + + + + + + + + + + + + +
DescriptionSize
Initialization table52 bytes
Source image9 bytes
Destination image13 bytes
Saving-48 bytes
+

LINKER-CREATED VENEERS

+

Arm-Arm range extension veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Thumb range extension veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Arm-Thumb mode switch veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Arm mode switch veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
Veneer TypeSize
Thumb-Arm mode switch0
Arm-Thumb mode switch0
Thumb-Thumb range extension0
Arm-Arm range extension0
Total:0
+

SYMBOL LIST

+

Function symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
ADC1_2_IRQHandler0x34183FE72CodeWkstm32n657xx_Vectors.o
ADF1_FLT0_IRQHandler0x341842252CodeWkstm32n657xx_Vectors.o
BCK_ECC_IRQHandler0x34181E4F2CodeWkstm32n657xx_Vectors.o
BusFault_Handler0x34181E5524CodeGbblto2_FSBL_lto.o
CACHEAXI_IRQHandler0x3418417D2CodeWkstm32n657xx_Vectors.o
CACHE_ECC_IRQHandler0x34181E472CodeWkstm32n657xx_Vectors.o
CRYP_IRQHandler0x34182FEB2CodeWkstm32n657xx_Vectors.o
CSI_IRQHandler0x3418406B2CodeWkstm32n657xx_Vectors.o
CTI_INT0_IRQHandler0x341842872CodeWkstm32n657xx_Vectors.o
CTI_INT1_IRQHandler0x341842892CodeWkstm32n657xx_Vectors.o
DCMIPP_IRQHandler0x341840EF2CodeWkstm32n657xx_Vectors.o
DCMI_PSSI_IRQHandler0x341842832CodeWkstm32n657xx_Vectors.o
DMA2D_IRQHandler0x341841832CodeWkstm32n657xx_Vectors.o
DTS_IRQHandler0x34181D072CodeWkstm32n657xx_Vectors.o
DebugMon_Handler0x34181E6124CodeGbblto2_FSBL_lto.o
ETH1_IRQHandler0x341842712CodeWkstm32n657xx_Vectors.o
EXTI0_IRQHandler0x3418213F2CodeWkstm32n657xx_Vectors.o
EXTI10_IRQHandler0x34182E9F2CodeWkstm32n657xx_Vectors.o
EXTI11_IRQHandler0x34182EAF2CodeWkstm32n657xx_Vectors.o
EXTI12_IRQHandler0x34182ECF2CodeWkstm32n657xx_Vectors.o
EXTI13_IRQHandler0x34182EDF2CodeWkstm32n657xx_Vectors.o
EXTI14_IRQHandler0x34182EEF2CodeWkstm32n657xx_Vectors.o
EXTI15_IRQHandler0x34182EFF2CodeWkstm32n657xx_Vectors.o
EXTI1_IRQHandler0x3418217F2CodeWkstm32n657xx_Vectors.o
EXTI2_IRQHandler0x341821BF2CodeWkstm32n657xx_Vectors.o
EXTI3_IRQHandler0x3418220F2CodeWkstm32n657xx_Vectors.o
EXTI4_IRQHandler0x341822772CodeWkstm32n657xx_Vectors.o
EXTI5_IRQHandler0x341822EB2CodeWkstm32n657xx_Vectors.o
EXTI6_IRQHandler0x3418235F2CodeWkstm32n657xx_Vectors.o
EXTI7_IRQHandler0x341823732CodeWkstm32n657xx_Vectors.o
EXTI8_IRQHandler0x341823832CodeWkstm32n657xx_Vectors.o
EXTI9_IRQHandler0x34182E7F2CodeWkstm32n657xx_Vectors.o
Error_Handler0x3418074D44CodeLcblto2_FSBL_lto.o
FDCAN1_IT0_IRQHandler0x341842732CodeWkstm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandler0x341842752CodeWkstm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandler0x341842772CodeWkstm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandler0x341842792CodeWkstm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandler0x3418427B2CodeWkstm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandler0x3418427D2CodeWkstm32n657xx_Vectors.o
FDCAN_CU_IRQHandler0x3418427F2CodeWkstm32n657xx_Vectors.o
FMC_IRQHandler0x341842652CodeWkstm32n657xx_Vectors.o
FPU_IRQHandler0x34181E532CodeWkstm32n657xx_Vectors.o
GFXMMU_IRQHandler0x341841892CodeWkstm32n657xx_Vectors.o
GFXTIM_IRQHandler0x3418418B2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandler0x341841B32CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandler0x341841C72CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandler0x341841C92CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandler0x341841CB2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandler0x341841CD2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandler0x341841CF2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandler0x341841D12CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandler0x341841B52CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandler0x341841B72CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandler0x341841B92CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandler0x341841BB2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandler0x341841BD2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandler0x341841BF2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandler0x341841C12CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandler0x341841C32CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandler0x341841C52CodeWkstm32n657xx_Vectors.o
GPU2D_ER_IRQHandler0x3418418F2CodeWkstm32n657xx_Vectors.o
GPU2D_IRQHandler0x3418418D2CodeWkstm32n657xx_Vectors.o
HAL_Delay0x34182105584CodeLcblto2_FSBL_lto.o
HAL_GPIO_Init0x34180C411 9284CodeLcblto2_FSBL_lto.o
HAL_GPIO_WritePin0x341822111024CodeLcblto2_FSBL_lto.o
HAL_GetTick0x34180ACD124CodeLcblto2_FSBL_lto.o
HAL_IncTick0x341820E9264CodeLcblto2_FSBL_lto.o
HAL_Init0x34180A9D484CodeLcblto2_FSBL_lto.o
HAL_InitTick0x341820691264CodeLcblto2_FSBL_lto.o
HAL_MspInit0x3418075184CodeLcblto2_FSBL_lto.o
HAL_NVIC_SetPriority0x34180B151684CodeLcblto2_FSBL_lto.o
HAL_NVIC_SetPriorityGrouping0x34182141624CodeLcblto2_FSBL_lto.o
HAL_PWREx_ConfigSupply0x341822791144CodeLcblto2_FSBL_lto.o
HAL_PWREx_ControlVoltageScaling0x341822ED1144CodeLcblto2_FSBL_lto.o
HAL_PWREx_EnableVddIO30x34182361184CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL1CLKFreq0x34183F651304CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL2CLKFreq0x34183FE91304CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL3CLKFreq0x3418406D1304CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL4CLKFreq0x341840F11304CodeLcblto2_FSBL_lto.o
HAL_RCC_ClockConfig0x3418339D2 4984CodeLcblto2_FSBL_lto.o
HAL_RCC_GetClockConfig0x341815D52404CodeLcblto2_FSBL_lto.o
HAL_RCC_GetCpuClockFreq0x34183E5D2384CodeLcblto2_FSBL_lto.o
HAL_RCC_OscConfig0x341823852 8104CodeLcblto2_FSBL_lto.o
HAL_SYSTICK_Config0x34180C31164CodeLcblto2_FSBL_lto.o
HASH_IRQHandler0x3418339B2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandler0x341841932CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandler0x341841A72CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandler0x341841A92CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandler0x341841AB2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandler0x341841AD2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandler0x341841AF2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandler0x341841B12CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandler0x341841952CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandler0x341841972CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandler0x341841992CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandler0x3418419B2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandler0x3418419D2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandler0x3418419F2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandler0x341841A12CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandler0x341841A32CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandler0x341841A52CodeWkstm32n657xx_Vectors.o
HardFault_Handler0x34181E4D24CodeGbblto2_FSBL_lto.o
I2C1_ER_IRQHandler0x341841D52CodeWkstm32n657xx_Vectors.o
I2C1_EV_IRQHandler0x341841D32CodeWkstm32n657xx_Vectors.o
I2C2_ER_IRQHandler0x341841D92CodeWkstm32n657xx_Vectors.o
I2C2_EV_IRQHandler0x341841D72CodeWkstm32n657xx_Vectors.o
I2C3_ER_IRQHandler0x341841DD2CodeWkstm32n657xx_Vectors.o
I2C3_EV_IRQHandler0x341841DB2CodeWkstm32n657xx_Vectors.o
I2C4_ER_IRQHandler0x341841E12CodeWkstm32n657xx_Vectors.o
I2C4_EV_IRQHandler0x341841DF2CodeWkstm32n657xx_Vectors.o
I3C1_ER_IRQHandler0x341841E52CodeWkstm32n657xx_Vectors.o
I3C1_EV_IRQHandler0x341841E32CodeWkstm32n657xx_Vectors.o
I3C2_ER_IRQHandler0x341841E92CodeWkstm32n657xx_Vectors.o
I3C2_EV_IRQHandler0x341841E72CodeWkstm32n657xx_Vectors.o
IAC_IRQHandler0x34181E632CodeWkstm32n657xx_Vectors.o
ICACHE_IRQHandler0x341841912CodeWkstm32n657xx_Vectors.o
IWDG_IRQHandler0x341820E72CodeWkstm32n657xx_Vectors.o
JPEG_IRQHandler0x341841852CodeWkstm32n657xx_Vectors.o
LL_AHB4_GRP1_EnableClock0x34181CE5344CodeLcblto2_FSBL_lto.o
LL_RCC_GetCpuClkSource0x341813F5164CodeLcblto2_FSBL_lto.o
LL_RCC_GetSysClkSource0x34181405164CodeLcblto2_FSBL_lto.o
LL_RCC_HSE_IsReady0x34181575164CodeLcblto2_FSBL_lto.o
LL_RCC_HSE_IsReady.630x341818A9164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_Disable0x34182EA1144CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_Enable0x34182375144CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_GetDivider0x34181585164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_GetDivider.610x34181879164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_IsReady0x341813E5164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_IsReady.600x34181869164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_SetCalibTrimming0x34182E81304CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_SetDivider0x341813C9284CodeLcblto2_FSBL_lto.o
LL_RCC_IC11_GetSource0x341814E1164CodeLcblto2_FSBL_lto.o
LL_RCC_IC1_Enable0x34183E4D144CodeLcblto2_FSBL_lto.o
LL_RCC_IC1_GetDivider0x34183F4D224CodeLcblto2_FSBL_lto.o
LL_RCC_IC1_GetSource0x341814B1164CodeLcblto2_FSBL_lto.o
LL_RCC_IC2_GetSource0x341814C1164CodeLcblto2_FSBL_lto.o
LL_RCC_IC6_GetSource0x341814D1164CodeLcblto2_FSBL_lto.o
LL_RCC_LSE_IsReady0x34181491164CodeLcblto2_FSBL_lto.o
LL_RCC_LSI_Disable0x34182F01144CodeLcblto2_FSBL_lto.o
LL_RCC_LSI_Enable0x34182EF1144CodeLcblto2_FSBL_lto.o
LL_RCC_LSI_IsReady0x34181481164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_Disable0x34182EE1144CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_Enable0x34182ED1144CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_GetFrequency0x34181899164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_IsReady0x34181471164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_IsReady.620x34181889164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_SetCalibTrimming0x34182EB1304CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_SetFrequency0x34181455284CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1P_IsEnabled0x341819E9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetFRACN0x34181A29164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetM0x34181A09164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetN0x34181A19164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetP10x34181A39164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetP20x34181A49164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetSource0x34181415164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetSource.710x341819F9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsEnabledBypass0x34181595164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsEnabledBypass.720x34181A59164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsReady0x341814A1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsReady.700x341819D9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2P_IsEnabled0x34181959164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetFRACN0x34181999164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetM0x34181979164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetN0x34181989164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetP10x341819A9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetP20x341819B9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetSource0x34181425164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetSource.680x34181969164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsEnabledBypass0x341815A5164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsEnabledBypass.690x341819C9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsReady0x341814F1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsReady.670x34181949164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3P_IsEnabled0x341818C9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetFRACN0x34181909164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetM0x341818E9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetN0x341818F9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetP10x34181919164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetP20x34181929164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetSource0x34181435164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetSource.650x341818D9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsEnabledBypass0x341815B5164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsEnabledBypass.660x34181939164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsReady0x34181501164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsReady.640x341818B9164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4P_IsEnabled0x341816D5164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetFRACN0x341817A1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetM0x34181781164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetN0x34181791164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetP10x341817B1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetP20x341817C1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetSource0x34181445164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetSource.580x341816E5164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsEnabledBypass0x341815C5164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsEnabledBypass.590x34181859164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsReady0x34181511164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsReady.570x341816C5164CodeLcblto2_FSBL_lto.o
LOCKUP_IRQHandler0x34181E3B2CodeWkstm32n657xx_Vectors.o
LPTIM1_IRQHandler0x3418421B2CodeWkstm32n657xx_Vectors.o
LPTIM2_IRQHandler0x3418421D2CodeWkstm32n657xx_Vectors.o
LPTIM3_IRQHandler0x3418421F2CodeWkstm32n657xx_Vectors.o
LPTIM4_IRQHandler0x341842212CodeWkstm32n657xx_Vectors.o
LPTIM5_IRQHandler0x341842232CodeWkstm32n657xx_Vectors.o
LPUART1_IRQHandler0x3418425D2CodeWkstm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandler0x341841812CodeWkstm32n657xx_Vectors.o
LTDC_LO_IRQHandler0x3418417F2CodeWkstm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandler0x3418428D2CodeWkstm32n657xx_Vectors.o
LTDC_UP_IRQHandler0x3418428B2CodeWkstm32n657xx_Vectors.o
MCE1_IRQHandler0x34183E4B2CodeWkstm32n657xx_Vectors.o
MCE2_IRQHandler0x34183E5B2CodeWkstm32n657xx_Vectors.o
MCE3_IRQHandler0x34183F4B2CodeWkstm32n657xx_Vectors.o
MCE4_IRQHandler0x34183F632CodeWkstm32n657xx_Vectors.o
MDF1_FLT0_IRQHandler0x341842272CodeWkstm32n657xx_Vectors.o
MDF1_FLT1_IRQHandler0x341842292CodeWkstm32n657xx_Vectors.o
MDF1_FLT2_IRQHandler0x3418422B2CodeWkstm32n657xx_Vectors.o
MDF1_FLT3_IRQHandler0x3418422D2CodeWkstm32n657xx_Vectors.o
MDF1_FLT4_IRQHandler0x3418422F2CodeWkstm32n657xx_Vectors.o
MDF1_FLT5_IRQHandler0x341842312CodeWkstm32n657xx_Vectors.o
MDIOS_IRQHandler0x341842812CodeWkstm32n657xx_Vectors.o
MX_GPIO_Init0x34181B114664CodeLcblto2_FSBL_lto.o
MemManage_Handler0x34181E5124CodeGbblto2_FSBL_lto.o
NMI_Handler0x34181E4924CodeGbblto2_FSBL_lto.o
NPU0_IRQHandler0x341841752CodeWkstm32n657xx_Vectors.o
NPU1_IRQHandler0x341841772CodeWkstm32n657xx_Vectors.o
NPU2_IRQHandler0x341841792CodeWkstm32n657xx_Vectors.o
NPU3_IRQHandler0x3418417B2CodeWkstm32n657xx_Vectors.o
NVIC_EncodePriority0x34180BCD1004CodeLcblto2_FSBL_lto.o
PAHB_ERR_IRQHandler0x341841732CodeWkstm32n657xx_Vectors.o
PKA_IRQHandler0x3418333B2CodeWkstm32n657xx_Vectors.o
PVD_PVM_IRQHandler0x34181CE32CodeWkstm32n657xx_Vectors.o
PendSV_Handler0x34181E6524CodeGbblto2_FSBL_lto.o
RCCEx_CalcPLLFreq0x341817D11364CodeLcblto2_FSBL_lto.o
RCCEx_GetPLLSourceFreq0x341816F51404CodeLcblto2_FSBL_lto.o
RCC_IC_CheckPLLSources0x34183D612344CodeLcblto2_FSBL_lto.o
RCC_IRQHandler0x34181D4B2CodeWkstm32n657xx_Vectors.o
RCC_PLL_Config0x34182FED8464CodeLcblto2_FSBL_lto.o
RCC_PLL_Enable0x3418333D944CodeLcblto2_FSBL_lto.o
RCC_PLL_IsNewConfig0x34182F112184CodeLcblto2_FSBL_lto.o
RCC_PLL_Source_IsReady0x34181521844CodeLcblto2_FSBL_lto.o
RCC_S_IRQHandler0x34181E672CodeWkstm32n657xx_Vectors.o
RIFSC_TAMPER_IRQHandler0x34181E5F2CodeWkstm32n657xx_Vectors.o
RNG_IRQHandler0x34183D5F2CodeWkstm32n657xx_Vectors.o
RTC_IRQHandler0x341820672CodeWkstm32n657xx_Vectors.o
RTC_S_IRQHandler0x34181E572CodeWkstm32n657xx_Vectors.o
Reset_Handler0x34181A7D4CodeGbSTM32N6xx_Startup.o
SAES_IRQHandler0x34182F0F2CodeWkstm32n657xx_Vectors.o
SAI1_A_IRQHandler0x341842332CodeWkstm32n657xx_Vectors.o
SAI1_B_IRQHandler0x341842352CodeWkstm32n657xx_Vectors.o
SAI2_A_IRQHandler0x341842372CodeWkstm32n657xx_Vectors.o
SAI2_B_IRQHandler0x341842392CodeWkstm32n657xx_Vectors.o
SDMMC1_IRQHandler0x341842672CodeWkstm32n657xx_Vectors.o
SDMMC2_IRQHandler0x341842692CodeWkstm32n657xx_Vectors.o
SPDIFRX_IRQHandler0x3418423B2CodeWkstm32n657xx_Vectors.o
SPI1_IRQHandler0x3418423D2CodeWkstm32n657xx_Vectors.o
SPI2_IRQHandler0x3418423F2CodeWkstm32n657xx_Vectors.o
SPI3_IRQHandler0x341842412CodeWkstm32n657xx_Vectors.o
SPI4_IRQHandler0x341842432CodeWkstm32n657xx_Vectors.o
SPI5_IRQHandler0x341842452CodeWkstm32n657xx_Vectors.o
SPI6_IRQHandler0x341842472CodeWkstm32n657xx_Vectors.o
SVC_Handler0x34181E5D24CodeGbblto2_FSBL_lto.o
SysTick_Config0x341821C1784CodeLcblto2_FSBL_lto.o
SysTick_Handler0x3418075984CodeGbblto2_FSBL_lto.o
SystemClock_Config0x34181D4D2384CodeLcblto2_FSBL_lto.o
SystemCoreClockUpdate0x341807618284CodeGbblto2_FSBL_lto.o
SystemInit0x34181E695104CodeGbblto2_FSBL_lto.o
TAMP_IRQHandler0x34181E5B2CodeWkstm32n657xx_Vectors.o
TCM_ECC_IRQHandler0x34181E4B2CodeWkstm32n657xx_Vectors.o
TIM10_IRQHandler0x341842092CodeWkstm32n657xx_Vectors.o
TIM11_IRQHandler0x3418420B2CodeWkstm32n657xx_Vectors.o
TIM12_IRQHandler0x3418420D2CodeWkstm32n657xx_Vectors.o
TIM13_IRQHandler0x3418420F2CodeWkstm32n657xx_Vectors.o
TIM14_IRQHandler0x341842112CodeWkstm32n657xx_Vectors.o
TIM15_IRQHandler0x341842132CodeWkstm32n657xx_Vectors.o
TIM16_IRQHandler0x341842152CodeWkstm32n657xx_Vectors.o
TIM17_IRQHandler0x341842172CodeWkstm32n657xx_Vectors.o
TIM18_IRQHandler0x341842192CodeWkstm32n657xx_Vectors.o
TIM1_BRK_IRQHandler0x341841EB2CodeWkstm32n657xx_Vectors.o
TIM1_CC_IRQHandler0x341841F12CodeWkstm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandler0x341841EF2CodeWkstm32n657xx_Vectors.o
TIM1_UP_IRQHandler0x341841ED2CodeWkstm32n657xx_Vectors.o
TIM2_IRQHandler0x341841F32CodeWkstm32n657xx_Vectors.o
TIM3_IRQHandler0x341841F52CodeWkstm32n657xx_Vectors.o
TIM4_IRQHandler0x341841F72CodeWkstm32n657xx_Vectors.o
TIM5_IRQHandler0x341841F92CodeWkstm32n657xx_Vectors.o
TIM6_IRQHandler0x341841FB2CodeWkstm32n657xx_Vectors.o
TIM7_IRQHandler0x341841FD2CodeWkstm32n657xx_Vectors.o
TIM8_BRK_IRQHandler0x341841FF2CodeWkstm32n657xx_Vectors.o
TIM8_CC_IRQHandler0x341842052CodeWkstm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandler0x341842032CodeWkstm32n657xx_Vectors.o
TIM8_UP_IRQHandler0x341842012CodeWkstm32n657xx_Vectors.o
TIM9_IRQHandler0x341842072CodeWkstm32n657xx_Vectors.o
UART4_IRQHandler0x3418424F2CodeWkstm32n657xx_Vectors.o
UART5_IRQHandler0x341842512CodeWkstm32n657xx_Vectors.o
UART7_IRQHandler0x341842552CodeWkstm32n657xx_Vectors.o
UART8_IRQHandler0x341842572CodeWkstm32n657xx_Vectors.o
UART9_IRQHandler0x341842592CodeWkstm32n657xx_Vectors.o
UCPD1_IRQHandler0x3418426B2CodeWkstm32n657xx_Vectors.o
USART10_IRQHandler0x3418425B2CodeWkstm32n657xx_Vectors.o
USART1_IRQHandler0x341842492CodeWkstm32n657xx_Vectors.o
USART2_IRQHandler0x3418424B2CodeWkstm32n657xx_Vectors.o
USART3_IRQHandler0x3418424D2CodeWkstm32n657xx_Vectors.o
USART6_IRQHandler0x341842532CodeWkstm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandler0x3418426D2CodeWkstm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandler0x3418426F2CodeWkstm32n657xx_Vectors.o
UsageFault_Handler0x34181E5924CodeGbblto2_FSBL_lto.o
VENC_IRQHandler0x341841872CodeWkstm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandler0x341842852CodeWkstm32n657xx_Vectors.o
WWDG_IRQHandler0x341821032CodeWkstm32n657xx_Vectors.o
XSPI1_IRQHandler0x3418425F2CodeWkstm32n657xx_Vectors.o
XSPI2_IRQHandler0x341842612CodeWkstm32n657xx_Vectors.o
XSPI3_IRQHandler0x341842632CodeWkstm32n657xx_Vectors.o
__NVIC_GetPriorityGrouping0x34180BBD164CodeLcblto2_FSBL_lto.o
__NVIC_SetPriority0x34182181624CodeLcblto2_FSBL_lto.o
__NVIC_SetPriorityGrouping0x34180AD9604CodeLcblto2_FSBL_lto.o
__SEGGER_init_copy0x341844C3202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_ctors0x3418444D264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_done0x34181A734CodeGbSEGGER_THUMB_Startup.o
__SEGGER_init_zero0x341844B1182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr0x34181AA91044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr40x34181AA94CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr80x34181AA94CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset0x34181AAB4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset40x34181AAB4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset80x34181AAB4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__startup_complete0x34181A734CodeGbSEGGER_THUMB_Startup.o
_start0x34181A69144CodeGbSEGGER_THUMB_Startup.o
assert_failed0x34181E3D104CodeLcblto2_FSBL_lto.o
exit0x34181A7724CodeGbSEGGER_THUMB_Startup.o
main0x34181D09664CodeGbblto2_FSBL_lto.o
memset0x34181AB14CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
reset_handler0x34181A7D4CodeGbSTM32N6xx_Startup.o
+

Function symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
0x3418074DError_Handler44CodeLcblto2_FSBL_lto.o
0x34180751HAL_MspInit84CodeLcblto2_FSBL_lto.o
0x34180759SysTick_Handler84CodeGbblto2_FSBL_lto.o
0x34180761SystemCoreClockUpdate8284CodeGbblto2_FSBL_lto.o
0x34180A9DHAL_Init484CodeLcblto2_FSBL_lto.o
0x34180ACDHAL_GetTick124CodeLcblto2_FSBL_lto.o
0x34180AD9__NVIC_SetPriorityGrouping604CodeLcblto2_FSBL_lto.o
0x34180B15HAL_NVIC_SetPriority1684CodeLcblto2_FSBL_lto.o
0x34180BBD__NVIC_GetPriorityGrouping164CodeLcblto2_FSBL_lto.o
0x34180BCDNVIC_EncodePriority1004CodeLcblto2_FSBL_lto.o
0x34180C31HAL_SYSTICK_Config164CodeLcblto2_FSBL_lto.o
0x34180C41HAL_GPIO_Init1 9284CodeLcblto2_FSBL_lto.o
0x341813C9LL_RCC_HSI_SetDivider284CodeLcblto2_FSBL_lto.o
0x341813E5LL_RCC_HSI_IsReady164CodeLcblto2_FSBL_lto.o
0x341813F5LL_RCC_GetCpuClkSource164CodeLcblto2_FSBL_lto.o
0x34181405LL_RCC_GetSysClkSource164CodeLcblto2_FSBL_lto.o
0x34181415LL_RCC_PLL1_GetSource164CodeLcblto2_FSBL_lto.o
0x34181425LL_RCC_PLL2_GetSource164CodeLcblto2_FSBL_lto.o
0x34181435LL_RCC_PLL3_GetSource164CodeLcblto2_FSBL_lto.o
0x34181445LL_RCC_PLL4_GetSource164CodeLcblto2_FSBL_lto.o
0x34181455LL_RCC_MSI_SetFrequency284CodeLcblto2_FSBL_lto.o
0x34181471LL_RCC_MSI_IsReady164CodeLcblto2_FSBL_lto.o
0x34181481LL_RCC_LSI_IsReady164CodeLcblto2_FSBL_lto.o
0x34181491LL_RCC_LSE_IsReady164CodeLcblto2_FSBL_lto.o
0x341814A1LL_RCC_PLL1_IsReady164CodeLcblto2_FSBL_lto.o
0x341814B1LL_RCC_IC1_GetSource164CodeLcblto2_FSBL_lto.o
0x341814C1LL_RCC_IC2_GetSource164CodeLcblto2_FSBL_lto.o
0x341814D1LL_RCC_IC6_GetSource164CodeLcblto2_FSBL_lto.o
0x341814E1LL_RCC_IC11_GetSource164CodeLcblto2_FSBL_lto.o
0x341814F1LL_RCC_PLL2_IsReady164CodeLcblto2_FSBL_lto.o
0x34181501LL_RCC_PLL3_IsReady164CodeLcblto2_FSBL_lto.o
0x34181511LL_RCC_PLL4_IsReady164CodeLcblto2_FSBL_lto.o
0x34181521RCC_PLL_Source_IsReady844CodeLcblto2_FSBL_lto.o
0x34181575LL_RCC_HSE_IsReady164CodeLcblto2_FSBL_lto.o
0x34181585LL_RCC_HSI_GetDivider164CodeLcblto2_FSBL_lto.o
0x34181595LL_RCC_PLL1_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
0x341815A5LL_RCC_PLL2_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
0x341815B5LL_RCC_PLL3_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
0x341815C5LL_RCC_PLL4_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
0x341815D5HAL_RCC_GetClockConfig2404CodeLcblto2_FSBL_lto.o
0x341816C5LL_RCC_PLL4_IsReady.57164CodeLcblto2_FSBL_lto.o
0x341816D5LL_RCC_PLL4P_IsEnabled164CodeLcblto2_FSBL_lto.o
0x341816E5LL_RCC_PLL4_GetSource.58164CodeLcblto2_FSBL_lto.o
0x341816F5RCCEx_GetPLLSourceFreq1404CodeLcblto2_FSBL_lto.o
0x34181781LL_RCC_PLL4_GetM164CodeLcblto2_FSBL_lto.o
0x34181791LL_RCC_PLL4_GetN164CodeLcblto2_FSBL_lto.o
0x341817A1LL_RCC_PLL4_GetFRACN164CodeLcblto2_FSBL_lto.o
0x341817B1LL_RCC_PLL4_GetP1164CodeLcblto2_FSBL_lto.o
0x341817C1LL_RCC_PLL4_GetP2164CodeLcblto2_FSBL_lto.o
0x341817D1RCCEx_CalcPLLFreq1364CodeLcblto2_FSBL_lto.o
0x34181859LL_RCC_PLL4_IsEnabledBypass.59164CodeLcblto2_FSBL_lto.o
0x34181869LL_RCC_HSI_IsReady.60164CodeLcblto2_FSBL_lto.o
0x34181879LL_RCC_HSI_GetDivider.61164CodeLcblto2_FSBL_lto.o
0x34181889LL_RCC_MSI_IsReady.62164CodeLcblto2_FSBL_lto.o
0x34181899LL_RCC_MSI_GetFrequency164CodeLcblto2_FSBL_lto.o
0x341818A9LL_RCC_HSE_IsReady.63164CodeLcblto2_FSBL_lto.o
0x341818B9LL_RCC_PLL3_IsReady.64164CodeLcblto2_FSBL_lto.o
0x341818C9LL_RCC_PLL3P_IsEnabled164CodeLcblto2_FSBL_lto.o
0x341818D9LL_RCC_PLL3_GetSource.65164CodeLcblto2_FSBL_lto.o
0x341818E9LL_RCC_PLL3_GetM164CodeLcblto2_FSBL_lto.o
0x341818F9LL_RCC_PLL3_GetN164CodeLcblto2_FSBL_lto.o
0x34181909LL_RCC_PLL3_GetFRACN164CodeLcblto2_FSBL_lto.o
0x34181919LL_RCC_PLL3_GetP1164CodeLcblto2_FSBL_lto.o
0x34181929LL_RCC_PLL3_GetP2164CodeLcblto2_FSBL_lto.o
0x34181939LL_RCC_PLL3_IsEnabledBypass.66164CodeLcblto2_FSBL_lto.o
0x34181949LL_RCC_PLL2_IsReady.67164CodeLcblto2_FSBL_lto.o
0x34181959LL_RCC_PLL2P_IsEnabled164CodeLcblto2_FSBL_lto.o
0x34181969LL_RCC_PLL2_GetSource.68164CodeLcblto2_FSBL_lto.o
0x34181979LL_RCC_PLL2_GetM164CodeLcblto2_FSBL_lto.o
0x34181989LL_RCC_PLL2_GetN164CodeLcblto2_FSBL_lto.o
0x34181999LL_RCC_PLL2_GetFRACN164CodeLcblto2_FSBL_lto.o
0x341819A9LL_RCC_PLL2_GetP1164CodeLcblto2_FSBL_lto.o
0x341819B9LL_RCC_PLL2_GetP2164CodeLcblto2_FSBL_lto.o
0x341819C9LL_RCC_PLL2_IsEnabledBypass.69164CodeLcblto2_FSBL_lto.o
0x341819D9LL_RCC_PLL1_IsReady.70164CodeLcblto2_FSBL_lto.o
0x341819E9LL_RCC_PLL1P_IsEnabled164CodeLcblto2_FSBL_lto.o
0x341819F9LL_RCC_PLL1_GetSource.71164CodeLcblto2_FSBL_lto.o
0x34181A09LL_RCC_PLL1_GetM164CodeLcblto2_FSBL_lto.o
0x34181A19LL_RCC_PLL1_GetN164CodeLcblto2_FSBL_lto.o
0x34181A29LL_RCC_PLL1_GetFRACN164CodeLcblto2_FSBL_lto.o
0x34181A39LL_RCC_PLL1_GetP1164CodeLcblto2_FSBL_lto.o
0x34181A49LL_RCC_PLL1_GetP2164CodeLcblto2_FSBL_lto.o
0x34181A59LL_RCC_PLL1_IsEnabledBypass.72164CodeLcblto2_FSBL_lto.o
0x34181A69_start144CodeGbSEGGER_THUMB_Startup.o
0x34181A73__startup_complete4CodeGbSEGGER_THUMB_Startup.o
0x34181A73__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
0x34181A77exit24CodeGbSEGGER_THUMB_Startup.o
0x34181A7Dreset_handler4CodeGbSTM32N6xx_Startup.o
0x34181A7DReset_Handler4CodeGbSTM32N6xx_Startup.o
0x34181AA9__aeabi_memclr84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181AA9__aeabi_memclr44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181AA9__aeabi_memclr1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181AAB__aeabi_memset84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181AAB__aeabi_memset44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181AAB__aeabi_memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181AB1memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181B11MX_GPIO_Init4664CodeLcblto2_FSBL_lto.o
0x34181CE3PVD_PVM_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181CE5LL_AHB4_GRP1_EnableClock344CodeLcblto2_FSBL_lto.o
0x34181D07DTS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181D09main664CodeGbblto2_FSBL_lto.o
0x34181D4BRCC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181D4DSystemClock_Config2384CodeLcblto2_FSBL_lto.o
0x34181E3BLOCKUP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E3Dassert_failed104CodeLcblto2_FSBL_lto.o
0x34181E47CACHE_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E49NMI_Handler24CodeGbblto2_FSBL_lto.o
0x34181E4BTCM_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E4DHardFault_Handler24CodeGbblto2_FSBL_lto.o
0x34181E4FBCK_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E51MemManage_Handler24CodeGbblto2_FSBL_lto.o
0x34181E53FPU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E55BusFault_Handler24CodeGbblto2_FSBL_lto.o
0x34181E57RTC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E59UsageFault_Handler24CodeGbblto2_FSBL_lto.o
0x34181E5BTAMP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E5DSVC_Handler24CodeGbblto2_FSBL_lto.o
0x34181E5FRIFSC_TAMPER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E61DebugMon_Handler24CodeGbblto2_FSBL_lto.o
0x34181E63IAC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E65PendSV_Handler24CodeGbblto2_FSBL_lto.o
0x34181E67RCC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181E69SystemInit5104CodeGbblto2_FSBL_lto.o
0x34182067RTC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182069HAL_InitTick1264CodeLcblto2_FSBL_lto.o
0x341820E7IWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341820E9HAL_IncTick264CodeLcblto2_FSBL_lto.o
0x34182103WWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182105HAL_Delay584CodeLcblto2_FSBL_lto.o
0x3418213FEXTI0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182141HAL_NVIC_SetPriorityGrouping624CodeLcblto2_FSBL_lto.o
0x3418217FEXTI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182181__NVIC_SetPriority624CodeLcblto2_FSBL_lto.o
0x341821BFEXTI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821C1SysTick_Config784CodeLcblto2_FSBL_lto.o
0x3418220FEXTI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182211HAL_GPIO_WritePin1024CodeLcblto2_FSBL_lto.o
0x34182277EXTI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182279HAL_PWREx_ConfigSupply1144CodeLcblto2_FSBL_lto.o
0x341822EBEXTI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341822EDHAL_PWREx_ControlVoltageScaling1144CodeLcblto2_FSBL_lto.o
0x3418235FEXTI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182361HAL_PWREx_EnableVddIO3184CodeLcblto2_FSBL_lto.o
0x34182373EXTI7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182375LL_RCC_HSI_Enable144CodeLcblto2_FSBL_lto.o
0x34182383EXTI8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182385HAL_RCC_OscConfig2 8104CodeLcblto2_FSBL_lto.o
0x34182E7FEXTI9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182E81LL_RCC_HSI_SetCalibTrimming304CodeLcblto2_FSBL_lto.o
0x34182E9FEXTI10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182EA1LL_RCC_HSI_Disable144CodeLcblto2_FSBL_lto.o
0x34182EAFEXTI11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182EB1LL_RCC_MSI_SetCalibTrimming304CodeLcblto2_FSBL_lto.o
0x34182ECFEXTI12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182ED1LL_RCC_MSI_Enable144CodeLcblto2_FSBL_lto.o
0x34182EDFEXTI13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182EE1LL_RCC_MSI_Disable144CodeLcblto2_FSBL_lto.o
0x34182EEFEXTI14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182EF1LL_RCC_LSI_Enable144CodeLcblto2_FSBL_lto.o
0x34182EFFEXTI15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182F01LL_RCC_LSI_Disable144CodeLcblto2_FSBL_lto.o
0x34182F0FSAES_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182F11RCC_PLL_IsNewConfig2184CodeLcblto2_FSBL_lto.o
0x34182FEBCRYP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182FEDRCC_PLL_Config8464CodeLcblto2_FSBL_lto.o
0x3418333BPKA_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418333DRCC_PLL_Enable944CodeLcblto2_FSBL_lto.o
0x3418339BHASH_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418339DHAL_RCC_ClockConfig2 4984CodeLcblto2_FSBL_lto.o
0x34183D5FRNG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34183D61RCC_IC_CheckPLLSources2344CodeLcblto2_FSBL_lto.o
0x34183E4BMCE1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34183E4DLL_RCC_IC1_Enable144CodeLcblto2_FSBL_lto.o
0x34183E5BMCE2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34183E5DHAL_RCC_GetCpuClockFreq2384CodeLcblto2_FSBL_lto.o
0x34183F4BMCE3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34183F4DLL_RCC_IC1_GetDivider224CodeLcblto2_FSBL_lto.o
0x34183F63MCE4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34183F65HAL_RCCEx_GetPLL1CLKFreq1304CodeLcblto2_FSBL_lto.o
0x34183FE7ADC1_2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34183FE9HAL_RCCEx_GetPLL2CLKFreq1304CodeLcblto2_FSBL_lto.o
0x3418406BCSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418406DHAL_RCCEx_GetPLL3CLKFreq1304CodeLcblto2_FSBL_lto.o
0x341840EFDCMIPP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341840F1HAL_RCCEx_GetPLL4CLKFreq1304CodeLcblto2_FSBL_lto.o
0x34184173PAHB_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184175NPU0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184177NPU1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184179NPU2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418417BNPU3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418417DCACHEAXI_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418417FLTDC_LO_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184181LTDC_LO_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184183DMA2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184185JPEG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184187VENC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184189GFXMMU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418418BGFXTIM_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418418DGPU2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418418FGPU2D_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184191ICACHE_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184193HPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184195HPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184197HPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184199HPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418419BHPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418419DHPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418419FHPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841A1HPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841A3HPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841A5HPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841A7HPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841A9HPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841ABHPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841ADHPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841AFHPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841B1HPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841B3GPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841B5GPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841B7GPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841B9GPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841BBGPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841BDGPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841BFGPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841C1GPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841C3GPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841C5GPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841C7GPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841C9GPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841CBGPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841CDGPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841CFGPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841D1GPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841D3I2C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841D5I2C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841D7I2C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841D9I2C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841DBI2C3_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841DDI2C3_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841DFI2C4_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841E1I2C4_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841E3I3C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841E5I3C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841E7I3C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841E9I3C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841EBTIM1_BRK_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841EDTIM1_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841EFTIM1_TRG_CCU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841F1TIM1_CC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841F3TIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841F5TIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841F7TIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841F9TIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841FBTIM6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841FDTIM7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341841FFTIM8_BRK_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184201TIM8_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184203TIM8_TRG_CCU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184205TIM8_CC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184207TIM9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184209TIM10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418420BTIM11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418420DTIM12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418420FTIM13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184211TIM14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184213TIM15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184215TIM16_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184217TIM17_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184219TIM18_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418421BLPTIM1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418421DLPTIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418421FLPTIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184221LPTIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184223LPTIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184225ADF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184227MDF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184229MDF1_FLT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418422BMDF1_FLT2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418422DMDF1_FLT3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418422FMDF1_FLT4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184231MDF1_FLT5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184233SAI1_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184235SAI1_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184237SAI2_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184239SAI2_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418423BSPDIFRX_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418423DSPI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418423FSPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184241SPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184243SPI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184245SPI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184247SPI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184249USART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418424BUSART2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418424DUSART3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418424FUART4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184251UART5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184253USART6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184255UART7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184257UART8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184259UART9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418425BUSART10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418425DLPUART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418425FXSPI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184261XSPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184263XSPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184265FMC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184267SDMMC1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184269SDMMC2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418426BUCPD1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418426DUSB1_OTG_HS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418426FUSB2_OTG_HS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184271ETH1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184273FDCAN1_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184275FDCAN1_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184277FDCAN2_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184279FDCAN2_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418427BFDCAN3_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418427DFDCAN3_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418427FFDCAN_CU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184281MDIOS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184283DCMI_PSSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184285WAKEUP_PIN_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184287CTI_INT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34184289CTI_INT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418428BLTDC_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418428DLTDC_UP_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418444D__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341844B1__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341844C3__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
+

Function symbols by descending size

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameSizeAlignTypeBdObject File
HAL_RCC_OscConfig2 8104CodeLcblto2_FSBL_lto.o
HAL_RCC_ClockConfig2 4984CodeLcblto2_FSBL_lto.o
HAL_GPIO_Init1 9284CodeLcblto2_FSBL_lto.o
RCC_PLL_Config8464CodeLcblto2_FSBL_lto.o
SystemCoreClockUpdate8284CodeGbblto2_FSBL_lto.o
SystemInit5104CodeGbblto2_FSBL_lto.o
MX_GPIO_Init4664CodeLcblto2_FSBL_lto.o
HAL_RCC_GetClockConfig2404CodeLcblto2_FSBL_lto.o
HAL_RCC_GetCpuClockFreq2384CodeLcblto2_FSBL_lto.o
SystemClock_Config2384CodeLcblto2_FSBL_lto.o
RCC_IC_CheckPLLSources2344CodeLcblto2_FSBL_lto.o
RCC_PLL_IsNewConfig2184CodeLcblto2_FSBL_lto.o
HAL_NVIC_SetPriority1684CodeLcblto2_FSBL_lto.o
RCCEx_GetPLLSourceFreq1404CodeLcblto2_FSBL_lto.o
RCCEx_CalcPLLFreq1364CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL1CLKFreq1304CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL2CLKFreq1304CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL3CLKFreq1304CodeLcblto2_FSBL_lto.o
HAL_RCCEx_GetPLL4CLKFreq1304CodeLcblto2_FSBL_lto.o
HAL_InitTick1264CodeLcblto2_FSBL_lto.o
HAL_PWREx_ConfigSupply1144CodeLcblto2_FSBL_lto.o
HAL_PWREx_ControlVoltageScaling1144CodeLcblto2_FSBL_lto.o
__aeabi_memclr1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
HAL_GPIO_WritePin1024CodeLcblto2_FSBL_lto.o
NVIC_EncodePriority1004CodeLcblto2_FSBL_lto.o
RCC_PLL_Enable944CodeLcblto2_FSBL_lto.o
RCC_PLL_Source_IsReady844CodeLcblto2_FSBL_lto.o
SysTick_Config784CodeLcblto2_FSBL_lto.o
main664CodeGbblto2_FSBL_lto.o
HAL_NVIC_SetPriorityGrouping624CodeLcblto2_FSBL_lto.o
__NVIC_SetPriority624CodeLcblto2_FSBL_lto.o
__NVIC_SetPriorityGrouping604CodeLcblto2_FSBL_lto.o
HAL_Delay584CodeLcblto2_FSBL_lto.o
HAL_Init484CodeLcblto2_FSBL_lto.o
LL_AHB4_GRP1_EnableClock344CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_SetCalibTrimming304CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_SetCalibTrimming304CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_SetDivider284CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_SetFrequency284CodeLcblto2_FSBL_lto.o
HAL_IncTick264CodeLcblto2_FSBL_lto.o
__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
LL_RCC_IC1_GetDivider224CodeLcblto2_FSBL_lto.o
__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
HAL_PWREx_EnableVddIO3184CodeLcblto2_FSBL_lto.o
__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
HAL_SYSTICK_Config164CodeLcblto2_FSBL_lto.o
LL_RCC_GetCpuClkSource164CodeLcblto2_FSBL_lto.o
LL_RCC_GetSysClkSource164CodeLcblto2_FSBL_lto.o
LL_RCC_HSE_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_HSE_IsReady.63164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_GetDivider164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_GetDivider.61164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_IsReady.60164CodeLcblto2_FSBL_lto.o
LL_RCC_IC11_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_IC1_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_IC2_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_IC6_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_LSE_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_LSI_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_GetFrequency164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_IsReady.62164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1P_IsEnabled164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetFRACN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetM164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetP1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetP2164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_GetSource.71164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsEnabledBypass.72164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL1_IsReady.70164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2P_IsEnabled164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetFRACN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetM164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetP1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetP2164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_GetSource.68164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsEnabledBypass.69164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL2_IsReady.67164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3P_IsEnabled164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetFRACN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetM164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetP1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetP2164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_GetSource.65164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsEnabledBypass.66164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL3_IsReady.64164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4P_IsEnabled164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetFRACN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetM164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetN164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetP1164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetP2164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetSource164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_GetSource.58164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsEnabledBypass164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsEnabledBypass.59164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsReady164CodeLcblto2_FSBL_lto.o
LL_RCC_PLL4_IsReady.57164CodeLcblto2_FSBL_lto.o
__NVIC_GetPriorityGrouping164CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_Disable144CodeLcblto2_FSBL_lto.o
LL_RCC_HSI_Enable144CodeLcblto2_FSBL_lto.o
LL_RCC_IC1_Enable144CodeLcblto2_FSBL_lto.o
LL_RCC_LSI_Disable144CodeLcblto2_FSBL_lto.o
LL_RCC_LSI_Enable144CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_Disable144CodeLcblto2_FSBL_lto.o
LL_RCC_MSI_Enable144CodeLcblto2_FSBL_lto.o
_start144CodeGbSEGGER_THUMB_Startup.o
HAL_GetTick124CodeLcblto2_FSBL_lto.o
assert_failed104CodeLcblto2_FSBL_lto.o
HAL_MspInit84CodeLcblto2_FSBL_lto.o
SysTick_Handler84CodeGbblto2_FSBL_lto.o
Error_Handler44CodeLcblto2_FSBL_lto.o
BusFault_Handler24CodeGbblto2_FSBL_lto.o
DebugMon_Handler24CodeGbblto2_FSBL_lto.o
HardFault_Handler24CodeGbblto2_FSBL_lto.o
MemManage_Handler24CodeGbblto2_FSBL_lto.o
NMI_Handler24CodeGbblto2_FSBL_lto.o
PendSV_Handler24CodeGbblto2_FSBL_lto.o
SVC_Handler24CodeGbblto2_FSBL_lto.o
UsageFault_Handler24CodeGbblto2_FSBL_lto.o
exit24CodeGbSEGGER_THUMB_Startup.o
ADC1_2_IRQHandler2CodeWkstm32n657xx_Vectors.o
ADF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
BCK_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
CACHEAXI_IRQHandler2CodeWkstm32n657xx_Vectors.o
CACHE_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
CRYP_IRQHandler2CodeWkstm32n657xx_Vectors.o
CSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
CTI_INT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
CTI_INT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
DCMIPP_IRQHandler2CodeWkstm32n657xx_Vectors.o
DCMI_PSSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
DMA2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
DTS_IRQHandler2CodeWkstm32n657xx_Vectors.o
ETH1_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI0_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI10_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI11_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI12_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI13_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI14_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI15_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI7_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI8_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI9_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN_CU_IRQHandler2CodeWkstm32n657xx_Vectors.o
FMC_IRQHandler2CodeWkstm32n657xx_Vectors.o
FPU_IRQHandler2CodeWkstm32n657xx_Vectors.o
GFXMMU_IRQHandler2CodeWkstm32n657xx_Vectors.o
GFXTIM_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPU2D_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPU2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
HASH_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C3_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C3_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C4_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C4_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
IAC_IRQHandler2CodeWkstm32n657xx_Vectors.o
ICACHE_IRQHandler2CodeWkstm32n657xx_Vectors.o
IWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
JPEG_IRQHandler2CodeWkstm32n657xx_Vectors.o
LOCKUP_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM1_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPUART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_LO_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE1_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE2_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE3_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE4_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT2_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT3_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT4_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT5_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDIOS_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU0_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU1_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU2_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU3_IRQHandler2CodeWkstm32n657xx_Vectors.o
PAHB_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
PKA_IRQHandler2CodeWkstm32n657xx_Vectors.o
PVD_PVM_IRQHandler2CodeWkstm32n657xx_Vectors.o
RCC_IRQHandler2CodeWkstm32n657xx_Vectors.o
RCC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
RIFSC_TAMPER_IRQHandler2CodeWkstm32n657xx_Vectors.o
RNG_IRQHandler2CodeWkstm32n657xx_Vectors.o
RTC_IRQHandler2CodeWkstm32n657xx_Vectors.o
RTC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
Reset_Handler4CodeGbSTM32N6xx_Startup.o
SAES_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI1_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI1_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI2_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI2_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
SDMMC1_IRQHandler2CodeWkstm32n657xx_Vectors.o
SDMMC2_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPDIFRX_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
TAMP_IRQHandler2CodeWkstm32n657xx_Vectors.o
TCM_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM10_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM11_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM12_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM13_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM14_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM15_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM16_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM17_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM18_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM1_BRK_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM1_CC_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM1_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM6_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM7_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM8_BRK_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM8_CC_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM8_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM9_IRQHandler2CodeWkstm32n657xx_Vectors.o
UART4_IRQHandler2CodeWkstm32n657xx_Vectors.o
UART5_IRQHandler2CodeWkstm32n657xx_Vectors.o
UART7_IRQHandler2CodeWkstm32n657xx_Vectors.o
UART8_IRQHandler2CodeWkstm32n657xx_Vectors.o
UART9_IRQHandler2CodeWkstm32n657xx_Vectors.o
UCPD1_IRQHandler2CodeWkstm32n657xx_Vectors.o
USART10_IRQHandler2CodeWkstm32n657xx_Vectors.o
USART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
USART2_IRQHandler2CodeWkstm32n657xx_Vectors.o
USART3_IRQHandler2CodeWkstm32n657xx_Vectors.o
USART6_IRQHandler2CodeWkstm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandler2CodeWkstm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandler2CodeWkstm32n657xx_Vectors.o
VENC_IRQHandler2CodeWkstm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandler2CodeWkstm32n657xx_Vectors.o
WWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
XSPI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
XSPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
XSPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
__aeabi_memclr44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__startup_complete4CodeGbSEGGER_THUMB_Startup.o
memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
reset_handler4CodeGbSTM32N6xx_Startup.o
+

Read-write data symbols by name

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SystemCoreClock0x3418444844InitLcblto2_FSBL_lto.o
uwTick0x3418444044ZeroLcblto2_FSBL_lto.o
uwTickFreq0x341843611InitLcblto2_FSBL_lto.o
uwTickPrio0x3418444444InitLcblto2_FSBL_lto.o
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Read-write data symbols by address

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0x34184361uwTickFreq1InitLcblto2_FSBL_lto.o
0x34184440uwTick44ZeroLcblto2_FSBL_lto.o
0x34184444uwTickPrio44InitLcblto2_FSBL_lto.o
0x34184448SystemCoreClock44InitLcblto2_FSBL_lto.o
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Read-write data symbols by descending size

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SystemCoreClock44InitLcblto2_FSBL_lto.o
uwTick44ZeroLcblto2_FSBL_lto.o
uwTickPrio44InitLcblto2_FSBL_lto.o
uwTickFreq1InitLcblto2_FSBL_lto.o
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Read-only data symbols by name

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Symbol nameAddressSizeAlignTypeBdObject File
__SEGGER_init_data__0x341844A4[12]4CnstLc[ Linker created ]
__SEGGER_init_table__0x34184470[52]4CnstLc[ Linker created ]
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Read-only data symbols by address

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0x34184470__SEGGER_init_table__[52]4CnstLc[ Linker created ]
0x341844A4__SEGGER_init_data__[12]4CnstLc[ Linker created ]
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Untyped symbols by name

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Symbol nameValueSizeAlignTypeBdObject File
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Untyped symbols by address

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+

REGION LIST

+

Regions by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSize
AHB_RAM138000000-38003FFF16 384
AHB_RAM238004000-38007FFF16 384
AXI_RAM134064000-340FFFFF638 976
AXI_RAM234180400-341FFFFF523 264
AXI_RAM334200000-3426FFFF458 752
AXI_RAM434270000-342DFFFF458 752
AXI_RAM5342E0000-3434FFFF458 752
AXI_RAM634350000-343BFFFF458 752
AXI_RAM7343C0000-343FFFFF262 144
AXI_RAM834400000-3441FFFF131 072
BKP_RAM3C000000-3C001FFF8 192
DTCM_RAM30000000-3001FFFF131 072
FLEX_RAM34000000-34063FFF409 600
ITCM_RAM10000000-1000FFFF65 536
RAM34180400-341FFFFF523 264
+

Analysis

+ +AXI_RAM2: + Identical to region RAM + +RAM: + Identical to region AXI_RAM2 +

BLOCK LIST

+

Blocks by name

+ + + + + + + + + + + + + + + + + + + + +
NameRangeSizeOrdering
ctors34184364-341843674Auto
stack341FC000-341FFFFF16 384Auto
+

Blocks by address

+ + + + + + + + + + + + + + + + + + + + +
RangeSizeNameOrdering
34184364-341843674ctorsAuto
341FC000-341FFFFF16 384stackAuto
+

STACK SIZES

+

Functions by stack size

+ + + + + + + +
Function nameStackObject File
+

Functions without stack size information

+ + MX_GPIO_Init + LL_AHB4_GRP1_EnableClock + HAL_GPIO_WritePin + HAL_GPIO_Init + HAL_Init + SystemClock_Config + HAL_Delay + HAL_PWREx_ConfigSupply + Error_Handler + HAL_PWREx_ControlVoltageScaling + HAL_RCC_OscConfig + HAL_RCC_GetClockConfig + HAL_RCC_ClockConfig + assert_failed + HAL_MspInit + HAL_PWREx_EnableVddIO3 + HAL_IncTick + HAL_NVIC_SetPriorityGrouping + HAL_InitTick + HAL_SYSTICK_Config + HAL_NVIC_SetPriority + HAL_GetTick + __NVIC_SetPriorityGrouping + __NVIC_GetPriorityGrouping + NVIC_EncodePriority + __NVIC_SetPriority + SysTick_Config + LL_RCC_HSI_SetDivider + LL_RCC_HSI_Enable + LL_RCC_HSI_IsReady + LL_RCC_GetCpuClkSource + LL_RCC_GetSysClkSource + LL_RCC_PLL1_GetSource + LL_RCC_PLL2_GetSource + LL_RCC_PLL3_GetSource + LL_RCC_PLL4_GetSource + LL_RCC_HSI_SetCalibTrimming + LL_RCC_HSI_Disable + LL_RCC_MSI_SetCalibTrimming + LL_RCC_MSI_SetFrequency + LL_RCC_MSI_Enable + LL_RCC_MSI_IsReady + LL_RCC_MSI_Disable + LL_RCC_LSI_Enable + LL_RCC_LSI_IsReady + LL_RCC_LSI_Disable + LL_RCC_LSE_IsReady + RCC_PLL_IsNewConfig + LL_RCC_PLL1_IsReady + LL_RCC_IC1_GetSource + LL_RCC_IC2_GetSource + LL_RCC_IC6_GetSource + LL_RCC_IC11_GetSource + RCC_PLL_Config + RCC_PLL_Enable + LL_RCC_PLL2_IsReady + LL_RCC_PLL3_IsReady + LL_RCC_PLL4_IsReady + RCC_PLL_Source_IsReady + LL_RCC_HSE_IsReady + RCC_IC_CheckPLLSources + LL_RCC_IC1_Enable + HAL_RCC_GetCpuClockFreq + LL_RCC_PLL1_IsEnabledBypass + LL_RCC_PLL2_IsEnabledBypass + LL_RCC_PLL3_IsEnabledBypass + LL_RCC_PLL4_IsEnabledBypass + LL_RCC_HSI_GetDivider + LL_RCC_IC1_GetDivider + HAL_RCCEx_GetPLL1CLKFreq + HAL_RCCEx_GetPLL2CLKFreq + HAL_RCCEx_GetPLL3CLKFreq + HAL_RCCEx_GetPLL4CLKFreq + LL_RCC_HSI_IsReady.60 + LL_RCC_HSI_GetDivider.61 + LL_RCC_MSI_IsReady.62 + LL_RCC_HSE_IsReady.63 + LL_RCC_PLL1_IsReady.70 + LL_RCC_PLL1P_IsEnabled + LL_RCC_PLL1_GetSource.71 + RCCEx_GetPLLSourceFreq + LL_RCC_PLL1_GetM + LL_RCC_PLL1_GetN + LL_RCC_PLL1_GetFRACN + LL_RCC_PLL1_GetP1 + LL_RCC_PLL1_GetP2 + RCCEx_CalcPLLFreq + LL_RCC_PLL1_IsEnabledBypass.72 + LL_RCC_PLL2_IsReady.67 + LL_RCC_PLL2P_IsEnabled + LL_RCC_PLL2_GetSource.68 + LL_RCC_PLL2_GetM + LL_RCC_PLL2_GetN + LL_RCC_PLL2_GetFRACN + LL_RCC_PLL2_GetP1 + LL_RCC_PLL2_GetP2 + LL_RCC_PLL2_IsEnabledBypass.69 + LL_RCC_PLL3_IsReady.64 + LL_RCC_PLL3P_IsEnabled + LL_RCC_PLL3_GetSource.65 + LL_RCC_PLL3_GetM + LL_RCC_PLL3_GetN + LL_RCC_PLL3_GetFRACN + LL_RCC_PLL3_GetP1 + LL_RCC_PLL3_GetP2 + LL_RCC_PLL3_IsEnabledBypass.66 + LL_RCC_PLL4_IsReady.57 + LL_RCC_PLL4P_IsEnabled + LL_RCC_PLL4_GetSource.58 + LL_RCC_PLL4_GetM + LL_RCC_PLL4_GetN + LL_RCC_PLL4_GetFRACN + LL_RCC_PLL4_GetP1 + LL_RCC_PLL4_GetP2 + LL_RCC_PLL4_IsEnabledBypass.59 + LL_RCC_MSI_GetFrequency + main + NMI_Handler + HardFault_Handler + MemManage_Handler + BusFault_Handler + UsageFault_Handler + SVC_Handler + DebugMon_Handler + PendSV_Handler + SysTick_Handler + SystemInit + SystemCoreClockUpdate + _start + __SEGGER_init_done + __startup_complete + exit + PVD_PVM_IRQHandler + DTS_IRQHandler + RCC_IRQHandler + LOCKUP_IRQHandler + CACHE_ECC_IRQHandler + TCM_ECC_IRQHandler + BCK_ECC_IRQHandler + FPU_IRQHandler + RTC_S_IRQHandler + TAMP_IRQHandler + RIFSC_TAMPER_IRQHandler + IAC_IRQHandler + RCC_S_IRQHandler + RTC_IRQHandler + IWDG_IRQHandler + WWDG_IRQHandler + EXTI0_IRQHandler + EXTI1_IRQHandler + EXTI2_IRQHandler + EXTI3_IRQHandler + EXTI4_IRQHandler + EXTI5_IRQHandler + EXTI6_IRQHandler + EXTI7_IRQHandler + EXTI8_IRQHandler + EXTI9_IRQHandler + EXTI10_IRQHandler + EXTI11_IRQHandler + EXTI12_IRQHandler + EXTI13_IRQHandler + EXTI14_IRQHandler + EXTI15_IRQHandler + SAES_IRQHandler + CRYP_IRQHandler + PKA_IRQHandler + HASH_IRQHandler + RNG_IRQHandler + MCE1_IRQHandler + MCE2_IRQHandler + MCE3_IRQHandler + MCE4_IRQHandler + ADC1_2_IRQHandler + CSI_IRQHandler + DCMIPP_IRQHandler + PAHB_ERR_IRQHandler + NPU0_IRQHandler + NPU1_IRQHandler + NPU2_IRQHandler + NPU3_IRQHandler + CACHEAXI_IRQHandler + LTDC_LO_IRQHandler + LTDC_LO_ERR_IRQHandler + DMA2D_IRQHandler + JPEG_IRQHandler + VENC_IRQHandler + GFXMMU_IRQHandler + GFXTIM_IRQHandler + GPU2D_IRQHandler + GPU2D_ER_IRQHandler + ICACHE_IRQHandler + HPDMA1_Channel0_IRQHandler + HPDMA1_Channel1_IRQHandler + HPDMA1_Channel2_IRQHandler + HPDMA1_Channel3_IRQHandler + HPDMA1_Channel4_IRQHandler + HPDMA1_Channel5_IRQHandler + HPDMA1_Channel6_IRQHandler + HPDMA1_Channel7_IRQHandler + HPDMA1_Channel8_IRQHandler + HPDMA1_Channel9_IRQHandler + HPDMA1_Channel10_IRQHandler + HPDMA1_Channel11_IRQHandler + HPDMA1_Channel12_IRQHandler + HPDMA1_Channel13_IRQHandler + HPDMA1_Channel14_IRQHandler + HPDMA1_Channel15_IRQHandler + GPDMA1_Channel0_IRQHandler + GPDMA1_Channel1_IRQHandler + GPDMA1_Channel2_IRQHandler + GPDMA1_Channel3_IRQHandler + GPDMA1_Channel4_IRQHandler + GPDMA1_Channel5_IRQHandler + GPDMA1_Channel6_IRQHandler + GPDMA1_Channel7_IRQHandler + GPDMA1_Channel8_IRQHandler + GPDMA1_Channel9_IRQHandler + GPDMA1_Channel10_IRQHandler + GPDMA1_Channel11_IRQHandler + GPDMA1_Channel12_IRQHandler + GPDMA1_Channel13_IRQHandler + GPDMA1_Channel14_IRQHandler + GPDMA1_Channel15_IRQHandler + I2C1_EV_IRQHandler + I2C1_ER_IRQHandler + I2C2_EV_IRQHandler + I2C2_ER_IRQHandler + I2C3_EV_IRQHandler + I2C3_ER_IRQHandler + I2C4_EV_IRQHandler + I2C4_ER_IRQHandler + I3C1_EV_IRQHandler + I3C1_ER_IRQHandler + I3C2_EV_IRQHandler + I3C2_ER_IRQHandler + TIM1_BRK_IRQHandler + TIM1_UP_IRQHandler + TIM1_TRG_CCU_IRQHandler + TIM1_CC_IRQHandler + TIM2_IRQHandler + TIM3_IRQHandler + TIM4_IRQHandler + TIM5_IRQHandler + TIM6_IRQHandler + TIM7_IRQHandler + TIM8_BRK_IRQHandler + TIM8_UP_IRQHandler + TIM8_TRG_CCU_IRQHandler + TIM8_CC_IRQHandler + TIM9_IRQHandler + TIM10_IRQHandler + TIM11_IRQHandler + TIM12_IRQHandler + TIM13_IRQHandler + TIM14_IRQHandler + TIM15_IRQHandler + TIM16_IRQHandler + TIM17_IRQHandler + TIM18_IRQHandler + LPTIM1_IRQHandler + LPTIM2_IRQHandler + LPTIM3_IRQHandler + LPTIM4_IRQHandler + LPTIM5_IRQHandler + ADF1_FLT0_IRQHandler + MDF1_FLT0_IRQHandler + MDF1_FLT1_IRQHandler + MDF1_FLT2_IRQHandler + MDF1_FLT3_IRQHandler + MDF1_FLT4_IRQHandler + MDF1_FLT5_IRQHandler + SAI1_A_IRQHandler + SAI1_B_IRQHandler + SAI2_A_IRQHandler + SAI2_B_IRQHandler + SPDIFRX_IRQHandler + SPI1_IRQHandler + SPI2_IRQHandler + SPI3_IRQHandler + SPI4_IRQHandler + SPI5_IRQHandler + SPI6_IRQHandler + USART1_IRQHandler + USART2_IRQHandler + USART3_IRQHandler + UART4_IRQHandler + UART5_IRQHandler + USART6_IRQHandler + UART7_IRQHandler + UART8_IRQHandler + UART9_IRQHandler + USART10_IRQHandler + LPUART1_IRQHandler + XSPI1_IRQHandler + XSPI2_IRQHandler + XSPI3_IRQHandler + FMC_IRQHandler + SDMMC1_IRQHandler + SDMMC2_IRQHandler + UCPD1_IRQHandler + USB1_OTG_HS_IRQHandler + USB2_OTG_HS_IRQHandler + ETH1_IRQHandler + FDCAN1_IT0_IRQHandler + FDCAN1_IT1_IRQHandler + FDCAN2_IT0_IRQHandler + FDCAN2_IT1_IRQHandler + FDCAN3_IT0_IRQHandler + FDCAN3_IT1_IRQHandler + FDCAN_CU_IRQHandler + MDIOS_IRQHandler + DCMI_PSSI_IRQHandler + WAKEUP_PIN_IRQHandler + CTI_INT0_IRQHandler + CTI_INT1_IRQHandler + LTDC_UP_IRQHandler + LTDC_UP_ERR_IRQHandler + reset_handler + Reset_Handler + __SEGGER_init_zero + __SEGGER_init_copy + __SEGGER_init_ctors + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset +

UNUSED INPUTS

+

Unused object files

+ +No unused object files +

ABSOLUTE LISTING

+

Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024

+ +
+
_vectors:
+g_pfnVectors:
+  0x34180400:  34200000     DC.W       34200000               ; R_ARM_ABS32
+  0x34180404:  34181A7D     DC.W       reset_handler
+  0x34180408:  34181E49     DC.W       NMI_Handler
+  0x3418040C:  34181E4D     DC.W       HardFault_Handler
+  0x34180410:  34181E51     DC.W       MemManage_Handler
+  0x34180414:  34181E55     DC.W       BusFault_Handler
+  0x34180418:  34181E59     DC.W       UsageFault_Handler
+  0x3418041C:  00           DC.B       0x00                     ; '\0'
+  0x3418041D:  00           DC.B       0x00                     ; '\0'
+  0x3418041E:  00           DC.B       0x00                     ; '\0'
+  0x3418041F:  00           DC.B       0x00                     ; '\0'
+  0x34180420:  00           DC.B       0x00                     ; '\0'
+  0x34180421:  00           DC.B       0x00                     ; '\0'
+  0x34180422:  00           DC.B       0x00                     ; '\0'
+  0x34180423:  00           DC.B       0x00                     ; '\0'
+  0x34180424:  00           DC.B       0x00                     ; '\0'
+  0x34180425:  00           DC.B       0x00                     ; '\0'
+  0x34180426:  00           DC.B       0x00                     ; '\0'
+  0x34180427:  00           DC.B       0x00                     ; '\0'
+  0x34180428:  00           DC.B       0x00                     ; '\0'
+  0x34180429:  00           DC.B       0x00                     ; '\0'
+  0x3418042A:  00           DC.B       0x00                     ; '\0'
+  0x3418042B:  00           DC.B       0x00                     ; '\0'
+  0x3418042C:  34181E5D     DC.W       SVC_Handler
+  0x34180430:  34181E61     DC.W       DebugMon_Handler
+  0x34180434:  00           DC.B       0x00                     ; '\0'
+  0x34180435:  00           DC.B       0x00                     ; '\0'
+  0x34180436:  00           DC.B       0x00                     ; '\0'
+  0x34180437:  00           DC.B       0x00                     ; '\0'
+  0x34180438:  34181E65     DC.W       PendSV_Handler
+  0x3418043C:  34180759     DC.W       SysTick_Handler
+  0x34180440:  34181CE3     DC.W       PVD_PVM_IRQHandler
+  0x34180444:  00           DC.B       0x00                     ; '\0'
+  0x34180445:  00           DC.B       0x00                     ; '\0'
+  0x34180446:  00           DC.B       0x00                     ; '\0'
+  0x34180447:  00           DC.B       0x00                     ; '\0'
+  0x34180448:  34181D07     DC.W       DTS_IRQHandler
+  0x3418044C:  34181D4B     DC.W       RCC_IRQHandler
+  0x34180450:  34181E3B     DC.W       LOCKUP_IRQHandler
+  0x34180454:  34181E47     DC.W       CACHE_ECC_IRQHandler
+  0x34180458:  34181E4B     DC.W       TCM_ECC_IRQHandler
+  0x3418045C:  34181E4F     DC.W       BCK_ECC_IRQHandler
+  0x34180460:  34181E53     DC.W       FPU_IRQHandler
+  0x34180464:  00           DC.B       0x00                     ; '\0'
+  0x34180465:  00           DC.B       0x00                     ; '\0'
+  0x34180466:  00           DC.B       0x00                     ; '\0'
+  0x34180467:  00           DC.B       0x00                     ; '\0'
+  0x34180468:  34181E57     DC.W       RTC_S_IRQHandler
+  0x3418046C:  34181E5B     DC.W       TAMP_IRQHandler
+  0x34180470:  34181E5F     DC.W       RIFSC_TAMPER_IRQHandler
+  0x34180474:  34181E63     DC.W       IAC_IRQHandler
+  0x34180478:  34181E67     DC.W       RCC_S_IRQHandler
+  0x3418047C:  00           DC.B       0x00                     ; '\0'
+  0x3418047D:  00           DC.B       0x00                     ; '\0'
+  0x3418047E:  00           DC.B       0x00                     ; '\0'
+  0x3418047F:  00           DC.B       0x00                     ; '\0'
+  0x34180480:  34182067     DC.W       RTC_IRQHandler
+  0x34180484:  00           DC.B       0x00                     ; '\0'
+  0x34180485:  00           DC.B       0x00                     ; '\0'
+  0x34180486:  00           DC.B       0x00                     ; '\0'
+  0x34180487:  00           DC.B       0x00                     ; '\0'
+  0x34180488:  341820E7     DC.W       IWDG_IRQHandler
+  0x3418048C:  34182103     DC.W       WWDG_IRQHandler
+  0x34180490:  3418213F     DC.W       EXTI0_IRQHandler
+  0x34180494:  3418217F     DC.W       EXTI1_IRQHandler
+  0x34180498:  341821BF     DC.W       EXTI2_IRQHandler
+  0x3418049C:  3418220F     DC.W       EXTI3_IRQHandler
+  0x341804A0:  34182277     DC.W       EXTI4_IRQHandler
+  0x341804A4:  341822EB     DC.W       EXTI5_IRQHandler
+  0x341804A8:  3418235F     DC.W       EXTI6_IRQHandler
+  0x341804AC:  34182373     DC.W       EXTI7_IRQHandler
+  0x341804B0:  34182383     DC.W       EXTI8_IRQHandler
+  0x341804B4:  34182E7F     DC.W       EXTI9_IRQHandler
+  0x341804B8:  34182E9F     DC.W       EXTI10_IRQHandler
+  0x341804BC:  34182EAF     DC.W       EXTI11_IRQHandler
+  0x341804C0:  34182ECF     DC.W       EXTI12_IRQHandler
+  0x341804C4:  34182EDF     DC.W       EXTI13_IRQHandler
+  0x341804C8:  34182EEF     DC.W       EXTI14_IRQHandler
+  0x341804CC:  34182EFF     DC.W       EXTI15_IRQHandler
+  0x341804D0:  34182F0F     DC.W       SAES_IRQHandler
+  0x341804D4:  34182FEB     DC.W       CRYP_IRQHandler
+  0x341804D8:  3418333B     DC.W       PKA_IRQHandler
+  0x341804DC:  3418339B     DC.W       HASH_IRQHandler
+  0x341804E0:  34183D5F     DC.W       RNG_IRQHandler
+  0x341804E4:  00           DC.B       0x00                     ; '\0'
+  0x341804E5:  00           DC.B       0x00                     ; '\0'
+  0x341804E6:  00           DC.B       0x00                     ; '\0'
+  0x341804E7:  00           DC.B       0x00                     ; '\0'
+  0x341804E8:  34183E4B     DC.W       MCE1_IRQHandler
+  0x341804EC:  34183E5B     DC.W       MCE2_IRQHandler
+  0x341804F0:  34183F4B     DC.W       MCE3_IRQHandler
+  0x341804F4:  34183F63     DC.W       MCE4_IRQHandler
+  0x341804F8:  34183FE7     DC.W       ADC1_2_IRQHandler
+  0x341804FC:  3418406B     DC.W       CSI_IRQHandler
+  0x34180500:  341840EF     DC.W       DCMIPP_IRQHandler
+  0x34180504:  00           DC.B       0x00                     ; '\0'
+  0x34180505:  00           DC.B       0x00                     ; '\0'
+  0x34180506:  00           DC.B       0x00                     ; '\0'
+  0x34180507:  00           DC.B       0x00                     ; '\0'
+  0x34180508:  00           DC.B       0x00                     ; '\0'
+  0x34180509:  00           DC.B       0x00                     ; '\0'
+  0x3418050A:  00           DC.B       0x00                     ; '\0'
+  0x3418050B:  00           DC.B       0x00                     ; '\0'
+  0x3418050C:  00           DC.B       0x00                     ; '\0'
+  0x3418050D:  00           DC.B       0x00                     ; '\0'
+  0x3418050E:  00           DC.B       0x00                     ; '\0'
+  0x3418050F:  00           DC.B       0x00                     ; '\0'
+  0x34180510:  34184173     DC.W       PAHB_ERR_IRQHandler
+  0x34180514:  34184175     DC.W       NPU0_IRQHandler
+  0x34180518:  34184177     DC.W       NPU1_IRQHandler
+  0x3418051C:  34184179     DC.W       NPU2_IRQHandler
+  0x34180520:  3418417B     DC.W       NPU3_IRQHandler
+  0x34180524:  3418417D     DC.W       CACHEAXI_IRQHandler
+  0x34180528:  3418417F     DC.W       LTDC_LO_IRQHandler
+  0x3418052C:  34184181     DC.W       LTDC_LO_ERR_IRQHandler
+  0x34180530:  34184183     DC.W       DMA2D_IRQHandler
+  0x34180534:  34184185     DC.W       JPEG_IRQHandler
+  0x34180538:  34184187     DC.W       VENC_IRQHandler
+  0x3418053C:  34184189     DC.W       GFXMMU_IRQHandler
+  0x34180540:  3418418B     DC.W       GFXTIM_IRQHandler
+  0x34180544:  3418418D     DC.W       GPU2D_IRQHandler
+  0x34180548:  3418418F     DC.W       GPU2D_ER_IRQHandler
+  0x3418054C:  34184191     DC.W       ICACHE_IRQHandler
+  0x34180550:  34184193     DC.W       HPDMA1_Channel0_IRQHandler
+  0x34180554:  34184195     DC.W       HPDMA1_Channel1_IRQHandler
+  0x34180558:  34184197     DC.W       HPDMA1_Channel2_IRQHandler
+  0x3418055C:  34184199     DC.W       HPDMA1_Channel3_IRQHandler
+  0x34180560:  3418419B     DC.W       HPDMA1_Channel4_IRQHandler
+  0x34180564:  3418419D     DC.W       HPDMA1_Channel5_IRQHandler
+  0x34180568:  3418419F     DC.W       HPDMA1_Channel6_IRQHandler
+  0x3418056C:  341841A1     DC.W       HPDMA1_Channel7_IRQHandler
+  0x34180570:  341841A3     DC.W       HPDMA1_Channel8_IRQHandler
+  0x34180574:  341841A5     DC.W       HPDMA1_Channel9_IRQHandler
+  0x34180578:  341841A7     DC.W       HPDMA1_Channel10_IRQHandler
+  0x3418057C:  341841A9     DC.W       HPDMA1_Channel11_IRQHandler
+  0x34180580:  341841AB     DC.W       HPDMA1_Channel12_IRQHandler
+  0x34180584:  341841AD     DC.W       HPDMA1_Channel13_IRQHandler
+  0x34180588:  341841AF     DC.W       HPDMA1_Channel14_IRQHandler
+  0x3418058C:  341841B1     DC.W       HPDMA1_Channel15_IRQHandler
+  0x34180590:  341841B3     DC.W       GPDMA1_Channel0_IRQHandler
+  0x34180594:  341841B5     DC.W       GPDMA1_Channel1_IRQHandler
+  0x34180598:  341841B7     DC.W       GPDMA1_Channel2_IRQHandler
+  0x3418059C:  341841B9     DC.W       GPDMA1_Channel3_IRQHandler
+  0x341805A0:  341841BB     DC.W       GPDMA1_Channel4_IRQHandler
+  0x341805A4:  341841BD     DC.W       GPDMA1_Channel5_IRQHandler
+  0x341805A8:  341841BF     DC.W       GPDMA1_Channel6_IRQHandler
+  0x341805AC:  341841C1     DC.W       GPDMA1_Channel7_IRQHandler
+  0x341805B0:  341841C3     DC.W       GPDMA1_Channel8_IRQHandler
+  0x341805B4:  341841C5     DC.W       GPDMA1_Channel9_IRQHandler
+  0x341805B8:  341841C7     DC.W       GPDMA1_Channel10_IRQHandler
+  0x341805BC:  341841C9     DC.W       GPDMA1_Channel11_IRQHandler
+  0x341805C0:  341841CB     DC.W       GPDMA1_Channel12_IRQHandler
+  0x341805C4:  341841CD     DC.W       GPDMA1_Channel13_IRQHandler
+  0x341805C8:  341841CF     DC.W       GPDMA1_Channel14_IRQHandler
+  0x341805CC:  341841D1     DC.W       GPDMA1_Channel15_IRQHandler
+  0x341805D0:  341841D3     DC.W       I2C1_EV_IRQHandler
+  0x341805D4:  341841D5     DC.W       I2C1_ER_IRQHandler
+  0x341805D8:  341841D7     DC.W       I2C2_EV_IRQHandler
+  0x341805DC:  341841D9     DC.W       I2C2_ER_IRQHandler
+  0x341805E0:  341841DB     DC.W       I2C3_EV_IRQHandler
+  0x341805E4:  341841DD     DC.W       I2C3_ER_IRQHandler
+  0x341805E8:  341841DF     DC.W       I2C4_EV_IRQHandler
+  0x341805EC:  341841E1     DC.W       I2C4_ER_IRQHandler
+  0x341805F0:  341841E3     DC.W       I3C1_EV_IRQHandler
+  0x341805F4:  341841E5     DC.W       I3C1_ER_IRQHandler
+  0x341805F8:  341841E7     DC.W       I3C2_EV_IRQHandler
+  0x341805FC:  341841E9     DC.W       I3C2_ER_IRQHandler
+  0x34180600:  341841EB     DC.W       TIM1_BRK_IRQHandler
+  0x34180604:  341841ED     DC.W       TIM1_UP_IRQHandler
+  0x34180608:  341841EF     DC.W       TIM1_TRG_CCU_IRQHandler
+  0x3418060C:  341841F1     DC.W       TIM1_CC_IRQHandler
+  0x34180610:  341841F3     DC.W       TIM2_IRQHandler
+  0x34180614:  341841F5     DC.W       TIM3_IRQHandler
+  0x34180618:  341841F7     DC.W       TIM4_IRQHandler
+  0x3418061C:  341841F9     DC.W       TIM5_IRQHandler
+  0x34180620:  341841FB     DC.W       TIM6_IRQHandler
+  0x34180624:  341841FD     DC.W       TIM7_IRQHandler
+  0x34180628:  341841FF     DC.W       TIM8_BRK_IRQHandler
+  0x3418062C:  34184201     DC.W       TIM8_UP_IRQHandler
+  0x34180630:  34184203     DC.W       TIM8_TRG_CCU_IRQHandler
+  0x34180634:  34184205     DC.W       TIM8_CC_IRQHandler
+  0x34180638:  34184207     DC.W       TIM9_IRQHandler
+  0x3418063C:  34184209     DC.W       TIM10_IRQHandler
+  0x34180640:  3418420B     DC.W       TIM11_IRQHandler
+  0x34180644:  3418420D     DC.W       TIM12_IRQHandler
+  0x34180648:  3418420F     DC.W       TIM13_IRQHandler
+  0x3418064C:  34184211     DC.W       TIM14_IRQHandler
+  0x34180650:  34184213     DC.W       TIM15_IRQHandler
+  0x34180654:  34184215     DC.W       TIM16_IRQHandler
+  0x34180658:  34184217     DC.W       TIM17_IRQHandler
+  0x3418065C:  34184219     DC.W       TIM18_IRQHandler
+  0x34180660:  3418421B     DC.W       LPTIM1_IRQHandler
+  0x34180664:  3418421D     DC.W       LPTIM2_IRQHandler
+  0x34180668:  3418421F     DC.W       LPTIM3_IRQHandler
+  0x3418066C:  34184221     DC.W       LPTIM4_IRQHandler
+  0x34180670:  34184223     DC.W       LPTIM5_IRQHandler
+  0x34180674:  34184225     DC.W       ADF1_FLT0_IRQHandler
+  0x34180678:  34184227     DC.W       MDF1_FLT0_IRQHandler
+  0x3418067C:  34184229     DC.W       MDF1_FLT1_IRQHandler
+  0x34180680:  3418422B     DC.W       MDF1_FLT2_IRQHandler
+  0x34180684:  3418422D     DC.W       MDF1_FLT3_IRQHandler
+  0x34180688:  3418422F     DC.W       MDF1_FLT4_IRQHandler
+  0x3418068C:  34184231     DC.W       MDF1_FLT5_IRQHandler
+  0x34180690:  34184233     DC.W       SAI1_A_IRQHandler
+  0x34180694:  34184235     DC.W       SAI1_B_IRQHandler
+  0x34180698:  34184237     DC.W       SAI2_A_IRQHandler
+  0x3418069C:  34184239     DC.W       SAI2_B_IRQHandler
+  0x341806A0:  3418423B     DC.W       SPDIFRX_IRQHandler
+  0x341806A4:  3418423D     DC.W       SPI1_IRQHandler
+  0x341806A8:  3418423F     DC.W       SPI2_IRQHandler
+  0x341806AC:  34184241     DC.W       SPI3_IRQHandler
+  0x341806B0:  34184243     DC.W       SPI4_IRQHandler
+  0x341806B4:  34184245     DC.W       SPI5_IRQHandler
+  0x341806B8:  34184247     DC.W       SPI6_IRQHandler
+  0x341806BC:  34184249     DC.W       USART1_IRQHandler
+  0x341806C0:  3418424B     DC.W       USART2_IRQHandler
+  0x341806C4:  3418424D     DC.W       USART3_IRQHandler
+  0x341806C8:  3418424F     DC.W       UART4_IRQHandler
+  0x341806CC:  34184251     DC.W       UART5_IRQHandler
+  0x341806D0:  34184253     DC.W       USART6_IRQHandler
+  0x341806D4:  34184255     DC.W       UART7_IRQHandler
+  0x341806D8:  34184257     DC.W       UART8_IRQHandler
+  0x341806DC:  34184259     DC.W       UART9_IRQHandler
+  0x341806E0:  3418425B     DC.W       USART10_IRQHandler
+  0x341806E4:  3418425D     DC.W       LPUART1_IRQHandler
+  0x341806E8:  3418425F     DC.W       XSPI1_IRQHandler
+  0x341806EC:  34184261     DC.W       XSPI2_IRQHandler
+  0x341806F0:  34184263     DC.W       XSPI3_IRQHandler
+  0x341806F4:  34184265     DC.W       FMC_IRQHandler
+  0x341806F8:  34184267     DC.W       SDMMC1_IRQHandler
+  0x341806FC:  34184269     DC.W       SDMMC2_IRQHandler
+  0x34180700:  3418426B     DC.W       UCPD1_IRQHandler
+  0x34180704:  3418426D     DC.W       USB1_OTG_HS_IRQHandler
+  0x34180708:  3418426F     DC.W       USB2_OTG_HS_IRQHandler
+  0x3418070C:  34184271     DC.W       ETH1_IRQHandler
+  0x34180710:  34184273     DC.W       FDCAN1_IT0_IRQHandler
+  0x34180714:  34184275     DC.W       FDCAN1_IT1_IRQHandler
+  0x34180718:  34184277     DC.W       FDCAN2_IT0_IRQHandler
+  0x3418071C:  34184279     DC.W       FDCAN2_IT1_IRQHandler
+  0x34180720:  3418427B     DC.W       FDCAN3_IT0_IRQHandler
+  0x34180724:  3418427D     DC.W       FDCAN3_IT1_IRQHandler
+  0x34180728:  3418427F     DC.W       FDCAN_CU_IRQHandler
+  0x3418072C:  34184281     DC.W       MDIOS_IRQHandler
+  0x34180730:  34184283     DC.W       DCMI_PSSI_IRQHandler
+  0x34180734:  34184285     DC.W       WAKEUP_PIN_IRQHandler
+  0x34180738:  34184287     DC.W       CTI_INT0_IRQHandler
+  0x3418073C:  34184289     DC.W       CTI_INT1_IRQHandler
+  0x34180740:  00           DC.B       0x00                     ; '\0'
+  0x34180741:  00           DC.B       0x00                     ; '\0'
+  0x34180742:  00           DC.B       0x00                     ; '\0'
+  0x34180743:  00           DC.B       0x00                     ; '\0'
+  0x34180744:  3418428B     DC.W       LTDC_UP_IRQHandler
+  0x34180748:  3418428D     DC.W       LTDC_UP_ERR_IRQHandler
+
+

Section .text.Error_Handler from blto2_FSBL_lto.o, size=4, align=4

+ +
+
Error_Handler:
+_vectors_end:
+  0x3418074C:  B672         CPSID      i
+
.L1:
+  0x3418074E:  E7FE         B          46L1                      ; 0x3418074E
+
+

Section .text.HAL_MspInit from blto2_FSBL_lto.o, size=8, align=4

+ +
+
HAL_MspInit:
+  0x34180750:  B580         PUSH       123R7, LR}
+  0x34180752:  F001 FE05    BL         HAL_PWREx_EnableVddIO3   ; 0x34182360
+  0x34180756:  BD80         POP        123R7, PC}
+
+

Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=8, align=4

+ +
+
SysTick_Handler:
+  0x34180758:  B580         PUSH       123R7, LR}
+  0x3418075A:  F001 FCC5    BL         HAL_IncTick              ; 0x341820E8
+  0x3418075E:  BD80         POP        123R7, PC}
+
+

Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=828, align=4

+ +
+
SystemCoreClockUpdate:
+  0x34180760:  B08E         SUB        SP, SP, #56
+  0x34180762:  2000         MOVS       R0, #0
+  0x34180764:  900D         STR        R0, [SP, #52]
+  0x34180766:  900C         STR        R0, [SP, #48]
+  0x34180768:  900B         STR        R0, [SP, #44]
+  0x3418076A:  900A         STR        R0, [SP, #40]
+  0x3418076C:  9009         STR        R0, [SP, #36]
+  0x3418076E:  9008         STR        R0, [SP, #32]
+  0x34180770:  F248 0020    MOVW       R0, #0x8020
+  0x34180774:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180778:  6800         LDR        R0, [R0]
+  0x3418077A:  F400 1040    AND        R0, R0, #0x300000
+  0x3418077E:  4601         MOV        R1, R0
+  0x34180780:  9102         STR        R1, [SP, #8]
+  0x34180782:  B160         CBZ        R0, .L1                  ; 0x3418079E
+  0x34180784:  9802         LDR        R0, [SP, #8]
+  0x34180786:  F5B0 1F80    CMP.W      R0, #0x100000
+  0x3418078A:  D016         BEQ        46L2                      ; 0x341807BA
+  0x3418078C:  9802         LDR        R0, [SP, #8]
+  0x3418078E:  F5B0 1F00    CMP.W      R0, #0x200000
+  0x34180792:  D026         BEQ        46L5                      ; 0x341807E2
+  0x34180794:  9802         LDR        R0, [SP, #8]
+  0x34180796:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x3418079A:  D028         BEQ        46L6                      ; 0x341807EE
+  0x3418079C:  E174         B          46L23                     ; 0x34180A88
+
.L1:
+  0x3418079E:  F248 0048    MOVW       R0, #0x8048
+  0x341807A2:  F2C5 6002    MOVT       R0, #0x5602
+  0x341807A6:  6800         LDR        R0, [R0]
+  0x341807A8:  F3C0 11C1    UBFX       R1, R0, #7, #2
+  0x341807AC:  F249 0000    MOVW       R0, #0x9000
+  0x341807B0:  F2C0 30D0    MOVT       R0, #0x03D0
+  0x341807B4:  40C8         LSRS       R0, R1
+  0x341807B6:  900D         STR        R0, [SP, #52]
+  0x341807B8:  E166         B          46L23                     ; 0x34180A88
+
.L2:
+  0x341807BA:  F248 0044    MOVW       R0, #0x8044
+  0x341807BE:  F2C5 6002    MOVT       R0, #0x5602
+  0x341807C2:  6800         LDR        R0, [R0]
+  0x341807C4:  0580         LSLS       R0, R0, #22
+  0x341807C6:  2800         CMP        R0, #0
+  0x341807C8:  D405         BMI        46L3                      ; 0x341807D6
+  0x341807CA:  F640 1000    MOVW       R0, #0x0900
+  0x341807CE:  F2C0 003D    MOVT       R0, #61
+  0x341807D2:  900D         STR        R0, [SP, #52]
+  0x341807D4:  E004         B          46L4                      ; 0x341807E0
+
.L3:
+  0x341807D6:  F242 4000    MOVW       R0, #0x2400
+  0x341807DA:  F2C0 00F4    MOVT       R0, #244
+  0x341807DE:  900D         STR        R0, [SP, #52]
+
.L4:
+  0x341807E0:  E152         B          46L23                     ; 0x34180A88
+
.L5:
+  0x341807E2:  F646 4000    MOVW       R0, #0x6C00
+  0x341807E6:  F2C0 20DC    MOVT       R0, #0x02DC
+  0x341807EA:  900D         STR        R0, [SP, #52]
+  0x341807EC:  E14C         B          46L23                     ; 0x34180A88
+
.L6:
+  0x341807EE:  F248 00C4    MOVW       R0, #0x80C4
+  0x341807F2:  F2C5 6002    MOVT       R0, #0x5602
+  0x341807F6:  6800         LDR        R0, [R0]
+  0x341807F8:  F000 5040    AND        R0, R0, #0x30000000
+  0x341807FC:  4601         MOV        R1, R0
+  0x341807FE:  9101         STR        R1, [SP, #4]
+  0x34180800:  B140         CBZ        R0, .L7                  ; 0x34180814
+  0x34180802:  9801         LDR        R0, [SP, #4]
+  0x34180804:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34180808:  D033         BEQ        46L9                      ; 0x34180872
+  0x3418080A:  9801         LDR        R0, [SP, #4]
+  0x3418080C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34180810:  D05E         BEQ        46L11                     ; 0x341808D0
+  0x34180812:  E08C         B          46L13                     ; 0x3418092E
+
.L7:
+  0x34180814:  F248 0080    MOVW       R0, #0x8080
+  0x34180818:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418081C:  6800         LDR        R0, [R0]
+  0x3418081E:  9007         STR        R0, [SP, #28]
+  0x34180820:  9807         LDR        R0, [SP, #28]
+  0x34180822:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34180826:  9006         STR        R0, [SP, #24]
+  0x34180828:  9807         LDR        R0, [SP, #28]
+  0x3418082A:  F000 6000    AND        R0, R0, #0x08000000
+  0x3418082E:  9005         STR        R0, [SP, #20]
+  0x34180830:  9805         LDR        R0, [SP, #20]
+  0x34180832:  B9E8         CBNZ       R0, .L8                  ; 0x34180870
+  0x34180834:  9807         LDR        R0, [SP, #28]
+  0x34180836:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x3418083A:  900C         STR        R0, [SP, #48]
+  0x3418083C:  9807         LDR        R0, [SP, #28]
+  0x3418083E:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x34180842:  900B         STR        R0, [SP, #44]
+  0x34180844:  F248 0084    MOVW       R0, #0x8084
+  0x34180848:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418084C:  6800         LDR        R0, [R0]
+  0x3418084E:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x34180852:  900A         STR        R0, [SP, #40]
+  0x34180854:  F248 0088    MOVW       R0, #0x8088
+  0x34180858:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418085C:  6800         LDR        R0, [R0]
+  0x3418085E:  9007         STR        R0, [SP, #28]
+  0x34180860:  9807         LDR        R0, [SP, #28]
+  0x34180862:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x34180866:  9009         STR        R0, [SP, #36]
+  0x34180868:  9807         LDR        R0, [SP, #28]
+  0x3418086A:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x3418086E:  9008         STR        R0, [SP, #32]
+
.L8:
+  0x34180870:  E08B         B          46L14                     ; 0x3418098A
+
.L9:
+  0x34180872:  F248 0090    MOVW       R0, #0x8090
+  0x34180876:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418087A:  6800         LDR        R0, [R0]
+  0x3418087C:  9007         STR        R0, [SP, #28]
+  0x3418087E:  9807         LDR        R0, [SP, #28]
+  0x34180880:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34180884:  9006         STR        R0, [SP, #24]
+  0x34180886:  9807         LDR        R0, [SP, #28]
+  0x34180888:  F000 6000    AND        R0, R0, #0x08000000
+  0x3418088C:  9005         STR        R0, [SP, #20]
+  0x3418088E:  9805         LDR        R0, [SP, #20]
+  0x34180890:  B9E8         CBNZ       R0, .L10                 ; 0x341808CE
+  0x34180892:  9807         LDR        R0, [SP, #28]
+  0x34180894:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x34180898:  900C         STR        R0, [SP, #48]
+  0x3418089A:  9807         LDR        R0, [SP, #28]
+  0x3418089C:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x341808A0:  900B         STR        R0, [SP, #44]
+  0x341808A2:  F248 0094    MOVW       R0, #0x8094
+  0x341808A6:  F2C5 6002    MOVT       R0, #0x5602
+  0x341808AA:  6800         LDR        R0, [R0]
+  0x341808AC:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x341808B0:  900A         STR        R0, [SP, #40]
+  0x341808B2:  F248 0098    MOVW       R0, #0x8098
+  0x341808B6:  F2C5 6002    MOVT       R0, #0x5602
+  0x341808BA:  6800         LDR        R0, [R0]
+  0x341808BC:  9007         STR        R0, [SP, #28]
+  0x341808BE:  9807         LDR        R0, [SP, #28]
+  0x341808C0:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x341808C4:  9009         STR        R0, [SP, #36]
+  0x341808C6:  9807         LDR        R0, [SP, #28]
+  0x341808C8:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x341808CC:  9008         STR        R0, [SP, #32]
+
.L10:
+  0x341808CE:  E05C         B          46L14                     ; 0x3418098A
+
.L11:
+  0x341808D0:  F248 00A0    MOVW       R0, #0x80A0
+  0x341808D4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341808D8:  6800         LDR        R0, [R0]
+  0x341808DA:  9007         STR        R0, [SP, #28]
+  0x341808DC:  9807         LDR        R0, [SP, #28]
+  0x341808DE:  F000 40E0    AND        R0, R0, #0x70000000
+  0x341808E2:  9006         STR        R0, [SP, #24]
+  0x341808E4:  9807         LDR        R0, [SP, #28]
+  0x341808E6:  F000 6000    AND        R0, R0, #0x08000000
+  0x341808EA:  9005         STR        R0, [SP, #20]
+  0x341808EC:  9805         LDR        R0, [SP, #20]
+  0x341808EE:  B9E8         CBNZ       R0, .L12                 ; 0x3418092C
+  0x341808F0:  9807         LDR        R0, [SP, #28]
+  0x341808F2:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x341808F6:  900C         STR        R0, [SP, #48]
+  0x341808F8:  9807         LDR        R0, [SP, #28]
+  0x341808FA:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x341808FE:  900B         STR        R0, [SP, #44]
+  0x34180900:  F248 00A4    MOVW       R0, #0x80A4
+  0x34180904:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180908:  6800         LDR        R0, [R0]
+  0x3418090A:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x3418090E:  900A         STR        R0, [SP, #40]
+  0x34180910:  F248 00A8    MOVW       R0, #0x80A8
+  0x34180914:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180918:  6800         LDR        R0, [R0]
+  0x3418091A:  9007         STR        R0, [SP, #28]
+  0x3418091C:  9807         LDR        R0, [SP, #28]
+  0x3418091E:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x34180922:  9009         STR        R0, [SP, #36]
+  0x34180924:  9807         LDR        R0, [SP, #28]
+  0x34180926:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x3418092A:  9008         STR        R0, [SP, #32]
+
.L12:
+  0x3418092C:  E02D         B          46L14                     ; 0x3418098A
+
.L13:
+  0x3418092E:  F248 00B0    MOVW       R0, #0x80B0
+  0x34180932:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180936:  6800         LDR        R0, [R0]
+  0x34180938:  9007         STR        R0, [SP, #28]
+  0x3418093A:  9807         LDR        R0, [SP, #28]
+  0x3418093C:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34180940:  9006         STR        R0, [SP, #24]
+  0x34180942:  9807         LDR        R0, [SP, #28]
+  0x34180944:  F000 6000    AND        R0, R0, #0x08000000
+  0x34180948:  9005         STR        R0, [SP, #20]
+  0x3418094A:  9805         LDR        R0, [SP, #20]
+  0x3418094C:  B9E8         CBNZ       R0, .L14                 ; 0x3418098A
+  0x3418094E:  9807         LDR        R0, [SP, #28]
+  0x34180950:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x34180954:  900C         STR        R0, [SP, #48]
+  0x34180956:  9807         LDR        R0, [SP, #28]
+  0x34180958:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x3418095C:  900B         STR        R0, [SP, #44]
+  0x3418095E:  F248 00B4    MOVW       R0, #0x80B4
+  0x34180962:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180966:  6800         LDR        R0, [R0]
+  0x34180968:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x3418096C:  900A         STR        R0, [SP, #40]
+  0x3418096E:  F248 00B8    MOVW       R0, #0x80B8
+  0x34180972:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180976:  6800         LDR        R0, [R0]
+  0x34180978:  9007         STR        R0, [SP, #28]
+  0x3418097A:  9807         LDR        R0, [SP, #28]
+  0x3418097C:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x34180980:  9009         STR        R0, [SP, #36]
+  0x34180982:  9807         LDR        R0, [SP, #28]
+  0x34180984:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x34180988:  9008         STR        R0, [SP, #32]
+
.L14:
+  0x3418098A:  9806         LDR        R0, [SP, #24]
+  0x3418098C:  9000         STR        R0, [SP, #0]
+  0x3418098E:  B160         CBZ        R0, .L15                 ; 0x341809AA
+  0x34180990:  9800         LDR        R0, [SP, #0]
+  0x34180992:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34180996:  D016         BEQ        46L16                     ; 0x341809C6
+  0x34180998:  9800         LDR        R0, [SP, #0]
+  0x3418099A:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x3418099E:  D026         BEQ        46L19                     ; 0x341809EE
+  0x341809A0:  9800         LDR        R0, [SP, #0]
+  0x341809A2:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x341809A6:  D028         BEQ        46L20                     ; 0x341809FA
+  0x341809A8:  E02D         B          46L21                     ; 0x34180A06
+
.L15:
+  0x341809AA:  F248 0048    MOVW       R0, #0x8048
+  0x341809AE:  F2C5 6002    MOVT       R0, #0x5602
+  0x341809B2:  6800         LDR        R0, [R0]
+  0x341809B4:  F3C0 11C1    UBFX       R1, R0, #7, #2
+  0x341809B8:  F249 0000    MOVW       R0, #0x9000
+  0x341809BC:  F2C0 30D0    MOVT       R0, #0x03D0
+  0x341809C0:  40C8         LSRS       R0, R1
+  0x341809C2:  900D         STR        R0, [SP, #52]
+  0x341809C4:  E01F         B          46L21                     ; 0x34180A06
+
.L16:
+  0x341809C6:  F248 0044    MOVW       R0, #0x8044
+  0x341809CA:  F2C5 6002    MOVT       R0, #0x5602
+  0x341809CE:  6800         LDR        R0, [R0]
+  0x341809D0:  0580         LSLS       R0, R0, #22
+  0x341809D2:  2800         CMP        R0, #0
+  0x341809D4:  D405         BMI        46L17                     ; 0x341809E2
+  0x341809D6:  F640 1000    MOVW       R0, #0x0900
+  0x341809DA:  F2C0 003D    MOVT       R0, #61
+  0x341809DE:  900D         STR        R0, [SP, #52]
+  0x341809E0:  E004         B          46L18                     ; 0x341809EC
+
.L17:
+  0x341809E2:  F242 4000    MOVW       R0, #0x2400
+  0x341809E6:  F2C0 00F4    MOVT       R0, #244
+  0x341809EA:  900D         STR        R0, [SP, #52]
+
.L18:
+  0x341809EC:  E00B         B          46L21                     ; 0x34180A06
+
.L19:
+  0x341809EE:  F646 4000    MOVW       R0, #0x6C00
+  0x341809F2:  F2C0 20DC    MOVT       R0, #0x02DC
+  0x341809F6:  900D         STR        R0, [SP, #52]
+  0x341809F8:  E005         B          46L21                     ; 0x34180A06
+
.L20:
+  0x341809FA:  F248 0000    MOVW       R0, #0x8000
+  0x341809FE:  F2C0 00BB    MOVT       R0, #187
+  0x34180A02:  900D         STR        R0, [SP, #52]
+  0x34180A04:  E7FF         B          46L21                     ; 0x34180A06
+
.L21:
+  0x34180A06:  9805         LDR        R0, [SP, #20]
+  0x34180A08:  BB68         CBNZ       R0, .L22                 ; 0x34180A66
+  0x34180A0A:  ED9D 0A0D    VLDR       S0, [SP, #52]
+  0x34180A0E:  EEB8 0A40    VCVT.F32.U32 S0, S0
+  0x34180A12:  ED9D 1A0B    VLDR       S2, [SP, #44]
+  0x34180A16:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180A1A:  ED9D 2A0A    VLDR       S4, [SP, #40]
+  0x34180A1E:  EEB8 2A42    VCVT.F32.U32 S4, S4
+  0x34180A22:  ED9F 3A1D    VLDR       S6, =0x33800000          ; [PC, #116] [0x34180A98]
+  0x34180A26:  EE22 2A03    VMUL.F32   S4, S4, S6
+  0x34180A2A:  EE31 1A02    VADD.F32   S2, S2, S4
+  0x34180A2E:  EE20 0A01    VMUL.F32   S0, S0, S2
+  0x34180A32:  ED9D 1A0C    VLDR       S2, [SP, #48]
+  0x34180A36:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180A3A:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34180A3E:  ED8D 0A03    VSTR       S0, [SP, #12]
+  0x34180A42:  ED9D 0A03    VLDR       S0, [SP, #12]
+  0x34180A46:  ED9D 1A09    VLDR       S2, [SP, #36]
+  0x34180A4A:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180A4E:  ED9D 2A08    VLDR       S4, [SP, #32]
+  0x34180A52:  EEB8 2A42    VCVT.F32.U32 S4, S4
+  0x34180A56:  EE21 1A02    VMUL.F32   S2, S2, S4
+  0x34180A5A:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34180A5E:  EEBC 0AC0    VCVT.U32.F32 S0, S0
+  0x34180A62:  ED8D 0A0D    VSTR       S0, [SP, #52]
+
.L22:
+  0x34180A66:  F248 00C4    MOVW       R0, #0x80C4
+  0x34180A6A:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180A6E:  6800         LDR        R0, [R0]
+  0x34180A70:  F400 017F    AND        R1, R0, #0xFF0000
+  0x34180A74:  2001         MOVS       R0, #1
+  0x34180A76:  EB00 4011    ADD.W      R0, R0, R1, LSR #16
+  0x34180A7A:  9004         STR        R0, [SP, #16]
+  0x34180A7C:  980D         LDR        R0, [SP, #52]
+  0x34180A7E:  9904         LDR        R1, [SP, #16]
+  0x34180A80:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34180A84:  900D         STR        R0, [SP, #52]
+  0x34180A86:  E7FF         B          46L23                     ; 0x34180A88
+
.L23:
+  0x34180A88:  980D         LDR        R0, [SP, #52]
+  0x34180A8A:  F244 4148    MOVW       R1, #0x4448              ; 0x34184448 = SystemCoreClock
+  0x34180A8E:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34184448 = SystemCoreClock
+  0x34180A92:  6008         STR        R0, [R1]
+  0x34180A94:  B00E         ADD        SP, SP, #56
+  0x34180A96:  4770         BX         LR
+  0x34180A98:  33800000     DC.W       0x33800000
+
+

Section .text.HAL_Init from blto2_FSBL_lto.o, size=48, align=4

+ +
+
HAL_Init:
+  0x34180A9C:  B580         PUSH       123R7, LR}
+  0x34180A9E:  B082         SUB        SP, SP, #8
+  0x34180AA0:  2003         MOVS       R0, #3
+  0x34180AA2:  F001 FB4D    BL         HAL_NVIC_SetPriorityGrouping ; 0x34182140
+  0x34180AA6:  F7FF FE5B    BL         SystemCoreClockUpdate    ; 0x34180760
+  0x34180AAA:  200F         MOVS       R0, #15
+  0x34180AAC:  F001 FADC    BL         HAL_InitTick             ; 0x34182068
+  0x34180AB0:  B118         CBZ        R0, .L1                  ; 0x34180ABA
+  0x34180AB2:  2001         MOVS       R0, #1
+  0x34180AB4:  F88D 0007    STRB.W     R0, [SP, #7]
+  0x34180AB8:  E004         B          46L2                      ; 0x34180AC4
+
.L1:
+  0x34180ABA:  F7FF FE49    BL         HAL_MspInit              ; 0x34180750
+  0x34180ABE:  2000         MOVS       R0, #0
+  0x34180AC0:  F88D 0007    STRB.W     R0, [SP, #7]
+
.L2:
+  0x34180AC4:  F89D 0007    LDRB.W     R0, [SP, #7]
+  0x34180AC8:  B002         ADD        SP, SP, #8
+  0x34180ACA:  BD80         POP        123R7, PC}
+
+

Section .text.HAL_GetTick from blto2_FSBL_lto.o, size=12, align=4

+ +
+
HAL_GetTick:
+  0x34180ACC:  F244 4040    MOVW       R0, #0x4440              ; 0x34184440 = uwTick
+  0x34180AD0:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184440 = uwTick
+  0x34180AD4:  6800         LDR        R0, [R0]
+  0x34180AD6:  4770         BX         LR
+
+

Section .text.__NVIC_SetPriorityGrouping from blto2_FSBL_lto.o, size=60, align=4

+ +
+
__NVIC_SetPriorityGrouping:
+  0x34180AD8:  B083         SUB        SP, SP, #12
+  0x34180ADA:  9002         STR        R0, [SP, #8]
+  0x34180ADC:  9802         LDR        R0, [SP, #8]
+  0x34180ADE:  F000 0007    AND        R0, R0, #7
+  0x34180AE2:  9000         STR        R0, [SP, #0]
+  0x34180AE4:  F64E 510C    MOVW       R1, #0xED0C
+  0x34180AE8:  F2CE 0100    MOVT       R1, #0xE000
+  0x34180AEC:  6808         LDR        R0, [R1]
+  0x34180AEE:  9001         STR        R0, [SP, #4]
+  0x34180AF0:  9801         LDR        R0, [SP, #4]
+  0x34180AF2:  F64F 02FF    MOVW       R2, #0xF8FF
+  0x34180AF6:  4010         ANDS       R0, R2
+  0x34180AF8:  9001         STR        R0, [SP, #4]
+  0x34180AFA:  9801         LDR        R0, [SP, #4]
+  0x34180AFC:  9A00         LDR        R2, [SP, #0]
+  0x34180AFE:  EA40 2002    ORR.W      R0, R0, R2, LSL #8
+  0x34180B02:  2200         MOVS       R2, #0
+  0x34180B04:  F2C0 52FA    MOVT       R2, #0x05FA
+  0x34180B08:  4310         ORRS       R0, R2
+  0x34180B0A:  9001         STR        R0, [SP, #4]
+  0x34180B0C:  9801         LDR        R0, [SP, #4]
+  0x34180B0E:  6008         STR        R0, [R1]
+  0x34180B10:  B003         ADD        SP, SP, #12
+  0x34180B12:  4770         BX         LR
+
+

Section .text.HAL_NVIC_SetPriority from blto2_FSBL_lto.o, size=168, align=4

+ +
+
HAL_NVIC_SetPriority:
+  0x34180B14:  B580         PUSH       123R7, LR}
+  0x34180B16:  B086         SUB        SP, SP, #24
+  0x34180B18:  F8AD 0016    STRH.W     R0, [SP, #22]
+  0x34180B1C:  9104         STR        R1, [SP, #16]
+  0x34180B1E:  9203         STR        R2, [SP, #12]
+  0x34180B20:  F9BD 0016    LDRSH.W    R0, [SP, #22]
+  0x34180B24:  F110 0F0C    CMN        R0, #12
+  0x34180B28:  DB04         BLT        46L1                      ; 0x34180B34
+  0x34180B2A:  F9BD 0016    LDRSH.W    R0, [SP, #22]
+  0x34180B2E:  3004         ADDS       R0, #4
+  0x34180B30:  B100         CBZ        R0, .L1                  ; 0x34180B34
+  0x34180B32:  E006         B          46L2                      ; 0x34180B42
+
.L1:
+  0x34180B34:  F244 3068    MOVW       R0, #0x4368              ; 0x34184368 = .rodata..L.str.10
+  0x34180B38:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184368 = .rodata..L.str.10
+  0x34180B3C:  21FF         MOVS       R1, #255
+  0x34180B3E:  F001 F97D    BL         assert_failed            ; 0x34181E3C
+
.L2:
+  0x34180B42:  F000 F83B    BL         __NVIC_GetPriorityGrouping ; 0x34180BBC
+  0x34180B46:  F000 0007    AND        R0, R0, #7
+  0x34180B4A:  9002         STR        R0, [SP, #8]
+  0x34180B4C:  9802         LDR        R0, [SP, #8]
+  0x34180B4E:  2802         CMP        R0, #2
+  0x34180B50:  D802         BHI        46L3                      ; 0x34180B58
+  0x34180B52:  9803         LDR        R0, [SP, #12]
+  0x34180B54:  B138         CBZ        R0, .L4                  ; 0x34180B66
+  0x34180B56:  E007         B          46L5                      ; 0x34180B68
+
.L3:
+  0x34180B58:  9803         LDR        R0, [SP, #12]
+  0x34180B5A:  9902         LDR        R1, [SP, #8]
+  0x34180B5C:  1ECA         SUBS       R2, R1, #3
+  0x34180B5E:  2101         MOVS       R1, #1
+  0x34180B60:  4091         LSLS       R1, R2
+  0x34180B62:  4288         CMP        R0, R1
+  0x34180B64:  D200         BCS        46L5                      ; 0x34180B68
+
.L4:
+  0x34180B66:  E007         B          46L6                      ; 0x34180B78
+
.L5:
+  0x34180B68:  F244 3068    MOVW       R0, #0x4368              ; 0x34184368 = .rodata..L.str.10
+  0x34180B6C:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184368 = .rodata..L.str.10
+  0x34180B70:  F44F 7181    MOV.W      R1, #0x0102
+  0x34180B74:  F001 F962    BL         assert_failed            ; 0x34181E3C
+
.L6:
+  0x34180B78:  9804         LDR        R0, [SP, #16]
+  0x34180B7A:  280F         CMP        R0, #15
+  0x34180B7C:  D808         BHI        46L7                      ; 0x34180B90
+  0x34180B7E:  9804         LDR        R0, [SP, #16]
+  0x34180B80:  9902         LDR        R1, [SP, #8]
+  0x34180B82:  F1C1 0207    RSB        R2, R1, #7
+  0x34180B86:  2101         MOVS       R1, #1
+  0x34180B88:  4091         LSLS       R1, R2
+  0x34180B8A:  4288         CMP        R0, R1
+  0x34180B8C:  D200         BCS        46L7                      ; 0x34180B90
+  0x34180B8E:  E007         B          46L8                      ; 0x34180BA0
+
.L7:
+  0x34180B90:  F244 3068    MOVW       R0, #0x4368              ; 0x34184368 = .rodata..L.str.10
+  0x34180B94:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184368 = .rodata..L.str.10
+  0x34180B98:  F240 1103    MOVW       R1, #0x0103
+  0x34180B9C:  F001 F94E    BL         assert_failed            ; 0x34181E3C
+
.L8:
+  0x34180BA0:  F9BD 0016    LDRSH.W    R0, [SP, #22]
+  0x34180BA4:  9001         STR        R0, [SP, #4]
+  0x34180BA6:  9802         LDR        R0, [SP, #8]
+  0x34180BA8:  9904         LDR        R1, [SP, #16]
+  0x34180BAA:  9A03         LDR        R2, [SP, #12]
+  0x34180BAC:  F000 F80E    BL         NVIC_EncodePriority      ; 0x34180BCC
+  0x34180BB0:  4601         MOV        R1, R0
+  0x34180BB2:  9801         LDR        R0, [SP, #4]
+  0x34180BB4:  F001 FAE4    BL         __NVIC_SetPriority       ; 0x34182180
+  0x34180BB8:  B006         ADD        SP, SP, #24
+  0x34180BBA:  BD80         POP        123R7, PC}
+
+

Section .text.__NVIC_GetPriorityGrouping from blto2_FSBL_lto.o, size=16, align=4

+ +
+
__NVIC_GetPriorityGrouping:
+  0x34180BBC:  F64E 500C    MOVW       R0, #0xED0C
+  0x34180BC0:  F2CE 0000    MOVT       R0, #0xE000
+  0x34180BC4:  6800         LDR        R0, [R0]
+  0x34180BC6:  F3C0 2002    UBFX       R0, R0, #8, #3
+  0x34180BCA:  4770         BX         LR
+
+

Section .text.NVIC_EncodePriority from blto2_FSBL_lto.o, size=100, align=4

+ +
+
NVIC_EncodePriority:
+  0x34180BCC:  B088         SUB        SP, SP, #32
+  0x34180BCE:  9007         STR        R0, [SP, #28]
+  0x34180BD0:  9106         STR        R1, [SP, #24]
+  0x34180BD2:  9205         STR        R2, [SP, #20]
+  0x34180BD4:  9807         LDR        R0, [SP, #28]
+  0x34180BD6:  F000 0007    AND        R0, R0, #7
+  0x34180BDA:  9004         STR        R0, [SP, #16]
+  0x34180BDC:  9804         LDR        R0, [SP, #16]
+  0x34180BDE:  F1C0 0007    RSB        R0, R0, #7
+  0x34180BE2:  2805         CMP        R0, #5
+  0x34180BE4:  D302         BCC        46L1                      ; 0x34180BEC
+  0x34180BE6:  2004         MOVS       R0, #4
+  0x34180BE8:  9001         STR        R0, [SP, #4]
+  0x34180BEA:  E003         B          46L2                      ; 0x34180BF4
+
.L1:
+  0x34180BEC:  9804         LDR        R0, [SP, #16]
+  0x34180BEE:  F1C0 0007    RSB        R0, R0, #7
+  0x34180BF2:  9001         STR        R0, [SP, #4]
+
.L2:
+  0x34180BF4:  9801         LDR        R0, [SP, #4]
+  0x34180BF6:  9003         STR        R0, [SP, #12]
+  0x34180BF8:  9804         LDR        R0, [SP, #16]
+  0x34180BFA:  3004         ADDS       R0, #4
+  0x34180BFC:  2806         CMP        R0, #6
+  0x34180BFE:  D802         BHI        46L3                      ; 0x34180C06
+  0x34180C00:  2000         MOVS       R0, #0
+  0x34180C02:  9000         STR        R0, [SP, #0]
+  0x34180C04:  E002         B          46L4                      ; 0x34180C0C
+
.L3:
+  0x34180C06:  9804         LDR        R0, [SP, #16]
+  0x34180C08:  3803         SUBS       R0, #3
+  0x34180C0A:  9000         STR        R0, [SP, #0]
+
.L4:
+  0x34180C0C:  9800         LDR        R0, [SP, #0]
+  0x34180C0E:  9002         STR        R0, [SP, #8]
+  0x34180C10:  9806         LDR        R0, [SP, #24]
+  0x34180C12:  9903         LDR        R1, [SP, #12]
+  0x34180C14:  2201         MOVS       R2, #1
+  0x34180C16:  FA02 F101    LSL.W      R1, R2, R1
+  0x34180C1A:  3901         SUBS       R1, #1
+  0x34180C1C:  4008         ANDS       R0, R1
+  0x34180C1E:  9B02         LDR        R3, [SP, #8]
+  0x34180C20:  4098         LSLS       R0, R3
+  0x34180C22:  9905         LDR        R1, [SP, #20]
+  0x34180C24:  409A         LSLS       R2, R3
+  0x34180C26:  3A01         SUBS       R2, #1
+  0x34180C28:  4011         ANDS       R1, R2
+  0x34180C2A:  4308         ORRS       R0, R1
+  0x34180C2C:  B008         ADD        SP, SP, #32
+  0x34180C2E:  4770         BX         LR
+
+

Section .text.HAL_SYSTICK_Config from blto2_FSBL_lto.o, size=16, align=4

+ +
+
HAL_SYSTICK_Config:
+  0x34180C30:  B580         PUSH       123R7, LR}
+  0x34180C32:  B082         SUB        SP, SP, #8
+  0x34180C34:  9001         STR        R0, [SP, #4]
+  0x34180C36:  9801         LDR        R0, [SP, #4]
+  0x34180C38:  F001 FAC2    BL         SysTick_Config           ; 0x341821C0
+  0x34180C3C:  B002         ADD        SP, SP, #8
+  0x34180C3E:  BD80         POP        123R7, PC}
+
+

Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=1928, align=4

+ +
+
HAL_GPIO_Init:
+  0x34180C40:  B580         PUSH       123R7, LR}
+  0x34180C42:  B090         SUB        SP, SP, #64
+  0x34180C44:  900F         STR        R0, [SP, #60]
+  0x34180C46:  910E         STR        R1, [SP, #56]
+  0x34180C48:  2000         MOVS       R0, #0
+  0x34180C4A:  900D         STR        R0, [SP, #52]
+  0x34180C4C:  980F         LDR        R0, [SP, #60]
+  0x34180C4E:  2100         MOVS       R1, #0
+  0x34180C50:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180C54:  4288         CMP        R0, R1
+  0x34180C56:  F000 80A4    BEQ.W      46L1                      ; 0x34180DA2
+  0x34180C5A:  980F         LDR        R0, [SP, #60]
+  0x34180C5C:  2100         MOVS       R1, #0
+  0x34180C5E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180C62:  4288         CMP        R0, R1
+  0x34180C64:  F000 809D    BEQ.W      46L1                      ; 0x34180DA2
+  0x34180C68:  980F         LDR        R0, [SP, #60]
+  0x34180C6A:  F240 4100    MOVW       R1, #0x0400
+  0x34180C6E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180C72:  4288         CMP        R0, R1
+  0x34180C74:  F000 8095    BEQ.W      46L1                      ; 0x34180DA2
+  0x34180C78:  980F         LDR        R0, [SP, #60]
+  0x34180C7A:  F240 4100    MOVW       R1, #0x0400
+  0x34180C7E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180C82:  4288         CMP        R0, R1
+  0x34180C84:  F000 808D    BEQ.W      46L1                      ; 0x34180DA2
+  0x34180C88:  980F         LDR        R0, [SP, #60]
+  0x34180C8A:  F640 0100    MOVW       R1, #0x0800
+  0x34180C8E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180C92:  4288         CMP        R0, R1
+  0x34180C94:  F000 8085    BEQ.W      46L1                      ; 0x34180DA2
+  0x34180C98:  980F         LDR        R0, [SP, #60]
+  0x34180C9A:  F640 0100    MOVW       R1, #0x0800
+  0x34180C9E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180CA2:  4288         CMP        R0, R1
+  0x34180CA4:  D07D         BEQ        46L1                      ; 0x34180DA2
+  0x34180CA6:  980F         LDR        R0, [SP, #60]
+  0x34180CA8:  F640 4100    MOVW       R1, #0x0C00
+  0x34180CAC:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180CB0:  4288         CMP        R0, R1
+  0x34180CB2:  D076         BEQ        46L1                      ; 0x34180DA2
+  0x34180CB4:  980F         LDR        R0, [SP, #60]
+  0x34180CB6:  F640 4100    MOVW       R1, #0x0C00
+  0x34180CBA:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180CBE:  4288         CMP        R0, R1
+  0x34180CC0:  D06F         BEQ        46L1                      ; 0x34180DA2
+  0x34180CC2:  980F         LDR        R0, [SP, #60]
+  0x34180CC4:  F241 0100    MOVW       R1, #0x1000
+  0x34180CC8:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180CCC:  4288         CMP        R0, R1
+  0x34180CCE:  D068         BEQ        46L1                      ; 0x34180DA2
+  0x34180CD0:  980F         LDR        R0, [SP, #60]
+  0x34180CD2:  F241 0100    MOVW       R1, #0x1000
+  0x34180CD6:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180CDA:  4288         CMP        R0, R1
+  0x34180CDC:  D061         BEQ        46L1                      ; 0x34180DA2
+  0x34180CDE:  980F         LDR        R0, [SP, #60]
+  0x34180CE0:  F241 4100    MOVW       R1, #0x1400
+  0x34180CE4:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180CE8:  4288         CMP        R0, R1
+  0x34180CEA:  D05A         BEQ        46L1                      ; 0x34180DA2
+  0x34180CEC:  980F         LDR        R0, [SP, #60]
+  0x34180CEE:  F241 4100    MOVW       R1, #0x1400
+  0x34180CF2:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180CF6:  4288         CMP        R0, R1
+  0x34180CF8:  D053         BEQ        46L1                      ; 0x34180DA2
+  0x34180CFA:  980F         LDR        R0, [SP, #60]
+  0x34180CFC:  F641 0100    MOVW       R1, #0x1800
+  0x34180D00:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180D04:  4288         CMP        R0, R1
+  0x34180D06:  D04C         BEQ        46L1                      ; 0x34180DA2
+  0x34180D08:  980F         LDR        R0, [SP, #60]
+  0x34180D0A:  F641 0100    MOVW       R1, #0x1800
+  0x34180D0E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180D12:  4288         CMP        R0, R1
+  0x34180D14:  D045         BEQ        46L1                      ; 0x34180DA2
+  0x34180D16:  980F         LDR        R0, [SP, #60]
+  0x34180D18:  F641 4100    MOVW       R1, #0x1C00
+  0x34180D1C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180D20:  4288         CMP        R0, R1
+  0x34180D22:  D03E         BEQ        46L1                      ; 0x34180DA2
+  0x34180D24:  980F         LDR        R0, [SP, #60]
+  0x34180D26:  F641 4100    MOVW       R1, #0x1C00
+  0x34180D2A:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180D2E:  4288         CMP        R0, R1
+  0x34180D30:  D037         BEQ        46L1                      ; 0x34180DA2
+  0x34180D32:  980F         LDR        R0, [SP, #60]
+  0x34180D34:  F243 4100    MOVW       R1, #0x3400
+  0x34180D38:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180D3C:  4288         CMP        R0, R1
+  0x34180D3E:  D030         BEQ        46L1                      ; 0x34180DA2
+  0x34180D40:  980F         LDR        R0, [SP, #60]
+  0x34180D42:  F243 4100    MOVW       R1, #0x3400
+  0x34180D46:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180D4A:  4288         CMP        R0, R1
+  0x34180D4C:  D029         BEQ        46L1                      ; 0x34180DA2
+  0x34180D4E:  980F         LDR        R0, [SP, #60]
+  0x34180D50:  F643 0100    MOVW       R1, #0x3800
+  0x34180D54:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180D58:  4288         CMP        R0, R1
+  0x34180D5A:  D022         BEQ        46L1                      ; 0x34180DA2
+  0x34180D5C:  980F         LDR        R0, [SP, #60]
+  0x34180D5E:  F643 0100    MOVW       R1, #0x3800
+  0x34180D62:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180D66:  4288         CMP        R0, R1
+  0x34180D68:  D01B         BEQ        46L1                      ; 0x34180DA2
+  0x34180D6A:  980F         LDR        R0, [SP, #60]
+  0x34180D6C:  F643 4100    MOVW       R1, #0x3C00
+  0x34180D70:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180D74:  4288         CMP        R0, R1
+  0x34180D76:  D014         BEQ        46L1                      ; 0x34180DA2
+  0x34180D78:  980F         LDR        R0, [SP, #60]
+  0x34180D7A:  F643 4100    MOVW       R1, #0x3C00
+  0x34180D7E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180D82:  4288         CMP        R0, R1
+  0x34180D84:  D00D         BEQ        46L1                      ; 0x34180DA2
+  0x34180D86:  980F         LDR        R0, [SP, #60]
+  0x34180D88:  F244 0100    MOVW       R1, #0x4000
+  0x34180D8C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180D90:  4288         CMP        R0, R1
+  0x34180D92:  D006         BEQ        46L1                      ; 0x34180DA2
+  0x34180D94:  980F         LDR        R0, [SP, #60]
+  0x34180D96:  F244 0100    MOVW       R1, #0x4000
+  0x34180D9A:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180D9E:  4288         CMP        R0, R1
+  0x34180DA0:  D100         BNE        46L2                      ; 0x34180DA4
+
.L1:
+  0x34180DA2:  E006         B          46L3                      ; 0x34180DB2
+
.L2:
+  0x34180DA4:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x34180DA8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34180DAC:  21AD         MOVS       R1, #173
+  0x34180DAE:  F001 F845    BL         assert_failed            ; 0x34181E3C
+
.L3:
+  0x34180DB2:  980E         LDR        R0, [SP, #56]
+  0x34180DB4:  8800         LDRH       R0, [R0]
+  0x34180DB6:  B118         CBZ        R0, .L4                  ; 0x34180DC0
+  0x34180DB8:  980E         LDR        R0, [SP, #56]
+  0x34180DBA:  8840         LDRH       R0, [R0, #2]
+  0x34180DBC:  B900         CBNZ       R0, .L4                  ; 0x34180DC0
+  0x34180DBE:  E006         B          46L5                      ; 0x34180DCE
+
.L4:
+  0x34180DC0:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x34180DC4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34180DC8:  21AE         MOVS       R1, #174
+  0x34180DCA:  F001 F837    BL         assert_failed            ; 0x34181E3C
+
.L5:
+  0x34180DCE:  980E         LDR        R0, [SP, #56]
+  0x34180DD0:  6840         LDR        R0, [R0, #4]
+  0x34180DD2:  B388         CBZ        R0, .L6                  ; 0x34180E38
+  0x34180DD4:  980E         LDR        R0, [SP, #56]
+  0x34180DD6:  6840         LDR        R0, [R0, #4]
+  0x34180DD8:  2801         CMP        R0, #1
+  0x34180DDA:  D02D         BEQ        46L6                      ; 0x34180E38
+  0x34180DDC:  980E         LDR        R0, [SP, #56]
+  0x34180DDE:  6840         LDR        R0, [R0, #4]
+  0x34180DE0:  2811         CMP        R0, #17
+  0x34180DE2:  D029         BEQ        46L6                      ; 0x34180E38
+  0x34180DE4:  980E         LDR        R0, [SP, #56]
+  0x34180DE6:  6840         LDR        R0, [R0, #4]
+  0x34180DE8:  2802         CMP        R0, #2
+  0x34180DEA:  D025         BEQ        46L6                      ; 0x34180E38
+  0x34180DEC:  980E         LDR        R0, [SP, #56]
+  0x34180DEE:  6840         LDR        R0, [R0, #4]
+  0x34180DF0:  2812         CMP        R0, #18
+  0x34180DF2:  D021         BEQ        46L6                      ; 0x34180E38
+  0x34180DF4:  980E         LDR        R0, [SP, #56]
+  0x34180DF6:  6840         LDR        R0, [R0, #4]
+  0x34180DF8:  F5B0 1F88    CMP.W      R0, #0x110000
+  0x34180DFC:  D01C         BEQ        46L6                      ; 0x34180E38
+  0x34180DFE:  980E         LDR        R0, [SP, #56]
+  0x34180E00:  6840         LDR        R0, [R0, #4]
+  0x34180E02:  F5B0 1F04    CMP.W      R0, #0x210000
+  0x34180E06:  D017         BEQ        46L6                      ; 0x34180E38
+  0x34180E08:  980E         LDR        R0, [SP, #56]
+  0x34180E0A:  6840         LDR        R0, [R0, #4]
+  0x34180E0C:  F5B0 1F44    CMP.W      R0, #0x310000
+  0x34180E10:  D012         BEQ        46L6                      ; 0x34180E38
+  0x34180E12:  980E         LDR        R0, [SP, #56]
+  0x34180E14:  6840         LDR        R0, [R0, #4]
+  0x34180E16:  F5B0 1F90    CMP.W      R0, #0x120000
+  0x34180E1A:  D00D         BEQ        46L6                      ; 0x34180E38
+  0x34180E1C:  980E         LDR        R0, [SP, #56]
+  0x34180E1E:  6840         LDR        R0, [R0, #4]
+  0x34180E20:  F5B0 1F08    CMP.W      R0, #0x220000
+  0x34180E24:  D008         BEQ        46L6                      ; 0x34180E38
+  0x34180E26:  980E         LDR        R0, [SP, #56]
+  0x34180E28:  6840         LDR        R0, [R0, #4]
+  0x34180E2A:  F5B0 1F48    CMP.W      R0, #0x320000
+  0x34180E2E:  D003         BEQ        46L6                      ; 0x34180E38
+  0x34180E30:  980E         LDR        R0, [SP, #56]
+  0x34180E32:  6840         LDR        R0, [R0, #4]
+  0x34180E34:  2803         CMP        R0, #3
+  0x34180E36:  D100         BNE        46L7                      ; 0x34180E3A
+
.L6:
+  0x34180E38:  E006         B          46L8                      ; 0x34180E48
+
.L7:
+  0x34180E3A:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x34180E3E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34180E42:  21AF         MOVS       R1, #175
+  0x34180E44:  F000 FFFA    BL         assert_failed            ; 0x34181E3C
+
.L8:
+  0x34180E48:  980E         LDR        R0, [SP, #56]
+  0x34180E4A:  6800         LDR        R0, [R0]
+  0x34180E4C:  990D         LDR        R1, [SP, #52]
+  0x34180E4E:  40C8         LSRS       R0, R1
+  0x34180E50:  2800         CMP        R0, #0
+  0x34180E52:  F000 82B7    BEQ.W      46L52                     ; 0x341813C4
+  0x34180E56:  980E         LDR        R0, [SP, #56]
+  0x34180E58:  6800         LDR        R0, [R0]
+  0x34180E5A:  9A0D         LDR        R2, [SP, #52]
+  0x34180E5C:  2101         MOVS       R1, #1
+  0x34180E5E:  4091         LSLS       R1, R2
+  0x34180E60:  4008         ANDS       R0, R1
+  0x34180E62:  900C         STR        R0, [SP, #48]
+  0x34180E64:  980C         LDR        R0, [SP, #48]
+  0x34180E66:  2800         CMP        R0, #0
+  0x34180E68:  F000 82A8    BEQ.W      46L51                     ; 0x341813BC
+  0x34180E6C:  980E         LDR        R0, [SP, #56]
+  0x34180E6E:  6840         LDR        R0, [R0, #4]
+  0x34180E70:  F000 0003    AND        R0, R0, #3
+  0x34180E74:  2801         CMP        R0, #1
+  0x34180E76:  D005         BEQ        46L9                      ; 0x34180E84
+  0x34180E78:  980E         LDR        R0, [SP, #56]
+  0x34180E7A:  6840         LDR        R0, [R0, #4]
+  0x34180E7C:  F000 0003    AND        R0, R0, #3
+  0x34180E80:  2802         CMP        R0, #2
+  0x34180E82:  D144         BNE        46L13                     ; 0x34180F0E
+
.L9:
+  0x34180E84:  980E         LDR        R0, [SP, #56]
+  0x34180E86:  68C0         LDR        R0, [R0, #12]
+  0x34180E88:  B158         CBZ        R0, .L10                 ; 0x34180EA2
+  0x34180E8A:  980E         LDR        R0, [SP, #56]
+  0x34180E8C:  68C0         LDR        R0, [R0, #12]
+  0x34180E8E:  2801         CMP        R0, #1
+  0x34180E90:  D007         BEQ        46L10                     ; 0x34180EA2
+  0x34180E92:  980E         LDR        R0, [SP, #56]
+  0x34180E94:  68C0         LDR        R0, [R0, #12]
+  0x34180E96:  2802         CMP        R0, #2
+  0x34180E98:  D003         BEQ        46L10                     ; 0x34180EA2
+  0x34180E9A:  980E         LDR        R0, [SP, #56]
+  0x34180E9C:  68C0         LDR        R0, [R0, #12]
+  0x34180E9E:  2803         CMP        R0, #3
+  0x34180EA0:  D100         BNE        46L11                     ; 0x34180EA4
+
.L10:
+  0x34180EA2:  E006         B          46L12                     ; 0x34180EB2
+
.L11:
+  0x34180EA4:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x34180EA8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34180EAC:  21BE         MOVS       R1, #190
+  0x34180EAE:  F000 FFC5    BL         assert_failed            ; 0x34181E3C
+
.L12:
+  0x34180EB2:  980F         LDR        R0, [SP, #60]
+  0x34180EB4:  6880         LDR        R0, [R0, #8]
+  0x34180EB6:  900B         STR        R0, [SP, #44]
+  0x34180EB8:  980D         LDR        R0, [SP, #52]
+  0x34180EBA:  0041         LSLS       R1, R0, #1
+  0x34180EBC:  2003         MOVS       R0, #3
+  0x34180EBE:  FA00 F101    LSL.W      R1, R0, R1
+  0x34180EC2:  980B         LDR        R0, [SP, #44]
+  0x34180EC4:  4388         BICS       R0, R1
+  0x34180EC6:  900B         STR        R0, [SP, #44]
+  0x34180EC8:  980E         LDR        R0, [SP, #56]
+  0x34180ECA:  68C0         LDR        R0, [R0, #12]
+  0x34180ECC:  990D         LDR        R1, [SP, #52]
+  0x34180ECE:  0049         LSLS       R1, R1, #1
+  0x34180ED0:  FA00 F101    LSL.W      R1, R0, R1
+  0x34180ED4:  980B         LDR        R0, [SP, #44]
+  0x34180ED6:  4308         ORRS       R0, R1
+  0x34180ED8:  900B         STR        R0, [SP, #44]
+  0x34180EDA:  980B         LDR        R0, [SP, #44]
+  0x34180EDC:  990F         LDR        R1, [SP, #60]
+  0x34180EDE:  6088         STR        R0, [R1, #8]
+  0x34180EE0:  980F         LDR        R0, [SP, #60]
+  0x34180EE2:  6840         LDR        R0, [R0, #4]
+  0x34180EE4:  900B         STR        R0, [SP, #44]
+  0x34180EE6:  990D         LDR        R1, [SP, #52]
+  0x34180EE8:  2001         MOVS       R0, #1
+  0x34180EEA:  FA00 F101    LSL.W      R1, R0, R1
+  0x34180EEE:  980B         LDR        R0, [SP, #44]
+  0x34180EF0:  4388         BICS       R0, R1
+  0x34180EF2:  900B         STR        R0, [SP, #44]
+  0x34180EF4:  980E         LDR        R0, [SP, #56]
+  0x34180EF6:  6840         LDR        R0, [R0, #4]
+  0x34180EF8:  F3C0 1000    UBFX       R0, R0, #4, #1
+  0x34180EFC:  990D         LDR        R1, [SP, #52]
+  0x34180EFE:  FA00 F101    LSL.W      R1, R0, R1
+  0x34180F02:  980B         LDR        R0, [SP, #44]
+  0x34180F04:  4308         ORRS       R0, R1
+  0x34180F06:  900B         STR        R0, [SP, #44]
+  0x34180F08:  980B         LDR        R0, [SP, #44]
+  0x34180F0A:  990F         LDR        R1, [SP, #60]
+  0x34180F0C:  6048         STR        R0, [R1, #4]
+
.L13:
+  0x34180F0E:  980E         LDR        R0, [SP, #56]
+  0x34180F10:  6840         LDR        R0, [R0, #4]
+  0x34180F12:  43C0         MVNS       R0, R0
+  0x34180F14:  0780         LSLS       R0, R0, #30
+  0x34180F16:  B940         CBNZ       R0, .L14                 ; 0x34180F2A
+  0x34180F18:  980E         LDR        R0, [SP, #56]
+  0x34180F1A:  6840         LDR        R0, [R0, #4]
+  0x34180F1C:  43C0         MVNS       R0, R0
+  0x34180F1E:  0780         LSLS       R0, R0, #30
+  0x34180F20:  BB68         CBNZ       R0, .L18                 ; 0x34180F7E
+  0x34180F22:  980E         LDR        R0, [SP, #56]
+  0x34180F24:  6880         LDR        R0, [R0, #8]
+  0x34180F26:  2801         CMP        R0, #1
+  0x34180F28:  D029         BEQ        46L18                     ; 0x34180F7E
+
.L14:
+  0x34180F2A:  980E         LDR        R0, [SP, #56]
+  0x34180F2C:  6880         LDR        R0, [R0, #8]
+  0x34180F2E:  B138         CBZ        R0, .L15                 ; 0x34180F40
+  0x34180F30:  980E         LDR        R0, [SP, #56]
+  0x34180F32:  6880         LDR        R0, [R0, #8]
+  0x34180F34:  2801         CMP        R0, #1
+  0x34180F36:  D003         BEQ        46L15                     ; 0x34180F40
+  0x34180F38:  980E         LDR        R0, [SP, #56]
+  0x34180F3A:  6880         LDR        R0, [R0, #8]
+  0x34180F3C:  2802         CMP        R0, #2
+  0x34180F3E:  D100         BNE        46L16                     ; 0x34180F42
+
.L15:
+  0x34180F40:  E006         B          46L17                     ; 0x34180F50
+
.L16:
+  0x34180F42:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x34180F46:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34180F4A:  21D1         MOVS       R1, #209
+  0x34180F4C:  F000 FF76    BL         assert_failed            ; 0x34181E3C
+
.L17:
+  0x34180F50:  980F         LDR        R0, [SP, #60]
+  0x34180F52:  68C0         LDR        R0, [R0, #12]
+  0x34180F54:  900B         STR        R0, [SP, #44]
+  0x34180F56:  980D         LDR        R0, [SP, #52]
+  0x34180F58:  0041         LSLS       R1, R0, #1
+  0x34180F5A:  2003         MOVS       R0, #3
+  0x34180F5C:  FA00 F101    LSL.W      R1, R0, R1
+  0x34180F60:  980B         LDR        R0, [SP, #44]
+  0x34180F62:  4388         BICS       R0, R1
+  0x34180F64:  900B         STR        R0, [SP, #44]
+  0x34180F66:  980E         LDR        R0, [SP, #56]
+  0x34180F68:  6880         LDR        R0, [R0, #8]
+  0x34180F6A:  990D         LDR        R1, [SP, #52]
+  0x34180F6C:  0049         LSLS       R1, R1, #1
+  0x34180F6E:  FA00 F101    LSL.W      R1, R0, R1
+  0x34180F72:  980B         LDR        R0, [SP, #44]
+  0x34180F74:  4308         ORRS       R0, R1
+  0x34180F76:  900B         STR        R0, [SP, #44]
+  0x34180F78:  980B         LDR        R0, [SP, #44]
+  0x34180F7A:  990F         LDR        R1, [SP, #60]
+  0x34180F7C:  60C8         STR        R0, [R1, #12]
+
.L18:
+  0x34180F7E:  980E         LDR        R0, [SP, #56]
+  0x34180F80:  6840         LDR        R0, [R0, #4]
+  0x34180F82:  F000 0003    AND        R0, R0, #3
+  0x34180F86:  2802         CMP        R0, #2
+  0x34180F88:  F040 80E4    BNE.W      46L24                     ; 0x34181154
+  0x34180F8C:  980F         LDR        R0, [SP, #60]
+  0x34180F8E:  2100         MOVS       R1, #0
+  0x34180F90:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180F94:  4288         CMP        R0, R1
+  0x34180F96:  F000 80A4    BEQ.W      46L19                     ; 0x341810E2
+  0x34180F9A:  980F         LDR        R0, [SP, #60]
+  0x34180F9C:  2100         MOVS       R1, #0
+  0x34180F9E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180FA2:  4288         CMP        R0, R1
+  0x34180FA4:  F000 809D    BEQ.W      46L19                     ; 0x341810E2
+  0x34180FA8:  980F         LDR        R0, [SP, #60]
+  0x34180FAA:  F240 4100    MOVW       R1, #0x0400
+  0x34180FAE:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180FB2:  4288         CMP        R0, R1
+  0x34180FB4:  F000 8095    BEQ.W      46L19                     ; 0x341810E2
+  0x34180FB8:  980F         LDR        R0, [SP, #60]
+  0x34180FBA:  F240 4100    MOVW       R1, #0x0400
+  0x34180FBE:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180FC2:  4288         CMP        R0, R1
+  0x34180FC4:  F000 808D    BEQ.W      46L19                     ; 0x341810E2
+  0x34180FC8:  980F         LDR        R0, [SP, #60]
+  0x34180FCA:  F640 0100    MOVW       R1, #0x0800
+  0x34180FCE:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180FD2:  4288         CMP        R0, R1
+  0x34180FD4:  F000 8085    BEQ.W      46L19                     ; 0x341810E2
+  0x34180FD8:  980F         LDR        R0, [SP, #60]
+  0x34180FDA:  F640 0100    MOVW       R1, #0x0800
+  0x34180FDE:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180FE2:  4288         CMP        R0, R1
+  0x34180FE4:  D07D         BEQ        46L19                     ; 0x341810E2
+  0x34180FE6:  980F         LDR        R0, [SP, #60]
+  0x34180FE8:  F640 4100    MOVW       R1, #0x0C00
+  0x34180FEC:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180FF0:  4288         CMP        R0, R1
+  0x34180FF2:  D076         BEQ        46L19                     ; 0x341810E2
+  0x34180FF4:  980F         LDR        R0, [SP, #60]
+  0x34180FF6:  F640 4100    MOVW       R1, #0x0C00
+  0x34180FFA:  F2C4 6102    MOVT       R1, #0x4602
+  0x34180FFE:  4288         CMP        R0, R1
+  0x34181000:  D06F         BEQ        46L19                     ; 0x341810E2
+  0x34181002:  980F         LDR        R0, [SP, #60]
+  0x34181004:  F241 0100    MOVW       R1, #0x1000
+  0x34181008:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418100C:  4288         CMP        R0, R1
+  0x3418100E:  D068         BEQ        46L19                     ; 0x341810E2
+  0x34181010:  980F         LDR        R0, [SP, #60]
+  0x34181012:  F241 0100    MOVW       R1, #0x1000
+  0x34181016:  F2C4 6102    MOVT       R1, #0x4602
+  0x3418101A:  4288         CMP        R0, R1
+  0x3418101C:  D061         BEQ        46L19                     ; 0x341810E2
+  0x3418101E:  980F         LDR        R0, [SP, #60]
+  0x34181020:  F241 4100    MOVW       R1, #0x1400
+  0x34181024:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181028:  4288         CMP        R0, R1
+  0x3418102A:  D05A         BEQ        46L19                     ; 0x341810E2
+  0x3418102C:  980F         LDR        R0, [SP, #60]
+  0x3418102E:  F241 4100    MOVW       R1, #0x1400
+  0x34181032:  F2C4 6102    MOVT       R1, #0x4602
+  0x34181036:  4288         CMP        R0, R1
+  0x34181038:  D053         BEQ        46L19                     ; 0x341810E2
+  0x3418103A:  980F         LDR        R0, [SP, #60]
+  0x3418103C:  F641 0100    MOVW       R1, #0x1800
+  0x34181040:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181044:  4288         CMP        R0, R1
+  0x34181046:  D04C         BEQ        46L19                     ; 0x341810E2
+  0x34181048:  980F         LDR        R0, [SP, #60]
+  0x3418104A:  F641 0100    MOVW       R1, #0x1800
+  0x3418104E:  F2C4 6102    MOVT       R1, #0x4602
+  0x34181052:  4288         CMP        R0, R1
+  0x34181054:  D045         BEQ        46L19                     ; 0x341810E2
+  0x34181056:  980F         LDR        R0, [SP, #60]
+  0x34181058:  F641 4100    MOVW       R1, #0x1C00
+  0x3418105C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181060:  4288         CMP        R0, R1
+  0x34181062:  D03E         BEQ        46L19                     ; 0x341810E2
+  0x34181064:  980F         LDR        R0, [SP, #60]
+  0x34181066:  F641 4100    MOVW       R1, #0x1C00
+  0x3418106A:  F2C4 6102    MOVT       R1, #0x4602
+  0x3418106E:  4288         CMP        R0, R1
+  0x34181070:  D037         BEQ        46L19                     ; 0x341810E2
+  0x34181072:  980F         LDR        R0, [SP, #60]
+  0x34181074:  F243 4100    MOVW       R1, #0x3400
+  0x34181078:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418107C:  4288         CMP        R0, R1
+  0x3418107E:  D030         BEQ        46L19                     ; 0x341810E2
+  0x34181080:  980F         LDR        R0, [SP, #60]
+  0x34181082:  F243 4100    MOVW       R1, #0x3400
+  0x34181086:  F2C4 6102    MOVT       R1, #0x4602
+  0x3418108A:  4288         CMP        R0, R1
+  0x3418108C:  D029         BEQ        46L19                     ; 0x341810E2
+  0x3418108E:  980F         LDR        R0, [SP, #60]
+  0x34181090:  F643 0100    MOVW       R1, #0x3800
+  0x34181094:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181098:  4288         CMP        R0, R1
+  0x3418109A:  D022         BEQ        46L19                     ; 0x341810E2
+  0x3418109C:  980F         LDR        R0, [SP, #60]
+  0x3418109E:  F643 0100    MOVW       R1, #0x3800
+  0x341810A2:  F2C4 6102    MOVT       R1, #0x4602
+  0x341810A6:  4288         CMP        R0, R1
+  0x341810A8:  D01B         BEQ        46L19                     ; 0x341810E2
+  0x341810AA:  980F         LDR        R0, [SP, #60]
+  0x341810AC:  F643 4100    MOVW       R1, #0x3C00
+  0x341810B0:  F2C5 6102    MOVT       R1, #0x5602
+  0x341810B4:  4288         CMP        R0, R1
+  0x341810B6:  D014         BEQ        46L19                     ; 0x341810E2
+  0x341810B8:  980F         LDR        R0, [SP, #60]
+  0x341810BA:  F643 4100    MOVW       R1, #0x3C00
+  0x341810BE:  F2C4 6102    MOVT       R1, #0x4602
+  0x341810C2:  4288         CMP        R0, R1
+  0x341810C4:  D00D         BEQ        46L19                     ; 0x341810E2
+  0x341810C6:  980F         LDR        R0, [SP, #60]
+  0x341810C8:  F244 0100    MOVW       R1, #0x4000
+  0x341810CC:  F2C5 6102    MOVT       R1, #0x5602
+  0x341810D0:  4288         CMP        R0, R1
+  0x341810D2:  D006         BEQ        46L19                     ; 0x341810E2
+  0x341810D4:  980F         LDR        R0, [SP, #60]
+  0x341810D6:  F244 0100    MOVW       R1, #0x4000
+  0x341810DA:  F2C4 6102    MOVT       R1, #0x4602
+  0x341810DE:  4288         CMP        R0, R1
+  0x341810E0:  D100         BNE        46L20                     ; 0x341810E4
+
.L19:
+  0x341810E2:  E006         B          46L21                     ; 0x341810F2
+
.L20:
+  0x341810E4:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x341810E8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x341810EC:  21DE         MOVS       R1, #222
+  0x341810EE:  F000 FEA5    BL         assert_failed            ; 0x34181E3C
+
.L21:
+  0x341810F2:  980E         LDR        R0, [SP, #56]
+  0x341810F4:  6900         LDR        R0, [R0, #16]
+  0x341810F6:  280F         CMP        R0, #15
+  0x341810F8:  D800         BHI        46L22                     ; 0x341810FC
+  0x341810FA:  E006         B          46L23                     ; 0x3418110A
+
.L22:
+  0x341810FC:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x34181100:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34181104:  21DF         MOVS       R1, #223
+  0x34181106:  F000 FE99    BL         assert_failed            ; 0x34181E3C
+
.L23:
+  0x3418110A:  980F         LDR        R0, [SP, #60]
+  0x3418110C:  990D         LDR        R1, [SP, #52]
+  0x3418110E:  F06F 0203    MVN        R2, #3
+  0x34181112:  EA02 0151    AND.W      R1, R2, R1, LSR #1
+  0x34181116:  4408         ADD        R0, R1
+  0x34181118:  6A00         LDR        R0, [R0, #32]
+  0x3418111A:  900B         STR        R0, [SP, #44]
+  0x3418111C:  980D         LDR        R0, [SP, #52]
+  0x3418111E:  F000 0007    AND        R0, R0, #7
+  0x34181122:  0081         LSLS       R1, R0, #2
+  0x34181124:  200F         MOVS       R0, #15
+  0x34181126:  FA00 F101    LSL.W      R1, R0, R1
+  0x3418112A:  980B         LDR        R0, [SP, #44]
+  0x3418112C:  4388         BICS       R0, R1
+  0x3418112E:  900B         STR        R0, [SP, #44]
+  0x34181130:  980E         LDR        R0, [SP, #56]
+  0x34181132:  6900         LDR        R0, [R0, #16]
+  0x34181134:  990D         LDR        R1, [SP, #52]
+  0x34181136:  F001 0107    AND        R1, R1, #7
+  0x3418113A:  0089         LSLS       R1, R1, #2
+  0x3418113C:  FA00 F101    LSL.W      R1, R0, R1
+  0x34181140:  980B         LDR        R0, [SP, #44]
+  0x34181142:  4308         ORRS       R0, R1
+  0x34181144:  900B         STR        R0, [SP, #44]
+  0x34181146:  980B         LDR        R0, [SP, #44]
+  0x34181148:  990F         LDR        R1, [SP, #60]
+  0x3418114A:  9B0D         LDR        R3, [SP, #52]
+  0x3418114C:  EA02 0253    AND.W      R2, R2, R3, LSR #1
+  0x34181150:  4411         ADD        R1, R2
+  0x34181152:  6208         STR        R0, [R1, #32]
+
.L24:
+  0x34181154:  980F         LDR        R0, [SP, #60]
+  0x34181156:  6800         LDR        R0, [R0]
+  0x34181158:  900B         STR        R0, [SP, #44]
+  0x3418115A:  980D         LDR        R0, [SP, #52]
+  0x3418115C:  0041         LSLS       R1, R0, #1
+  0x3418115E:  2003         MOVS       R0, #3
+  0x34181160:  FA00 F101    LSL.W      R1, R0, R1
+  0x34181164:  980B         LDR        R0, [SP, #44]
+  0x34181166:  4388         BICS       R0, R1
+  0x34181168:  900B         STR        R0, [SP, #44]
+  0x3418116A:  980E         LDR        R0, [SP, #56]
+  0x3418116C:  6840         LDR        R0, [R0, #4]
+  0x3418116E:  F000 0003    AND        R0, R0, #3
+  0x34181172:  990D         LDR        R1, [SP, #52]
+  0x34181174:  0049         LSLS       R1, R1, #1
+  0x34181176:  FA00 F101    LSL.W      R1, R0, R1
+  0x3418117A:  980B         LDR        R0, [SP, #44]
+  0x3418117C:  4308         ORRS       R0, R1
+  0x3418117E:  900B         STR        R0, [SP, #44]
+  0x34181180:  980B         LDR        R0, [SP, #44]
+  0x34181182:  990F         LDR        R1, [SP, #60]
+  0x34181184:  6008         STR        R0, [R1]
+  0x34181186:  980E         LDR        R0, [SP, #56]
+  0x34181188:  7980         LDRB       R0, [R0, #6]
+  0x3418118A:  0780         LSLS       R0, R0, #30
+  0x3418118C:  2800         CMP        R0, #0
+  0x3418118E:  F000 8115    BEQ.W      46L51                     ; 0x341813BC
+  0x34181192:  980D         LDR        R0, [SP, #52]
+  0x34181194:  F020 0003    BIC        R0, R0, #3
+  0x34181198:  F245 0160    MOVW       R1, #0x5060
+  0x3418119C:  F2C5 6102    MOVT       R1, #0x5602
+  0x341811A0:  5840         LDR        R0, [R0, R1]
+  0x341811A2:  900B         STR        R0, [SP, #44]
+  0x341811A4:  980D         LDR        R0, [SP, #52]
+  0x341811A6:  F000 0003    AND        R0, R0, #3
+  0x341811AA:  00C1         LSLS       R1, R0, #3
+  0x341811AC:  200F         MOVS       R0, #15
+  0x341811AE:  FA00 F101    LSL.W      R1, R0, R1
+  0x341811B2:  980B         LDR        R0, [SP, #44]
+  0x341811B4:  4388         BICS       R0, R1
+  0x341811B6:  900B         STR        R0, [SP, #44]
+  0x341811B8:  980F         LDR        R0, [SP, #60]
+  0x341811BA:  2100         MOVS       R1, #0
+  0x341811BC:  F2C5 6102    MOVT       R1, #0x5602
+  0x341811C0:  4288         CMP        R0, R1
+  0x341811C2:  D102         BNE        46L25                     ; 0x341811CA
+  0x341811C4:  2000         MOVS       R0, #0
+  0x341811C6:  900A         STR        R0, [SP, #40]
+  0x341811C8:  E082         B          46L46                     ; 0x341812D0
+
.L25:
+  0x341811CA:  980F         LDR        R0, [SP, #60]
+  0x341811CC:  F240 4100    MOVW       R1, #0x0400
+  0x341811D0:  F2C5 6102    MOVT       R1, #0x5602
+  0x341811D4:  4288         CMP        R0, R1
+  0x341811D6:  D102         BNE        46L26                     ; 0x341811DE
+  0x341811D8:  2001         MOVS       R0, #1
+  0x341811DA:  9009         STR        R0, [SP, #36]
+  0x341811DC:  E076         B          46L45                     ; 0x341812CC
+
.L26:
+  0x341811DE:  980F         LDR        R0, [SP, #60]
+  0x341811E0:  F640 0100    MOVW       R1, #0x0800
+  0x341811E4:  F2C5 6102    MOVT       R1, #0x5602
+  0x341811E8:  4288         CMP        R0, R1
+  0x341811EA:  D102         BNE        46L27                     ; 0x341811F2
+  0x341811EC:  2002         MOVS       R0, #2
+  0x341811EE:  9008         STR        R0, [SP, #32]
+  0x341811F0:  E06A         B          46L44                     ; 0x341812C8
+
.L27:
+  0x341811F2:  980F         LDR        R0, [SP, #60]
+  0x341811F4:  F640 4100    MOVW       R1, #0x0C00
+  0x341811F8:  F2C5 6102    MOVT       R1, #0x5602
+  0x341811FC:  4288         CMP        R0, R1
+  0x341811FE:  D102         BNE        46L28                     ; 0x34181206
+  0x34181200:  2003         MOVS       R0, #3
+  0x34181202:  9007         STR        R0, [SP, #28]
+  0x34181204:  E05E         B          46L43                     ; 0x341812C4
+
.L28:
+  0x34181206:  980F         LDR        R0, [SP, #60]
+  0x34181208:  F241 0100    MOVW       R1, #0x1000
+  0x3418120C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181210:  4288         CMP        R0, R1
+  0x34181212:  D102         BNE        46L29                     ; 0x3418121A
+  0x34181214:  2004         MOVS       R0, #4
+  0x34181216:  9006         STR        R0, [SP, #24]
+  0x34181218:  E052         B          46L42                     ; 0x341812C0
+
.L29:
+  0x3418121A:  980F         LDR        R0, [SP, #60]
+  0x3418121C:  F241 4100    MOVW       R1, #0x1400
+  0x34181220:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181224:  4288         CMP        R0, R1
+  0x34181226:  D102         BNE        46L30                     ; 0x3418122E
+  0x34181228:  2005         MOVS       R0, #5
+  0x3418122A:  9005         STR        R0, [SP, #20]
+  0x3418122C:  E046         B          46L41                     ; 0x341812BC
+
.L30:
+  0x3418122E:  980F         LDR        R0, [SP, #60]
+  0x34181230:  F641 0100    MOVW       R1, #0x1800
+  0x34181234:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181238:  4288         CMP        R0, R1
+  0x3418123A:  D102         BNE        46L31                     ; 0x34181242
+  0x3418123C:  2006         MOVS       R0, #6
+  0x3418123E:  9004         STR        R0, [SP, #16]
+  0x34181240:  E03A         B          46L40                     ; 0x341812B8
+
.L31:
+  0x34181242:  980F         LDR        R0, [SP, #60]
+  0x34181244:  F641 4100    MOVW       R1, #0x1C00
+  0x34181248:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418124C:  4288         CMP        R0, R1
+  0x3418124E:  D102         BNE        46L32                     ; 0x34181256
+  0x34181250:  2007         MOVS       R0, #7
+  0x34181252:  9003         STR        R0, [SP, #12]
+  0x34181254:  E02E         B          46L39                     ; 0x341812B4
+
.L32:
+  0x34181256:  980F         LDR        R0, [SP, #60]
+  0x34181258:  F243 4100    MOVW       R1, #0x3400
+  0x3418125C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181260:  4288         CMP        R0, R1
+  0x34181262:  D102         BNE        46L33                     ; 0x3418126A
+  0x34181264:  2008         MOVS       R0, #8
+  0x34181266:  9002         STR        R0, [SP, #8]
+  0x34181268:  E022         B          46L38                     ; 0x341812B0
+
.L33:
+  0x3418126A:  980F         LDR        R0, [SP, #60]
+  0x3418126C:  F643 0100    MOVW       R1, #0x3800
+  0x34181270:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181274:  4288         CMP        R0, R1
+  0x34181276:  D102         BNE        46L34                     ; 0x3418127E
+  0x34181278:  2009         MOVS       R0, #9
+  0x3418127A:  9001         STR        R0, [SP, #4]
+  0x3418127C:  E016         B          46L37                     ; 0x341812AC
+
.L34:
+  0x3418127E:  980F         LDR        R0, [SP, #60]
+  0x34181280:  F643 4100    MOVW       R1, #0x3C00
+  0x34181284:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181288:  4288         CMP        R0, R1
+  0x3418128A:  D102         BNE        46L35                     ; 0x34181292
+  0x3418128C:  200A         MOVS       R0, #10
+  0x3418128E:  9000         STR        R0, [SP, #0]
+  0x34181290:  E00A         B          46L36                     ; 0x341812A8
+
.L35:
+  0x34181292:  980F         LDR        R0, [SP, #60]
+  0x34181294:  F244 0100    MOVW       R1, #0x4000
+  0x34181298:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418129C:  4288         CMP        R0, R1
+  0x3418129E:  F04F 0010    MOV.W      R0, #16
+  0x341812A2:  BF08         IT         EQ
+  0x341812A4:  200B         MOVEQ      R0, #11
+  0x341812A6:  9000         STR        R0, [SP, #0]
+
.L36:
+  0x341812A8:  9800         LDR        R0, [SP, #0]
+  0x341812AA:  9001         STR        R0, [SP, #4]
+
.L37:
+  0x341812AC:  9801         LDR        R0, [SP, #4]
+  0x341812AE:  9002         STR        R0, [SP, #8]
+
.L38:
+  0x341812B0:  9802         LDR        R0, [SP, #8]
+  0x341812B2:  9003         STR        R0, [SP, #12]
+
.L39:
+  0x341812B4:  9803         LDR        R0, [SP, #12]
+  0x341812B6:  9004         STR        R0, [SP, #16]
+
.L40:
+  0x341812B8:  9804         LDR        R0, [SP, #16]
+  0x341812BA:  9005         STR        R0, [SP, #20]
+
.L41:
+  0x341812BC:  9805         LDR        R0, [SP, #20]
+  0x341812BE:  9006         STR        R0, [SP, #24]
+
.L42:
+  0x341812C0:  9806         LDR        R0, [SP, #24]
+  0x341812C2:  9007         STR        R0, [SP, #28]
+
.L43:
+  0x341812C4:  9807         LDR        R0, [SP, #28]
+  0x341812C6:  9008         STR        R0, [SP, #32]
+
.L44:
+  0x341812C8:  9808         LDR        R0, [SP, #32]
+  0x341812CA:  9009         STR        R0, [SP, #36]
+
.L45:
+  0x341812CC:  9809         LDR        R0, [SP, #36]
+  0x341812CE:  900A         STR        R0, [SP, #40]
+
.L46:
+  0x341812D0:  980A         LDR        R0, [SP, #40]
+  0x341812D2:  990D         LDR        R1, [SP, #52]
+  0x341812D4:  F001 0103    AND        R1, R1, #3
+  0x341812D8:  00C9         LSLS       R1, R1, #3
+  0x341812DA:  FA00 F101    LSL.W      R1, R0, R1
+  0x341812DE:  980B         LDR        R0, [SP, #44]
+  0x341812E0:  4308         ORRS       R0, R1
+  0x341812E2:  900B         STR        R0, [SP, #44]
+  0x341812E4:  980B         LDR        R0, [SP, #44]
+  0x341812E6:  990D         LDR        R1, [SP, #52]
+  0x341812E8:  F021 0103    BIC        R1, R1, #3
+  0x341812EC:  F245 0260    MOVW       R2, #0x5060
+  0x341812F0:  F2C5 6202    MOVT       R2, #0x5602
+  0x341812F4:  5088         STR        R0, [R1, R2]
+  0x341812F6:  F245 0080    MOVW       R0, #0x5080
+  0x341812FA:  F2C5 6002    MOVT       R0, #0x5602
+  0x341812FE:  6800         LDR        R0, [R0]
+  0x34181300:  900B         STR        R0, [SP, #44]
+  0x34181302:  990C         LDR        R1, [SP, #48]
+  0x34181304:  980B         LDR        R0, [SP, #44]
+  0x34181306:  4388         BICS       R0, R1
+  0x34181308:  900B         STR        R0, [SP, #44]
+  0x3418130A:  980E         LDR        R0, [SP, #56]
+  0x3418130C:  7980         LDRB       R0, [R0, #6]
+  0x3418130E:  07C0         LSLS       R0, R0, #31
+  0x34181310:  B118         CBZ        R0, .L47                 ; 0x3418131A
+  0x34181312:  990C         LDR        R1, [SP, #48]
+  0x34181314:  980B         LDR        R0, [SP, #44]
+  0x34181316:  4308         ORRS       R0, R1
+  0x34181318:  900B         STR        R0, [SP, #44]
+
.L47:
+  0x3418131A:  980B         LDR        R0, [SP, #44]
+  0x3418131C:  F245 0180    MOVW       R1, #0x5080
+  0x34181320:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181324:  6008         STR        R0, [R1]
+  0x34181326:  F245 0084    MOVW       R0, #0x5084
+  0x3418132A:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418132E:  6800         LDR        R0, [R0]
+  0x34181330:  900B         STR        R0, [SP, #44]
+  0x34181332:  990C         LDR        R1, [SP, #48]
+  0x34181334:  980B         LDR        R0, [SP, #44]
+  0x34181336:  4388         BICS       R0, R1
+  0x34181338:  900B         STR        R0, [SP, #44]
+  0x3418133A:  980E         LDR        R0, [SP, #56]
+  0x3418133C:  7980         LDRB       R0, [R0, #6]
+  0x3418133E:  0780         LSLS       R0, R0, #30
+  0x34181340:  2800         CMP        R0, #0
+  0x34181342:  D503         BPL        46L48                     ; 0x3418134C
+  0x34181344:  990C         LDR        R1, [SP, #48]
+  0x34181346:  980B         LDR        R0, [SP, #44]
+  0x34181348:  4308         ORRS       R0, R1
+  0x3418134A:  900B         STR        R0, [SP, #44]
+
.L48:
+  0x3418134C:  980B         LDR        R0, [SP, #44]
+  0x3418134E:  F245 0184    MOVW       R1, #0x5084
+  0x34181352:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181356:  6008         STR        R0, [R1]
+  0x34181358:  F245 0000    MOVW       R0, #0x5000
+  0x3418135C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181360:  6800         LDR        R0, [R0]
+  0x34181362:  900B         STR        R0, [SP, #44]
+  0x34181364:  990C         LDR        R1, [SP, #48]
+  0x34181366:  980B         LDR        R0, [SP, #44]
+  0x34181368:  4388         BICS       R0, R1
+  0x3418136A:  900B         STR        R0, [SP, #44]
+  0x3418136C:  980E         LDR        R0, [SP, #56]
+  0x3418136E:  7980         LDRB       R0, [R0, #6]
+  0x34181370:  06C0         LSLS       R0, R0, #27
+  0x34181372:  2800         CMP        R0, #0
+  0x34181374:  D503         BPL        46L49                     ; 0x3418137E
+  0x34181376:  990C         LDR        R1, [SP, #48]
+  0x34181378:  980B         LDR        R0, [SP, #44]
+  0x3418137A:  4308         ORRS       R0, R1
+  0x3418137C:  900B         STR        R0, [SP, #44]
+
.L49:
+  0x3418137E:  980B         LDR        R0, [SP, #44]
+  0x34181380:  F245 0100    MOVW       R1, #0x5000
+  0x34181384:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181388:  6008         STR        R0, [R1]
+  0x3418138A:  F245 0004    MOVW       R0, #0x5004
+  0x3418138E:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181392:  6800         LDR        R0, [R0]
+  0x34181394:  900B         STR        R0, [SP, #44]
+  0x34181396:  990C         LDR        R1, [SP, #48]
+  0x34181398:  980B         LDR        R0, [SP, #44]
+  0x3418139A:  4388         BICS       R0, R1
+  0x3418139C:  900B         STR        R0, [SP, #44]
+  0x3418139E:  980E         LDR        R0, [SP, #56]
+  0x341813A0:  7980         LDRB       R0, [R0, #6]
+  0x341813A2:  0680         LSLS       R0, R0, #26
+  0x341813A4:  2800         CMP        R0, #0
+  0x341813A6:  D503         BPL        46L50                     ; 0x341813B0
+  0x341813A8:  990C         LDR        R1, [SP, #48]
+  0x341813AA:  980B         LDR        R0, [SP, #44]
+  0x341813AC:  4308         ORRS       R0, R1
+  0x341813AE:  900B         STR        R0, [SP, #44]
+
.L50:
+  0x341813B0:  980B         LDR        R0, [SP, #44]
+  0x341813B2:  F245 0104    MOVW       R1, #0x5004
+  0x341813B6:  F2C5 6102    MOVT       R1, #0x5602
+  0x341813BA:  6008         STR        R0, [R1]
+
.L51:
+  0x341813BC:  980D         LDR        R0, [SP, #52]
+  0x341813BE:  3001         ADDS       R0, #1
+  0x341813C0:  900D         STR        R0, [SP, #52]
+  0x341813C2:  E541         B          46L8                      ; 0x34180E48
+
.L52:
+  0x341813C4:  B010         ADD        SP, SP, #64
+  0x341813C6:  BD80         POP        123R7, PC}
+
+

Section .text.LL_RCC_HSI_SetDivider from blto2_FSBL_lto.o, size=28, align=4

+ +
+
LL_RCC_HSI_SetDivider:
+  0x341813C8:  B081         SUB        SP, SP, #4
+  0x341813CA:  9000         STR        R0, [SP, #0]
+  0x341813CC:  F248 0148    MOVW       R1, #0x8048
+  0x341813D0:  F2C5 6102    MOVT       R1, #0x5602
+  0x341813D4:  6808         LDR        R0, [R1]
+  0x341813D6:  F420 70C0    BIC        R0, R0, #0x0180
+  0x341813DA:  9A00         LDR        R2, [SP, #0]
+  0x341813DC:  4310         ORRS       R0, R2
+  0x341813DE:  6008         STR        R0, [R1]
+  0x341813E0:  B001         ADD        SP, SP, #4
+  0x341813E2:  4770         BX         LR
+
+

Section .text.LL_RCC_HSI_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_HSI_IsReady:
+  0x341813E4:  F248 0004    MOVW       R0, #0x8004
+  0x341813E8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341813EC:  6800         LDR        R0, [R0]
+  0x341813EE:  F3C0 00C0    UBFX       R0, R0, #3, #1
+  0x341813F2:  4770         BX         LR
+
+

Section .text.LL_RCC_GetCpuClkSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_GetCpuClkSource:
+  0x341813F4:  F248 0020    MOVW       R0, #0x8020
+  0x341813F8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341813FC:  6800         LDR        R0, [R0]
+  0x341813FE:  F400 1040    AND        R0, R0, #0x300000
+  0x34181402:  4770         BX         LR
+
+

Section .text.LL_RCC_GetSysClkSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_GetSysClkSource:
+  0x34181404:  F248 0020    MOVW       R0, #0x8020
+  0x34181408:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418140C:  6800         LDR        R0, [R0]
+  0x3418140E:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181412:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetSource:
+  0x34181414:  F248 0080    MOVW       R0, #0x8080
+  0x34181418:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418141C:  6800         LDR        R0, [R0]
+  0x3418141E:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181422:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetSource:
+  0x34181424:  F248 0090    MOVW       R0, #0x8090
+  0x34181428:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418142C:  6800         LDR        R0, [R0]
+  0x3418142E:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181432:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetSource:
+  0x34181434:  F248 00A0    MOVW       R0, #0x80A0
+  0x34181438:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418143C:  6800         LDR        R0, [R0]
+  0x3418143E:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181442:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetSource:
+  0x34181444:  F248 00B0    MOVW       R0, #0x80B0
+  0x34181448:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418144C:  6800         LDR        R0, [R0]
+  0x3418144E:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181452:  4770         BX         LR
+
+

Section .text.LL_RCC_MSI_SetFrequency from blto2_FSBL_lto.o, size=28, align=4

+ +
+
LL_RCC_MSI_SetFrequency:
+  0x34181454:  B081         SUB        SP, SP, #4
+  0x34181456:  9000         STR        R0, [SP, #0]
+  0x34181458:  F248 0144    MOVW       R1, #0x8044
+  0x3418145C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181460:  6808         LDR        R0, [R1]
+  0x34181462:  F420 7000    BIC        R0, R0, #0x0200
+  0x34181466:  9A00         LDR        R2, [SP, #0]
+  0x34181468:  4310         ORRS       R0, R2
+  0x3418146A:  6008         STR        R0, [R1]
+  0x3418146C:  B001         ADD        SP, SP, #4
+  0x3418146E:  4770         BX         LR
+
+

Section .text.LL_RCC_MSI_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_MSI_IsReady:
+  0x34181470:  F248 0004    MOVW       R0, #0x8004
+  0x34181474:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181478:  6800         LDR        R0, [R0]
+  0x3418147A:  F3C0 0080    UBFX       R0, R0, #2, #1
+  0x3418147E:  4770         BX         LR
+
+

Section .text.LL_RCC_LSI_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_LSI_IsReady:
+  0x34181480:  F248 0004    MOVW       R0, #0x8004
+  0x34181484:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181488:  6800         LDR        R0, [R0]
+  0x3418148A:  F000 0001    AND        R0, R0, #1
+  0x3418148E:  4770         BX         LR
+
+

Section .text.LL_RCC_LSE_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_LSE_IsReady:
+  0x34181490:  F248 0004    MOVW       R0, #0x8004
+  0x34181494:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181498:  6800         LDR        R0, [R0]
+  0x3418149A:  F3C0 0040    UBFX       R0, R0, #1, #1
+  0x3418149E:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_IsReady:
+  0x341814A0:  F248 0004    MOVW       R0, #0x8004
+  0x341814A4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341814A8:  6800         LDR        R0, [R0]
+  0x341814AA:  F3C0 2000    UBFX       R0, R0, #8, #1
+  0x341814AE:  4770         BX         LR
+
+

Section .text.LL_RCC_IC1_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_IC1_GetSource:
+  0x341814B0:  F248 00C4    MOVW       R0, #0x80C4
+  0x341814B4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341814B8:  6800         LDR        R0, [R0]
+  0x341814BA:  F000 5040    AND        R0, R0, #0x30000000
+  0x341814BE:  4770         BX         LR
+
+

Section .text.LL_RCC_IC2_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_IC2_GetSource:
+  0x341814C0:  F248 00C8    MOVW       R0, #0x80C8
+  0x341814C4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341814C8:  6800         LDR        R0, [R0]
+  0x341814CA:  F000 5040    AND        R0, R0, #0x30000000
+  0x341814CE:  4770         BX         LR
+
+

Section .text.LL_RCC_IC6_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_IC6_GetSource:
+  0x341814D0:  F248 00D8    MOVW       R0, #0x80D8
+  0x341814D4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341814D8:  6800         LDR        R0, [R0]
+  0x341814DA:  F000 5040    AND        R0, R0, #0x30000000
+  0x341814DE:  4770         BX         LR
+
+

Section .text.LL_RCC_IC11_GetSource from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_IC11_GetSource:
+  0x341814E0:  F248 00EC    MOVW       R0, #0x80EC
+  0x341814E4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341814E8:  6800         LDR        R0, [R0]
+  0x341814EA:  F000 5040    AND        R0, R0, #0x30000000
+  0x341814EE:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_IsReady:
+  0x341814F0:  F248 0004    MOVW       R0, #0x8004
+  0x341814F4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341814F8:  6800         LDR        R0, [R0]
+  0x341814FA:  F3C0 2040    UBFX       R0, R0, #9, #1
+  0x341814FE:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_IsReady:
+  0x34181500:  F248 0004    MOVW       R0, #0x8004
+  0x34181504:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181508:  6800         LDR        R0, [R0]
+  0x3418150A:  F3C0 2080    UBFX       R0, R0, #10, #1
+  0x3418150E:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_IsReady:
+  0x34181510:  F248 0004    MOVW       R0, #0x8004
+  0x34181514:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181518:  6800         LDR        R0, [R0]
+  0x3418151A:  F3C0 20C0    UBFX       R0, R0, #11, #1
+  0x3418151E:  4770         BX         LR
+
+

Section .text.RCC_PLL_Source_IsReady from blto2_FSBL_lto.o, size=84, align=4

+ +
+
RCC_PLL_Source_IsReady:
+  0x34181520:  B580         PUSH       123R7, LR}
+  0x34181522:  B084         SUB        SP, SP, #16
+  0x34181524:  9003         STR        R0, [SP, #12]
+  0x34181526:  2001         MOVS       R0, #1
+  0x34181528:  9002         STR        R0, [SP, #8]
+  0x3418152A:  9803         LDR        R0, [SP, #12]
+  0x3418152C:  9001         STR        R0, [SP, #4]
+  0x3418152E:  B160         CBZ        R0, .L1                  ; 0x3418154A
+  0x34181530:  9801         LDR        R0, [SP, #4]
+  0x34181532:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34181536:  D00E         BEQ        46L3                      ; 0x34181556
+  0x34181538:  9801         LDR        R0, [SP, #4]
+  0x3418153A:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x3418153E:  D010         BEQ        46L5                      ; 0x34181562
+  0x34181540:  9801         LDR        R0, [SP, #4]
+  0x34181542:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34181546:  D012         BEQ        46L7                      ; 0x3418156E
+  0x34181548:  E011         B          46L7                      ; 0x3418156E
+
.L1:
+  0x3418154A:  F7FF FF4B    BL         LL_RCC_HSI_IsReady       ; 0x341813E4
+  0x3418154E:  B908         CBNZ       R0, .L2                  ; 0x34181554
+  0x34181550:  2000         MOVS       R0, #0
+  0x34181552:  9002         STR        R0, [SP, #8]
+
.L2:
+  0x34181554:  E00B         B          46L7                      ; 0x3418156E
+
.L3:
+  0x34181556:  F7FF FF8B    BL         LL_RCC_MSI_IsReady       ; 0x34181470
+  0x3418155A:  B908         CBNZ       R0, .L4                  ; 0x34181560
+  0x3418155C:  2000         MOVS       R0, #0
+  0x3418155E:  9002         STR        R0, [SP, #8]
+
.L4:
+  0x34181560:  E005         B          46L7                      ; 0x3418156E
+
.L5:
+  0x34181562:  F000 F807    BL         LL_RCC_HSE_IsReady       ; 0x34181574
+  0x34181566:  B908         CBNZ       R0, .L6                  ; 0x3418156C
+  0x34181568:  2000         MOVS       R0, #0
+  0x3418156A:  9002         STR        R0, [SP, #8]
+
.L6:
+  0x3418156C:  E7FF         B          46L7                      ; 0x3418156E
+
.L7:
+  0x3418156E:  9802         LDR        R0, [SP, #8]
+  0x34181570:  B004         ADD        SP, SP, #16
+  0x34181572:  BD80         POP        123R7, PC}
+
+

Section .text.LL_RCC_HSE_IsReady from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_HSE_IsReady:
+  0x34181574:  F248 0004    MOVW       R0, #0x8004
+  0x34181578:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418157C:  6800         LDR        R0, [R0]
+  0x3418157E:  F3C0 1000    UBFX       R0, R0, #4, #1
+  0x34181582:  4770         BX         LR
+
+

Section .text.LL_RCC_HSI_GetDivider from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_HSI_GetDivider:
+  0x34181584:  F248 0048    MOVW       R0, #0x8048
+  0x34181588:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418158C:  6800         LDR        R0, [R0]
+  0x3418158E:  F400 70C0    AND        R0, R0, #0x0180
+  0x34181592:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_IsEnabledBypass from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_IsEnabledBypass:
+  0x34181594:  F248 0080    MOVW       R0, #0x8080
+  0x34181598:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418159C:  6800         LDR        R0, [R0]
+  0x3418159E:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x341815A2:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_IsEnabledBypass from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_IsEnabledBypass:
+  0x341815A4:  F248 0090    MOVW       R0, #0x8090
+  0x341815A8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341815AC:  6800         LDR        R0, [R0]
+  0x341815AE:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x341815B2:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_IsEnabledBypass from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_IsEnabledBypass:
+  0x341815B4:  F248 00A0    MOVW       R0, #0x80A0
+  0x341815B8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341815BC:  6800         LDR        R0, [R0]
+  0x341815BE:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x341815C2:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_IsEnabledBypass from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_IsEnabledBypass:
+  0x341815C4:  F248 00B0    MOVW       R0, #0x80B0
+  0x341815C8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341815CC:  6800         LDR        R0, [R0]
+  0x341815CE:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x341815D2:  4770         BX         LR
+
+

Section .text.HAL_RCC_GetClockConfig from blto2_FSBL_lto.o, size=240, align=4

+ +
+
HAL_RCC_GetClockConfig:
+  0x341815D4:  B082         SUB        SP, SP, #8
+  0x341815D6:  9001         STR        R0, [SP, #4]
+  0x341815D8:  9901         LDR        R1, [SP, #4]
+  0x341815DA:  207F         MOVS       R0, #127
+  0x341815DC:  6008         STR        R0, [R1]
+  0x341815DE:  F248 0020    MOVW       R0, #0x8020
+  0x341815E2:  F2C5 6002    MOVT       R0, #0x5602
+  0x341815E6:  6800         LDR        R0, [R0]
+  0x341815E8:  9000         STR        R0, [SP, #0]
+  0x341815EA:  9800         LDR        R0, [SP, #0]
+  0x341815EC:  F400 1040    AND        R0, R0, #0x300000
+  0x341815F0:  0900         LSRS       R0, R0, #4
+  0x341815F2:  9901         LDR        R1, [SP, #4]
+  0x341815F4:  6048         STR        R0, [R1, #4]
+  0x341815F6:  9800         LDR        R0, [SP, #0]
+  0x341815F8:  F000 5040    AND        R0, R0, #0x30000000
+  0x341815FC:  0900         LSRS       R0, R0, #4
+  0x341815FE:  9901         LDR        R1, [SP, #4]
+  0x34181600:  6088         STR        R0, [R1, #8]
+  0x34181602:  F248 0024    MOVW       R0, #0x8024
+  0x34181606:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418160A:  6800         LDR        R0, [R0]
+  0x3418160C:  9000         STR        R0, [SP, #0]
+  0x3418160E:  9800         LDR        R0, [SP, #0]
+  0x34181610:  F400 00E0    AND        R0, R0, #0x700000
+  0x34181614:  9901         LDR        R1, [SP, #4]
+  0x34181616:  60C8         STR        R0, [R1, #12]
+  0x34181618:  9800         LDR        R0, [SP, #0]
+  0x3418161A:  F000 0007    AND        R0, R0, #7
+  0x3418161E:  9901         LDR        R1, [SP, #4]
+  0x34181620:  6108         STR        R0, [R1, #16]
+  0x34181622:  9800         LDR        R0, [SP, #0]
+  0x34181624:  F000 0070    AND        R0, R0, #112
+  0x34181628:  9901         LDR        R1, [SP, #4]
+  0x3418162A:  6148         STR        R0, [R1, #20]
+  0x3418162C:  9800         LDR        R0, [SP, #0]
+  0x3418162E:  F400 40E0    AND        R0, R0, #0x7000
+  0x34181632:  9901         LDR        R1, [SP, #4]
+  0x34181634:  6188         STR        R0, [R1, #24]
+  0x34181636:  9800         LDR        R0, [SP, #0]
+  0x34181638:  F400 20E0    AND        R0, R0, #0x070000
+  0x3418163C:  9901         LDR        R1, [SP, #4]
+  0x3418163E:  61C8         STR        R0, [R1, #28]
+  0x34181640:  F248 00C4    MOVW       R0, #0x80C4
+  0x34181644:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181648:  6800         LDR        R0, [R0]
+  0x3418164A:  9000         STR        R0, [SP, #0]
+  0x3418164C:  9800         LDR        R0, [SP, #0]
+  0x3418164E:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181652:  9901         LDR        R1, [SP, #4]
+  0x34181654:  6208         STR        R0, [R1, #32]
+  0x34181656:  F89D 0002    LDRB.W     R0, [SP, #2]
+  0x3418165A:  3001         ADDS       R0, #1
+  0x3418165C:  9901         LDR        R1, [SP, #4]
+  0x3418165E:  6248         STR        R0, [R1, #36]
+  0x34181660:  F248 00C8    MOVW       R0, #0x80C8
+  0x34181664:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181668:  6800         LDR        R0, [R0]
+  0x3418166A:  9000         STR        R0, [SP, #0]
+  0x3418166C:  9800         LDR        R0, [SP, #0]
+  0x3418166E:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181672:  9901         LDR        R1, [SP, #4]
+  0x34181674:  6288         STR        R0, [R1, #40]
+  0x34181676:  F89D 0002    LDRB.W     R0, [SP, #2]
+  0x3418167A:  3001         ADDS       R0, #1
+  0x3418167C:  9901         LDR        R1, [SP, #4]
+  0x3418167E:  62C8         STR        R0, [R1, #44]
+  0x34181680:  F248 00D8    MOVW       R0, #0x80D8
+  0x34181684:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181688:  6800         LDR        R0, [R0]
+  0x3418168A:  9000         STR        R0, [SP, #0]
+  0x3418168C:  9800         LDR        R0, [SP, #0]
+  0x3418168E:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181692:  9901         LDR        R1, [SP, #4]
+  0x34181694:  6308         STR        R0, [R1, #48]
+  0x34181696:  F89D 0002    LDRB.W     R0, [SP, #2]
+  0x3418169A:  3001         ADDS       R0, #1
+  0x3418169C:  9901         LDR        R1, [SP, #4]
+  0x3418169E:  6348         STR        R0, [R1, #52]
+  0x341816A0:  F248 00EC    MOVW       R0, #0x80EC
+  0x341816A4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341816A8:  6800         LDR        R0, [R0]
+  0x341816AA:  9000         STR        R0, [SP, #0]
+  0x341816AC:  9800         LDR        R0, [SP, #0]
+  0x341816AE:  F000 5040    AND        R0, R0, #0x30000000
+  0x341816B2:  9901         LDR        R1, [SP, #4]
+  0x341816B4:  6388         STR        R0, [R1, #56]
+  0x341816B6:  F89D 0002    LDRB.W     R0, [SP, #2]
+  0x341816BA:  3001         ADDS       R0, #1
+  0x341816BC:  9901         LDR        R1, [SP, #4]
+  0x341816BE:  63C8         STR        R0, [R1, #60]
+  0x341816C0:  B002         ADD        SP, SP, #8
+  0x341816C2:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_IsReady.57 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_IsReady.57:
+  0x341816C4:  F248 0004    MOVW       R0, #0x8004
+  0x341816C8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341816CC:  6800         LDR        R0, [R0]
+  0x341816CE:  F3C0 20C0    UBFX       R0, R0, #11, #1
+  0x341816D2:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4P_IsEnabled from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4P_IsEnabled:
+  0x341816D4:  F248 00B8    MOVW       R0, #0x80B8
+  0x341816D8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341816DC:  6800         LDR        R0, [R0]
+  0x341816DE:  F3C0 7080    UBFX       R0, R0, #30, #1
+  0x341816E2:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_GetSource.58 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetSource.58:
+  0x341816E4:  F248 00B0    MOVW       R0, #0x80B0
+  0x341816E8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341816EC:  6800         LDR        R0, [R0]
+  0x341816EE:  F000 40E0    AND        R0, R0, #0x70000000
+  0x341816F2:  4770         BX         LR
+
+

Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=140, align=4

+ +
+
RCCEx_GetPLLSourceFreq:
+  0x341816F4:  B580         PUSH       123R7, LR}
+  0x341816F6:  B084         SUB        SP, SP, #16
+  0x341816F8:  9003         STR        R0, [SP, #12]
+  0x341816FA:  2000         MOVS       R0, #0
+  0x341816FC:  9002         STR        R0, [SP, #8]
+  0x341816FE:  9803         LDR        R0, [SP, #12]
+  0x34181700:  9001         STR        R0, [SP, #4]
+  0x34181702:  B160         CBZ        R0, .L1                  ; 0x3418171E
+  0x34181704:  9801         LDR        R0, [SP, #4]
+  0x34181706:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x3418170A:  D015         BEQ        46L3                      ; 0x34181738
+  0x3418170C:  9801         LDR        R0, [SP, #4]
+  0x3418170E:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34181712:  D023         BEQ        46L6                      ; 0x3418175C
+  0x34181714:  9801         LDR        R0, [SP, #4]
+  0x34181716:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x3418171A:  D028         BEQ        46L8                      ; 0x3418176E
+  0x3418171C:  E02D         B          46L9                      ; 0x3418177A
+
.L1:
+  0x3418171E:  F000 F8A3    BL         LL_RCC_HSI_IsReady.60    ; 0x34181868
+  0x34181722:  B140         CBZ        R0, .L2                  ; 0x34181736
+  0x34181724:  F000 F8A8    BL         LL_RCC_HSI_GetDivider.61 ; 0x34181878
+  0x34181728:  09C1         LSRS       R1, R0, #7
+  0x3418172A:  F249 0000    MOVW       R0, #0x9000
+  0x3418172E:  F2C0 30D0    MOVT       R0, #0x03D0
+  0x34181732:  40C8         LSRS       R0, R1
+  0x34181734:  9002         STR        R0, [SP, #8]
+
.L2:
+  0x34181736:  E020         B          46L9                      ; 0x3418177A
+
.L3:
+  0x34181738:  F000 F8A6    BL         LL_RCC_MSI_IsReady.62    ; 0x34181888
+  0x3418173C:  B168         CBZ        R0, .L5                  ; 0x3418175A
+  0x3418173E:  F000 F8AB    BL         LL_RCC_MSI_GetFrequency  ; 0x34181898
+  0x34181742:  B928         CBNZ       R0, .L4                  ; 0x34181750
+  0x34181744:  F640 1000    MOVW       R0, #0x0900
+  0x34181748:  F2C0 003D    MOVT       R0, #61
+  0x3418174C:  9002         STR        R0, [SP, #8]
+  0x3418174E:  E004         B          46L5                      ; 0x3418175A
+
.L4:
+  0x34181750:  F242 4000    MOVW       R0, #0x2400
+  0x34181754:  F2C0 00F4    MOVT       R0, #244
+  0x34181758:  9002         STR        R0, [SP, #8]
+
.L5:
+  0x3418175A:  E00E         B          46L9                      ; 0x3418177A
+
.L6:
+  0x3418175C:  F000 F8A4    BL         LL_RCC_HSE_IsReady.63    ; 0x341818A8
+  0x34181760:  B120         CBZ        R0, .L7                  ; 0x3418176C
+  0x34181762:  F646 4000    MOVW       R0, #0x6C00
+  0x34181766:  F2C0 20DC    MOVT       R0, #0x02DC
+  0x3418176A:  9002         STR        R0, [SP, #8]
+
.L7:
+  0x3418176C:  E005         B          46L9                      ; 0x3418177A
+
.L8:
+  0x3418176E:  F248 0000    MOVW       R0, #0x8000
+  0x34181772:  F2C0 00BB    MOVT       R0, #187
+  0x34181776:  9002         STR        R0, [SP, #8]
+  0x34181778:  E7FF         B          46L9                      ; 0x3418177A
+
.L9:
+  0x3418177A:  9802         LDR        R0, [SP, #8]
+  0x3418177C:  B004         ADD        SP, SP, #16
+  0x3418177E:  BD80         POP        123R7, PC}
+
+

Section .text.LL_RCC_PLL4_GetM from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetM:
+  0x34181780:  F248 00B0    MOVW       R0, #0x80B0
+  0x34181784:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181788:  6800         LDR        R0, [R0]
+  0x3418178A:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x3418178E:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_GetN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetN:
+  0x34181790:  F248 00B0    MOVW       R0, #0x80B0
+  0x34181794:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181798:  6800         LDR        R0, [R0]
+  0x3418179A:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x3418179E:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_GetFRACN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetFRACN:
+  0x341817A0:  F248 00B4    MOVW       R0, #0x80B4
+  0x341817A4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341817A8:  6800         LDR        R0, [R0]
+  0x341817AA:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x341817AE:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_GetP1 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetP1:
+  0x341817B0:  F248 00B8    MOVW       R0, #0x80B8
+  0x341817B4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341817B8:  6800         LDR        R0, [R0]
+  0x341817BA:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x341817BE:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL4_GetP2 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_GetP2:
+  0x341817C0:  F248 00B8    MOVW       R0, #0x80B8
+  0x341817C4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341817C8:  6800         LDR        R0, [R0]
+  0x341817CA:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x341817CE:  4770         BX         LR
+
+

Section .text.RCCEx_CalcPLLFreq from blto2_FSBL_lto.o, size=136, align=4

+ +
+
RCCEx_CalcPLLFreq:
+  0x341817D0:  B085         SUB        SP, SP, #20
+  0x341817D2:  F8DD C018    LDR.W      R12, [SP, #24]
+  0x341817D6:  F8DD C014    LDR.W      R12, [SP, #20]
+  0x341817DA:  9004         STR        R0, [SP, #16]
+  0x341817DC:  9103         STR        R1, [SP, #12]
+  0x341817DE:  9202         STR        R2, [SP, #8]
+  0x341817E0:  9301         STR        R3, [SP, #4]
+  0x341817E2:  ED9D 0A04    VLDR       S0, [SP, #16]
+  0x341817E6:  EEB8 0A40    VCVT.F32.U32 S0, S0
+  0x341817EA:  ED9D 1A02    VLDR       S2, [SP, #8]
+  0x341817EE:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x341817F2:  ED9D 2A01    VLDR       S4, [SP, #4]
+  0x341817F6:  EEB8 2A42    VCVT.F32.U32 S4, S4
+  0x341817FA:  ED9F 3A16    VLDR       S6, =0x33800000          ; [PC, #88] [0x34181854]
+  0x341817FE:  EE22 2A03    VMUL.F32   S4, S4, S6
+  0x34181802:  EE31 1A02    VADD.F32   S2, S2, S4
+  0x34181806:  EE20 0A01    VMUL.F32   S0, S0, S2
+  0x3418180A:  ED9D 1A03    VLDR       S2, [SP, #12]
+  0x3418180E:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34181812:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34181816:  ED8D 0A00    VSTR       S0, [SP]
+  0x3418181A:  ED9D 0A00    VLDR       S0, [SP]
+  0x3418181E:  ED9D 1A05    VLDR       S2, [SP, #20]
+  0x34181822:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34181826:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x3418182A:  ED8D 0A00    VSTR       S0, [SP]
+  0x3418182E:  ED9D 0A00    VLDR       S0, [SP]
+  0x34181832:  ED9D 1A06    VLDR       S2, [SP, #24]
+  0x34181836:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x3418183A:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x3418183E:  ED8D 0A00    VSTR       S0, [SP]
+  0x34181842:  ED9D 0A00    VLDR       S0, [SP]
+  0x34181846:  EEBC 0AC0    VCVT.U32.F32 S0, S0
+  0x3418184A:  EE10 0A10    VMOV       R0, S0
+  0x3418184E:  B005         ADD        SP, SP, #20
+  0x34181850:  4770         BX         LR
+  0x34181852:  BF00         NOP
+  0x34181854:  33800000     DC.W       0x33800000
+
+

Section .text.LL_RCC_PLL4_IsEnabledBypass.59 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL4_IsEnabledBypass.59:
+  0x34181858:  F248 00B0    MOVW       R0, #0x80B0
+  0x3418185C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181860:  6800         LDR        R0, [R0]
+  0x34181862:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x34181866:  4770         BX         LR
+
+

Section .text.LL_RCC_HSI_IsReady.60 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_HSI_IsReady.60:
+  0x34181868:  F248 0004    MOVW       R0, #0x8004
+  0x3418186C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181870:  6800         LDR        R0, [R0]
+  0x34181872:  F3C0 00C0    UBFX       R0, R0, #3, #1
+  0x34181876:  4770         BX         LR
+
+

Section .text.LL_RCC_HSI_GetDivider.61 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_HSI_GetDivider.61:
+  0x34181878:  F248 0048    MOVW       R0, #0x8048
+  0x3418187C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181880:  6800         LDR        R0, [R0]
+  0x34181882:  F400 70C0    AND        R0, R0, #0x0180
+  0x34181886:  4770         BX         LR
+
+

Section .text.LL_RCC_MSI_IsReady.62 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_MSI_IsReady.62:
+  0x34181888:  F248 0004    MOVW       R0, #0x8004
+  0x3418188C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181890:  6800         LDR        R0, [R0]
+  0x34181892:  F3C0 0080    UBFX       R0, R0, #2, #1
+  0x34181896:  4770         BX         LR
+
+

Section .text.LL_RCC_MSI_GetFrequency from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_MSI_GetFrequency:
+  0x34181898:  F248 0044    MOVW       R0, #0x8044
+  0x3418189C:  F2C5 6002    MOVT       R0, #0x5602
+  0x341818A0:  6800         LDR        R0, [R0]
+  0x341818A2:  F400 7000    AND        R0, R0, #0x0200
+  0x341818A6:  4770         BX         LR
+
+

Section .text.LL_RCC_HSE_IsReady.63 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_HSE_IsReady.63:
+  0x341818A8:  F248 0004    MOVW       R0, #0x8004
+  0x341818AC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341818B0:  6800         LDR        R0, [R0]
+  0x341818B2:  F3C0 1000    UBFX       R0, R0, #4, #1
+  0x341818B6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_IsReady.64 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_IsReady.64:
+  0x341818B8:  F248 0004    MOVW       R0, #0x8004
+  0x341818BC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341818C0:  6800         LDR        R0, [R0]
+  0x341818C2:  F3C0 2080    UBFX       R0, R0, #10, #1
+  0x341818C6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3P_IsEnabled from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3P_IsEnabled:
+  0x341818C8:  F248 00A8    MOVW       R0, #0x80A8
+  0x341818CC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341818D0:  6800         LDR        R0, [R0]
+  0x341818D2:  F3C0 7080    UBFX       R0, R0, #30, #1
+  0x341818D6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetSource.65 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetSource.65:
+  0x341818D8:  F248 00A0    MOVW       R0, #0x80A0
+  0x341818DC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341818E0:  6800         LDR        R0, [R0]
+  0x341818E2:  F000 40E0    AND        R0, R0, #0x70000000
+  0x341818E6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetM from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetM:
+  0x341818E8:  F248 00A0    MOVW       R0, #0x80A0
+  0x341818EC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341818F0:  6800         LDR        R0, [R0]
+  0x341818F2:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x341818F6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetN:
+  0x341818F8:  F248 00A0    MOVW       R0, #0x80A0
+  0x341818FC:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181900:  6800         LDR        R0, [R0]
+  0x34181902:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x34181906:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetFRACN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetFRACN:
+  0x34181908:  F248 00A4    MOVW       R0, #0x80A4
+  0x3418190C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181910:  6800         LDR        R0, [R0]
+  0x34181912:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x34181916:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetP1 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetP1:
+  0x34181918:  F248 00A8    MOVW       R0, #0x80A8
+  0x3418191C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181920:  6800         LDR        R0, [R0]
+  0x34181922:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x34181926:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_GetP2 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_GetP2:
+  0x34181928:  F248 00A8    MOVW       R0, #0x80A8
+  0x3418192C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181930:  6800         LDR        R0, [R0]
+  0x34181932:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x34181936:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL3_IsEnabledBypass.66 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL3_IsEnabledBypass.66:
+  0x34181938:  F248 00A0    MOVW       R0, #0x80A0
+  0x3418193C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181940:  6800         LDR        R0, [R0]
+  0x34181942:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x34181946:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_IsReady.67 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_IsReady.67:
+  0x34181948:  F248 0004    MOVW       R0, #0x8004
+  0x3418194C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181950:  6800         LDR        R0, [R0]
+  0x34181952:  F3C0 2040    UBFX       R0, R0, #9, #1
+  0x34181956:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2P_IsEnabled from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2P_IsEnabled:
+  0x34181958:  F248 0098    MOVW       R0, #0x8098
+  0x3418195C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181960:  6800         LDR        R0, [R0]
+  0x34181962:  F3C0 7080    UBFX       R0, R0, #30, #1
+  0x34181966:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetSource.68 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetSource.68:
+  0x34181968:  F248 0090    MOVW       R0, #0x8090
+  0x3418196C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181970:  6800         LDR        R0, [R0]
+  0x34181972:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181976:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetM from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetM:
+  0x34181978:  F248 0090    MOVW       R0, #0x8090
+  0x3418197C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181980:  6800         LDR        R0, [R0]
+  0x34181982:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x34181986:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetN:
+  0x34181988:  F248 0090    MOVW       R0, #0x8090
+  0x3418198C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181990:  6800         LDR        R0, [R0]
+  0x34181992:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x34181996:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetFRACN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetFRACN:
+  0x34181998:  F248 0094    MOVW       R0, #0x8094
+  0x3418199C:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819A0:  6800         LDR        R0, [R0]
+  0x341819A2:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x341819A6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetP1 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetP1:
+  0x341819A8:  F248 0098    MOVW       R0, #0x8098
+  0x341819AC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819B0:  6800         LDR        R0, [R0]
+  0x341819B2:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x341819B6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_GetP2 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_GetP2:
+  0x341819B8:  F248 0098    MOVW       R0, #0x8098
+  0x341819BC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819C0:  6800         LDR        R0, [R0]
+  0x341819C2:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x341819C6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL2_IsEnabledBypass.69 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL2_IsEnabledBypass.69:
+  0x341819C8:  F248 0090    MOVW       R0, #0x8090
+  0x341819CC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819D0:  6800         LDR        R0, [R0]
+  0x341819D2:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x341819D6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_IsReady.70 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_IsReady.70:
+  0x341819D8:  F248 0004    MOVW       R0, #0x8004
+  0x341819DC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819E0:  6800         LDR        R0, [R0]
+  0x341819E2:  F3C0 2000    UBFX       R0, R0, #8, #1
+  0x341819E6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1P_IsEnabled from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1P_IsEnabled:
+  0x341819E8:  F248 0088    MOVW       R0, #0x8088
+  0x341819EC:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819F0:  6800         LDR        R0, [R0]
+  0x341819F2:  F3C0 7080    UBFX       R0, R0, #30, #1
+  0x341819F6:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetSource.71 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetSource.71:
+  0x341819F8:  F248 0080    MOVW       R0, #0x8080
+  0x341819FC:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A00:  6800         LDR        R0, [R0]
+  0x34181A02:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181A06:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetM from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetM:
+  0x34181A08:  F248 0080    MOVW       R0, #0x8080
+  0x34181A0C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A10:  6800         LDR        R0, [R0]
+  0x34181A12:  F3C0 5005    UBFX       R0, R0, #20, #6
+  0x34181A16:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetN:
+  0x34181A18:  F248 0080    MOVW       R0, #0x8080
+  0x34181A1C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A20:  6800         LDR        R0, [R0]
+  0x34181A22:  F3C0 200B    UBFX       R0, R0, #8, #12
+  0x34181A26:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetFRACN from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetFRACN:
+  0x34181A28:  F248 0084    MOVW       R0, #0x8084
+  0x34181A2C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A30:  6800         LDR        R0, [R0]
+  0x34181A32:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x34181A36:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetP1 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetP1:
+  0x34181A38:  F248 0088    MOVW       R0, #0x8088
+  0x34181A3C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A40:  6800         LDR        R0, [R0]
+  0x34181A42:  F3C0 60C2    UBFX       R0, R0, #27, #3
+  0x34181A46:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_GetP2 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_GetP2:
+  0x34181A48:  F248 0088    MOVW       R0, #0x8088
+  0x34181A4C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A50:  6800         LDR        R0, [R0]
+  0x34181A52:  F3C0 6002    UBFX       R0, R0, #24, #3
+  0x34181A56:  4770         BX         LR
+
+

Section .text.LL_RCC_PLL1_IsEnabledBypass.72 from blto2_FSBL_lto.o, size=16, align=4

+ +
+
LL_RCC_PLL1_IsEnabledBypass.72:
+  0x34181A58:  F248 0080    MOVW       R0, #0x8080
+  0x34181A5C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A60:  6800         LDR        R0, [R0]
+  0x34181A62:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x34181A66:  4770         BX         LR
+
+

Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

+ +
+
_start:
+  0x34181A68:  4C03         LDR        R4, =0x34184470          ; [PC, #12] [0x34181A78] 
+
.L1:
+  0x34181A6A:  6820         LDR        R0, [R4]
+  0x34181A6C:  3404         ADDS       R4, #4
+  0x34181A6E:  4780         BLX        R0
+  0x34181A70:  E7FB         B          46L1                      ; 0x34181A6A
+
__SEGGER_init_done:
+__startup_complete:
+  0x34181A72:  F000 F949    BL         main                     ; 0x34181D08
+
exit:
+  0x34181A76:  E7FE         B          exit                     ; 0x34181A76
+  0x34181A78:  34184470     DC.W       34184470               ; R_ARM_ABS32
+
+

Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4

+ +
+
reset_handler:
+Reset_Handler:
+  0x34181A7C:  4909         LDR        R1, =0x341FC000          ; [PC, #36] [0x34181AA4] 
+  0x34181A7E:  F381 880A    MSR        MSPLIM, R1
+  0x34181A82:  F04F 0100    MOV.W      R1, #0
+  0x34181A86:  F381 880B    MSR        PSPLIM, R1
+  0x34181A8A:  F000 F9ED    BL         SystemInit               ; 0x34181E68
+  0x34181A8E:  F64E 5088    MOVW       R0, #0xED88
+  0x34181A92:  F2CE 0000    MOVT       R0, #0xE000
+  0x34181A96:  6801         LDR        R1, [R0]
+  0x34181A98:  F451 0170    ORRS       R1, R1, #0xF00000
+  0x34181A9C:  6001         STR        R1, [R0]
+  0x34181A9E:  F7FF FFE3    BL         _start                   ; 0x34181A68
+  0x34181AA2:  00           DC.B       0x00                     ; '\0'
+  0x34181AA3:  00           DC.B       0x00                     ; '\0'
+  0x34181AA4:  341FC000     DC.W       341FC000               ; R_ARM_ABS32
+
+

Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4

+ +
+
__aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x34181AA8:  2200         MOVS       R2, #0
+
__aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x34181AAA:  000B         MOVS       R3, R1
+  0x34181AAC:  0011         MOVS       R1, R2
+  0x34181AAE:  001A         MOVS       R2, R3
+
memset:
+  0x34181AB0:  4684         MOV        R12, R0
+  0x34181AB2:  B35A         CBZ        R2, .L7                  ; 0x34181B0C
+
.L1:
+  0x34181AB4:  0783         LSLS       R3, R0, #30
+  0x34181AB6:  D004         BEQ        46L2                      ; 0x34181AC2
+  0x34181AB8:  F800 1B01    STRB       R1, [R0], #1
+  0x34181ABC:  1E52         SUBS       R2, R2, #1
+  0x34181ABE:  D1F9         BNE        46L1                      ; 0x34181AB4
+  0x34181AC0:  E024         B          46L7                      ; 0x34181B0C
+
.L2:
+  0x34181AC2:  B2C9         UXTB       R1, R1
+  0x34181AC4:  EA41 2101    ORR.W      R1, R1, R1, LSL #8
+  0x34181AC8:  EA41 4101    ORR.W      R1, R1, R1, LSL #16
+  0x34181ACC:  2A20         CMP        R2, #32
+  0x34181ACE:  D311         BCC        46L4                      ; 0x34181AF4
+  0x34181AD0:  3A20         SUBS       R2, #32
+  0x34181AD2:  E92D 03F0    PUSH.W     123R4-R9}
+  0x34181AD6:  460B         MOV        R3, R1
+  0x34181AD8:  460C         MOV        R4, R1
+  0x34181ADA:  460D         MOV        R5, R1
+  0x34181ADC:  460E         MOV        R6, R1
+  0x34181ADE:  460F         MOV        R7, R1
+  0x34181AE0:  4688         MOV        R8, R1
+  0x34181AE2:  4689         MOV        R9, R1
+
.L3:
+  0x34181AE4:  E8A0 03FA    STM.W      R0!, {R1, R3-R9}
+  0x34181AE8:  3A20         SUBS       R2, #32
+  0x34181AEA:  D2FB         BCS        46L3                      ; 0x34181AE4
+  0x34181AEC:  E8BD 03F0    POP.W      123R4-R9}
+  0x34181AF0:  3220         ADDS       R2, #32
+  0x34181AF2:  D00B         BEQ        46L7                      ; 0x34181B0C
+
.L4:
+  0x34181AF4:  2A04         CMP        R2, #4
+  0x34181AF6:  D305         BCC        46L6                      ; 0x34181B04
+
.L5:
+  0x34181AF8:  F840 1B04    STR        R1, [R0], #4
+  0x34181AFC:  1F12         SUBS       R2, R2, #4
+  0x34181AFE:  D005         BEQ        46L7                      ; 0x34181B0C
+  0x34181B00:  2A04         CMP        R2, #4
+  0x34181B02:  D2F9         BCS        46L5                      ; 0x34181AF8
+
.L6:
+  0x34181B04:  F800 1B01    STRB       R1, [R0], #1
+  0x34181B08:  1E52         SUBS       R2, R2, #1
+  0x34181B0A:  D1FB         BNE        46L6                      ; 0x34181B04
+
.L7:
+  0x34181B0C:  4660         MOV        R0, R12
+  0x34181B0E:  4770         BX         LR
+
+

Section .text.MX_GPIO_Init from blto2_FSBL_lto.o, size=466, align=4

+ +
+
MX_GPIO_Init:
+  0x34181B10:  B580         PUSH       123R7, LR}
+  0x34181B12:  B08C         SUB        SP, SP, #48
+  0x34181B14:  2000         MOVS       R0, #0
+  0x34181B16:  9004         STR        R0, [SP, #16]
+  0x34181B18:  900B         STR        R0, [SP, #44]
+  0x34181B1A:  900A         STR        R0, [SP, #40]
+  0x34181B1C:  9009         STR        R0, [SP, #36]
+  0x34181B1E:  9008         STR        R0, [SP, #32]
+  0x34181B20:  9007         STR        R0, [SP, #28]
+  0x34181B22:  F44F 3080    MOV.W      R0, #0x010000
+  0x34181B26:  F000 F8DD    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B2A:  2004         MOVS       R0, #4
+  0x34181B2C:  F000 F8DA    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B30:  2010         MOVS       R0, #16
+  0x34181B32:  F000 F8D7    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B36:  2008         MOVS       R0, #8
+  0x34181B38:  F000 F8D4    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B3C:  2080         MOVS       R0, #128
+  0x34181B3E:  F000 F8D1    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B42:  2002         MOVS       R0, #2
+  0x34181B44:  F000 F8CE    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B48:  F44F 4000    MOV.W      R0, #0x8000
+  0x34181B4C:  F000 F8CA    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B50:  F44F 4080    MOV.W      R0, #0x4000
+  0x34181B54:  F000 F8C6    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B58:  2040         MOVS       R0, #64
+  0x34181B5A:  F000 F8C3    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B5E:  2020         MOVS       R0, #32
+  0x34181B60:  F000 F8C0    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B64:  F44F 5000    MOV.W      R0, #0x2000
+  0x34181B68:  F000 F8BC    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B6C:  2001         MOVS       R0, #1
+  0x34181B6E:  9003         STR        R0, [SP, #12]
+  0x34181B70:  F000 F8B8    BL         LL_AHB4_GRP1_EnableClock ; 0x34181CE4
+  0x34181B74:  9903         LDR        R1, [SP, #12]
+  0x34181B76:  9A04         LDR        R2, [SP, #16]
+  0x34181B78:  F641 0000    MOVW       R0, #0x1800
+  0x34181B7C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181B80:  9005         STR        R0, [SP, #20]
+  0x34181B82:  F000 FB45    BL         HAL_GPIO_WritePin        ; 0x34182210
+  0x34181B86:  9804         LDR        R0, [SP, #16]
+  0x34181B88:  21FF         MOVS       R1, #255
+  0x34181B8A:  9107         STR        R1, [SP, #28]
+  0x34181B8C:  2103         MOVS       R1, #3
+  0x34181B8E:  9102         STR        R1, [SP, #8]
+  0x34181B90:  9108         STR        R1, [SP, #32]
+  0x34181B92:  9009         STR        R0, [SP, #36]
+  0x34181B94:  F244 0000    MOVW       R0, #0x4000
+  0x34181B98:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181B9C:  A907         ADD        R1, SP, #28
+  0x34181B9E:  9106         STR        R1, [SP, #24]
+  0x34181BA0:  F7FF F84E    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181BA4:  9A02         LDR        R2, [SP, #8]
+  0x34181BA6:  9804         LDR        R0, [SP, #16]
+  0x34181BA8:  9906         LDR        R1, [SP, #24]
+  0x34181BAA:  F643 73FF    MOVW       R3, #0x3FFF
+  0x34181BAE:  9307         STR        R3, [SP, #28]
+  0x34181BB0:  9208         STR        R2, [SP, #32]
+  0x34181BB2:  9009         STR        R0, [SP, #36]
+  0x34181BB4:  F640 0000    MOVW       R0, #0x0800
+  0x34181BB8:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181BBC:  F7FF F840    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181BC0:  9A02         LDR        R2, [SP, #8]
+  0x34181BC2:  9804         LDR        R0, [SP, #16]
+  0x34181BC4:  9906         LDR        R1, [SP, #24]
+  0x34181BC6:  F64F 73FF    MOVW       R3, #0xFFFF
+  0x34181BCA:  9301         STR        R3, [SP, #4]
+  0x34181BCC:  9307         STR        R3, [SP, #28]
+  0x34181BCE:  9208         STR        R2, [SP, #32]
+  0x34181BD0:  9009         STR        R0, [SP, #36]
+  0x34181BD2:  F241 0000    MOVW       R0, #0x1000
+  0x34181BD6:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181BDA:  F7FF F831    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181BDE:  9B01         LDR        R3, [SP, #4]
+  0x34181BE0:  9A02         LDR        R2, [SP, #8]
+  0x34181BE2:  9804         LDR        R0, [SP, #16]
+  0x34181BE4:  9906         LDR        R1, [SP, #24]
+  0x34181BE6:  9307         STR        R3, [SP, #28]
+  0x34181BE8:  9208         STR        R2, [SP, #32]
+  0x34181BEA:  9009         STR        R0, [SP, #36]
+  0x34181BEC:  F640 4000    MOVW       R0, #0x0C00
+  0x34181BF0:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181BF4:  F7FF F824    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181BF8:  9A02         LDR        R2, [SP, #8]
+  0x34181BFA:  9804         LDR        R0, [SP, #16]
+  0x34181BFC:  9906         LDR        R1, [SP, #24]
+  0x34181BFE:  F44F 737F    MOV.W      R3, #0x03FC
+  0x34181C02:  9307         STR        R3, [SP, #28]
+  0x34181C04:  9208         STR        R2, [SP, #32]
+  0x34181C06:  9009         STR        R0, [SP, #36]
+  0x34181C08:  F641 4000    MOVW       R0, #0x1C00
+  0x34181C0C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181C10:  F7FF F816    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181C14:  9B01         LDR        R3, [SP, #4]
+  0x34181C16:  9A02         LDR        R2, [SP, #8]
+  0x34181C18:  9804         LDR        R0, [SP, #16]
+  0x34181C1A:  9906         LDR        R1, [SP, #24]
+  0x34181C1C:  9307         STR        R3, [SP, #28]
+  0x34181C1E:  9208         STR        R2, [SP, #32]
+  0x34181C20:  9009         STR        R0, [SP, #36]
+  0x34181C22:  F240 4000    MOVW       R0, #0x0400
+  0x34181C26:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181C2A:  F7FF F809    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181C2E:  9B01         LDR        R3, [SP, #4]
+  0x34181C30:  9A02         LDR        R2, [SP, #8]
+  0x34181C32:  9804         LDR        R0, [SP, #16]
+  0x34181C34:  9906         LDR        R1, [SP, #24]
+  0x34181C36:  9307         STR        R3, [SP, #28]
+  0x34181C38:  9208         STR        R2, [SP, #32]
+  0x34181C3A:  9009         STR        R0, [SP, #36]
+  0x34181C3C:  F643 4000    MOVW       R0, #0x3C00
+  0x34181C40:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181C44:  F7FE FFFC    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181C48:  9A02         LDR        R2, [SP, #8]
+  0x34181C4A:  9804         LDR        R0, [SP, #16]
+  0x34181C4C:  9906         LDR        R1, [SP, #24]
+  0x34181C4E:  233F         MOVS       R3, #63
+  0x34181C50:  9307         STR        R3, [SP, #28]
+  0x34181C52:  9208         STR        R2, [SP, #32]
+  0x34181C54:  9009         STR        R0, [SP, #36]
+  0x34181C56:  F643 0000    MOVW       R0, #0x3800
+  0x34181C5A:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181C5E:  F7FE FFEF    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181C62:  9B02         LDR        R3, [SP, #8]
+  0x34181C64:  9A04         LDR        R2, [SP, #16]
+  0x34181C66:  9805         LDR        R0, [SP, #20]
+  0x34181C68:  9906         LDR        R1, [SP, #24]
+  0x34181C6A:  F64F 3CFE    MOVW       R12, #0xFBFE
+  0x34181C6E:  F8CD C01C    STR.W      R12, [SP, #28]
+  0x34181C72:  9308         STR        R3, [SP, #32]
+  0x34181C74:  9209         STR        R2, [SP, #36]
+  0x34181C76:  F7FE FFE3    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181C7A:  9B01         LDR        R3, [SP, #4]
+  0x34181C7C:  9A02         LDR        R2, [SP, #8]
+  0x34181C7E:  9804         LDR        R0, [SP, #16]
+  0x34181C80:  9906         LDR        R1, [SP, #24]
+  0x34181C82:  9307         STR        R3, [SP, #28]
+  0x34181C84:  9208         STR        R2, [SP, #32]
+  0x34181C86:  9009         STR        R0, [SP, #36]
+  0x34181C88:  F241 4000    MOVW       R0, #0x1400
+  0x34181C8C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181C90:  F7FE FFD6    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181C94:  9A02         LDR        R2, [SP, #8]
+  0x34181C96:  9804         LDR        R0, [SP, #16]
+  0x34181C98:  9906         LDR        R1, [SP, #24]
+  0x34181C9A:  F649 73FF    MOVW       R3, #0x9FFF
+  0x34181C9E:  9307         STR        R3, [SP, #28]
+  0x34181CA0:  9208         STR        R2, [SP, #32]
+  0x34181CA2:  9009         STR        R0, [SP, #36]
+  0x34181CA4:  2000         MOVS       R0, #0
+  0x34181CA6:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181CAA:  F7FE FFC9    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181CAE:  9A02         LDR        R2, [SP, #8]
+  0x34181CB0:  9804         LDR        R0, [SP, #16]
+  0x34181CB2:  9906         LDR        R1, [SP, #24]
+  0x34181CB4:  F44F 5384    MOV.W      R3, #0x1080
+  0x34181CB8:  9307         STR        R3, [SP, #28]
+  0x34181CBA:  9208         STR        R2, [SP, #32]
+  0x34181CBC:  9009         STR        R0, [SP, #36]
+  0x34181CBE:  F243 4000    MOVW       R0, #0x3400
+  0x34181CC2:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181CC6:  F7FE FFBB    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181CCA:  9B03         LDR        R3, [SP, #12]
+  0x34181CCC:  9A04         LDR        R2, [SP, #16]
+  0x34181CCE:  9805         LDR        R0, [SP, #20]
+  0x34181CD0:  9906         LDR        R1, [SP, #24]
+  0x34181CD2:  9307         STR        R3, [SP, #28]
+  0x34181CD4:  9308         STR        R3, [SP, #32]
+  0x34181CD6:  9209         STR        R2, [SP, #36]
+  0x34181CD8:  920A         STR        R2, [SP, #40]
+  0x34181CDA:  F7FE FFB1    BL         HAL_GPIO_Init            ; 0x34180C40
+  0x34181CDE:  B00C         ADD        SP, SP, #48
+  0x34181CE0:  BD80         POP        123R7, PC}
+
+

Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
PVD_PVM_IRQHandler:
+  0x34181CE2:  E7FE         B          PVD_PVM_IRQHandler       ; 0x34181CE2
+
+

Section .text.LL_AHB4_GRP1_EnableClock from blto2_FSBL_lto.o, size=34, align=4

+ +
+
LL_AHB4_GRP1_EnableClock:
+  0x34181CE4:  B082         SUB        SP, SP, #8
+  0x34181CE6:  9001         STR        R0, [SP, #4]
+  0x34181CE8:  9801         LDR        R0, [SP, #4]
+  0x34181CEA:  F648 215C    MOVW       R1, #0x8A5C
+  0x34181CEE:  F2C5 6102    MOVT       R1, #0x5602
+  0x34181CF2:  6008         STR        R0, [R1]
+  0x34181CF4:  F248 205C    MOVW       R0, #0x825C
+  0x34181CF8:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181CFC:  6800         LDR        R0, [R0]
+  0x34181CFE:  9000         STR        R0, [SP, #0]
+  0x34181D00:  9800         LDR        R0, [SP, #0]
+  0x34181D02:  B002         ADD        SP, SP, #8
+  0x34181D04:  4770         BX         LR
+
+

Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DTS_IRQHandler:
+  0x34181D06:  E7FE         B          DTS_IRQHandler           ; 0x34181D06
+
+

Section .text.main from blto2_FSBL_lto.o, size=66, align=4

+ +
+
main:
+  0x34181D08:  B580         PUSH       123R7, LR}
+  0x34181D0A:  B084         SUB        SP, SP, #16
+  0x34181D0C:  2000         MOVS       R0, #0
+  0x34181D0E:  9003         STR        R0, [SP, #12]
+  0x34181D10:  F7FE FEC4    BL         HAL_Init                 ; 0x34180A9C
+  0x34181D14:  F000 F81A    BL         SystemClock_Config       ; 0x34181D4C
+  0x34181D18:  F7FF FEFA    BL         MX_GPIO_Init             ; 0x34181B10
+
.L1:
+  0x34181D1C:  F641 0000    MOVW       R0, #0x1800
+  0x34181D20:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181D24:  9000         STR        R0, [SP, #0]
+  0x34181D26:  2201         MOVS       R2, #1
+  0x34181D28:  9201         STR        R2, [SP, #4]
+  0x34181D2A:  4611         MOV        R1, R2
+  0x34181D2C:  F000 FA70    BL         HAL_GPIO_WritePin        ; 0x34182210
+  0x34181D30:  20FA         MOVS       R0, #250
+  0x34181D32:  9002         STR        R0, [SP, #8]
+  0x34181D34:  F000 F9E6    BL         HAL_Delay                ; 0x34182104
+  0x34181D38:  9800         LDR        R0, [SP, #0]
+  0x34181D3A:  9901         LDR        R1, [SP, #4]
+  0x34181D3C:  2200         MOVS       R2, #0
+  0x34181D3E:  F000 FA67    BL         HAL_GPIO_WritePin        ; 0x34182210
+  0x34181D42:  9802         LDR        R0, [SP, #8]
+  0x34181D44:  F000 F9DE    BL         HAL_Delay                ; 0x34182104
+  0x34181D48:  E7E8         B          46L1                      ; 0x34181D1C
+
+

Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RCC_IRQHandler:
+  0x34181D4A:  E7FE         B          RCC_IRQHandler           ; 0x34181D4A
+
+

Section .text.SystemClock_Config from blto2_FSBL_lto.o, size=238, align=4

+ +
+
SystemClock_Config:
+  0x34181D4C:  B580         PUSH       123R7, LR}
+  0x34181D4E:  B0B8         SUB        SP, SP, #224
+  0x34181D50:  A812         ADD        R0, SP, #72
+  0x34181D52:  2198         MOVS       R1, #152
+  0x34181D54:  F7FF FEA8    BL         __aeabi_memclr           ; 0x34181AA8
+  0x34181D58:  A802         ADD        R0, SP, #8
+  0x34181D5A:  2140         MOVS       R1, #64
+  0x34181D5C:  F7FF FEA4    BL         __aeabi_memclr           ; 0x34181AA8
+  0x34181D60:  2000         MOVS       R0, #0
+  0x34181D62:  F000 FA89    BL         HAL_PWREx_ConfigSupply   ; 0x34182278
+  0x34181D66:  B108         CBZ        R0, .L1                  ; 0x34181D6C
+  0x34181D68:  F7FE FCF0    BL         Error_Handler            ; 0x3418074C
+
.L1:
+  0x34181D6C:  2001         MOVS       R0, #1
+  0x34181D6E:  F000 FABD    BL         HAL_PWREx_ControlVoltageScaling ; 0x341822EC
+  0x34181D72:  B108         CBZ        R0, .L2                  ; 0x34181D78
+  0x34181D74:  F7FE FCEA    BL         Error_Handler            ; 0x3418074C
+
.L2:
+  0x34181D78:  2002         MOVS       R0, #2
+  0x34181D7A:  9012         STR        R0, [SP, #72]
+  0x34181D7C:  2008         MOVS       R0, #8
+  0x34181D7E:  9015         STR        R0, [SP, #84]
+  0x34181D80:  2000         MOVS       R0, #0
+  0x34181D82:  9016         STR        R0, [SP, #88]
+  0x34181D84:  9017         STR        R0, [SP, #92]
+  0x34181D86:  901C         STR        R0, [SP, #112]
+  0x34181D88:  9023         STR        R0, [SP, #140]
+  0x34181D8A:  902A         STR        R0, [SP, #168]
+  0x34181D8C:  9031         STR        R0, [SP, #196]
+  0x34181D8E:  A812         ADD        R0, SP, #72
+  0x34181D90:  F000 FAF8    BL         HAL_RCC_OscConfig        ; 0x34182384
+  0x34181D94:  B108         CBZ        R0, .L3                  ; 0x34181D9A
+  0x34181D96:  F7FE FCD9    BL         Error_Handler            ; 0x3418074C
+
.L3:
+  0x34181D9A:  A802         ADD        R0, SP, #8
+  0x34181D9C:  F7FF FC1A    BL         HAL_RCC_GetClockConfig   ; 0x341815D4
+  0x34181DA0:  9803         LDR        R0, [SP, #12]
+  0x34181DA2:  F5B0 3F40    CMP.W      R0, #0x030000
+  0x34181DA6:  D003         BEQ        46L4                      ; 0x34181DB0
+  0x34181DA8:  9804         LDR        R0, [SP, #16]
+  0x34181DAA:  F1B0 7F40    CMP.W      R0, #0x03000000
+  0x34181DAE:  D10A         BNE        46L5                      ; 0x34181DC6
+
.L4:
+  0x34181DB0:  2003         MOVS       R0, #3
+  0x34181DB2:  9002         STR        R0, [SP, #8]
+  0x34181DB4:  2000         MOVS       R0, #0
+  0x34181DB6:  9003         STR        R0, [SP, #12]
+  0x34181DB8:  9004         STR        R0, [SP, #16]
+  0x34181DBA:  A802         ADD        R0, SP, #8
+  0x34181DBC:  F001 FAEE    BL         HAL_RCC_ClockConfig      ; 0x3418339C
+  0x34181DC0:  B108         CBZ        R0, .L5                  ; 0x34181DC6
+  0x34181DC2:  F7FE FCC3    BL         Error_Handler            ; 0x3418074C
+
.L5:
+  0x34181DC6:  2000         MOVS       R0, #0
+  0x34181DC8:  9012         STR        R0, [SP, #72]
+  0x34181DCA:  2102         MOVS       R1, #2
+  0x34181DCC:  911C         STR        R1, [SP, #112]
+  0x34181DCE:  901D         STR        R0, [SP, #116]
+  0x34181DD0:  2104         MOVS       R1, #4
+  0x34181DD2:  911E         STR        R1, [SP, #120]
+  0x34181DD4:  214B         MOVS       R1, #75
+  0x34181DD6:  9120         STR        R1, [SP, #128]
+  0x34181DD8:  901F         STR        R0, [SP, #124]
+  0x34181DDA:  2101         MOVS       R1, #1
+  0x34181DDC:  9121         STR        R1, [SP, #132]
+  0x34181DDE:  9122         STR        R1, [SP, #136]
+  0x34181DE0:  9023         STR        R0, [SP, #140]
+  0x34181DE2:  902A         STR        R0, [SP, #168]
+  0x34181DE4:  9031         STR        R0, [SP, #196]
+  0x34181DE6:  A812         ADD        R0, SP, #72
+  0x34181DE8:  F000 FACC    BL         HAL_RCC_OscConfig        ; 0x34182384
+  0x34181DEC:  B108         CBZ        R0, .L6                  ; 0x34181DF2
+  0x34181DEE:  F7FE FCAD    BL         Error_Handler            ; 0x3418074C
+
.L6:
+  0x34181DF2:  207F         MOVS       R0, #127
+  0x34181DF4:  9002         STR        R0, [SP, #8]
+  0x34181DF6:  F44F 3040    MOV.W      R0, #0x030000
+  0x34181DFA:  9003         STR        R0, [SP, #12]
+  0x34181DFC:  F04F 7040    MOV.W      R0, #0x03000000
+  0x34181E00:  9004         STR        R0, [SP, #16]
+  0x34181E02:  F44F 1080    MOV.W      R0, #0x100000
+  0x34181E06:  9005         STR        R0, [SP, #20]
+  0x34181E08:  2100         MOVS       R1, #0
+  0x34181E0A:  9101         STR        R1, [SP, #4]
+  0x34181E0C:  9106         STR        R1, [SP, #24]
+  0x34181E0E:  9107         STR        R1, [SP, #28]
+  0x34181E10:  9108         STR        R1, [SP, #32]
+  0x34181E12:  9109         STR        R1, [SP, #36]
+  0x34181E14:  910A         STR        R1, [SP, #40]
+  0x34181E16:  2002         MOVS       R0, #2
+  0x34181E18:  900B         STR        R0, [SP, #44]
+  0x34181E1A:  910C         STR        R1, [SP, #48]
+  0x34181E1C:  2003         MOVS       R0, #3
+  0x34181E1E:  900D         STR        R0, [SP, #52]
+  0x34181E20:  910E         STR        R1, [SP, #56]
+  0x34181E22:  2204         MOVS       R2, #4
+  0x34181E24:  920F         STR        R2, [SP, #60]
+  0x34181E26:  9110         STR        R1, [SP, #64]
+  0x34181E28:  9011         STR        R0, [SP, #68]
+  0x34181E2A:  A802         ADD        R0, SP, #8
+  0x34181E2C:  F001 FAB6    BL         HAL_RCC_ClockConfig      ; 0x3418339C
+  0x34181E30:  B108         CBZ        R0, .L7                  ; 0x34181E36
+  0x34181E32:  F7FE FC8B    BL         Error_Handler            ; 0x3418074C
+
.L7:
+  0x34181E36:  B038         ADD        SP, SP, #224
+  0x34181E38:  BD80         POP        123R7, PC}
+
+

Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LOCKUP_IRQHandler:
+  0x34181E3A:  E7FE         B          LOCKUP_IRQHandler        ; 0x34181E3A
+
+

Section .text.assert_failed from blto2_FSBL_lto.o, size=10, align=4

+ +
+
assert_failed:
+  0x34181E3C:  B082         SUB        SP, SP, #8
+  0x34181E3E:  9001         STR        R0, [SP, #4]
+  0x34181E40:  9100         STR        R1, [SP, #0]
+  0x34181E42:  B002         ADD        SP, SP, #8
+  0x34181E44:  4770         BX         LR
+
+

Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CACHE_ECC_IRQHandler:
+  0x34181E46:  E7FE         B          CACHE_ECC_IRQHandler     ; 0x34181E46
+
+

Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
NMI_Handler:
+  0x34181E48:  E7FE         B          NMI_Handler              ; 0x34181E48
+
+

Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TCM_ECC_IRQHandler:
+  0x34181E4A:  E7FE         B          TCM_ECC_IRQHandler       ; 0x34181E4A
+
+

Section .text.HardFault_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
HardFault_Handler:
+  0x34181E4C:  E7FE         B          HardFault_Handler        ; 0x34181E4C
+
+

Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
BCK_ECC_IRQHandler:
+  0x34181E4E:  E7FE         B          BCK_ECC_IRQHandler       ; 0x34181E4E
+
+

Section .text.MemManage_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
MemManage_Handler:
+  0x34181E50:  E7FE         B          MemManage_Handler        ; 0x34181E50
+
+

Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FPU_IRQHandler:
+  0x34181E52:  E7FE         B          FPU_IRQHandler           ; 0x34181E52
+
+

Section .text.BusFault_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
BusFault_Handler:
+  0x34181E54:  E7FE         B          BusFault_Handler         ; 0x34181E54
+
+

Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RTC_S_IRQHandler:
+  0x34181E56:  E7FE         B          RTC_S_IRQHandler         ; 0x34181E56
+
+

Section .text.UsageFault_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
UsageFault_Handler:
+  0x34181E58:  E7FE         B          UsageFault_Handler       ; 0x34181E58
+
+

Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TAMP_IRQHandler:
+  0x34181E5A:  E7FE         B          TAMP_IRQHandler          ; 0x34181E5A
+
+

Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
SVC_Handler:
+  0x34181E5C:  4770         BX         LR
+
+

Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RIFSC_TAMPER_IRQHandler:
+  0x34181E5E:  E7FE         B          RIFSC_TAMPER_IRQHandler  ; 0x34181E5E
+
+

Section .text.DebugMon_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
DebugMon_Handler:
+  0x34181E60:  4770         BX         LR
+
+

Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
IAC_IRQHandler:
+  0x34181E62:  E7FE         B          IAC_IRQHandler           ; 0x34181E62
+
+

Section .text.PendSV_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
PendSV_Handler:
+  0x34181E64:  4770         BX         LR
+
+

Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RCC_S_IRQHandler:
+  0x34181E66:  E7FE         B          RCC_S_IRQHandler         ; 0x34181E66
+
+

Section .text.SystemInit from blto2_FSBL_lto.o, size=510, align=4

+ +
+
SystemInit:
+  0x34181E68:  B510         PUSH       123R4, LR}
+  0x34181E6A:  F240 4000    MOVW       R0, #0x0400              ; 0x34180400 = g_pfnVectors
+  0x34181E6E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34180400 = g_pfnVectors
+  0x34181E72:  F64E 5108    MOVW       R1, #0xED08
+  0x34181E76:  F2CE 0100    MOVT       R1, #0xE000
+  0x34181E7A:  6008         STR        R0, [R1]
+  0x34181E7C:  F648 2218    MOVW       R2, #0x8A18
+  0x34181E80:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181E84:  2001         MOVS       R0, #1
+  0x34181E86:  6010         STR        R0, [R2]
+  0x34181E88:  F249 2218    MOVW       R2, #0x9218
+  0x34181E8C:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181E90:  6010         STR        R0, [R2]
+  0x34181E92:  F249 2258    MOVW       R2, #0x9258
+  0x34181E96:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181E9A:  6010         STR        R0, [R2]
+  0x34181E9C:  F64E 54D8    MOVW       R4, #0xEDD8
+  0x34181EA0:  F2CE 0400    MOVT       R4, #0xE000
+  0x34181EA4:  2200         MOVS       R2, #0
+  0x34181EA6:  6022         STR        R2, [R4]
+  0x34181EA8:  F64E 5CDC    MOVW       R12, #0xEDDC
+  0x34181EAC:  F2CE 0C00    MOVT       R12, #0xE000
+  0x34181EB0:  F8CC 2000    STR.W      R2, [R12]
+  0x34181EB4:  F64E 53E0    MOVW       R3, #0xEDE0
+  0x34181EB8:  F2CE 0300    MOVT       R3, #0xE000
+  0x34181EBC:  601A         STR        R2, [R3]
+  0x34181EBE:  6020         STR        R0, [R4]
+  0x34181EC0:  F8CC 2000    STR.W      R2, [R12]
+  0x34181EC4:  601A         STR        R2, [R3]
+  0x34181EC6:  F04F 0E02    MOV.W      LR, #2
+  0x34181ECA:  F8C4 E000    STR.W      LR, [R4]
+  0x34181ECE:  F8CC 2000    STR.W      R2, [R12]
+  0x34181ED2:  601A         STR        R2, [R3]
+  0x34181ED4:  F04F 0E03    MOV.W      LR, #3
+  0x34181ED8:  F8C4 E000    STR.W      LR, [R4]
+  0x34181EDC:  F8CC 2000    STR.W      R2, [R12]
+  0x34181EE0:  601A         STR        R2, [R3]
+  0x34181EE2:  F04F 0E04    MOV.W      LR, #4
+  0x34181EE6:  F8C4 E000    STR.W      LR, [R4]
+  0x34181EEA:  F8CC 2000    STR.W      R2, [R12]
+  0x34181EEE:  601A         STR        R2, [R3]
+  0x34181EF0:  F04F 0E05    MOV.W      LR, #5
+  0x34181EF4:  F8C4 E000    STR.W      LR, [R4]
+  0x34181EF8:  F8CC 2000    STR.W      R2, [R12]
+  0x34181EFC:  601A         STR        R2, [R3]
+  0x34181EFE:  F04F 0E06    MOV.W      LR, #6
+  0x34181F02:  F8C4 E000    STR.W      LR, [R4]
+  0x34181F06:  F8CC 2000    STR.W      R2, [R12]
+  0x34181F0A:  601A         STR        R2, [R3]
+  0x34181F0C:  F04F 0E07    MOV.W      LR, #7
+  0x34181F10:  F8C4 E000    STR.W      LR, [R4]
+  0x34181F14:  F8CC 2000    STR.W      R2, [R12]
+  0x34181F18:  601A         STR        R2, [R3]
+  0x34181F1A:  F648 2278    MOVW       R2, #0x8A78
+  0x34181F1E:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181F22:  6010         STR        R0, [R2]
+  0x34181F24:  F248 2378    MOVW       R3, #0x8278
+  0x34181F28:  F2C5 6302    MOVT       R3, #0x5602
+  0x34181F2C:  681A         LDR        R2, [R3]
+  0x34181F2E:  680A         LDR        R2, [R1]
+  0x34181F30:  F248 0110    MOVW       R1, #0x8010
+  0x34181F34:  F2C5 6100    MOVT       R1, #0x5600
+  0x34181F38:  600A         STR        R2, [R1]
+  0x34181F3A:  F644 0C34    MOVW       R12, #0x4834
+  0x34181F3E:  F2C5 6C02    MOVT       R12, #0x5602
+  0x34181F42:  F8DC 2000    LDR.W      R2, [R12]
+  0x34181F46:  F442 7280    ORR        R2, R2, #0x0100
+  0x34181F4A:  F8CC 2000    STR.W      R2, [R12]
+  0x34181F4E:  F644 0C38    MOVW       R12, #0x4838
+  0x34181F52:  F2C5 6C02    MOVT       R12, #0x5602
+  0x34181F56:  F8DC 2000    LDR.W      R2, [R12]
+  0x34181F5A:  F442 7280    ORR        R2, R2, #0x0100
+  0x34181F5E:  F8CC 2000    STR.W      R2, [R12]
+  0x34181F62:  F644 023C    MOVW       R2, #0x483C
+  0x34181F66:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181F6A:  F8D2 C000    LDR.W      R12, [R2]
+  0x34181F6E:  F44C 7C40    ORR        R12, R12, #0x0300
+  0x34181F72:  F8C2 C000    STR.W      R12, [R2]
+  0x34181F76:  F248 0E54    MOVW       LR, #0x8054
+  0x34181F7A:  F2C5 6E00    MOVT       LR, #0x5600
+  0x34181F7E:  F240 2C87    MOVW       R12, #0x0287
+  0x34181F82:  F8CE C000    STR.W      R12, [LR]
+  0x34181F86:  F248 0E5C    MOVW       LR, #0x805C
+  0x34181F8A:  F2C5 6E00    MOVT       LR, #0x5600
+  0x34181F8E:  F8CE C000    STR.W      R12, [LR]
+  0x34181F92:  F248 0E44    MOVW       LR, #0x8044
+  0x34181F96:  F2C5 6E00    MOVT       LR, #0x5600
+  0x34181F9A:  F8CE C000    STR.W      R12, [LR]
+  0x34181F9E:  F248 0E4C    MOVW       LR, #0x804C
+  0x34181FA2:  F2C5 6E00    MOVT       LR, #0x5600
+  0x34181FA6:  F8CE C000    STR.W      R12, [LR]
+  0x34181FAA:  F248 0E64    MOVW       LR, #0x8064
+  0x34181FAE:  F2C5 6E00    MOVT       LR, #0x5600
+  0x34181FB2:  F8CE C000    STR.W      R12, [LR]
+  0x34181FB6:  F8D2 C000    LDR.W      R12, [R2]
+  0x34181FBA:  F44C 5C80    ORR        R12, R12, #0x1000
+  0x34181FBE:  F8C2 C000    STR.W      R12, [R2]
+  0x34181FC2:  F8D2 C000    LDR.W      R12, [R2]
+  0x34181FC6:  F04C 0C10    ORR        R12, R12, #16
+  0x34181FCA:  F8C2 C000    STR.W      R12, [R2]
+  0x34181FCE:  6812         LDR        R2, [R2]
+  0x34181FD0:  F248 2C74    MOVW       R12, #0x8274
+  0x34181FD4:  F2C5 6C02    MOVT       R12, #0x5602
+  0x34181FD8:  F8DC 2000    LDR.W      R2, [R12]
+  0x34181FDC:  F442 4200    ORR        R2, R2, #0x8000
+  0x34181FE0:  F8CC 2000    STR.W      R2, [R12]
+  0x34181FE4:  681A         LDR        R2, [R3]
+  0x34181FE6:  F042 0210    ORR        R2, R2, #16
+  0x34181FEA:  601A         STR        R2, [R3]
+  0x34181FEC:  681A         LDR        R2, [R3]
+  0x34181FEE:  681A         LDR        R2, [R3]
+  0x34181FF0:  F022 0210    BIC        R2, R2, #16
+  0x34181FF4:  601A         STR        R2, [R3]
+  0x34181FF6:  F648 2320    MOVW       R3, #0x8A20
+  0x34181FFA:  F2C5 6302    MOVT       R3, #0x5602
+  0x34181FFE:  F44F 5240    MOV.W      R2, #0x3000
+  0x34182002:  601A         STR        R2, [R3]
+  0x34182004:  F249 2320    MOVW       R3, #0x9220
+  0x34182008:  F2C5 6302    MOVT       R3, #0x5602
+  0x3418200C:  601A         STR        R2, [R3]
+  0x3418200E:  F648 2224    MOVW       R2, #0x8A24
+  0x34182012:  F2C5 6202    MOVT       R2, #0x5602
+  0x34182016:  6010         STR        R0, [R2]
+  0x34182018:  F249 2224    MOVW       R2, #0x9224
+  0x3418201C:  F2C5 6202    MOVT       R2, #0x5602
+  0x34182020:  6010         STR        R0, [R2]
+  0x34182022:  F249 2264    MOVW       R2, #0x9264
+  0x34182026:  F2C5 6202    MOVT       R2, #0x5602
+  0x3418202A:  6010         STR        R0, [R2]
+  0x3418202C:  F249 235C    MOVW       R3, #0x925C
+  0x34182030:  F2C5 6302    MOVT       R3, #0x5602
+  0x34182034:  2240         MOVS       R2, #64
+  0x34182036:  601A         STR        R2, [R3]
+  0x34182038:  6809         LDR        R1, [R1]
+  0x3418203A:  F249 2178    MOVW       R1, #0x9278
+  0x3418203E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182042:  6008         STR        R0, [R1]
+  0x34182044:  F64E 5188    MOVW       R1, #0xED88
+  0x34182048:  F2CE 0100    MOVT       R1, #0xE000
+  0x3418204C:  6808         LDR        R0, [R1]
+  0x3418204E:  F440 0070    ORR        R0, R0, #0xF00000
+  0x34182052:  6008         STR        R0, [R1]
+  0x34182054:  F64E 5188    MOVW       R1, #0xED88
+  0x34182058:  F2CE 0102    MOVT       R1, #0xE002
+  0x3418205C:  6808         LDR        R0, [R1]
+  0x3418205E:  F440 0070    ORR        R0, R0, #0xF00000
+  0x34182062:  6008         STR        R0, [R1]
+  0x34182064:  BD10         POP        123R4, PC}
+
+

Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RTC_IRQHandler:
+  0x34182066:  E7FE         B          RTC_IRQHandler           ; 0x34182066
+
+

Section .text.HAL_InitTick from blto2_FSBL_lto.o, size=126, align=4

+ +
+
HAL_InitTick:
+  0x34182068:  B580         PUSH       123R7, LR}
+  0x3418206A:  B082         SUB        SP, SP, #8
+  0x3418206C:  9000         STR        R0, [SP, #0]
+  0x3418206E:  F244 3061    MOVW       R0, #0x4361              ; 0x34184361 = uwTickFreq
+  0x34182072:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184361 = uwTickFreq
+  0x34182076:  7800         LDRB       R0, [R0]
+  0x34182078:  B918         CBNZ       R0, .L1                  ; 0x34182082
+  0x3418207A:  2001         MOVS       R0, #1
+  0x3418207C:  F88D 0007    STRB.W     R0, [SP, #7]
+  0x34182080:  E02D         B          46L5                      ; 0x341820DE
+
.L1:
+  0x34182082:  F244 4048    MOVW       R0, #0x4448              ; 0x34184448 = SystemCoreClock
+  0x34182086:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184448 = SystemCoreClock
+  0x3418208A:  6800         LDR        R0, [R0]
+  0x3418208C:  F244 3161    MOVW       R1, #0x4361              ; 0x34184361 = uwTickFreq
+  0x34182090:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34184361 = uwTickFreq
+  0x34182094:  780A         LDRB       R2, [R1]
+  0x34182096:  F44F 717A    MOV.W      R1, #0x03E8
+  0x3418209A:  FBB1 F1F2    UDIV       R1, R1, R2
+  0x3418209E:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x341820A2:  F7FE FDC5    BL         HAL_SYSTICK_Config       ; 0x34180C30
+  0x341820A6:  B118         CBZ        R0, .L2                  ; 0x341820B0
+  0x341820A8:  2001         MOVS       R0, #1
+  0x341820AA:  F88D 0007    STRB.W     R0, [SP, #7]
+  0x341820AE:  E016         B          46L5                      ; 0x341820DE
+
.L2:
+  0x341820B0:  9800         LDR        R0, [SP, #0]
+  0x341820B2:  280F         CMP        R0, #15
+  0x341820B4:  D80C         BHI        46L3                      ; 0x341820D0
+  0x341820B6:  9900         LDR        R1, [SP, #0]
+  0x341820B8:  F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+  0x341820BC:  2200         MOVS       R2, #0
+  0x341820BE:  F7FE FD29    BL         HAL_NVIC_SetPriority     ; 0x34180B14
+  0x341820C2:  9800         LDR        R0, [SP, #0]
+  0x341820C4:  F244 4144    MOVW       R1, #0x4444              ; 0x34184444 = uwTickPrio
+  0x341820C8:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34184444 = uwTickPrio
+  0x341820CC:  6008         STR        R0, [R1]
+  0x341820CE:  E003         B          46L4                      ; 0x341820D8
+
.L3:
+  0x341820D0:  2001         MOVS       R0, #1
+  0x341820D2:  F88D 0007    STRB.W     R0, [SP, #7]
+  0x341820D6:  E002         B          46L5                      ; 0x341820DE
+
.L4:
+  0x341820D8:  2000         MOVS       R0, #0
+  0x341820DA:  F88D 0007    STRB.W     R0, [SP, #7]
+
.L5:
+  0x341820DE:  F89D 0007    LDRB.W     R0, [SP, #7]
+  0x341820E2:  B002         ADD        SP, SP, #8
+  0x341820E4:  BD80         POP        123R7, PC}
+
+

Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
IWDG_IRQHandler:
+  0x341820E6:  E7FE         B          IWDG_IRQHandler          ; 0x341820E6
+
+

Section .text.HAL_IncTick from blto2_FSBL_lto.o, size=26, align=4

+ +
+
HAL_IncTick:
+  0x341820E8:  F244 3061    MOVW       R0, #0x4361              ; 0x34184361 = uwTickFreq
+  0x341820EC:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184361 = uwTickFreq
+  0x341820F0:  7802         LDRB       R2, [R0]
+  0x341820F2:  F244 4140    MOVW       R1, #0x4440              ; 0x34184440 = uwTick
+  0x341820F6:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34184440 = uwTick
+  0x341820FA:  6808         LDR        R0, [R1]
+  0x341820FC:  4410         ADD        R0, R2
+  0x341820FE:  6008         STR        R0, [R1]
+  0x34182100:  4770         BX         LR
+
+

Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
WWDG_IRQHandler:
+  0x34182102:  E7FE         B          WWDG_IRQHandler          ; 0x34182102
+
+

Section .text.HAL_Delay from blto2_FSBL_lto.o, size=58, align=4

+ +
+
HAL_Delay:
+  0x34182104:  B580         PUSH       123R7, LR}
+  0x34182106:  B084         SUB        SP, SP, #16
+  0x34182108:  9003         STR        R0, [SP, #12]
+  0x3418210A:  F7FE FCDF    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418210E:  9002         STR        R0, [SP, #8]
+  0x34182110:  9803         LDR        R0, [SP, #12]
+  0x34182112:  9001         STR        R0, [SP, #4]
+  0x34182114:  9801         LDR        R0, [SP, #4]
+  0x34182116:  3001         ADDS       R0, #1
+  0x34182118:  B138         CBZ        R0, .L1                  ; 0x3418212A
+  0x3418211A:  F244 3061    MOVW       R0, #0x4361              ; 0x34184361 = uwTickFreq
+  0x3418211E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184361 = uwTickFreq
+  0x34182122:  7801         LDRB       R1, [R0]
+  0x34182124:  9801         LDR        R0, [SP, #4]
+  0x34182126:  4408         ADD        R0, R1
+  0x34182128:  9001         STR        R0, [SP, #4]
+
.L1:
+  0x3418212A:  F7FE FCCF    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418212E:  9902         LDR        R1, [SP, #8]
+  0x34182130:  1A40         SUBS       R0, R0, R1
+  0x34182132:  9901         LDR        R1, [SP, #4]
+  0x34182134:  4288         CMP        R0, R1
+  0x34182136:  D200         BCS        46L2                      ; 0x3418213A
+  0x34182138:  E7F7         B          46L1                      ; 0x3418212A
+
.L2:
+  0x3418213A:  B004         ADD        SP, SP, #16
+  0x3418213C:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI0_IRQHandler:
+  0x3418213E:  E7FE         B          EXTI0_IRQHandler         ; 0x3418213E
+
+

Section .text.HAL_NVIC_SetPriorityGrouping from blto2_FSBL_lto.o, size=62, align=4

+ +
+
HAL_NVIC_SetPriorityGrouping:
+  0x34182140:  B580         PUSH       123R7, LR}
+  0x34182142:  B082         SUB        SP, SP, #8
+  0x34182144:  9001         STR        R0, [SP, #4]
+  0x34182146:  9801         LDR        R0, [SP, #4]
+  0x34182148:  2807         CMP        R0, #7
+  0x3418214A:  D00B         BEQ        46L1                      ; 0x34182164
+  0x3418214C:  9801         LDR        R0, [SP, #4]
+  0x3418214E:  2806         CMP        R0, #6
+  0x34182150:  D008         BEQ        46L1                      ; 0x34182164
+  0x34182152:  9801         LDR        R0, [SP, #4]
+  0x34182154:  2805         CMP        R0, #5
+  0x34182156:  D005         BEQ        46L1                      ; 0x34182164
+  0x34182158:  9801         LDR        R0, [SP, #4]
+  0x3418215A:  2804         CMP        R0, #4
+  0x3418215C:  D002         BEQ        46L1                      ; 0x34182164
+  0x3418215E:  9801         LDR        R0, [SP, #4]
+  0x34182160:  2803         CMP        R0, #3
+  0x34182162:  D100         BNE        46L2                      ; 0x34182166
+
.L1:
+  0x34182164:  E006         B          46L3                      ; 0x34182174
+
.L2:
+  0x34182166:  F244 3068    MOVW       R0, #0x4368              ; 0x34184368 = .rodata..L.str.10
+  0x3418216A:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184368 = .rodata..L.str.10
+  0x3418216E:  21E6         MOVS       R1, #230
+  0x34182170:  F7FF FE64    BL         assert_failed            ; 0x34181E3C
+
.L3:
+  0x34182174:  9801         LDR        R0, [SP, #4]
+  0x34182176:  F7FE FCAF    BL         __NVIC_SetPriorityGrouping ; 0x34180AD8
+  0x3418217A:  B002         ADD        SP, SP, #8
+  0x3418217C:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI1_IRQHandler:
+  0x3418217E:  E7FE         B          EXTI1_IRQHandler         ; 0x3418217E
+
+

Section .text.__NVIC_SetPriority from blto2_FSBL_lto.o, size=62, align=4

+ +
+
__NVIC_SetPriority:
+  0x34182180:  B082         SUB        SP, SP, #8
+  0x34182182:  F8AD 0006    STRH.W     R0, [SP, #6]
+  0x34182186:  9100         STR        R1, [SP, #0]
+  0x34182188:  F9BD 0006    LDRSH.W    R0, [SP, #6]
+  0x3418218C:  2800         CMP        R0, #0
+  0x3418218E:  D409         BMI        46L1                      ; 0x341821A4
+  0x34182190:  9800         LDR        R0, [SP, #0]
+  0x34182192:  0100         LSLS       R0, R0, #4
+  0x34182194:  F9BD 1006    LDRSH.W    R1, [SP, #6]
+  0x34182198:  F24E 4200    MOVW       R2, #0xE400
+  0x3418219C:  F2CE 0200    MOVT       R2, #0xE000
+  0x341821A0:  5488         STRB       R0, [R1, R2]
+  0x341821A2:  E00A         B          46L2                      ; 0x341821BA
+
.L1:
+  0x341821A4:  9800         LDR        R0, [SP, #0]
+  0x341821A6:  0100         LSLS       R0, R0, #4
+  0x341821A8:  F8BD 1006    LDRH.W     R1, [SP, #6]
+  0x341821AC:  F001 010F    AND        R1, R1, #15
+  0x341821B0:  F64E 5214    MOVW       R2, #0xED14
+  0x341821B4:  F2CE 0200    MOVT       R2, #0xE000
+  0x341821B8:  5488         STRB       R0, [R1, R2]
+
.L2:
+  0x341821BA:  B002         ADD        SP, SP, #8
+  0x341821BC:  4770         BX         LR
+
+

Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI2_IRQHandler:
+  0x341821BE:  E7FE         B          EXTI2_IRQHandler         ; 0x341821BE
+
+

Section .text.SysTick_Config from blto2_FSBL_lto.o, size=78, align=4

+ +
+
SysTick_Config:
+  0x341821C0:  B580         PUSH       123R7, LR}
+  0x341821C2:  B082         SUB        SP, SP, #8
+  0x341821C4:  9000         STR        R0, [SP, #0]
+  0x341821C6:  9800         LDR        R0, [SP, #0]
+  0x341821C8:  3801         SUBS       R0, #1
+  0x341821CA:  F1B0 7F80    CMP.W      R0, #0x01000000
+  0x341821CE:  D302         BCC        46L1                      ; 0x341821D6
+  0x341821D0:  2001         MOVS       R0, #1
+  0x341821D2:  9001         STR        R0, [SP, #4]
+  0x341821D4:  E018         B          46L2                      ; 0x34182208
+
.L1:
+  0x341821D6:  9800         LDR        R0, [SP, #0]
+  0x341821D8:  3801         SUBS       R0, #1
+  0x341821DA:  F24E 0114    MOVW       R1, #0xE014
+  0x341821DE:  F2CE 0100    MOVT       R1, #0xE000
+  0x341821E2:  6008         STR        R0, [R1]
+  0x341821E4:  F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+  0x341821E8:  210F         MOVS       R1, #15
+  0x341821EA:  F7FF FFC9    BL         __NVIC_SetPriority       ; 0x34182180
+  0x341821EE:  F24E 0118    MOVW       R1, #0xE018
+  0x341821F2:  F2CE 0100    MOVT       R1, #0xE000
+  0x341821F6:  2000         MOVS       R0, #0
+  0x341821F8:  6008         STR        R0, [R1]
+  0x341821FA:  F24E 0210    MOVW       R2, #0xE010
+  0x341821FE:  F2CE 0200    MOVT       R2, #0xE000
+  0x34182202:  2107         MOVS       R1, #7
+  0x34182204:  6011         STR        R1, [R2]
+  0x34182206:  9001         STR        R0, [SP, #4]
+
.L2:
+  0x34182208:  9801         LDR        R0, [SP, #4]
+  0x3418220A:  B002         ADD        SP, SP, #8
+  0x3418220C:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI3_IRQHandler:
+  0x3418220E:  E7FE         B          EXTI3_IRQHandler         ; 0x3418220E
+
+

Section .text.HAL_GPIO_WritePin from blto2_FSBL_lto.o, size=102, align=4

+ +
+
HAL_GPIO_WritePin:
+  0x34182210:  B580         PUSH       123R7, LR}
+  0x34182212:  B082         SUB        SP, SP, #8
+  0x34182214:  9001         STR        R0, [SP, #4]
+  0x34182216:  F8AD 1002    STRH.W     R1, [SP, #2]
+  0x3418221A:  F88D 2001    STRB.W     R2, [SP, #1]
+  0x3418221E:  F8BD 0002    LDRH.W     R0, [SP, #2]
+  0x34182222:  B110         CBZ        R0, .L1                  ; 0x3418222A
+  0x34182224:  2000         MOVS       R0, #0
+  0x34182226:  B900         CBNZ       R0, .L1                  ; 0x3418222A
+  0x34182228:  E007         B          46L2                      ; 0x3418223A
+
.L1:
+  0x3418222A:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x3418222E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34182232:  F44F 71D0    MOV.W      R1, #0x01A0
+  0x34182236:  F7FF FE01    BL         assert_failed            ; 0x34181E3C
+
.L2:
+  0x3418223A:  F89D 0001    LDRB.W     R0, [SP, #1]
+  0x3418223E:  B118         CBZ        R0, .L3                  ; 0x34182248
+  0x34182240:  F89D 0001    LDRB.W     R0, [SP, #1]
+  0x34182244:  2801         CMP        R0, #1
+  0x34182246:  D100         BNE        46L4                      ; 0x3418224A
+
.L3:
+  0x34182248:  E007         B          46L5                      ; 0x3418225A
+
.L4:
+  0x3418224A:  F244 208E    MOVW       R0, #0x428E              ; 0x3418428E = .rodata..L.str.20
+  0x3418224E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418428E = .rodata..L.str.20
+  0x34182252:  F240 11A1    MOVW       R1, #0x01A1
+  0x34182256:  F7FF FDF1    BL         assert_failed            ; 0x34181E3C
+
.L5:
+  0x3418225A:  F89D 0001    LDRB.W     R0, [SP, #1]
+  0x3418225E:  B120         CBZ        R0, .L6                  ; 0x3418226A
+  0x34182260:  F8BD 0002    LDRH.W     R0, [SP, #2]
+  0x34182264:  9901         LDR        R1, [SP, #4]
+  0x34182266:  6188         STR        R0, [R1, #24]
+  0x34182268:  E003         B          46L7                      ; 0x34182272
+
.L6:
+  0x3418226A:  F8BD 0002    LDRH.W     R0, [SP, #2]
+  0x3418226E:  9901         LDR        R1, [SP, #4]
+  0x34182270:  6288         STR        R0, [R1, #40]
+
.L7:
+  0x34182272:  B002         ADD        SP, SP, #8
+  0x34182274:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI4_IRQHandler:
+  0x34182276:  E7FE         B          EXTI4_IRQHandler         ; 0x34182276
+
+

Section .text.HAL_PWREx_ConfigSupply from blto2_FSBL_lto.o, size=114, align=4

+ +
+
HAL_PWREx_ConfigSupply:
+  0x34182278:  B580         PUSH       123R7, LR}
+  0x3418227A:  B084         SUB        SP, SP, #16
+  0x3418227C:  9002         STR        R0, [SP, #8]
+  0x3418227E:  9802         LDR        R0, [SP, #8]
+  0x34182280:  2804         CMP        R0, #4
+  0x34182282:  D001         BEQ        46L1                      ; 0x34182288
+  0x34182284:  9802         LDR        R0, [SP, #8]
+  0x34182286:  B900         CBNZ       R0, .L2                  ; 0x3418228A
+
.L1:
+  0x34182288:  E007         B          46L3                      ; 0x3418229A
+
.L2:
+  0x3418228A:  F244 30D4    MOVW       R0, #0x43D4              ; 0x341843D4 = .rodata..L.str.28
+  0x3418228E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341843D4 = .rodata..L.str.28
+  0x34182292:  F44F 7187    MOV.W      R1, #0x010E
+  0x34182296:  F7FF FDD1    BL         assert_failed            ; 0x34181E3C
+
.L3:
+  0x3418229A:  F644 0100    MOVW       R1, #0x4800
+  0x3418229E:  F2C5 6102    MOVT       R1, #0x5602
+  0x341822A2:  6808         LDR        R0, [R1]
+  0x341822A4:  F020 0004    BIC        R0, R0, #4
+  0x341822A8:  9A02         LDR        R2, [SP, #8]
+  0x341822AA:  4310         ORRS       R0, R2
+  0x341822AC:  6008         STR        R0, [R1]
+  0x341822AE:  F7FE FC0D    BL         HAL_GetTick              ; 0x34180ACC
+  0x341822B2:  9001         STR        R0, [SP, #4]
+
.L4:
+  0x341822B4:  F644 0020    MOVW       R0, #0x4820
+  0x341822B8:  F2C5 6002    MOVT       R0, #0x5602
+  0x341822BC:  6800         LDR        R0, [R0]
+  0x341822BE:  0380         LSLS       R0, R0, #14
+  0x341822C0:  2800         CMP        R0, #0
+  0x341822C2:  D40B         BMI        46L6                      ; 0x341822DC
+  0x341822C4:  F7FE FC02    BL         HAL_GetTick              ; 0x34180ACC
+  0x341822C8:  9901         LDR        R1, [SP, #4]
+  0x341822CA:  1A40         SUBS       R0, R0, R1
+  0x341822CC:  F5B0 7F7A    CMP.W      R0, #0x03E8
+  0x341822D0:  D903         BLS        46L5                      ; 0x341822DA
+  0x341822D2:  2001         MOVS       R0, #1
+  0x341822D4:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341822D8:  E003         B          46L7                      ; 0x341822E2
+
.L5:
+  0x341822DA:  E7EB         B          46L4                      ; 0x341822B4
+
.L6:
+  0x341822DC:  2000         MOVS       R0, #0
+  0x341822DE:  F88D 000F    STRB.W     R0, [SP, #15]
+
.L7:
+  0x341822E2:  F89D 000F    LDRB.W     R0, [SP, #15]
+  0x341822E6:  B004         ADD        SP, SP, #16
+  0x341822E8:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI5_IRQHandler:
+  0x341822EA:  E7FE         B          EXTI5_IRQHandler         ; 0x341822EA
+
+

Section .text.HAL_PWREx_ControlVoltageScaling from blto2_FSBL_lto.o, size=114, align=4

+ +
+
HAL_PWREx_ControlVoltageScaling:
+  0x341822EC:  B580         PUSH       123R7, LR}
+  0x341822EE:  B084         SUB        SP, SP, #16
+  0x341822F0:  9002         STR        R0, [SP, #8]
+  0x341822F2:  9802         LDR        R0, [SP, #8]
+  0x341822F4:  2801         CMP        R0, #1
+  0x341822F6:  D001         BEQ        46L1                      ; 0x341822FC
+  0x341822F8:  9802         LDR        R0, [SP, #8]
+  0x341822FA:  B900         CBNZ       R0, .L2                  ; 0x341822FE
+
.L1:
+  0x341822FC:  E007         B          46L3                      ; 0x3418230E
+
.L2:
+  0x341822FE:  F244 30D4    MOVW       R0, #0x43D4              ; 0x341843D4 = .rodata..L.str.28
+  0x34182302:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341843D4 = .rodata..L.str.28
+  0x34182306:  F240 1141    MOVW       R1, #0x0141
+  0x3418230A:  F7FF FD97    BL         assert_failed            ; 0x34181E3C
+
.L3:
+  0x3418230E:  F644 0120    MOVW       R1, #0x4820
+  0x34182312:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182316:  6808         LDR        R0, [R1]
+  0x34182318:  F020 0001    BIC        R0, R0, #1
+  0x3418231C:  9A02         LDR        R2, [SP, #8]
+  0x3418231E:  4310         ORRS       R0, R2
+  0x34182320:  6008         STR        R0, [R1]
+  0x34182322:  F7FE FBD3    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182326:  9001         STR        R0, [SP, #4]
+
.L4:
+  0x34182328:  F644 0020    MOVW       R0, #0x4820
+  0x3418232C:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182330:  6800         LDR        R0, [R0]
+  0x34182332:  0780         LSLS       R0, R0, #30
+  0x34182334:  2800         CMP        R0, #0
+  0x34182336:  D40B         BMI        46L6                      ; 0x34182350
+  0x34182338:  F7FE FBC8    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418233C:  9901         LDR        R1, [SP, #4]
+  0x3418233E:  1A40         SUBS       R0, R0, R1
+  0x34182340:  F5B0 7F7A    CMP.W      R0, #0x03E8
+  0x34182344:  D903         BLS        46L5                      ; 0x3418234E
+  0x34182346:  2001         MOVS       R0, #1
+  0x34182348:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x3418234C:  E003         B          46L7                      ; 0x34182356
+
.L5:
+  0x3418234E:  E7EB         B          46L4                      ; 0x34182328
+
.L6:
+  0x34182350:  2000         MOVS       R0, #0
+  0x34182352:  F88D 000F    STRB.W     R0, [SP, #15]
+
.L7:
+  0x34182356:  F89D 000F    LDRB.W     R0, [SP, #15]
+  0x3418235A:  B004         ADD        SP, SP, #16
+  0x3418235C:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI6_IRQHandler:
+  0x3418235E:  E7FE         B          EXTI6_IRQHandler         ; 0x3418235E
+
+

Section .text.HAL_PWREx_EnableVddIO3 from blto2_FSBL_lto.o, size=18, align=4

+ +
+
HAL_PWREx_EnableVddIO3:
+  0x34182360:  F644 013C    MOVW       R1, #0x483C
+  0x34182364:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182368:  6808         LDR        R0, [R1]
+  0x3418236A:  F440 7000    ORR        R0, R0, #0x0200
+  0x3418236E:  6008         STR        R0, [R1]
+  0x34182370:  4770         BX         LR
+
+

Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI7_IRQHandler:
+  0x34182372:  E7FE         B          EXTI7_IRQHandler         ; 0x34182372
+
+

Section .text.LL_RCC_HSI_Enable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_HSI_Enable:
+  0x34182374:  F648 0100    MOVW       R1, #0x8800
+  0x34182378:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418237C:  2008         MOVS       R0, #8
+  0x3418237E:  6008         STR        R0, [R1]
+  0x34182380:  4770         BX         LR
+
+

Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI8_IRQHandler:
+  0x34182382:  E7FE         B          EXTI8_IRQHandler         ; 0x34182382
+
+

Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=2810, align=4

+ +
+
HAL_RCC_OscConfig:
+  0x34182384:  B580         PUSH       123R7, LR}
+  0x34182386:  B0A2         SUB        SP, SP, #136
+  0x34182388:  9020         STR        R0, [SP, #128]
+  0x3418238A:  9820         LDR        R0, [SP, #128]
+  0x3418238C:  B920         CBNZ       R0, .L1                  ; 0x34182398
+  0x3418238E:  2001         MOVS       R0, #1
+  0x34182390:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182394:  F000 BD6F    B.W        46L144                    ; 0x34182E76
+
.L1:
+  0x34182398:  9820         LDR        R0, [SP, #128]
+  0x3418239A:  6800         LDR        R0, [R0]
+  0x3418239C:  B1E0         CBZ        R0, .L2                  ; 0x341823D8
+  0x3418239E:  9820         LDR        R0, [SP, #128]
+  0x341823A0:  6800         LDR        R0, [R0]
+  0x341823A2:  F000 0001    AND        R0, R0, #1
+  0x341823A6:  2801         CMP        R0, #1
+  0x341823A8:  D016         BEQ        46L2                      ; 0x341823D8
+  0x341823AA:  9820         LDR        R0, [SP, #128]
+  0x341823AC:  6800         LDR        R0, [R0]
+  0x341823AE:  F000 0002    AND        R0, R0, #2
+  0x341823B2:  2802         CMP        R0, #2
+  0x341823B4:  D010         BEQ        46L2                      ; 0x341823D8
+  0x341823B6:  9820         LDR        R0, [SP, #128]
+  0x341823B8:  6800         LDR        R0, [R0]
+  0x341823BA:  F000 0010    AND        R0, R0, #16
+  0x341823BE:  2810         CMP        R0, #16
+  0x341823C0:  D00A         BEQ        46L2                      ; 0x341823D8
+  0x341823C2:  9820         LDR        R0, [SP, #128]
+  0x341823C4:  6800         LDR        R0, [R0]
+  0x341823C6:  F000 0008    AND        R0, R0, #8
+  0x341823CA:  2808         CMP        R0, #8
+  0x341823CC:  D004         BEQ        46L2                      ; 0x341823D8
+  0x341823CE:  9820         LDR        R0, [SP, #128]
+  0x341823D0:  7800         LDRB       R0, [R0]
+  0x341823D2:  0740         LSLS       R0, R0, #29
+  0x341823D4:  2800         CMP        R0, #0
+  0x341823D6:  D500         BPL        46L3                      ; 0x341823DA
+
.L2:
+  0x341823D8:  E007         B          46L4                      ; 0x341823EA
+
.L3:
+  0x341823DA:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341823DE:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341823E2:  F44F 71BB    MOV.W      R1, #0x0176
+  0x341823E6:  F7FF FD29    BL         assert_failed            ; 0x34181E3C
+
.L4:
+  0x341823EA:  F7FF F803    BL         LL_RCC_GetCpuClkSource   ; 0x341813F4
+  0x341823EE:  901D         STR        R0, [SP, #116]
+  0x341823F0:  F7FF F808    BL         LL_RCC_GetSysClkSource   ; 0x34181404
+  0x341823F4:  901E         STR        R0, [SP, #120]
+  0x341823F6:  F7FF F80D    BL         LL_RCC_PLL1_GetSource    ; 0x34181414
+  0x341823FA:  901C         STR        R0, [SP, #112]
+  0x341823FC:  F7FF F812    BL         LL_RCC_PLL2_GetSource    ; 0x34181424
+  0x34182400:  901B         STR        R0, [SP, #108]
+  0x34182402:  F7FF F817    BL         LL_RCC_PLL3_GetSource    ; 0x34181434
+  0x34182406:  901A         STR        R0, [SP, #104]
+  0x34182408:  F7FF F81C    BL         LL_RCC_PLL4_GetSource    ; 0x34181444
+  0x3418240C:  9019         STR        R0, [SP, #100]
+  0x3418240E:  F248 0004    MOVW       R0, #0x8004
+  0x34182412:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182416:  6800         LDR        R0, [R0]
+  0x34182418:  9018         STR        R0, [SP, #96]
+  0x3418241A:  9820         LDR        R0, [SP, #128]
+  0x3418241C:  7800         LDRB       R0, [R0]
+  0x3418241E:  07C0         LSLS       R0, R0, #31
+  0x34182420:  2800         CMP        R0, #0
+  0x34182422:  F000 8101    BEQ.W      46L29                     ; 0x34182628
+  0x34182426:  9820         LDR        R0, [SP, #128]
+  0x34182428:  6840         LDR        R0, [R0, #4]
+  0x3418242A:  B188         CBZ        R0, .L5                  ; 0x34182450
+  0x3418242C:  9820         LDR        R0, [SP, #128]
+  0x3418242E:  6840         LDR        R0, [R0, #4]
+  0x34182430:  2810         CMP        R0, #16
+  0x34182432:  D00D         BEQ        46L5                      ; 0x34182450
+  0x34182434:  9820         LDR        R0, [SP, #128]
+  0x34182436:  6840         LDR        R0, [R0, #4]
+  0x34182438:  F248 0110    MOVW       R1, #0x8010
+  0x3418243C:  4288         CMP        R0, R1
+  0x3418243E:  D007         BEQ        46L5                      ; 0x34182450
+  0x34182440:  9820         LDR        R0, [SP, #128]
+  0x34182442:  6840         LDR        R0, [R0, #4]
+  0x34182444:  F248 0110    MOVW       R1, #0x8010
+  0x34182448:  F2C0 0101    MOVT       R1, #1
+  0x3418244C:  4288         CMP        R0, R1
+  0x3418244E:  D100         BNE        46L6                      ; 0x34182452
+
.L5:
+  0x34182450:  E007         B          46L7                      ; 0x34182462
+
.L6:
+  0x34182452:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182456:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418245A:  F44F 71C2    MOV.W      R1, #0x0184
+  0x3418245E:  F7FF FCED    BL         assert_failed            ; 0x34181E3C
+
.L7:
+  0x34182462:  981D         LDR        R0, [SP, #116]
+  0x34182464:  F5B0 1F00    CMP.W      R0, #0x200000
+  0x34182468:  D02A         BEQ        46L11                     ; 0x341824C0
+  0x3418246A:  981E         LDR        R0, [SP, #120]
+  0x3418246C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34182470:  D026         BEQ        46L11                     ; 0x341824C0
+  0x34182472:  981C         LDR        R0, [SP, #112]
+  0x34182474:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34182478:  D105         BNE        46L8                      ; 0x34182486
+  0x3418247A:  9818         LDR        R0, [SP, #96]
+  0x3418247C:  F400 7080    AND        R0, R0, #0x0100
+  0x34182480:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x34182484:  D01C         BEQ        46L11                     ; 0x341824C0
+
.L8:
+  0x34182486:  981B         LDR        R0, [SP, #108]
+  0x34182488:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x3418248C:  D105         BNE        46L9                      ; 0x3418249A
+  0x3418248E:  9818         LDR        R0, [SP, #96]
+  0x34182490:  F400 7000    AND        R0, R0, #0x0200
+  0x34182494:  F5B0 7F00    CMP.W      R0, #0x0200
+  0x34182498:  D012         BEQ        46L11                     ; 0x341824C0
+
.L9:
+  0x3418249A:  981A         LDR        R0, [SP, #104]
+  0x3418249C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x341824A0:  D105         BNE        46L10                     ; 0x341824AE
+  0x341824A2:  9818         LDR        R0, [SP, #96]
+  0x341824A4:  F400 6080    AND        R0, R0, #0x0400
+  0x341824A8:  F5B0 6F80    CMP.W      R0, #0x0400
+  0x341824AC:  D008         BEQ        46L11                     ; 0x341824C0
+
.L10:
+  0x341824AE:  9819         LDR        R0, [SP, #100]
+  0x341824B0:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x341824B4:  D12E         BNE        46L18                     ; 0x34182514
+  0x341824B6:  F89D 0061    LDRB.W     R0, [SP, #97]
+  0x341824BA:  0700         LSLS       R0, R0, #28
+  0x341824BC:  2800         CMP        R0, #0
+  0x341824BE:  D529         BPL        46L18                     ; 0x34182514
+
.L11:
+  0x341824C0:  9820         LDR        R0, [SP, #128]
+  0x341824C2:  6840         LDR        R0, [R0, #4]
+  0x341824C4:  B920         CBNZ       R0, .L12                 ; 0x341824D0
+  0x341824C6:  2001         MOVS       R0, #1
+  0x341824C8:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x341824CC:  F000 BCD3    B.W        46L144                    ; 0x34182E76
+
.L12:
+  0x341824D0:  F7FE FAFC    BL         HAL_GetTick              ; 0x34180ACC
+  0x341824D4:  901F         STR        R0, [SP, #124]
+
.L13:
+  0x341824D6:  F248 0004    MOVW       R0, #0x8004
+  0x341824DA:  F2C5 6002    MOVT       R0, #0x5602
+  0x341824DE:  6800         LDR        R0, [R0]
+  0x341824E0:  06C0         LSLS       R0, R0, #27
+  0x341824E2:  2800         CMP        R0, #0
+  0x341824E4:  D40B         BMI        46L15                     ; 0x341824FE
+  0x341824E6:  F7FE FAF1    BL         HAL_GetTick              ; 0x34180ACC
+  0x341824EA:  991F         LDR        R1, [SP, #124]
+  0x341824EC:  1A40         SUBS       R0, R0, R1
+  0x341824EE:  2865         CMP        R0, #101
+  0x341824F0:  D304         BCC        46L14                     ; 0x341824FC
+  0x341824F2:  2003         MOVS       R0, #3
+  0x341824F4:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x341824F8:  F000 BCBD    B.W        46L144                    ; 0x34182E76
+
.L14:
+  0x341824FC:  E7EB         B          46L13                     ; 0x341824D6
+
.L15:
+  0x341824FE:  F7FE FAE5    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182502:  901F         STR        R0, [SP, #124]
+
.L16:
+  0x34182504:  F7FE FAE2    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182508:  991F         LDR        R1, [SP, #124]
+  0x3418250A:  1A40         SUBS       R0, R0, R1
+  0x3418250C:  2801         CMP        R0, #1
+  0x3418250E:  D800         BHI        46L17                     ; 0x34182512
+  0x34182510:  E7F8         B          46L16                     ; 0x34182504
+
.L17:
+  0x34182512:  E089         B          46L29                     ; 0x34182628
+
.L18:
+  0x34182514:  9820         LDR        R0, [SP, #128]
+  0x34182516:  6840         LDR        R0, [R0, #4]
+  0x34182518:  2810         CMP        R0, #16
+  0x3418251A:  D106         BNE        46L19                     ; 0x3418252A
+  0x3418251C:  F648 0100    MOVW       R1, #0x8800
+  0x34182520:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182524:  2010         MOVS       R0, #16
+  0x34182526:  6008         STR        R0, [R1]
+  0x34182528:  E04F         B          46L23                     ; 0x341825CA
+
.L19:
+  0x3418252A:  9820         LDR        R0, [SP, #128]
+  0x3418252C:  6840         LDR        R0, [R0, #4]
+  0x3418252E:  B970         CBNZ       R0, .L20                 ; 0x3418254E
+  0x34182530:  F249 0100    MOVW       R1, #0x9000
+  0x34182534:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182538:  2010         MOVS       R0, #16
+  0x3418253A:  6008         STR        R0, [R1]
+  0x3418253C:  F248 0154    MOVW       R1, #0x8054
+  0x34182540:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182544:  6808         LDR        R0, [R1]
+  0x34182546:  F420 30C0    BIC        R0, R0, #0x018000
+  0x3418254A:  6008         STR        R0, [R1]
+  0x3418254C:  E03D         B          46L23                     ; 0x341825CA
+
.L20:
+  0x3418254E:  9820         LDR        R0, [SP, #128]
+  0x34182550:  6840         LDR        R0, [R0, #4]
+  0x34182552:  F248 0110    MOVW       R1, #0x8010
+  0x34182556:  4288         CMP        R0, R1
+  0x34182558:  D112         BNE        46L21                     ; 0x34182580
+  0x3418255A:  F248 0154    MOVW       R1, #0x8054
+  0x3418255E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182562:  6808         LDR        R0, [R1]
+  0x34182564:  F440 4000    ORR        R0, R0, #0x8000
+  0x34182568:  6008         STR        R0, [R1]
+  0x3418256A:  6808         LDR        R0, [R1]
+  0x3418256C:  F420 3080    BIC        R0, R0, #0x010000
+  0x34182570:  6008         STR        R0, [R1]
+  0x34182572:  F648 0100    MOVW       R1, #0x8800
+  0x34182576:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418257A:  2010         MOVS       R0, #16
+  0x3418257C:  6008         STR        R0, [R1]
+  0x3418257E:  E024         B          46L23                     ; 0x341825CA
+
.L21:
+  0x34182580:  9820         LDR        R0, [SP, #128]
+  0x34182582:  6840         LDR        R0, [R0, #4]
+  0x34182584:  F248 0110    MOVW       R1, #0x8010
+  0x34182588:  F2C0 0101    MOVT       R1, #1
+  0x3418258C:  4288         CMP        R0, R1
+  0x3418258E:  D10E         BNE        46L22                     ; 0x341825AE
+  0x34182590:  F248 0154    MOVW       R1, #0x8054
+  0x34182594:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182598:  6808         LDR        R0, [R1]
+  0x3418259A:  F440 30C0    ORR        R0, R0, #0x018000
+  0x3418259E:  6008         STR        R0, [R1]
+  0x341825A0:  F648 0100    MOVW       R1, #0x8800
+  0x341825A4:  F2C5 6102    MOVT       R1, #0x5602
+  0x341825A8:  2010         MOVS       R0, #16
+  0x341825AA:  6008         STR        R0, [R1]
+  0x341825AC:  E00D         B          46L23                     ; 0x341825CA
+
.L22:
+  0x341825AE:  F249 0100    MOVW       R1, #0x9000
+  0x341825B2:  F2C5 6102    MOVT       R1, #0x5602
+  0x341825B6:  2010         MOVS       R0, #16
+  0x341825B8:  6008         STR        R0, [R1]
+  0x341825BA:  F248 0154    MOVW       R1, #0x8054
+  0x341825BE:  F2C5 6102    MOVT       R1, #0x5602
+  0x341825C2:  6808         LDR        R0, [R1]
+  0x341825C4:  F420 30C0    BIC        R0, R0, #0x018000
+  0x341825C8:  6008         STR        R0, [R1]
+
.L23:
+  0x341825CA:  F7FE FA7F    BL         HAL_GetTick              ; 0x34180ACC
+  0x341825CE:  901F         STR        R0, [SP, #124]
+  0x341825D0:  9820         LDR        R0, [SP, #128]
+  0x341825D2:  6840         LDR        R0, [R0, #4]
+  0x341825D4:  B1A0         CBZ        R0, .L27                 ; 0x34182600
+
.L24:
+  0x341825D6:  F248 0004    MOVW       R0, #0x8004
+  0x341825DA:  F2C5 6002    MOVT       R0, #0x5602
+  0x341825DE:  6800         LDR        R0, [R0]
+  0x341825E0:  06C0         LSLS       R0, R0, #27
+  0x341825E2:  2800         CMP        R0, #0
+  0x341825E4:  D40B         BMI        46L26                     ; 0x341825FE
+  0x341825E6:  F7FE FA71    BL         HAL_GetTick              ; 0x34180ACC
+  0x341825EA:  991F         LDR        R1, [SP, #124]
+  0x341825EC:  1A40         SUBS       R0, R0, R1
+  0x341825EE:  2865         CMP        R0, #101
+  0x341825F0:  D304         BCC        46L25                     ; 0x341825FC
+  0x341825F2:  2003         MOVS       R0, #3
+  0x341825F4:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x341825F8:  F000 BC3D    B.W        46L144                    ; 0x34182E76
+
.L25:
+  0x341825FC:  E7EB         B          46L24                     ; 0x341825D6
+
.L26:
+  0x341825FE:  E013         B          46L29                     ; 0x34182628
+
.L27:
+  0x34182600:  F248 0004    MOVW       R0, #0x8004
+  0x34182604:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182608:  6800         LDR        R0, [R0]
+  0x3418260A:  06C0         LSLS       R0, R0, #27
+  0x3418260C:  2800         CMP        R0, #0
+  0x3418260E:  D50B         BPL        46L29                     ; 0x34182628
+  0x34182610:  F7FE FA5C    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182614:  991F         LDR        R1, [SP, #124]
+  0x34182616:  1A40         SUBS       R0, R0, R1
+  0x34182618:  2865         CMP        R0, #101
+  0x3418261A:  D304         BCC        46L28                     ; 0x34182626
+  0x3418261C:  2003         MOVS       R0, #3
+  0x3418261E:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182622:  F000 BC28    B.W        46L144                    ; 0x34182E76
+
.L28:
+  0x34182626:  E7EB         B          46L27                     ; 0x34182600
+
.L29:
+  0x34182628:  9820         LDR        R0, [SP, #128]
+  0x3418262A:  7800         LDRB       R0, [R0]
+  0x3418262C:  0780         LSLS       R0, R0, #30
+  0x3418262E:  2800         CMP        R0, #0
+  0x34182630:  F140 80C4    BPL.W      46L55                     ; 0x341827BC
+  0x34182634:  9820         LDR        R0, [SP, #128]
+  0x34182636:  68C0         LDR        R0, [R0, #12]
+  0x34182638:  B118         CBZ        R0, .L30                 ; 0x34182642
+  0x3418263A:  9820         LDR        R0, [SP, #128]
+  0x3418263C:  68C0         LDR        R0, [R0, #12]
+  0x3418263E:  2808         CMP        R0, #8
+  0x34182640:  D100         BNE        46L31                     ; 0x34182644
+
.L30:
+  0x34182642:  E007         B          46L32                     ; 0x34182654
+
.L31:
+  0x34182644:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182648:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418264C:  F240 11CD    MOVW       R1, #0x01CD
+  0x34182650:  F7FF FBF4    BL         assert_failed            ; 0x34181E3C
+
.L32:
+  0x34182654:  981D         LDR        R0, [SP, #116]
+  0x34182656:  B300         CBZ        R0, .L36                 ; 0x3418269A
+  0x34182658:  981E         LDR        R0, [SP, #120]
+  0x3418265A:  B1F0         CBZ        R0, .L36                 ; 0x3418269A
+  0x3418265C:  981C         LDR        R0, [SP, #112]
+  0x3418265E:  B928         CBNZ       R0, .L33                 ; 0x3418266C
+  0x34182660:  9818         LDR        R0, [SP, #96]
+  0x34182662:  F400 7080    AND        R0, R0, #0x0100
+  0x34182666:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x3418266A:  D016         BEQ        46L36                     ; 0x3418269A
+
.L33:
+  0x3418266C:  981B         LDR        R0, [SP, #108]
+  0x3418266E:  B928         CBNZ       R0, .L34                 ; 0x3418267C
+  0x34182670:  9818         LDR        R0, [SP, #96]
+  0x34182672:  F400 7000    AND        R0, R0, #0x0200
+  0x34182676:  F5B0 7F00    CMP.W      R0, #0x0200
+  0x3418267A:  D00E         BEQ        46L36                     ; 0x3418269A
+
.L34:
+  0x3418267C:  981A         LDR        R0, [SP, #104]
+  0x3418267E:  B928         CBNZ       R0, .L35                 ; 0x3418268C
+  0x34182680:  9818         LDR        R0, [SP, #96]
+  0x34182682:  F400 6080    AND        R0, R0, #0x0400
+  0x34182686:  F5B0 6F80    CMP.W      R0, #0x0400
+  0x3418268A:  D006         BEQ        46L36                     ; 0x3418269A
+
.L35:
+  0x3418268C:  9819         LDR        R0, [SP, #100]
+  0x3418268E:  BBD8         CBNZ       R0, .L43                 ; 0x34182708
+  0x34182690:  F89D 0061    LDRB.W     R0, [SP, #97]
+  0x34182694:  0700         LSLS       R0, R0, #28
+  0x34182696:  2800         CMP        R0, #0
+  0x34182698:  D536         BPL        46L43                     ; 0x34182708
+
.L36:
+  0x3418269A:  9820         LDR        R0, [SP, #128]
+  0x3418269C:  68C0         LDR        R0, [R0, #12]
+  0x3418269E:  B918         CBNZ       R0, .L37                 ; 0x341826A8
+  0x341826A0:  2001         MOVS       R0, #1
+  0x341826A2:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x341826A6:  E3E6         B          46L144                    ; 0x34182E76
+
.L37:
+  0x341826A8:  9820         LDR        R0, [SP, #128]
+  0x341826AA:  6900         LDR        R0, [R0, #16]
+  0x341826AC:  B168         CBZ        R0, .L38                 ; 0x341826CA
+  0x341826AE:  9820         LDR        R0, [SP, #128]
+  0x341826B0:  6900         LDR        R0, [R0, #16]
+  0x341826B2:  2880         CMP        R0, #128
+  0x341826B4:  D009         BEQ        46L38                     ; 0x341826CA
+  0x341826B6:  9820         LDR        R0, [SP, #128]
+  0x341826B8:  6900         LDR        R0, [R0, #16]
+  0x341826BA:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x341826BE:  D004         BEQ        46L38                     ; 0x341826CA
+  0x341826C0:  9820         LDR        R0, [SP, #128]
+  0x341826C2:  6900         LDR        R0, [R0, #16]
+  0x341826C4:  F5B0 7FC0    CMP.W      R0, #0x0180
+  0x341826C8:  D100         BNE        46L39                     ; 0x341826CC
+
.L38:
+  0x341826CA:  E007         B          46L40                     ; 0x341826DC
+
.L39:
+  0x341826CC:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341826D0:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341826D4:  F240 11DF    MOVW       R1, #0x01DF
+  0x341826D8:  F7FF FBB0    BL         assert_failed            ; 0x34181E3C
+
.L40:
+  0x341826DC:  9820         LDR        R0, [SP, #128]
+  0x341826DE:  6940         LDR        R0, [R0, #20]
+  0x341826E0:  287F         CMP        R0, #127
+  0x341826E2:  D800         BHI        46L41                     ; 0x341826E6
+  0x341826E4:  E007         B          46L42                     ; 0x341826F6
+
.L41:
+  0x341826E6:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341826EA:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341826EE:  F44F 71F0    MOV.W      R1, #0x01E0
+  0x341826F2:  F7FF FBA3    BL         assert_failed            ; 0x34181E3C
+
.L42:
+  0x341826F6:  9820         LDR        R0, [SP, #128]
+  0x341826F8:  6900         LDR        R0, [R0, #16]
+  0x341826FA:  F7FE FE65    BL         LL_RCC_HSI_SetDivider    ; 0x341813C8
+  0x341826FE:  9820         LDR        R0, [SP, #128]
+  0x34182700:  6940         LDR        R0, [R0, #20]
+  0x34182702:  F000 FBBD    BL         LL_RCC_HSI_SetCalibTrimming ; 0x34182E80
+  0x34182706:  E059         B          46L55                     ; 0x341827BC
+
.L43:
+  0x34182708:  9820         LDR        R0, [SP, #128]
+  0x3418270A:  68C0         LDR        R0, [R0, #12]
+  0x3418270C:  2800         CMP        R0, #0
+  0x3418270E:  D042         BEQ        46L52                     ; 0x34182796
+  0x34182710:  9820         LDR        R0, [SP, #128]
+  0x34182712:  6900         LDR        R0, [R0, #16]
+  0x34182714:  B168         CBZ        R0, .L44                 ; 0x34182732
+  0x34182716:  9820         LDR        R0, [SP, #128]
+  0x34182718:  6900         LDR        R0, [R0, #16]
+  0x3418271A:  2880         CMP        R0, #128
+  0x3418271C:  D009         BEQ        46L44                     ; 0x34182732
+  0x3418271E:  9820         LDR        R0, [SP, #128]
+  0x34182720:  6900         LDR        R0, [R0, #16]
+  0x34182722:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x34182726:  D004         BEQ        46L44                     ; 0x34182732
+  0x34182728:  9820         LDR        R0, [SP, #128]
+  0x3418272A:  6900         LDR        R0, [R0, #16]
+  0x3418272C:  F5B0 7FC0    CMP.W      R0, #0x0180
+  0x34182730:  D100         BNE        46L45                     ; 0x34182734
+
.L44:
+  0x34182732:  E007         B          46L46                     ; 0x34182744
+
.L45:
+  0x34182734:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182738:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418273C:  F44F 71F7    MOV.W      R1, #0x01EE
+  0x34182740:  F7FF FB7C    BL         assert_failed            ; 0x34181E3C
+
.L46:
+  0x34182744:  9820         LDR        R0, [SP, #128]
+  0x34182746:  6940         LDR        R0, [R0, #20]
+  0x34182748:  287F         CMP        R0, #127
+  0x3418274A:  D800         BHI        46L47                     ; 0x3418274E
+  0x3418274C:  E007         B          46L48                     ; 0x3418275E
+
.L47:
+  0x3418274E:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182752:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182756:  F240 11EF    MOVW       R1, #0x01EF
+  0x3418275A:  F7FF FB6F    BL         assert_failed            ; 0x34181E3C
+
.L48:
+  0x3418275E:  F7FF FE09    BL         LL_RCC_HSI_Enable        ; 0x34182374
+  0x34182762:  F7FE F9B3    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182766:  901F         STR        R0, [SP, #124]
+
.L49:
+  0x34182768:  F7FE FE3C    BL         LL_RCC_HSI_IsReady       ; 0x341813E4
+  0x3418276C:  B950         CBNZ       R0, .L51                 ; 0x34182784
+  0x3418276E:  F7FE F9AD    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182772:  991F         LDR        R1, [SP, #124]
+  0x34182774:  1A40         SUBS       R0, R0, R1
+  0x34182776:  2802         CMP        R0, #2
+  0x34182778:  D303         BCC        46L50                     ; 0x34182782
+  0x3418277A:  2003         MOVS       R0, #3
+  0x3418277C:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182780:  E379         B          46L144                    ; 0x34182E76
+
.L50:
+  0x34182782:  E7F1         B          46L49                     ; 0x34182768
+
.L51:
+  0x34182784:  9820         LDR        R0, [SP, #128]
+  0x34182786:  6900         LDR        R0, [R0, #16]
+  0x34182788:  F7FE FE1E    BL         LL_RCC_HSI_SetDivider    ; 0x341813C8
+  0x3418278C:  9820         LDR        R0, [SP, #128]
+  0x3418278E:  6940         LDR        R0, [R0, #20]
+  0x34182790:  F000 FB76    BL         LL_RCC_HSI_SetCalibTrimming ; 0x34182E80
+  0x34182794:  E012         B          46L55                     ; 0x341827BC
+
.L52:
+  0x34182796:  F000 FB83    BL         LL_RCC_HSI_Disable       ; 0x34182EA0
+  0x3418279A:  F7FE F997    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418279E:  901F         STR        R0, [SP, #124]
+
.L53:
+  0x341827A0:  F7FE FE20    BL         LL_RCC_HSI_IsReady       ; 0x341813E4
+  0x341827A4:  B150         CBZ        R0, .L55                 ; 0x341827BC
+  0x341827A6:  F7FE F991    BL         HAL_GetTick              ; 0x34180ACC
+  0x341827AA:  991F         LDR        R1, [SP, #124]
+  0x341827AC:  1A40         SUBS       R0, R0, R1
+  0x341827AE:  2802         CMP        R0, #2
+  0x341827B0:  D303         BCC        46L54                     ; 0x341827BA
+  0x341827B2:  2003         MOVS       R0, #3
+  0x341827B4:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x341827B8:  E35D         B          46L144                    ; 0x34182E76
+
.L54:
+  0x341827BA:  E7F1         B          46L53                     ; 0x341827A0
+
.L55:
+  0x341827BC:  9820         LDR        R0, [SP, #128]
+  0x341827BE:  7800         LDRB       R0, [R0]
+  0x341827C0:  06C0         LSLS       R0, R0, #27
+  0x341827C2:  2800         CMP        R0, #0
+  0x341827C4:  F140 80A8    BPL.W      46L78                     ; 0x34182918
+  0x341827C8:  9820         LDR        R0, [SP, #128]
+  0x341827CA:  69C0         LDR        R0, [R0, #28]
+  0x341827CC:  B118         CBZ        R0, .L56                 ; 0x341827D6
+  0x341827CE:  9820         LDR        R0, [SP, #128]
+  0x341827D0:  69C0         LDR        R0, [R0, #28]
+  0x341827D2:  2804         CMP        R0, #4
+  0x341827D4:  D100         BNE        46L57                     ; 0x341827D8
+
.L56:
+  0x341827D6:  E007         B          46L58                     ; 0x341827E8
+
.L57:
+  0x341827D8:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341827DC:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341827E0:  F240 211D    MOVW       R1, #0x021D
+  0x341827E4:  F7FF FB2A    BL         assert_failed            ; 0x34181E3C
+
.L58:
+  0x341827E8:  981D         LDR        R0, [SP, #116]
+  0x341827EA:  F5B0 1F80    CMP.W      R0, #0x100000
+  0x341827EE:  D02A         BEQ        46L62                     ; 0x34182846
+  0x341827F0:  981E         LDR        R0, [SP, #120]
+  0x341827F2:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x341827F6:  D026         BEQ        46L62                     ; 0x34182846
+  0x341827F8:  981C         LDR        R0, [SP, #112]
+  0x341827FA:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x341827FE:  D105         BNE        46L59                     ; 0x3418280C
+  0x34182800:  9818         LDR        R0, [SP, #96]
+  0x34182802:  F400 7080    AND        R0, R0, #0x0100
+  0x34182806:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x3418280A:  D01C         BEQ        46L62                     ; 0x34182846
+
.L59:
+  0x3418280C:  981B         LDR        R0, [SP, #108]
+  0x3418280E:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34182812:  D105         BNE        46L60                     ; 0x34182820
+  0x34182814:  9818         LDR        R0, [SP, #96]
+  0x34182816:  F400 7000    AND        R0, R0, #0x0200
+  0x3418281A:  F5B0 7F00    CMP.W      R0, #0x0200
+  0x3418281E:  D012         BEQ        46L62                     ; 0x34182846
+
.L60:
+  0x34182820:  981A         LDR        R0, [SP, #104]
+  0x34182822:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34182826:  D105         BNE        46L61                     ; 0x34182834
+  0x34182828:  9818         LDR        R0, [SP, #96]
+  0x3418282A:  F400 6080    AND        R0, R0, #0x0400
+  0x3418282E:  F5B0 6F80    CMP.W      R0, #0x0400
+  0x34182832:  D008         BEQ        46L62                     ; 0x34182846
+
.L61:
+  0x34182834:  9819         LDR        R0, [SP, #100]
+  0x34182836:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x3418283A:  D11D         BNE        46L66                     ; 0x34182878
+  0x3418283C:  F89D 0061    LDRB.W     R0, [SP, #97]
+  0x34182840:  0700         LSLS       R0, R0, #28
+  0x34182842:  2800         CMP        R0, #0
+  0x34182844:  D518         BPL        46L66                     ; 0x34182878
+
.L62:
+  0x34182846:  9820         LDR        R0, [SP, #128]
+  0x34182848:  69C0         LDR        R0, [R0, #28]
+  0x3418284A:  B918         CBNZ       R0, .L63                 ; 0x34182854
+  0x3418284C:  2001         MOVS       R0, #1
+  0x3418284E:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182852:  E310         B          46L144                    ; 0x34182E76
+
.L63:
+  0x34182854:  9820         LDR        R0, [SP, #128]
+  0x34182856:  6A40         LDR        R0, [R0, #36]
+  0x34182858:  281F         CMP        R0, #31
+  0x3418285A:  D800         BHI        46L64                     ; 0x3418285E
+  0x3418285C:  E007         B          46L65                     ; 0x3418286E
+
.L64:
+  0x3418285E:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182862:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182866:  F44F 710C    MOV.W      R1, #0x0230
+  0x3418286A:  F7FF FAE7    BL         assert_failed            ; 0x34181E3C
+
.L65:
+  0x3418286E:  9820         LDR        R0, [SP, #128]
+  0x34182870:  6A40         LDR        R0, [R0, #36]
+  0x34182872:  F000 FB1D    BL         LL_RCC_MSI_SetCalibTrimming ; 0x34182EB0
+  0x34182876:  E04F         B          46L78                     ; 0x34182918
+
.L66:
+  0x34182878:  9820         LDR        R0, [SP, #128]
+  0x3418287A:  69C0         LDR        R0, [R0, #28]
+  0x3418287C:  B3C8         CBZ        R0, .L75                 ; 0x341828F2
+  0x3418287E:  9820         LDR        R0, [SP, #128]
+  0x34182880:  6A00         LDR        R0, [R0, #32]
+  0x34182882:  B120         CBZ        R0, .L67                 ; 0x3418288E
+  0x34182884:  9820         LDR        R0, [SP, #128]
+  0x34182886:  6A00         LDR        R0, [R0, #32]
+  0x34182888:  F5B0 7F00    CMP.W      R0, #0x0200
+  0x3418288C:  D100         BNE        46L68                     ; 0x34182890
+
.L67:
+  0x3418288E:  E007         B          46L69                     ; 0x341828A0
+
.L68:
+  0x34182890:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182894:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182898:  F44F 710F    MOV.W      R1, #0x023C
+  0x3418289C:  F7FF FACE    BL         assert_failed            ; 0x34181E3C
+
.L69:
+  0x341828A0:  9820         LDR        R0, [SP, #128]
+  0x341828A2:  6A40         LDR        R0, [R0, #36]
+  0x341828A4:  281F         CMP        R0, #31
+  0x341828A6:  D800         BHI        46L70                     ; 0x341828AA
+  0x341828A8:  E007         B          46L71                     ; 0x341828BA
+
.L70:
+  0x341828AA:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341828AE:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341828B2:  F240 213D    MOVW       R1, #0x023D
+  0x341828B6:  F7FF FAC1    BL         assert_failed            ; 0x34181E3C
+
.L71:
+  0x341828BA:  9820         LDR        R0, [SP, #128]
+  0x341828BC:  6A00         LDR        R0, [R0, #32]
+  0x341828BE:  F7FE FDC9    BL         LL_RCC_MSI_SetFrequency  ; 0x34181454
+  0x341828C2:  F000 FB05    BL         LL_RCC_MSI_Enable        ; 0x34182ED0
+  0x341828C6:  F7FE F901    BL         HAL_GetTick              ; 0x34180ACC
+  0x341828CA:  901F         STR        R0, [SP, #124]
+
.L72:
+  0x341828CC:  F7FE FDD0    BL         LL_RCC_MSI_IsReady       ; 0x34181470
+  0x341828D0:  B950         CBNZ       R0, .L74                 ; 0x341828E8
+  0x341828D2:  F7FE F8FB    BL         HAL_GetTick              ; 0x34180ACC
+  0x341828D6:  991F         LDR        R1, [SP, #124]
+  0x341828D8:  1A40         SUBS       R0, R0, R1
+  0x341828DA:  2802         CMP        R0, #2
+  0x341828DC:  D303         BCC        46L73                     ; 0x341828E6
+  0x341828DE:  2003         MOVS       R0, #3
+  0x341828E0:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x341828E4:  E2C7         B          46L144                    ; 0x34182E76
+
.L73:
+  0x341828E6:  E7F1         B          46L72                     ; 0x341828CC
+
.L74:
+  0x341828E8:  9820         LDR        R0, [SP, #128]
+  0x341828EA:  6A40         LDR        R0, [R0, #36]
+  0x341828EC:  F000 FAE0    BL         LL_RCC_MSI_SetCalibTrimming ; 0x34182EB0
+  0x341828F0:  E012         B          46L78                     ; 0x34182918
+
.L75:
+  0x341828F2:  F000 FAF5    BL         LL_RCC_MSI_Disable       ; 0x34182EE0
+  0x341828F6:  F7FE F8E9    BL         HAL_GetTick              ; 0x34180ACC
+  0x341828FA:  901F         STR        R0, [SP, #124]
+
.L76:
+  0x341828FC:  F7FE FDB8    BL         LL_RCC_MSI_IsReady       ; 0x34181470
+  0x34182900:  B150         CBZ        R0, .L78                 ; 0x34182918
+  0x34182902:  F7FE F8E3    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182906:  991F         LDR        R1, [SP, #124]
+  0x34182908:  1A40         SUBS       R0, R0, R1
+  0x3418290A:  2802         CMP        R0, #2
+  0x3418290C:  D303         BCC        46L77                     ; 0x34182916
+  0x3418290E:  2003         MOVS       R0, #3
+  0x34182910:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182914:  E2AF         B          46L144                    ; 0x34182E76
+
.L77:
+  0x34182916:  E7F1         B          46L76                     ; 0x341828FC
+
.L78:
+  0x34182918:  9820         LDR        R0, [SP, #128]
+  0x3418291A:  7800         LDRB       R0, [R0]
+  0x3418291C:  0700         LSLS       R0, R0, #28
+  0x3418291E:  2800         CMP        R0, #0
+  0x34182920:  D539         BPL        46L88                     ; 0x34182996
+  0x34182922:  9820         LDR        R0, [SP, #128]
+  0x34182924:  6980         LDR        R0, [R0, #24]
+  0x34182926:  B118         CBZ        R0, .L79                 ; 0x34182930
+  0x34182928:  9820         LDR        R0, [SP, #128]
+  0x3418292A:  6980         LDR        R0, [R0, #24]
+  0x3418292C:  2801         CMP        R0, #1
+  0x3418292E:  D100         BNE        46L80                     ; 0x34182932
+
.L79:
+  0x34182930:  E007         B          46L81                     ; 0x34182942
+
.L80:
+  0x34182932:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182936:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418293A:  F240 216D    MOVW       R1, #0x026D
+  0x3418293E:  F7FF FA7D    BL         assert_failed            ; 0x34181E3C
+
.L81:
+  0x34182942:  9820         LDR        R0, [SP, #128]
+  0x34182944:  6980         LDR        R0, [R0, #24]
+  0x34182946:  B198         CBZ        R0, .L85                 ; 0x34182970
+  0x34182948:  F000 FAD2    BL         LL_RCC_LSI_Enable        ; 0x34182EF0
+  0x3418294C:  F7FE F8BE    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182950:  901F         STR        R0, [SP, #124]
+
.L82:
+  0x34182952:  F7FE FD95    BL         LL_RCC_LSI_IsReady       ; 0x34181480
+  0x34182956:  B950         CBNZ       R0, .L84                 ; 0x3418296E
+  0x34182958:  F7FE F8B8    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418295C:  991F         LDR        R1, [SP, #124]
+  0x3418295E:  1A40         SUBS       R0, R0, R1
+  0x34182960:  2802         CMP        R0, #2
+  0x34182962:  D303         BCC        46L83                     ; 0x3418296C
+  0x34182964:  2003         MOVS       R0, #3
+  0x34182966:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x3418296A:  E284         B          46L144                    ; 0x34182E76
+
.L83:
+  0x3418296C:  E7F1         B          46L82                     ; 0x34182952
+
.L84:
+  0x3418296E:  E012         B          46L88                     ; 0x34182996
+
.L85:
+  0x34182970:  F000 FAC6    BL         LL_RCC_LSI_Disable       ; 0x34182F00
+  0x34182974:  F7FE F8AA    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182978:  901F         STR        R0, [SP, #124]
+
.L86:
+  0x3418297A:  F7FE FD81    BL         LL_RCC_LSI_IsReady       ; 0x34181480
+  0x3418297E:  B150         CBZ        R0, .L88                 ; 0x34182996
+  0x34182980:  F7FE F8A4    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182984:  991F         LDR        R1, [SP, #124]
+  0x34182986:  1A40         SUBS       R0, R0, R1
+  0x34182988:  2802         CMP        R0, #2
+  0x3418298A:  D303         BCC        46L87                     ; 0x34182994
+  0x3418298C:  2003         MOVS       R0, #3
+  0x3418298E:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182992:  E270         B          46L144                    ; 0x34182E76
+
.L87:
+  0x34182994:  E7F1         B          46L86                     ; 0x3418297A
+
.L88:
+  0x34182996:  9820         LDR        R0, [SP, #128]
+  0x34182998:  7800         LDRB       R0, [R0]
+  0x3418299A:  0740         LSLS       R0, R0, #29
+  0x3418299C:  2800         CMP        R0, #0
+  0x3418299E:  F140 80AF    BPL.W      46L103                    ; 0x34182B00
+  0x341829A2:  9820         LDR        R0, [SP, #128]
+  0x341829A4:  6880         LDR        R0, [R0, #8]
+  0x341829A6:  B188         CBZ        R0, .L89                 ; 0x341829CC
+  0x341829A8:  9820         LDR        R0, [SP, #128]
+  0x341829AA:  6880         LDR        R0, [R0, #8]
+  0x341829AC:  2802         CMP        R0, #2
+  0x341829AE:  D00D         BEQ        46L89                     ; 0x341829CC
+  0x341829B0:  9820         LDR        R0, [SP, #128]
+  0x341829B2:  6880         LDR        R0, [R0, #8]
+  0x341829B4:  F248 0102    MOVW       R1, #0x8002
+  0x341829B8:  4288         CMP        R0, R1
+  0x341829BA:  D007         BEQ        46L89                     ; 0x341829CC
+  0x341829BC:  9820         LDR        R0, [SP, #128]
+  0x341829BE:  6880         LDR        R0, [R0, #8]
+  0x341829C0:  F248 0102    MOVW       R1, #0x8002
+  0x341829C4:  F2C0 0101    MOVT       R1, #1
+  0x341829C8:  4288         CMP        R0, R1
+  0x341829CA:  D100         BNE        46L90                     ; 0x341829CE
+
.L89:
+  0x341829CC:  E007         B          46L91                     ; 0x341829DE
+
.L90:
+  0x341829CE:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341829D2:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341829D6:  F44F 7126    MOV.W      R1, #0x0298
+  0x341829DA:  F7FF FA2F    BL         assert_failed            ; 0x34181E3C
+
.L91:
+  0x341829DE:  9820         LDR        R0, [SP, #128]
+  0x341829E0:  6880         LDR        R0, [R0, #8]
+  0x341829E2:  2802         CMP        R0, #2
+  0x341829E4:  D106         BNE        46L92                     ; 0x341829F4
+  0x341829E6:  F648 0100    MOVW       R1, #0x8800
+  0x341829EA:  F2C5 6102    MOVT       R1, #0x5602
+  0x341829EE:  2002         MOVS       R0, #2
+  0x341829F0:  6008         STR        R0, [R1]
+  0x341829F2:  E05B         B          46L96                     ; 0x34182AAC
+
.L92:
+  0x341829F4:  9820         LDR        R0, [SP, #128]
+  0x341829F6:  6880         LDR        R0, [R0, #8]
+  0x341829F8:  B990         CBNZ       R0, .L93                 ; 0x34182A20
+  0x341829FA:  F249 0100    MOVW       R1, #0x9000
+  0x341829FE:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A02:  2002         MOVS       R0, #2
+  0x34182A04:  6008         STR        R0, [R1]
+  0x34182A06:  F248 0140    MOVW       R1, #0x8040
+  0x34182A0A:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A0E:  6808         LDR        R0, [R1]
+  0x34182A10:  F420 3080    BIC        R0, R0, #0x010000
+  0x34182A14:  6008         STR        R0, [R1]
+  0x34182A16:  6808         LDR        R0, [R1]
+  0x34182A18:  F420 4000    BIC        R0, R0, #0x8000
+  0x34182A1C:  6008         STR        R0, [R1]
+  0x34182A1E:  E045         B          46L96                     ; 0x34182AAC
+
.L93:
+  0x34182A20:  9820         LDR        R0, [SP, #128]
+  0x34182A22:  6880         LDR        R0, [R0, #8]
+  0x34182A24:  F248 0102    MOVW       R1, #0x8002
+  0x34182A28:  4288         CMP        R0, R1
+  0x34182A2A:  D112         BNE        46L94                     ; 0x34182A52
+  0x34182A2C:  F248 0140    MOVW       R1, #0x8040
+  0x34182A30:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A34:  6808         LDR        R0, [R1]
+  0x34182A36:  F440 4000    ORR        R0, R0, #0x8000
+  0x34182A3A:  6008         STR        R0, [R1]
+  0x34182A3C:  6808         LDR        R0, [R1]
+  0x34182A3E:  F420 3080    BIC        R0, R0, #0x010000
+  0x34182A42:  6008         STR        R0, [R1]
+  0x34182A44:  F648 0100    MOVW       R1, #0x8800
+  0x34182A48:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A4C:  2002         MOVS       R0, #2
+  0x34182A4E:  6008         STR        R0, [R1]
+  0x34182A50:  E02C         B          46L96                     ; 0x34182AAC
+
.L94:
+  0x34182A52:  9820         LDR        R0, [SP, #128]
+  0x34182A54:  6880         LDR        R0, [R0, #8]
+  0x34182A56:  F248 0102    MOVW       R1, #0x8002
+  0x34182A5A:  F2C0 0101    MOVT       R1, #1
+  0x34182A5E:  4288         CMP        R0, R1
+  0x34182A60:  D112         BNE        46L95                     ; 0x34182A88
+  0x34182A62:  F248 0140    MOVW       R1, #0x8040
+  0x34182A66:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A6A:  6808         LDR        R0, [R1]
+  0x34182A6C:  F440 4000    ORR        R0, R0, #0x8000
+  0x34182A70:  6008         STR        R0, [R1]
+  0x34182A72:  6808         LDR        R0, [R1]
+  0x34182A74:  F440 3080    ORR        R0, R0, #0x010000
+  0x34182A78:  6008         STR        R0, [R1]
+  0x34182A7A:  F648 0100    MOVW       R1, #0x8800
+  0x34182A7E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A82:  2002         MOVS       R0, #2
+  0x34182A84:  6008         STR        R0, [R1]
+  0x34182A86:  E011         B          46L96                     ; 0x34182AAC
+
.L95:
+  0x34182A88:  F249 0100    MOVW       R1, #0x9000
+  0x34182A8C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A90:  2002         MOVS       R0, #2
+  0x34182A92:  6008         STR        R0, [R1]
+  0x34182A94:  F248 0140    MOVW       R1, #0x8040
+  0x34182A98:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182A9C:  6808         LDR        R0, [R1]
+  0x34182A9E:  F420 4000    BIC        R0, R0, #0x8000
+  0x34182AA2:  6008         STR        R0, [R1]
+  0x34182AA4:  6808         LDR        R0, [R1]
+  0x34182AA6:  F420 3080    BIC        R0, R0, #0x010000
+  0x34182AAA:  6008         STR        R0, [R1]
+
.L96:
+  0x34182AAC:  9820         LDR        R0, [SP, #128]
+  0x34182AAE:  6880         LDR        R0, [R0, #8]
+  0x34182AB0:  B198         CBZ        R0, .L100                ; 0x34182ADA
+  0x34182AB2:  F7FE F80B    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182AB6:  901F         STR        R0, [SP, #124]
+
.L97:
+  0x34182AB8:  F7FE FCEA    BL         LL_RCC_LSE_IsReady       ; 0x34181490
+  0x34182ABC:  B960         CBNZ       R0, .L99                 ; 0x34182AD8
+  0x34182ABE:  F7FE F805    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182AC2:  991F         LDR        R1, [SP, #124]
+  0x34182AC4:  1A40         SUBS       R0, R0, R1
+  0x34182AC6:  F241 3189    MOVW       R1, #0x1389
+  0x34182ACA:  4288         CMP        R0, R1
+  0x34182ACC:  D303         BCC        46L98                     ; 0x34182AD6
+  0x34182ACE:  2003         MOVS       R0, #3
+  0x34182AD0:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182AD4:  E1CF         B          46L144                    ; 0x34182E76
+
.L98:
+  0x34182AD6:  E7EF         B          46L97                     ; 0x34182AB8
+
.L99:
+  0x34182AD8:  E012         B          46L103                    ; 0x34182B00
+
.L100:
+  0x34182ADA:  F7FD FFF7    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182ADE:  901F         STR        R0, [SP, #124]
+
.L101:
+  0x34182AE0:  F7FE FCD6    BL         LL_RCC_LSE_IsReady       ; 0x34181490
+  0x34182AE4:  B160         CBZ        R0, .L103                ; 0x34182B00
+  0x34182AE6:  F7FD FFF1    BL         HAL_GetTick              ; 0x34180ACC
+  0x34182AEA:  991F         LDR        R1, [SP, #124]
+  0x34182AEC:  1A40         SUBS       R0, R0, R1
+  0x34182AEE:  F241 3189    MOVW       R1, #0x1389
+  0x34182AF2:  4288         CMP        R0, R1
+  0x34182AF4:  D303         BCC        46L102                    ; 0x34182AFE
+  0x34182AF6:  2003         MOVS       R0, #3
+  0x34182AF8:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182AFC:  E1BB         B          46L144                    ; 0x34182E76
+
.L102:
+  0x34182AFE:  E7EF         B          46L101                    ; 0x34182AE0
+
.L103:
+  0x34182B00:  9820         LDR        R0, [SP, #128]
+  0x34182B02:  6A80         LDR        R0, [R0, #40]
+  0x34182B04:  B158         CBZ        R0, .L104                ; 0x34182B1E
+  0x34182B06:  9820         LDR        R0, [SP, #128]
+  0x34182B08:  6A80         LDR        R0, [R0, #40]
+  0x34182B0A:  2801         CMP        R0, #1
+  0x34182B0C:  D007         BEQ        46L104                    ; 0x34182B1E
+  0x34182B0E:  9820         LDR        R0, [SP, #128]
+  0x34182B10:  6A80         LDR        R0, [R0, #40]
+  0x34182B12:  2802         CMP        R0, #2
+  0x34182B14:  D003         BEQ        46L104                    ; 0x34182B1E
+  0x34182B16:  9820         LDR        R0, [SP, #128]
+  0x34182B18:  6A80         LDR        R0, [R0, #40]
+  0x34182B1A:  2803         CMP        R0, #3
+  0x34182B1C:  D100         BNE        46L105                    ; 0x34182B20
+
.L104:
+  0x34182B1E:  E007         B          46L106                    ; 0x34182B30
+
.L105:
+  0x34182B20:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182B24:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182B28:  F240 21BD    MOVW       R1, #0x02BD
+  0x34182B2C:  F7FF F986    BL         assert_failed            ; 0x34181E3C
+
.L106:
+  0x34182B30:  9820         LDR        R0, [SP, #128]
+  0x34182B32:  6A80         LDR        R0, [R0, #40]
+  0x34182B34:  2800         CMP        R0, #0
+  0x34182B36:  D04B         BEQ        46L113                    ; 0x34182BD0
+  0x34182B38:  9820         LDR        R0, [SP, #128]
+  0x34182B3A:  F100 0128    ADD.W      R1, R0, #40
+  0x34182B3E:  2000         MOVS       R0, #0
+  0x34182B40:  F000 F9E6    BL         RCC_PLL_IsNewConfig      ; 0x34182F10
+  0x34182B44:  9017         STR        R0, [SP, #92]
+  0x34182B46:  F7FE FCAB    BL         LL_RCC_PLL1_IsReady      ; 0x341814A0
+  0x34182B4A:  9016         STR        R0, [SP, #88]
+  0x34182B4C:  9817         LDR        R0, [SP, #92]
+  0x34182B4E:  2801         CMP        R0, #1
+  0x34182B50:  D12F         BNE        46L111                    ; 0x34182BB2
+  0x34182B52:  F7FE FCAD    BL         LL_RCC_IC1_GetSource     ; 0x341814B0
+  0x34182B56:  9015         STR        R0, [SP, #84]
+  0x34182B58:  F7FE FCB2    BL         LL_RCC_IC2_GetSource     ; 0x341814C0
+  0x34182B5C:  9014         STR        R0, [SP, #80]
+  0x34182B5E:  F7FE FCB7    BL         LL_RCC_IC6_GetSource     ; 0x341814D0
+  0x34182B62:  9013         STR        R0, [SP, #76]
+  0x34182B64:  F7FE FCBC    BL         LL_RCC_IC11_GetSource    ; 0x341814E0
+  0x34182B68:  9012         STR        R0, [SP, #72]
+  0x34182B6A:  981D         LDR        R0, [SP, #116]
+  0x34182B6C:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x34182B70:  D105         BNE        46L107                    ; 0x34182B7E
+  0x34182B72:  9815         LDR        R0, [SP, #84]
+  0x34182B74:  B918         CBNZ       R0, .L107                ; 0x34182B7E
+  0x34182B76:  2001         MOVS       R0, #1
+  0x34182B78:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182B7C:  E17B         B          46L144                    ; 0x34182E76
+
.L107:
+  0x34182B7E:  981E         LDR        R0, [SP, #120]
+  0x34182B80:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182B84:  D109         BNE        46L109                    ; 0x34182B9A
+  0x34182B86:  9814         LDR        R0, [SP, #80]
+  0x34182B88:  B118         CBZ        R0, .L108                ; 0x34182B92
+  0x34182B8A:  9813         LDR        R0, [SP, #76]
+  0x34182B8C:  B108         CBZ        R0, .L108                ; 0x34182B92
+  0x34182B8E:  9812         LDR        R0, [SP, #72]
+  0x34182B90:  B918         CBNZ       R0, .L109                ; 0x34182B9A
+
.L108:
+  0x34182B92:  2001         MOVS       R0, #1
+  0x34182B94:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182B98:  E16D         B          46L144                    ; 0x34182E76
+
.L109:
+  0x34182B9A:  9820         LDR        R0, [SP, #128]
+  0x34182B9C:  F100 0128    ADD.W      R1, R0, #40
+  0x34182BA0:  2000         MOVS       R0, #0
+  0x34182BA2:  F000 FA23    BL         RCC_PLL_Config           ; 0x34182FEC
+  0x34182BA6:  B118         CBZ        R0, .L110                ; 0x34182BB0
+  0x34182BA8:  2001         MOVS       R0, #1
+  0x34182BAA:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182BAE:  E162         B          46L144                    ; 0x34182E76
+
.L110:
+  0x34182BB0:  E00E         B          46L113                    ; 0x34182BD0
+
.L111:
+  0x34182BB2:  9820         LDR        R0, [SP, #128]
+  0x34182BB4:  6A80         LDR        R0, [R0, #40]
+  0x34182BB6:  2802         CMP        R0, #2
+  0x34182BB8:  D10A         BNE        46L113                    ; 0x34182BD0
+  0x34182BBA:  9816         LDR        R0, [SP, #88]
+  0x34182BBC:  B940         CBNZ       R0, .L113                ; 0x34182BD0
+  0x34182BBE:  2000         MOVS       R0, #0
+  0x34182BC0:  F000 FBBC    BL         RCC_PLL_Enable           ; 0x3418333C
+  0x34182BC4:  B118         CBZ        R0, .L112                ; 0x34182BCE
+  0x34182BC6:  2001         MOVS       R0, #1
+  0x34182BC8:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182BCC:  E153         B          46L144                    ; 0x34182E76
+
.L112:
+  0x34182BCE:  E7FF         B          46L113                    ; 0x34182BD0
+
.L113:
+  0x34182BD0:  9820         LDR        R0, [SP, #128]
+  0x34182BD2:  6C40         LDR        R0, [R0, #68]
+  0x34182BD4:  B158         CBZ        R0, .L114                ; 0x34182BEE
+  0x34182BD6:  9820         LDR        R0, [SP, #128]
+  0x34182BD8:  6C40         LDR        R0, [R0, #68]
+  0x34182BDA:  2801         CMP        R0, #1
+  0x34182BDC:  D007         BEQ        46L114                    ; 0x34182BEE
+  0x34182BDE:  9820         LDR        R0, [SP, #128]
+  0x34182BE0:  6C40         LDR        R0, [R0, #68]
+  0x34182BE2:  2802         CMP        R0, #2
+  0x34182BE4:  D003         BEQ        46L114                    ; 0x34182BEE
+  0x34182BE6:  9820         LDR        R0, [SP, #128]
+  0x34182BE8:  6C40         LDR        R0, [R0, #68]
+  0x34182BEA:  2803         CMP        R0, #3
+  0x34182BEC:  D100         BNE        46L115                    ; 0x34182BF0
+
.L114:
+  0x34182BEE:  E007         B          46L116                    ; 0x34182C00
+
.L115:
+  0x34182BF0:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182BF4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182BF8:  F240 21EB    MOVW       R1, #0x02EB
+  0x34182BFC:  F7FF F91E    BL         assert_failed            ; 0x34181E3C
+
.L116:
+  0x34182C00:  9820         LDR        R0, [SP, #128]
+  0x34182C02:  6C40         LDR        R0, [R0, #68]
+  0x34182C04:  2800         CMP        R0, #0
+  0x34182C06:  D053         BEQ        46L123                    ; 0x34182CB0
+  0x34182C08:  9820         LDR        R0, [SP, #128]
+  0x34182C0A:  F100 0144    ADD.W      R1, R0, #68
+  0x34182C0E:  2001         MOVS       R0, #1
+  0x34182C10:  F000 F97E    BL         RCC_PLL_IsNewConfig      ; 0x34182F10
+  0x34182C14:  9011         STR        R0, [SP, #68]
+  0x34182C16:  F7FE FC6B    BL         LL_RCC_PLL2_IsReady      ; 0x341814F0
+  0x34182C1A:  9010         STR        R0, [SP, #64]
+  0x34182C1C:  9811         LDR        R0, [SP, #68]
+  0x34182C1E:  2801         CMP        R0, #1
+  0x34182C20:  D137         BNE        46L121                    ; 0x34182C92
+  0x34182C22:  F7FE FC45    BL         LL_RCC_IC1_GetSource     ; 0x341814B0
+  0x34182C26:  900F         STR        R0, [SP, #60]
+  0x34182C28:  F7FE FC4A    BL         LL_RCC_IC2_GetSource     ; 0x341814C0
+  0x34182C2C:  900E         STR        R0, [SP, #56]
+  0x34182C2E:  F7FE FC4F    BL         LL_RCC_IC6_GetSource     ; 0x341814D0
+  0x34182C32:  900D         STR        R0, [SP, #52]
+  0x34182C34:  F7FE FC54    BL         LL_RCC_IC11_GetSource    ; 0x341814E0
+  0x34182C38:  900C         STR        R0, [SP, #48]
+  0x34182C3A:  981D         LDR        R0, [SP, #116]
+  0x34182C3C:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x34182C40:  D107         BNE        46L117                    ; 0x34182C52
+  0x34182C42:  980F         LDR        R0, [SP, #60]
+  0x34182C44:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34182C48:  D103         BNE        46L117                    ; 0x34182C52
+  0x34182C4A:  2001         MOVS       R0, #1
+  0x34182C4C:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182C50:  E111         B          46L144                    ; 0x34182E76
+
.L117:
+  0x34182C52:  981E         LDR        R0, [SP, #120]
+  0x34182C54:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182C58:  D10F         BNE        46L119                    ; 0x34182C7A
+  0x34182C5A:  980E         LDR        R0, [SP, #56]
+  0x34182C5C:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34182C60:  D007         BEQ        46L118                    ; 0x34182C72
+  0x34182C62:  980D         LDR        R0, [SP, #52]
+  0x34182C64:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34182C68:  D003         BEQ        46L118                    ; 0x34182C72
+  0x34182C6A:  980C         LDR        R0, [SP, #48]
+  0x34182C6C:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34182C70:  D103         BNE        46L119                    ; 0x34182C7A
+
.L118:
+  0x34182C72:  2001         MOVS       R0, #1
+  0x34182C74:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182C78:  E0FD         B          46L144                    ; 0x34182E76
+
.L119:
+  0x34182C7A:  9820         LDR        R0, [SP, #128]
+  0x34182C7C:  F100 0144    ADD.W      R1, R0, #68
+  0x34182C80:  2001         MOVS       R0, #1
+  0x34182C82:  F000 F9B3    BL         RCC_PLL_Config           ; 0x34182FEC
+  0x34182C86:  B118         CBZ        R0, .L120                ; 0x34182C90
+  0x34182C88:  2001         MOVS       R0, #1
+  0x34182C8A:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182C8E:  E0F2         B          46L144                    ; 0x34182E76
+
.L120:
+  0x34182C90:  E00E         B          46L123                    ; 0x34182CB0
+
.L121:
+  0x34182C92:  9820         LDR        R0, [SP, #128]
+  0x34182C94:  6C40         LDR        R0, [R0, #68]
+  0x34182C96:  2802         CMP        R0, #2
+  0x34182C98:  D10A         BNE        46L123                    ; 0x34182CB0
+  0x34182C9A:  9810         LDR        R0, [SP, #64]
+  0x34182C9C:  B940         CBNZ       R0, .L123                ; 0x34182CB0
+  0x34182C9E:  2001         MOVS       R0, #1
+  0x34182CA0:  F000 FB4C    BL         RCC_PLL_Enable           ; 0x3418333C
+  0x34182CA4:  B118         CBZ        R0, .L122                ; 0x34182CAE
+  0x34182CA6:  2001         MOVS       R0, #1
+  0x34182CA8:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182CAC:  E0E3         B          46L144                    ; 0x34182E76
+
.L122:
+  0x34182CAE:  E7FF         B          46L123                    ; 0x34182CB0
+
.L123:
+  0x34182CB0:  9820         LDR        R0, [SP, #128]
+  0x34182CB2:  6E00         LDR        R0, [R0, #96]
+  0x34182CB4:  B158         CBZ        R0, .L124                ; 0x34182CCE
+  0x34182CB6:  9820         LDR        R0, [SP, #128]
+  0x34182CB8:  6E00         LDR        R0, [R0, #96]
+  0x34182CBA:  2801         CMP        R0, #1
+  0x34182CBC:  D007         BEQ        46L124                    ; 0x34182CCE
+  0x34182CBE:  9820         LDR        R0, [SP, #128]
+  0x34182CC0:  6E00         LDR        R0, [R0, #96]
+  0x34182CC2:  2802         CMP        R0, #2
+  0x34182CC4:  D003         BEQ        46L124                    ; 0x34182CCE
+  0x34182CC6:  9820         LDR        R0, [SP, #128]
+  0x34182CC8:  6E00         LDR        R0, [R0, #96]
+  0x34182CCA:  2803         CMP        R0, #3
+  0x34182CCC:  D100         BNE        46L125                    ; 0x34182CD0
+
.L124:
+  0x34182CCE:  E007         B          46L126                    ; 0x34182CE0
+
.L125:
+  0x34182CD0:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182CD4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182CD8:  F240 3119    MOVW       R1, #0x0319
+  0x34182CDC:  F7FF F8AE    BL         assert_failed            ; 0x34181E3C
+
.L126:
+  0x34182CE0:  9820         LDR        R0, [SP, #128]
+  0x34182CE2:  6E00         LDR        R0, [R0, #96]
+  0x34182CE4:  2800         CMP        R0, #0
+  0x34182CE6:  D053         BEQ        46L133                    ; 0x34182D90
+  0x34182CE8:  9820         LDR        R0, [SP, #128]
+  0x34182CEA:  F100 0160    ADD.W      R1, R0, #96
+  0x34182CEE:  2002         MOVS       R0, #2
+  0x34182CF0:  F000 F90E    BL         RCC_PLL_IsNewConfig      ; 0x34182F10
+  0x34182CF4:  900B         STR        R0, [SP, #44]
+  0x34182CF6:  F7FE FC03    BL         LL_RCC_PLL3_IsReady      ; 0x34181500
+  0x34182CFA:  900A         STR        R0, [SP, #40]
+  0x34182CFC:  980B         LDR        R0, [SP, #44]
+  0x34182CFE:  2801         CMP        R0, #1
+  0x34182D00:  D137         BNE        46L131                    ; 0x34182D72
+  0x34182D02:  F7FE FBD5    BL         LL_RCC_IC1_GetSource     ; 0x341814B0
+  0x34182D06:  9009         STR        R0, [SP, #36]
+  0x34182D08:  F7FE FBDA    BL         LL_RCC_IC2_GetSource     ; 0x341814C0
+  0x34182D0C:  9008         STR        R0, [SP, #32]
+  0x34182D0E:  F7FE FBDF    BL         LL_RCC_IC6_GetSource     ; 0x341814D0
+  0x34182D12:  9007         STR        R0, [SP, #28]
+  0x34182D14:  F7FE FBE4    BL         LL_RCC_IC11_GetSource    ; 0x341814E0
+  0x34182D18:  9006         STR        R0, [SP, #24]
+  0x34182D1A:  981D         LDR        R0, [SP, #116]
+  0x34182D1C:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x34182D20:  D107         BNE        46L127                    ; 0x34182D32
+  0x34182D22:  9809         LDR        R0, [SP, #36]
+  0x34182D24:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34182D28:  D103         BNE        46L127                    ; 0x34182D32
+  0x34182D2A:  2001         MOVS       R0, #1
+  0x34182D2C:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182D30:  E0A1         B          46L144                    ; 0x34182E76
+
.L127:
+  0x34182D32:  981E         LDR        R0, [SP, #120]
+  0x34182D34:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182D38:  D10F         BNE        46L129                    ; 0x34182D5A
+  0x34182D3A:  9808         LDR        R0, [SP, #32]
+  0x34182D3C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34182D40:  D007         BEQ        46L128                    ; 0x34182D52
+  0x34182D42:  9807         LDR        R0, [SP, #28]
+  0x34182D44:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34182D48:  D003         BEQ        46L128                    ; 0x34182D52
+  0x34182D4A:  9806         LDR        R0, [SP, #24]
+  0x34182D4C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34182D50:  D103         BNE        46L129                    ; 0x34182D5A
+
.L128:
+  0x34182D52:  2001         MOVS       R0, #1
+  0x34182D54:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182D58:  E08D         B          46L144                    ; 0x34182E76
+
.L129:
+  0x34182D5A:  9820         LDR        R0, [SP, #128]
+  0x34182D5C:  F100 0160    ADD.W      R1, R0, #96
+  0x34182D60:  2002         MOVS       R0, #2
+  0x34182D62:  F000 F943    BL         RCC_PLL_Config           ; 0x34182FEC
+  0x34182D66:  B118         CBZ        R0, .L130                ; 0x34182D70
+  0x34182D68:  2001         MOVS       R0, #1
+  0x34182D6A:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182D6E:  E082         B          46L144                    ; 0x34182E76
+
.L130:
+  0x34182D70:  E00E         B          46L133                    ; 0x34182D90
+
.L131:
+  0x34182D72:  9820         LDR        R0, [SP, #128]
+  0x34182D74:  6E00         LDR        R0, [R0, #96]
+  0x34182D76:  2802         CMP        R0, #2
+  0x34182D78:  D10A         BNE        46L133                    ; 0x34182D90
+  0x34182D7A:  980A         LDR        R0, [SP, #40]
+  0x34182D7C:  B940         CBNZ       R0, .L133                ; 0x34182D90
+  0x34182D7E:  2002         MOVS       R0, #2
+  0x34182D80:  F000 FADC    BL         RCC_PLL_Enable           ; 0x3418333C
+  0x34182D84:  B118         CBZ        R0, .L132                ; 0x34182D8E
+  0x34182D86:  2001         MOVS       R0, #1
+  0x34182D88:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182D8C:  E073         B          46L144                    ; 0x34182E76
+
.L132:
+  0x34182D8E:  E7FF         B          46L133                    ; 0x34182D90
+
.L133:
+  0x34182D90:  9820         LDR        R0, [SP, #128]
+  0x34182D92:  6FC0         LDR        R0, [R0, #124]
+  0x34182D94:  B158         CBZ        R0, .L134                ; 0x34182DAE
+  0x34182D96:  9820         LDR        R0, [SP, #128]
+  0x34182D98:  6FC0         LDR        R0, [R0, #124]
+  0x34182D9A:  2801         CMP        R0, #1
+  0x34182D9C:  D007         BEQ        46L134                    ; 0x34182DAE
+  0x34182D9E:  9820         LDR        R0, [SP, #128]
+  0x34182DA0:  6FC0         LDR        R0, [R0, #124]
+  0x34182DA2:  2802         CMP        R0, #2
+  0x34182DA4:  D003         BEQ        46L134                    ; 0x34182DAE
+  0x34182DA6:  9820         LDR        R0, [SP, #128]
+  0x34182DA8:  6FC0         LDR        R0, [R0, #124]
+  0x34182DAA:  2803         CMP        R0, #3
+  0x34182DAC:  D100         BNE        46L135                    ; 0x34182DB0
+
.L134:
+  0x34182DAE:  E007         B          46L136                    ; 0x34182DC0
+
.L135:
+  0x34182DB0:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34182DB4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34182DB8:  F240 3146    MOVW       R1, #0x0346
+  0x34182DBC:  F7FF F83E    BL         assert_failed            ; 0x34181E3C
+
.L136:
+  0x34182DC0:  9820         LDR        R0, [SP, #128]
+  0x34182DC2:  6FC0         LDR        R0, [R0, #124]
+  0x34182DC4:  2800         CMP        R0, #0
+  0x34182DC6:  D053         BEQ        46L143                    ; 0x34182E70
+  0x34182DC8:  9820         LDR        R0, [SP, #128]
+  0x34182DCA:  F100 017C    ADD.W      R1, R0, #124
+  0x34182DCE:  2003         MOVS       R0, #3
+  0x34182DD0:  F000 F89E    BL         RCC_PLL_IsNewConfig      ; 0x34182F10
+  0x34182DD4:  9005         STR        R0, [SP, #20]
+  0x34182DD6:  F7FE FB9B    BL         LL_RCC_PLL4_IsReady      ; 0x34181510
+  0x34182DDA:  9004         STR        R0, [SP, #16]
+  0x34182DDC:  9805         LDR        R0, [SP, #20]
+  0x34182DDE:  2801         CMP        R0, #1
+  0x34182DE0:  D137         BNE        46L141                    ; 0x34182E52
+  0x34182DE2:  F7FE FB65    BL         LL_RCC_IC1_GetSource     ; 0x341814B0
+  0x34182DE6:  9003         STR        R0, [SP, #12]
+  0x34182DE8:  F7FE FB6A    BL         LL_RCC_IC2_GetSource     ; 0x341814C0
+  0x34182DEC:  9002         STR        R0, [SP, #8]
+  0x34182DEE:  F7FE FB6F    BL         LL_RCC_IC6_GetSource     ; 0x341814D0
+  0x34182DF2:  9001         STR        R0, [SP, #4]
+  0x34182DF4:  F7FE FB74    BL         LL_RCC_IC11_GetSource    ; 0x341814E0
+  0x34182DF8:  9000         STR        R0, [SP, #0]
+  0x34182DFA:  981D         LDR        R0, [SP, #116]
+  0x34182DFC:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x34182E00:  D107         BNE        46L137                    ; 0x34182E12
+  0x34182E02:  9803         LDR        R0, [SP, #12]
+  0x34182E04:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182E08:  D103         BNE        46L137                    ; 0x34182E12
+  0x34182E0A:  2001         MOVS       R0, #1
+  0x34182E0C:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182E10:  E031         B          46L144                    ; 0x34182E76
+
.L137:
+  0x34182E12:  981E         LDR        R0, [SP, #120]
+  0x34182E14:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182E18:  D10F         BNE        46L139                    ; 0x34182E3A
+  0x34182E1A:  9802         LDR        R0, [SP, #8]
+  0x34182E1C:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182E20:  D007         BEQ        46L138                    ; 0x34182E32
+  0x34182E22:  9801         LDR        R0, [SP, #4]
+  0x34182E24:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182E28:  D003         BEQ        46L138                    ; 0x34182E32
+  0x34182E2A:  9800         LDR        R0, [SP, #0]
+  0x34182E2C:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34182E30:  D103         BNE        46L139                    ; 0x34182E3A
+
.L138:
+  0x34182E32:  2001         MOVS       R0, #1
+  0x34182E34:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182E38:  E01D         B          46L144                    ; 0x34182E76
+
.L139:
+  0x34182E3A:  9820         LDR        R0, [SP, #128]
+  0x34182E3C:  F100 017C    ADD.W      R1, R0, #124
+  0x34182E40:  2003         MOVS       R0, #3
+  0x34182E42:  F000 F8D3    BL         RCC_PLL_Config           ; 0x34182FEC
+  0x34182E46:  B118         CBZ        R0, .L140                ; 0x34182E50
+  0x34182E48:  2001         MOVS       R0, #1
+  0x34182E4A:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182E4E:  E012         B          46L144                    ; 0x34182E76
+
.L140:
+  0x34182E50:  E00E         B          46L143                    ; 0x34182E70
+
.L141:
+  0x34182E52:  9820         LDR        R0, [SP, #128]
+  0x34182E54:  6FC0         LDR        R0, [R0, #124]
+  0x34182E56:  2802         CMP        R0, #2
+  0x34182E58:  D10A         BNE        46L143                    ; 0x34182E70
+  0x34182E5A:  9804         LDR        R0, [SP, #16]
+  0x34182E5C:  B940         CBNZ       R0, .L143                ; 0x34182E70
+  0x34182E5E:  2003         MOVS       R0, #3
+  0x34182E60:  F000 FA6C    BL         RCC_PLL_Enable           ; 0x3418333C
+  0x34182E64:  B118         CBZ        R0, .L142                ; 0x34182E6E
+  0x34182E66:  2001         MOVS       R0, #1
+  0x34182E68:  F88D 0087    STRB.W     R0, [SP, #135]
+  0x34182E6C:  E003         B          46L144                    ; 0x34182E76
+
.L142:
+  0x34182E6E:  E7FF         B          46L143                    ; 0x34182E70
+
.L143:
+  0x34182E70:  2000         MOVS       R0, #0
+  0x34182E72:  F88D 0087    STRB.W     R0, [SP, #135]
+
.L144:
+  0x34182E76:  F89D 0087    LDRB.W     R0, [SP, #135]
+  0x34182E7A:  B022         ADD        SP, SP, #136
+  0x34182E7C:  BD80         POP        123R7, PC}
+
+

Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI9_IRQHandler:
+  0x34182E7E:  E7FE         B          EXTI9_IRQHandler         ; 0x34182E7E
+
+

Section .text.LL_RCC_HSI_SetCalibTrimming from blto2_FSBL_lto.o, size=30, align=4

+ +
+
LL_RCC_HSI_SetCalibTrimming:
+  0x34182E80:  B081         SUB        SP, SP, #4
+  0x34182E82:  9000         STR        R0, [SP, #0]
+  0x34182E84:  F248 0148    MOVW       R1, #0x8048
+  0x34182E88:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182E8C:  6808         LDR        R0, [R1]
+  0x34182E8E:  F420 00FE    BIC        R0, R0, #0x7F0000
+  0x34182E92:  9A00         LDR        R2, [SP, #0]
+  0x34182E94:  EA40 4002    ORR.W      R0, R0, R2, LSL #16
+  0x34182E98:  6008         STR        R0, [R1]
+  0x34182E9A:  B001         ADD        SP, SP, #4
+  0x34182E9C:  4770         BX         LR
+
+

Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI10_IRQHandler:
+  0x34182E9E:  E7FE         B          EXTI10_IRQHandler        ; 0x34182E9E
+
+

Section .text.LL_RCC_HSI_Disable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_HSI_Disable:
+  0x34182EA0:  F249 0100    MOVW       R1, #0x9000
+  0x34182EA4:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182EA8:  2008         MOVS       R0, #8
+  0x34182EAA:  6008         STR        R0, [R1]
+  0x34182EAC:  4770         BX         LR
+
+

Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI11_IRQHandler:
+  0x34182EAE:  E7FE         B          EXTI11_IRQHandler        ; 0x34182EAE
+
+

Section .text.LL_RCC_MSI_SetCalibTrimming from blto2_FSBL_lto.o, size=30, align=4

+ +
+
LL_RCC_MSI_SetCalibTrimming:
+  0x34182EB0:  B081         SUB        SP, SP, #4
+  0x34182EB2:  9000         STR        R0, [SP, #0]
+  0x34182EB4:  F248 0144    MOVW       R1, #0x8044
+  0x34182EB8:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182EBC:  6808         LDR        R0, [R1]
+  0x34182EBE:  F420 10F8    BIC        R0, R0, #0x1F0000
+  0x34182EC2:  9A00         LDR        R2, [SP, #0]
+  0x34182EC4:  EA40 4002    ORR.W      R0, R0, R2, LSL #16
+  0x34182EC8:  6008         STR        R0, [R1]
+  0x34182ECA:  B001         ADD        SP, SP, #4
+  0x34182ECC:  4770         BX         LR
+
+

Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI12_IRQHandler:
+  0x34182ECE:  E7FE         B          EXTI12_IRQHandler        ; 0x34182ECE
+
+

Section .text.LL_RCC_MSI_Enable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_MSI_Enable:
+  0x34182ED0:  F648 0100    MOVW       R1, #0x8800
+  0x34182ED4:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182ED8:  2004         MOVS       R0, #4
+  0x34182EDA:  6008         STR        R0, [R1]
+  0x34182EDC:  4770         BX         LR
+
+

Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI13_IRQHandler:
+  0x34182EDE:  E7FE         B          EXTI13_IRQHandler        ; 0x34182EDE
+
+

Section .text.LL_RCC_MSI_Disable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_MSI_Disable:
+  0x34182EE0:  F249 0100    MOVW       R1, #0x9000
+  0x34182EE4:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182EE8:  2004         MOVS       R0, #4
+  0x34182EEA:  6008         STR        R0, [R1]
+  0x34182EEC:  4770         BX         LR
+
+

Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI14_IRQHandler:
+  0x34182EEE:  E7FE         B          EXTI14_IRQHandler        ; 0x34182EEE
+
+

Section .text.LL_RCC_LSI_Enable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_LSI_Enable:
+  0x34182EF0:  F648 0100    MOVW       R1, #0x8800
+  0x34182EF4:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182EF8:  2001         MOVS       R0, #1
+  0x34182EFA:  6008         STR        R0, [R1]
+  0x34182EFC:  4770         BX         LR
+
+

Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI15_IRQHandler:
+  0x34182EFE:  E7FE         B          EXTI15_IRQHandler        ; 0x34182EFE
+
+

Section .text.LL_RCC_LSI_Disable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_LSI_Disable:
+  0x34182F00:  F249 0100    MOVW       R1, #0x9000
+  0x34182F04:  F2C5 6102    MOVT       R1, #0x5602
+  0x34182F08:  2001         MOVS       R0, #1
+  0x34182F0A:  6008         STR        R0, [R1]
+  0x34182F0C:  4770         BX         LR
+
+

Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAES_IRQHandler:
+  0x34182F0E:  E7FE         B          SAES_IRQHandler          ; 0x34182F0E
+
+

Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=218, align=4

+ +
+
RCC_PLL_IsNewConfig:
+  0x34182F10:  B087         SUB        SP, SP, #28
+  0x34182F12:  9006         STR        R0, [SP, #24]
+  0x34182F14:  9105         STR        R1, [SP, #20]
+  0x34182F16:  2000         MOVS       R0, #0
+  0x34182F18:  9001         STR        R0, [SP, #4]
+  0x34182F1A:  9906         LDR        R1, [SP, #24]
+  0x34182F1C:  F248 0080    MOVW       R0, #0x8080
+  0x34182F20:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182F24:  EB00 1001    ADD.W      R0, R0, R1, LSL #4
+  0x34182F28:  9004         STR        R0, [SP, #16]
+  0x34182F2A:  9906         LDR        R1, [SP, #24]
+  0x34182F2C:  F248 0084    MOVW       R0, #0x8084
+  0x34182F30:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182F34:  EB00 1001    ADD.W      R0, R0, R1, LSL #4
+  0x34182F38:  9003         STR        R0, [SP, #12]
+  0x34182F3A:  9906         LDR        R1, [SP, #24]
+  0x34182F3C:  F248 0088    MOVW       R0, #0x8088
+  0x34182F40:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182F44:  EB00 1001    ADD.W      R0, R0, R1, LSL #4
+  0x34182F48:  9002         STR        R0, [SP, #8]
+  0x34182F4A:  9804         LDR        R0, [SP, #16]
+  0x34182F4C:  6800         LDR        R0, [R0]
+  0x34182F4E:  F64F 7100    MOVW       R1, #0xFF00
+  0x34182F52:  F2C7 31FF    MOVT       R1, #0x73FF
+  0x34182F56:  4008         ANDS       R0, R1
+  0x34182F58:  9A05         LDR        R2, [SP, #20]
+  0x34182F5A:  6851         LDR        R1, [R2, #4]
+  0x34182F5C:  6893         LDR        R3, [R2, #8]
+  0x34182F5E:  6912         LDR        R2, [R2, #16]
+  0x34182F60:  EA41 5103    ORR.W      R1, R1, R3, LSL #20
+  0x34182F64:  EA41 2102    ORR.W      R1, R1, R2, LSL #8
+  0x34182F68:  4288         CMP        R0, R1
+  0x34182F6A:  D002         BEQ        46L1                      ; 0x34182F72
+  0x34182F6C:  2001         MOVS       R0, #1
+  0x34182F6E:  9001         STR        R0, [SP, #4]
+  0x34182F70:  E038         B          46L7                      ; 0x34182FE4
+
.L1:
+  0x34182F72:  9803         LDR        R0, [SP, #12]
+  0x34182F74:  6800         LDR        R0, [R0]
+  0x34182F76:  F020 407F    BIC        R0, R0, #0xFF000000
+  0x34182F7A:  9905         LDR        R1, [SP, #20]
+  0x34182F7C:  68C9         LDR        R1, [R1, #12]
+  0x34182F7E:  4288         CMP        R0, R1
+  0x34182F80:  D002         BEQ        46L2                      ; 0x34182F88
+  0x34182F82:  2001         MOVS       R0, #1
+  0x34182F84:  9001         STR        R0, [SP, #4]
+  0x34182F86:  E02D         B          46L7                      ; 0x34182FE4
+
.L2:
+  0x34182F88:  9802         LDR        R0, [SP, #8]
+  0x34182F8A:  6800         LDR        R0, [R0]
+  0x34182F8C:  F000 507C    AND        R0, R0, #0x3F000000
+  0x34182F90:  9A05         LDR        R2, [SP, #20]
+  0x34182F92:  6951         LDR        R1, [R2, #20]
+  0x34182F94:  6992         LDR        R2, [R2, #24]
+  0x34182F96:  06C9         LSLS       R1, R1, #27
+  0x34182F98:  EA41 6102    ORR.W      R1, R1, R2, LSL #24
+  0x34182F9C:  4288         CMP        R0, R1
+  0x34182F9E:  D002         BEQ        46L3                      ; 0x34182FA6
+  0x34182FA0:  2001         MOVS       R0, #1
+  0x34182FA2:  9001         STR        R0, [SP, #4]
+  0x34182FA4:  E01E         B          46L7                      ; 0x34182FE4
+
.L3:
+  0x34182FA6:  F248 0004    MOVW       R0, #0x8004
+  0x34182FAA:  F2C5 6002    MOVT       R0, #0x5602
+  0x34182FAE:  6800         LDR        R0, [R0]
+  0x34182FB0:  43C0         MVNS       R0, R0
+  0x34182FB2:  9906         LDR        R1, [SP, #24]
+  0x34182FB4:  40C8         LSRS       R0, R1
+  0x34182FB6:  05C0         LSLS       R0, R0, #23
+  0x34182FB8:  2800         CMP        R0, #0
+  0x34182FBA:  D402         BMI        46L4                      ; 0x34182FC2
+  0x34182FBC:  2002         MOVS       R0, #2
+  0x34182FBE:  9000         STR        R0, [SP, #0]
+  0x34182FC0:  E009         B          46L6                      ; 0x34182FD6
+
.L4:
+  0x34182FC2:  9804         LDR        R0, [SP, #16]
+  0x34182FC4:  6800         LDR        R0, [R0]
+  0x34182FC6:  0100         LSLS       R0, R0, #4
+  0x34182FC8:  2800         CMP        R0, #0
+  0x34182FCA:  D502         BPL        46L5                      ; 0x34182FD2
+  0x34182FCC:  2003         MOVS       R0, #3
+  0x34182FCE:  9000         STR        R0, [SP, #0]
+  0x34182FD0:  E001         B          46L6                      ; 0x34182FD6
+
.L5:
+  0x34182FD2:  2001         MOVS       R0, #1
+  0x34182FD4:  9000         STR        R0, [SP, #0]
+
.L6:
+  0x34182FD6:  9800         LDR        R0, [SP, #0]
+  0x34182FD8:  9905         LDR        R1, [SP, #20]
+  0x34182FDA:  6809         LDR        R1, [R1]
+  0x34182FDC:  4288         CMP        R0, R1
+  0x34182FDE:  D001         BEQ        46L7                      ; 0x34182FE4
+  0x34182FE0:  2001         MOVS       R0, #1
+  0x34182FE2:  9001         STR        R0, [SP, #4]
+
.L7:
+  0x34182FE4:  9801         LDR        R0, [SP, #4]
+  0x34182FE6:  B007         ADD        SP, SP, #28
+  0x34182FE8:  4770         BX         LR
+
+

Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CRYP_IRQHandler:
+  0x34182FEA:  E7FE         B          CRYP_IRQHandler          ; 0x34182FEA
+
+

Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=846, align=4

+ +
+
RCC_PLL_Config:
+  0x34182FEC:  B580         PUSH       123R7, LR}
+  0x34182FEE:  B088         SUB        SP, SP, #32
+  0x34182FF0:  9006         STR        R0, [SP, #24]
+  0x34182FF2:  9105         STR        R1, [SP, #20]
+  0x34182FF4:  2000         MOVS       R0, #0
+  0x34182FF6:  F88D 0007    STRB.W     R0, [SP, #7]
+  0x34182FFA:  9906         LDR        R1, [SP, #24]
+  0x34182FFC:  F248 0080    MOVW       R0, #0x8080
+  0x34183000:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183004:  EB00 1001    ADD.W      R0, R0, R1, LSL #4
+  0x34183008:  9004         STR        R0, [SP, #16]
+  0x3418300A:  9906         LDR        R1, [SP, #24]
+  0x3418300C:  F248 0084    MOVW       R0, #0x8084
+  0x34183010:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183014:  EB00 1001    ADD.W      R0, R0, R1, LSL #4
+  0x34183018:  9003         STR        R0, [SP, #12]
+  0x3418301A:  9906         LDR        R1, [SP, #24]
+  0x3418301C:  F248 0088    MOVW       R0, #0x8088
+  0x34183020:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183024:  EB00 1001    ADD.W      R0, R0, R1, LSL #4
+  0x34183028:  9002         STR        R0, [SP, #8]
+  0x3418302A:  9805         LDR        R0, [SP, #20]
+  0x3418302C:  6800         LDR        R0, [R0]
+  0x3418302E:  2802         CMP        R0, #2
+  0x34183030:  F040 80F3    BNE.W      46L21                     ; 0x3418321A
+  0x34183034:  9805         LDR        R0, [SP, #20]
+  0x34183036:  6840         LDR        R0, [R0, #4]
+  0x34183038:  B170         CBZ        R0, .L1                  ; 0x34183058
+  0x3418303A:  9805         LDR        R0, [SP, #20]
+  0x3418303C:  6840         LDR        R0, [R0, #4]
+  0x3418303E:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34183042:  D009         BEQ        46L1                      ; 0x34183058
+  0x34183044:  9805         LDR        R0, [SP, #20]
+  0x34183046:  6840         LDR        R0, [R0, #4]
+  0x34183048:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x3418304C:  D004         BEQ        46L1                      ; 0x34183058
+  0x3418304E:  9805         LDR        R0, [SP, #20]
+  0x34183050:  6840         LDR        R0, [R0, #4]
+  0x34183052:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34183056:  D100         BNE        46L2                      ; 0x3418305A
+
.L1:
+  0x34183058:  E007         B          46L3                      ; 0x3418306A
+
.L2:
+  0x3418305A:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x3418305E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183062:  F640 0159    MOVW       R1, #0x0859
+  0x34183066:  F7FE FEE9    BL         assert_failed            ; 0x34181E3C
+
.L3:
+  0x3418306A:  9805         LDR        R0, [SP, #20]
+  0x3418306C:  7BC0         LDRB       R0, [R0, #15]
+  0x3418306E:  B900         CBNZ       R0, .L4                  ; 0x34183072
+  0x34183070:  E007         B          46L5                      ; 0x34183082
+
.L4:
+  0x34183072:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183076:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418307A:  F640 015A    MOVW       R1, #0x085A
+  0x3418307E:  F7FE FEDD    BL         assert_failed            ; 0x34181E3C
+
.L5:
+  0x34183082:  9805         LDR        R0, [SP, #20]
+  0x34183084:  6880         LDR        R0, [R0, #8]
+  0x34183086:  B120         CBZ        R0, .L6                  ; 0x34183092
+  0x34183088:  9805         LDR        R0, [SP, #20]
+  0x3418308A:  6880         LDR        R0, [R0, #8]
+  0x3418308C:  283F         CMP        R0, #63
+  0x3418308E:  D800         BHI        46L6                      ; 0x34183092
+  0x34183090:  E007         B          46L7                      ; 0x341830A2
+
.L6:
+  0x34183092:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183096:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418309A:  F640 015B    MOVW       R1, #0x085B
+  0x3418309E:  F7FE FECD    BL         assert_failed            ; 0x34181E3C
+
.L7:
+  0x341830A2:  9805         LDR        R0, [SP, #20]
+  0x341830A4:  6900         LDR        R0, [R0, #16]
+  0x341830A6:  280A         CMP        R0, #10
+  0x341830A8:  D306         BCC        46L8                      ; 0x341830B8
+  0x341830AA:  9805         LDR        R0, [SP, #20]
+  0x341830AC:  6900         LDR        R0, [R0, #16]
+  0x341830AE:  F640 11C4    MOVW       R1, #0x09C4
+  0x341830B2:  4288         CMP        R0, R1
+  0x341830B4:  D800         BHI        46L8                      ; 0x341830B8
+  0x341830B6:  E007         B          46L9                      ; 0x341830C8
+
.L8:
+  0x341830B8:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341830BC:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341830C0:  F640 015C    MOVW       R1, #0x085C
+  0x341830C4:  F7FE FEBA    BL         assert_failed            ; 0x34181E3C
+
.L9:
+  0x341830C8:  9805         LDR        R0, [SP, #20]
+  0x341830CA:  6940         LDR        R0, [R0, #20]
+  0x341830CC:  B120         CBZ        R0, .L10                 ; 0x341830D8
+  0x341830CE:  9805         LDR        R0, [SP, #20]
+  0x341830D0:  6940         LDR        R0, [R0, #20]
+  0x341830D2:  2807         CMP        R0, #7
+  0x341830D4:  D800         BHI        46L10                     ; 0x341830D8
+  0x341830D6:  E007         B          46L11                     ; 0x341830E8
+
.L10:
+  0x341830D8:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341830DC:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341830E0:  F640 015D    MOVW       R1, #0x085D
+  0x341830E4:  F7FE FEAA    BL         assert_failed            ; 0x34181E3C
+
.L11:
+  0x341830E8:  9805         LDR        R0, [SP, #20]
+  0x341830EA:  6980         LDR        R0, [R0, #24]
+  0x341830EC:  B120         CBZ        R0, .L12                 ; 0x341830F8
+  0x341830EE:  9805         LDR        R0, [SP, #20]
+  0x341830F0:  6980         LDR        R0, [R0, #24]
+  0x341830F2:  2807         CMP        R0, #7
+  0x341830F4:  D800         BHI        46L12                     ; 0x341830F8
+  0x341830F6:  E007         B          46L13                     ; 0x34183108
+
.L12:
+  0x341830F8:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341830FC:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183100:  F640 015E    MOVW       R1, #0x085E
+  0x34183104:  F7FE FE9A    BL         assert_failed            ; 0x34181E3C
+
.L13:
+  0x34183108:  9906         LDR        R1, [SP, #24]
+  0x3418310A:  F44F 7080    MOV.W      R0, #0x0100
+  0x3418310E:  4088         LSLS       R0, R1
+  0x34183110:  F249 0100    MOVW       R1, #0x9000
+  0x34183114:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183118:  6008         STR        R0, [R1]
+  0x3418311A:  F7FD FCD7    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418311E:  9000         STR        R0, [SP, #0]
+
.L14:
+  0x34183120:  F248 0004    MOVW       R0, #0x8004
+  0x34183124:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183128:  6800         LDR        R0, [R0]
+  0x3418312A:  43C0         MVNS       R0, R0
+  0x3418312C:  9906         LDR        R1, [SP, #24]
+  0x3418312E:  40C8         LSRS       R0, R1
+  0x34183130:  05C0         LSLS       R0, R0, #23
+  0x34183132:  2800         CMP        R0, #0
+  0x34183134:  D40A         BMI        46L16                     ; 0x3418314C
+  0x34183136:  F7FD FCC9    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418313A:  9900         LDR        R1, [SP, #0]
+  0x3418313C:  1A40         SUBS       R0, R0, R1
+  0x3418313E:  2802         CMP        R0, #2
+  0x34183140:  D303         BCC        46L15                     ; 0x3418314A
+  0x34183142:  2003         MOVS       R0, #3
+  0x34183144:  F88D 001F    STRB.W     R0, [SP, #31]
+  0x34183148:  E0F3         B          46L35                     ; 0x34183332
+
.L15:
+  0x3418314A:  E7E9         B          46L14                     ; 0x34183120
+
.L16:
+  0x3418314C:  9902         LDR        R1, [SP, #8]
+  0x3418314E:  6808         LDR        R0, [R1]
+  0x34183150:  F040 0004    ORR        R0, R0, #4
+  0x34183154:  6008         STR        R0, [R1]
+  0x34183156:  9904         LDR        R1, [SP, #16]
+  0x34183158:  6808         LDR        R0, [R1]
+  0x3418315A:  F020 6000    BIC        R0, R0, #0x08000000
+  0x3418315E:  6008         STR        R0, [R1]
+  0x34183160:  9804         LDR        R0, [SP, #16]
+  0x34183162:  6800         LDR        R0, [R0]
+  0x34183164:  21FF         MOVS       R1, #255
+  0x34183166:  F6C8 4100    MOVT       R1, #0x8C00
+  0x3418316A:  4008         ANDS       R0, R1
+  0x3418316C:  9A05         LDR        R2, [SP, #20]
+  0x3418316E:  6851         LDR        R1, [R2, #4]
+  0x34183170:  6893         LDR        R3, [R2, #8]
+  0x34183172:  6912         LDR        R2, [R2, #16]
+  0x34183174:  EA41 5103    ORR.W      R1, R1, R3, LSL #20
+  0x34183178:  EA41 2102    ORR.W      R1, R1, R2, LSL #8
+  0x3418317C:  4308         ORRS       R0, R1
+  0x3418317E:  9904         LDR        R1, [SP, #16]
+  0x34183180:  6008         STR        R0, [R1]
+  0x34183182:  9802         LDR        R0, [SP, #8]
+  0x34183184:  6800         LDR        R0, [R0]
+  0x34183186:  F020 507C    BIC        R0, R0, #0x3F000000
+  0x3418318A:  9A05         LDR        R2, [SP, #20]
+  0x3418318C:  6951         LDR        R1, [R2, #20]
+  0x3418318E:  6992         LDR        R2, [R2, #24]
+  0x34183190:  06C9         LSLS       R1, R1, #27
+  0x34183192:  EA41 6102    ORR.W      R1, R1, R2, LSL #24
+  0x34183196:  4308         ORRS       R0, R1
+  0x34183198:  9902         LDR        R1, [SP, #8]
+  0x3418319A:  6008         STR        R0, [R1]
+  0x3418319C:  9803         LDR        R0, [SP, #12]
+  0x3418319E:  6800         LDR        R0, [R0]
+  0x341831A0:  F000 407F    AND        R0, R0, #0xFF000000
+  0x341831A4:  9905         LDR        R1, [SP, #20]
+  0x341831A6:  68C9         LDR        R1, [R1, #12]
+  0x341831A8:  4308         ORRS       R0, R1
+  0x341831AA:  9903         LDR        R1, [SP, #12]
+  0x341831AC:  6008         STR        R0, [R1]
+  0x341831AE:  9902         LDR        R1, [SP, #8]
+  0x341831B0:  6808         LDR        R0, [R1]
+  0x341831B2:  F020 0008    BIC        R0, R0, #8
+  0x341831B6:  6008         STR        R0, [R1]
+  0x341831B8:  9805         LDR        R0, [SP, #20]
+  0x341831BA:  68C0         LDR        R0, [R0, #12]
+  0x341831BC:  B120         CBZ        R0, .L17                 ; 0x341831C8
+  0x341831BE:  9902         LDR        R1, [SP, #8]
+  0x341831C0:  6808         LDR        R0, [R1]
+  0x341831C2:  F040 000A    ORR        R0, R0, #10
+  0x341831C6:  6008         STR        R0, [R1]
+
.L17:
+  0x341831C8:  9902         LDR        R1, [SP, #8]
+  0x341831CA:  6808         LDR        R0, [R1]
+  0x341831CC:  2201         MOVS       R2, #1
+  0x341831CE:  F2C4 0200    MOVT       R2, #0x4000
+  0x341831D2:  4310         ORRS       R0, R2
+  0x341831D4:  6008         STR        R0, [R1]
+  0x341831D6:  9906         LDR        R1, [SP, #24]
+  0x341831D8:  F44F 7080    MOV.W      R0, #0x0100
+  0x341831DC:  4088         LSLS       R0, R1
+  0x341831DE:  F648 0100    MOVW       R1, #0x8800
+  0x341831E2:  F2C5 6102    MOVT       R1, #0x5602
+  0x341831E6:  6008         STR        R0, [R1]
+  0x341831E8:  F7FD FC70    BL         HAL_GetTick              ; 0x34180ACC
+  0x341831EC:  9000         STR        R0, [SP, #0]
+
.L18:
+  0x341831EE:  F248 0004    MOVW       R0, #0x8004
+  0x341831F2:  F2C5 6002    MOVT       R0, #0x5602
+  0x341831F6:  6800         LDR        R0, [R0]
+  0x341831F8:  9906         LDR        R1, [SP, #24]
+  0x341831FA:  40C8         LSRS       R0, R1
+  0x341831FC:  05C0         LSLS       R0, R0, #23
+  0x341831FE:  2800         CMP        R0, #0
+  0x34183200:  D40A         BMI        46L20                     ; 0x34183218
+  0x34183202:  F7FD FC63    BL         HAL_GetTick              ; 0x34180ACC
+  0x34183206:  9900         LDR        R1, [SP, #0]
+  0x34183208:  1A40         SUBS       R0, R0, R1
+  0x3418320A:  2802         CMP        R0, #2
+  0x3418320C:  D303         BCC        46L19                     ; 0x34183216
+  0x3418320E:  2003         MOVS       R0, #3
+  0x34183210:  F88D 001F    STRB.W     R0, [SP, #31]
+  0x34183214:  E08D         B          46L35                     ; 0x34183332
+
.L19:
+  0x34183216:  E7EA         B          46L18                     ; 0x341831EE
+
.L20:
+  0x34183218:  E087         B          46L34                     ; 0x3418332A
+
.L21:
+  0x3418321A:  9805         LDR        R0, [SP, #20]
+  0x3418321C:  6800         LDR        R0, [R0]
+  0x3418321E:  2803         CMP        R0, #3
+  0x34183220:  D152         BNE        46L30                     ; 0x341832C8
+  0x34183222:  9805         LDR        R0, [SP, #20]
+  0x34183224:  6840         LDR        R0, [R0, #4]
+  0x34183226:  B170         CBZ        R0, .L22                 ; 0x34183246
+  0x34183228:  9805         LDR        R0, [SP, #20]
+  0x3418322A:  6840         LDR        R0, [R0, #4]
+  0x3418322C:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34183230:  D009         BEQ        46L22                     ; 0x34183246
+  0x34183232:  9805         LDR        R0, [SP, #20]
+  0x34183234:  6840         LDR        R0, [R0, #4]
+  0x34183236:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x3418323A:  D004         BEQ        46L22                     ; 0x34183246
+  0x3418323C:  9805         LDR        R0, [SP, #20]
+  0x3418323E:  6840         LDR        R0, [R0, #4]
+  0x34183240:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34183244:  D100         BNE        46L23                     ; 0x34183248
+
.L22:
+  0x34183246:  E007         B          46L24                     ; 0x34183258
+
.L23:
+  0x34183248:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x3418324C:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183250:  F640 019E    MOVW       R1, #0x089E
+  0x34183254:  F7FE FDF2    BL         assert_failed            ; 0x34181E3C
+
.L24:
+  0x34183258:  9805         LDR        R0, [SP, #20]
+  0x3418325A:  6840         LDR        R0, [R0, #4]
+  0x3418325C:  F7FE F960    BL         RCC_PLL_Source_IsReady   ; 0x34181520
+  0x34183260:  2801         CMP        R0, #1
+  0x34183262:  D12D         BNE        46L28                     ; 0x341832C0
+  0x34183264:  9906         LDR        R1, [SP, #24]
+  0x34183266:  F44F 7080    MOV.W      R0, #0x0100
+  0x3418326A:  4088         LSLS       R0, R1
+  0x3418326C:  F249 0100    MOVW       R1, #0x9000
+  0x34183270:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183274:  6008         STR        R0, [R1]
+  0x34183276:  F7FD FC29    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418327A:  9000         STR        R0, [SP, #0]
+
.L25:
+  0x3418327C:  F248 0004    MOVW       R0, #0x8004
+  0x34183280:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183284:  6800         LDR        R0, [R0]
+  0x34183286:  43C0         MVNS       R0, R0
+  0x34183288:  9906         LDR        R1, [SP, #24]
+  0x3418328A:  40C8         LSRS       R0, R1
+  0x3418328C:  05C0         LSLS       R0, R0, #23
+  0x3418328E:  2800         CMP        R0, #0
+  0x34183290:  D40A         BMI        46L27                     ; 0x341832A8
+  0x34183292:  F7FD FC1B    BL         HAL_GetTick              ; 0x34180ACC
+  0x34183296:  9900         LDR        R1, [SP, #0]
+  0x34183298:  1A40         SUBS       R0, R0, R1
+  0x3418329A:  2802         CMP        R0, #2
+  0x3418329C:  D303         BCC        46L26                     ; 0x341832A6
+  0x3418329E:  2003         MOVS       R0, #3
+  0x341832A0:  F88D 001F    STRB.W     R0, [SP, #31]
+  0x341832A4:  E045         B          46L35                     ; 0x34183332
+
.L26:
+  0x341832A6:  E7E9         B          46L25                     ; 0x3418327C
+
.L27:
+  0x341832A8:  9804         LDR        R0, [SP, #16]
+  0x341832AA:  6800         LDR        R0, [R0]
+  0x341832AC:  F020 41F0    BIC        R1, R0, #0x78000000
+  0x341832B0:  9805         LDR        R0, [SP, #20]
+  0x341832B2:  6840         LDR        R0, [R0, #4]
+  0x341832B4:  4308         ORRS       R0, R1
+  0x341832B6:  F040 6000    ORR        R0, R0, #0x08000000
+  0x341832BA:  9904         LDR        R1, [SP, #16]
+  0x341832BC:  6008         STR        R0, [R1]
+  0x341832BE:  E002         B          46L29                     ; 0x341832C6
+
.L28:
+  0x341832C0:  2001         MOVS       R0, #1
+  0x341832C2:  F88D 0007    STRB.W     R0, [SP, #7]
+
.L29:
+  0x341832C6:  E030         B          46L34                     ; 0x3418332A
+
.L30:
+  0x341832C8:  9805         LDR        R0, [SP, #20]
+  0x341832CA:  6800         LDR        R0, [R0]
+  0x341832CC:  2801         CMP        R0, #1
+  0x341832CE:  D12C         BNE        46L34                     ; 0x3418332A
+  0x341832D0:  9902         LDR        R1, [SP, #8]
+  0x341832D2:  6808         LDR        R0, [R1]
+  0x341832D4:  F020 4080    BIC        R0, R0, #0x40000000
+  0x341832D8:  6008         STR        R0, [R1]
+  0x341832DA:  9906         LDR        R1, [SP, #24]
+  0x341832DC:  F44F 7080    MOV.W      R0, #0x0100
+  0x341832E0:  4088         LSLS       R0, R1
+  0x341832E2:  F249 0100    MOVW       R1, #0x9000
+  0x341832E6:  F2C5 6102    MOVT       R1, #0x5602
+  0x341832EA:  6008         STR        R0, [R1]
+  0x341832EC:  F7FD FBEE    BL         HAL_GetTick              ; 0x34180ACC
+  0x341832F0:  9000         STR        R0, [SP, #0]
+
.L31:
+  0x341832F2:  F248 0004    MOVW       R0, #0x8004
+  0x341832F6:  F2C5 6002    MOVT       R0, #0x5602
+  0x341832FA:  6800         LDR        R0, [R0]
+  0x341832FC:  43C0         MVNS       R0, R0
+  0x341832FE:  9906         LDR        R1, [SP, #24]
+  0x34183300:  40C8         LSRS       R0, R1
+  0x34183302:  05C0         LSLS       R0, R0, #23
+  0x34183304:  2800         CMP        R0, #0
+  0x34183306:  D40A         BMI        46L33                     ; 0x3418331E
+  0x34183308:  F7FD FBE0    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418330C:  9900         LDR        R1, [SP, #0]
+  0x3418330E:  1A40         SUBS       R0, R0, R1
+  0x34183310:  2802         CMP        R0, #2
+  0x34183312:  D303         BCC        46L32                     ; 0x3418331C
+  0x34183314:  2003         MOVS       R0, #3
+  0x34183316:  F88D 001F    STRB.W     R0, [SP, #31]
+  0x3418331A:  E00A         B          46L35                     ; 0x34183332
+
.L32:
+  0x3418331C:  E7E9         B          46L31                     ; 0x341832F2
+
.L33:
+  0x3418331E:  9904         LDR        R1, [SP, #16]
+  0x34183320:  6808         LDR        R0, [R1]
+  0x34183322:  F020 6000    BIC        R0, R0, #0x08000000
+  0x34183326:  6008         STR        R0, [R1]
+  0x34183328:  E7FF         B          46L34                     ; 0x3418332A
+
.L34:
+  0x3418332A:  F89D 0007    LDRB.W     R0, [SP, #7]
+  0x3418332E:  F88D 001F    STRB.W     R0, [SP, #31]
+
.L35:
+  0x34183332:  F89D 001F    LDRB.W     R0, [SP, #31]
+  0x34183336:  B008         ADD        SP, SP, #32
+  0x34183338:  BD80         POP        123R7, PC}
+
+

Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
PKA_IRQHandler:
+  0x3418333A:  E7FE         B          PKA_IRQHandler           ; 0x3418333A
+
+

Section .text.RCC_PLL_Enable from blto2_FSBL_lto.o, size=94, align=4

+ +
+
RCC_PLL_Enable:
+  0x3418333C:  B580         PUSH       123R7, LR}
+  0x3418333E:  B084         SUB        SP, SP, #16
+  0x34183340:  9002         STR        R0, [SP, #8]
+  0x34183342:  2000         MOVS       R0, #0
+  0x34183344:  F88D 0007    STRB.W     R0, [SP, #7]
+  0x34183348:  9902         LDR        R1, [SP, #8]
+  0x3418334A:  F44F 7080    MOV.W      R0, #0x0100
+  0x3418334E:  4088         LSLS       R0, R1
+  0x34183350:  F648 0100    MOVW       R1, #0x8800
+  0x34183354:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183358:  6008         STR        R0, [R1]
+  0x3418335A:  F7FD FBB7    BL         HAL_GetTick              ; 0x34180ACC
+  0x3418335E:  9000         STR        R0, [SP, #0]
+
.L1:
+  0x34183360:  F248 0004    MOVW       R0, #0x8004
+  0x34183364:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183368:  6800         LDR        R0, [R0]
+  0x3418336A:  9902         LDR        R1, [SP, #8]
+  0x3418336C:  40C8         LSRS       R0, R1
+  0x3418336E:  05C0         LSLS       R0, R0, #23
+  0x34183370:  2800         CMP        R0, #0
+  0x34183372:  D40A         BMI        46L3                      ; 0x3418338A
+  0x34183374:  F7FD FBAA    BL         HAL_GetTick              ; 0x34180ACC
+  0x34183378:  9900         LDR        R1, [SP, #0]
+  0x3418337A:  1A40         SUBS       R0, R0, R1
+  0x3418337C:  2802         CMP        R0, #2
+  0x3418337E:  D303         BCC        46L2                      ; 0x34183388
+  0x34183380:  2003         MOVS       R0, #3
+  0x34183382:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x34183386:  E004         B          46L4                      ; 0x34183392
+
.L2:
+  0x34183388:  E7EA         B          46L1                      ; 0x34183360
+
.L3:
+  0x3418338A:  F89D 0007    LDRB.W     R0, [SP, #7]
+  0x3418338E:  F88D 000F    STRB.W     R0, [SP, #15]
+
.L4:
+  0x34183392:  F89D 000F    LDRB.W     R0, [SP, #15]
+  0x34183396:  B004         ADD        SP, SP, #16
+  0x34183398:  BD80         POP        123R7, PC}
+
+

Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HASH_IRQHandler:
+  0x3418339A:  E7FE         B          HASH_IRQHandler          ; 0x3418339A
+
+

Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=2498, align=4

+ +
+
HAL_RCC_ClockConfig:
+  0x3418339C:  B580         PUSH       123R7, LR}
+  0x3418339E:  B084         SUB        SP, SP, #16
+  0x341833A0:  9002         STR        R0, [SP, #8]
+  0x341833A2:  9802         LDR        R0, [SP, #8]
+  0x341833A4:  B920         CBNZ       R0, .L1                  ; 0x341833B0
+  0x341833A6:  2001         MOVS       R0, #1
+  0x341833A8:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341833AC:  F000 BCD3    B.W        46L93                     ; 0x34183D56
+
.L1:
+  0x341833B0:  9802         LDR        R0, [SP, #8]
+  0x341833B2:  6800         LDR        R0, [R0]
+  0x341833B4:  287F         CMP        R0, #127
+  0x341833B6:  D800         BHI        46L2                      ; 0x341833BA
+  0x341833B8:  E007         B          46L3                      ; 0x341833CA
+
.L2:
+  0x341833BA:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341833BE:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341833C2:  F240 3196    MOVW       R1, #0x0396
+  0x341833C6:  F7FE FD39    BL         assert_failed            ; 0x34181E3C
+
.L3:
+  0x341833CA:  9802         LDR        R0, [SP, #8]
+  0x341833CC:  7800         LDRB       R0, [R0]
+  0x341833CE:  0700         LSLS       R0, R0, #28
+  0x341833D0:  2800         CMP        R0, #0
+  0x341833D2:  D53D         BPL        46L7                      ; 0x34183450
+  0x341833D4:  9802         LDR        R0, [SP, #8]
+  0x341833D6:  6900         LDR        R0, [R0, #16]
+  0x341833D8:  B1D8         CBZ        R0, .L4                  ; 0x34183412
+  0x341833DA:  9802         LDR        R0, [SP, #8]
+  0x341833DC:  6900         LDR        R0, [R0, #16]
+  0x341833DE:  2801         CMP        R0, #1
+  0x341833E0:  D017         BEQ        46L4                      ; 0x34183412
+  0x341833E2:  9802         LDR        R0, [SP, #8]
+  0x341833E4:  6900         LDR        R0, [R0, #16]
+  0x341833E6:  2802         CMP        R0, #2
+  0x341833E8:  D013         BEQ        46L4                      ; 0x34183412
+  0x341833EA:  9802         LDR        R0, [SP, #8]
+  0x341833EC:  6900         LDR        R0, [R0, #16]
+  0x341833EE:  2803         CMP        R0, #3
+  0x341833F0:  D00F         BEQ        46L4                      ; 0x34183412
+  0x341833F2:  9802         LDR        R0, [SP, #8]
+  0x341833F4:  6900         LDR        R0, [R0, #16]
+  0x341833F6:  2804         CMP        R0, #4
+  0x341833F8:  D00B         BEQ        46L4                      ; 0x34183412
+  0x341833FA:  9802         LDR        R0, [SP, #8]
+  0x341833FC:  6900         LDR        R0, [R0, #16]
+  0x341833FE:  2805         CMP        R0, #5
+  0x34183400:  D007         BEQ        46L4                      ; 0x34183412
+  0x34183402:  9802         LDR        R0, [SP, #8]
+  0x34183404:  6900         LDR        R0, [R0, #16]
+  0x34183406:  2806         CMP        R0, #6
+  0x34183408:  D003         BEQ        46L4                      ; 0x34183412
+  0x3418340A:  9802         LDR        R0, [SP, #8]
+  0x3418340C:  6900         LDR        R0, [R0, #16]
+  0x3418340E:  2807         CMP        R0, #7
+  0x34183410:  D100         BNE        46L5                      ; 0x34183414
+
.L4:
+  0x34183412:  E007         B          46L6                      ; 0x34183424
+
.L5:
+  0x34183414:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183418:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418341C:  F240 319D    MOVW       R1, #0x039D
+  0x34183420:  F7FE FD0C    BL         assert_failed            ; 0x34181E3C
+
.L6:
+  0x34183424:  9802         LDR        R0, [SP, #8]
+  0x34183426:  6900         LDR        R0, [R0, #16]
+  0x34183428:  F248 0124    MOVW       R1, #0x8024
+  0x3418342C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183430:  6809         LDR        R1, [R1]
+  0x34183432:  F001 0107    AND        R1, R1, #7
+  0x34183436:  4288         CMP        R0, R1
+  0x34183438:  D90A         BLS        46L7                      ; 0x34183450
+  0x3418343A:  F248 0124    MOVW       R1, #0x8024
+  0x3418343E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183442:  6808         LDR        R0, [R1]
+  0x34183444:  F020 0007    BIC        R0, R0, #7
+  0x34183448:  9A02         LDR        R2, [SP, #8]
+  0x3418344A:  6912         LDR        R2, [R2, #16]
+  0x3418344C:  4310         ORRS       R0, R2
+  0x3418344E:  6008         STR        R0, [R1]
+
.L7:
+  0x34183450:  9802         LDR        R0, [SP, #8]
+  0x34183452:  7800         LDRB       R0, [R0]
+  0x34183454:  06C0         LSLS       R0, R0, #27
+  0x34183456:  2800         CMP        R0, #0
+  0x34183458:  D53D         BPL        46L11                     ; 0x341834D6
+  0x3418345A:  9802         LDR        R0, [SP, #8]
+  0x3418345C:  6940         LDR        R0, [R0, #20]
+  0x3418345E:  B1D8         CBZ        R0, .L8                  ; 0x34183498
+  0x34183460:  9802         LDR        R0, [SP, #8]
+  0x34183462:  6940         LDR        R0, [R0, #20]
+  0x34183464:  2810         CMP        R0, #16
+  0x34183466:  D017         BEQ        46L8                      ; 0x34183498
+  0x34183468:  9802         LDR        R0, [SP, #8]
+  0x3418346A:  6940         LDR        R0, [R0, #20]
+  0x3418346C:  2820         CMP        R0, #32
+  0x3418346E:  D013         BEQ        46L8                      ; 0x34183498
+  0x34183470:  9802         LDR        R0, [SP, #8]
+  0x34183472:  6940         LDR        R0, [R0, #20]
+  0x34183474:  2830         CMP        R0, #48
+  0x34183476:  D00F         BEQ        46L8                      ; 0x34183498
+  0x34183478:  9802         LDR        R0, [SP, #8]
+  0x3418347A:  6940         LDR        R0, [R0, #20]
+  0x3418347C:  2840         CMP        R0, #64
+  0x3418347E:  D00B         BEQ        46L8                      ; 0x34183498
+  0x34183480:  9802         LDR        R0, [SP, #8]
+  0x34183482:  6940         LDR        R0, [R0, #20]
+  0x34183484:  2850         CMP        R0, #80
+  0x34183486:  D007         BEQ        46L8                      ; 0x34183498
+  0x34183488:  9802         LDR        R0, [SP, #8]
+  0x3418348A:  6940         LDR        R0, [R0, #20]
+  0x3418348C:  2860         CMP        R0, #96
+  0x3418348E:  D003         BEQ        46L8                      ; 0x34183498
+  0x34183490:  9802         LDR        R0, [SP, #8]
+  0x34183492:  6940         LDR        R0, [R0, #20]
+  0x34183494:  2870         CMP        R0, #112
+  0x34183496:  D100         BNE        46L9                      ; 0x3418349A
+
.L8:
+  0x34183498:  E007         B          46L10                     ; 0x341834AA
+
.L9:
+  0x3418349A:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x3418349E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341834A2:  F240 31A7    MOVW       R1, #0x03A7
+  0x341834A6:  F7FE FCC9    BL         assert_failed            ; 0x34181E3C
+
.L10:
+  0x341834AA:  9802         LDR        R0, [SP, #8]
+  0x341834AC:  6940         LDR        R0, [R0, #20]
+  0x341834AE:  F248 0124    MOVW       R1, #0x8024
+  0x341834B2:  F2C5 6102    MOVT       R1, #0x5602
+  0x341834B6:  6809         LDR        R1, [R1]
+  0x341834B8:  F001 0170    AND        R1, R1, #112
+  0x341834BC:  4288         CMP        R0, R1
+  0x341834BE:  D90A         BLS        46L11                     ; 0x341834D6
+  0x341834C0:  F248 0124    MOVW       R1, #0x8024
+  0x341834C4:  F2C5 6102    MOVT       R1, #0x5602
+  0x341834C8:  6808         LDR        R0, [R1]
+  0x341834CA:  F020 0070    BIC        R0, R0, #112
+  0x341834CE:  9A02         LDR        R2, [SP, #8]
+  0x341834D0:  6952         LDR        R2, [R2, #20]
+  0x341834D2:  4310         ORRS       R0, R2
+  0x341834D4:  6008         STR        R0, [R1]
+
.L11:
+  0x341834D6:  9802         LDR        R0, [SP, #8]
+  0x341834D8:  7800         LDRB       R0, [R0]
+  0x341834DA:  0680         LSLS       R0, R0, #26
+  0x341834DC:  2800         CMP        R0, #0
+  0x341834DE:  D544         BPL        46L15                     ; 0x3418356A
+  0x341834E0:  9802         LDR        R0, [SP, #8]
+  0x341834E2:  6980         LDR        R0, [R0, #24]
+  0x341834E4:  B310         CBZ        R0, .L12                 ; 0x3418352C
+  0x341834E6:  9802         LDR        R0, [SP, #8]
+  0x341834E8:  6980         LDR        R0, [R0, #24]
+  0x341834EA:  F5B0 5F80    CMP.W      R0, #0x1000
+  0x341834EE:  D01D         BEQ        46L12                     ; 0x3418352C
+  0x341834F0:  9802         LDR        R0, [SP, #8]
+  0x341834F2:  6980         LDR        R0, [R0, #24]
+  0x341834F4:  F5B0 5F00    CMP.W      R0, #0x2000
+  0x341834F8:  D018         BEQ        46L12                     ; 0x3418352C
+  0x341834FA:  9802         LDR        R0, [SP, #8]
+  0x341834FC:  6980         LDR        R0, [R0, #24]
+  0x341834FE:  F5B0 5F40    CMP.W      R0, #0x3000
+  0x34183502:  D013         BEQ        46L12                     ; 0x3418352C
+  0x34183504:  9802         LDR        R0, [SP, #8]
+  0x34183506:  6980         LDR        R0, [R0, #24]
+  0x34183508:  F5B0 4F80    CMP.W      R0, #0x4000
+  0x3418350C:  D00E         BEQ        46L12                     ; 0x3418352C
+  0x3418350E:  9802         LDR        R0, [SP, #8]
+  0x34183510:  6980         LDR        R0, [R0, #24]
+  0x34183512:  F5B0 4FA0    CMP.W      R0, #0x5000
+  0x34183516:  D009         BEQ        46L12                     ; 0x3418352C
+  0x34183518:  9802         LDR        R0, [SP, #8]
+  0x3418351A:  6980         LDR        R0, [R0, #24]
+  0x3418351C:  F5B0 4FC0    CMP.W      R0, #0x6000
+  0x34183520:  D004         BEQ        46L12                     ; 0x3418352C
+  0x34183522:  9802         LDR        R0, [SP, #8]
+  0x34183524:  6980         LDR        R0, [R0, #24]
+  0x34183526:  F5B0 4FE0    CMP.W      R0, #0x7000
+  0x3418352A:  D100         BNE        46L13                     ; 0x3418352E
+
.L12:
+  0x3418352C:  E007         B          46L14                     ; 0x3418353E
+
.L13:
+  0x3418352E:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183532:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183536:  F240 31B1    MOVW       R1, #0x03B1
+  0x3418353A:  F7FE FC7F    BL         assert_failed            ; 0x34181E3C
+
.L14:
+  0x3418353E:  9802         LDR        R0, [SP, #8]
+  0x34183540:  6980         LDR        R0, [R0, #24]
+  0x34183542:  F248 0124    MOVW       R1, #0x8024
+  0x34183546:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418354A:  6809         LDR        R1, [R1]
+  0x3418354C:  F401 41E0    AND        R1, R1, #0x7000
+  0x34183550:  4288         CMP        R0, R1
+  0x34183552:  D90A         BLS        46L15                     ; 0x3418356A
+  0x34183554:  F248 0124    MOVW       R1, #0x8024
+  0x34183558:  F2C5 6102    MOVT       R1, #0x5602
+  0x3418355C:  6808         LDR        R0, [R1]
+  0x3418355E:  F420 40E0    BIC        R0, R0, #0x7000
+  0x34183562:  9A02         LDR        R2, [SP, #8]
+  0x34183564:  6992         LDR        R2, [R2, #24]
+  0x34183566:  4310         ORRS       R0, R2
+  0x34183568:  6008         STR        R0, [R1]
+
.L15:
+  0x3418356A:  9802         LDR        R0, [SP, #8]
+  0x3418356C:  7800         LDRB       R0, [R0]
+  0x3418356E:  0640         LSLS       R0, R0, #25
+  0x34183570:  2800         CMP        R0, #0
+  0x34183572:  D544         BPL        46L19                     ; 0x341835FE
+  0x34183574:  9802         LDR        R0, [SP, #8]
+  0x34183576:  69C0         LDR        R0, [R0, #28]
+  0x34183578:  B310         CBZ        R0, .L16                 ; 0x341835C0
+  0x3418357A:  9802         LDR        R0, [SP, #8]
+  0x3418357C:  69C0         LDR        R0, [R0, #28]
+  0x3418357E:  F5B0 3F80    CMP.W      R0, #0x010000
+  0x34183582:  D01D         BEQ        46L16                     ; 0x341835C0
+  0x34183584:  9802         LDR        R0, [SP, #8]
+  0x34183586:  69C0         LDR        R0, [R0, #28]
+  0x34183588:  F5B0 3F00    CMP.W      R0, #0x020000
+  0x3418358C:  D018         BEQ        46L16                     ; 0x341835C0
+  0x3418358E:  9802         LDR        R0, [SP, #8]
+  0x34183590:  69C0         LDR        R0, [R0, #28]
+  0x34183592:  F5B0 3F40    CMP.W      R0, #0x030000
+  0x34183596:  D013         BEQ        46L16                     ; 0x341835C0
+  0x34183598:  9802         LDR        R0, [SP, #8]
+  0x3418359A:  69C0         LDR        R0, [R0, #28]
+  0x3418359C:  F5B0 2F80    CMP.W      R0, #0x040000
+  0x341835A0:  D00E         BEQ        46L16                     ; 0x341835C0
+  0x341835A2:  9802         LDR        R0, [SP, #8]
+  0x341835A4:  69C0         LDR        R0, [R0, #28]
+  0x341835A6:  F5B0 2FA0    CMP.W      R0, #0x050000
+  0x341835AA:  D009         BEQ        46L16                     ; 0x341835C0
+  0x341835AC:  9802         LDR        R0, [SP, #8]
+  0x341835AE:  69C0         LDR        R0, [R0, #28]
+  0x341835B0:  F5B0 2FC0    CMP.W      R0, #0x060000
+  0x341835B4:  D004         BEQ        46L16                     ; 0x341835C0
+  0x341835B6:  9802         LDR        R0, [SP, #8]
+  0x341835B8:  69C0         LDR        R0, [R0, #28]
+  0x341835BA:  F5B0 2FE0    CMP.W      R0, #0x070000
+  0x341835BE:  D100         BNE        46L17                     ; 0x341835C2
+
.L16:
+  0x341835C0:  E007         B          46L18                     ; 0x341835D2
+
.L17:
+  0x341835C2:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341835C6:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341835CA:  F240 31BB    MOVW       R1, #0x03BB
+  0x341835CE:  F7FE FC35    BL         assert_failed            ; 0x34181E3C
+
.L18:
+  0x341835D2:  9802         LDR        R0, [SP, #8]
+  0x341835D4:  69C0         LDR        R0, [R0, #28]
+  0x341835D6:  F248 0124    MOVW       R1, #0x8024
+  0x341835DA:  F2C5 6102    MOVT       R1, #0x5602
+  0x341835DE:  6809         LDR        R1, [R1]
+  0x341835E0:  F401 21E0    AND        R1, R1, #0x070000
+  0x341835E4:  4288         CMP        R0, R1
+  0x341835E6:  D90A         BLS        46L19                     ; 0x341835FE
+  0x341835E8:  F248 0124    MOVW       R1, #0x8024
+  0x341835EC:  F2C5 6102    MOVT       R1, #0x5602
+  0x341835F0:  6808         LDR        R0, [R1]
+  0x341835F2:  F420 20E0    BIC        R0, R0, #0x070000
+  0x341835F6:  9A02         LDR        R2, [SP, #8]
+  0x341835F8:  69D2         LDR        R2, [R2, #28]
+  0x341835FA:  4310         ORRS       R0, R2
+  0x341835FC:  6008         STR        R0, [R1]
+
.L19:
+  0x341835FE:  9802         LDR        R0, [SP, #8]
+  0x34183600:  7800         LDRB       R0, [R0]
+  0x34183602:  0740         LSLS       R0, R0, #29
+  0x34183604:  2800         CMP        R0, #0
+  0x34183606:  D544         BPL        46L23                     ; 0x34183692
+  0x34183608:  9802         LDR        R0, [SP, #8]
+  0x3418360A:  68C0         LDR        R0, [R0, #12]
+  0x3418360C:  B310         CBZ        R0, .L20                 ; 0x34183654
+  0x3418360E:  9802         LDR        R0, [SP, #8]
+  0x34183610:  68C0         LDR        R0, [R0, #12]
+  0x34183612:  F5B0 1F80    CMP.W      R0, #0x100000
+  0x34183616:  D01D         BEQ        46L20                     ; 0x34183654
+  0x34183618:  9802         LDR        R0, [SP, #8]
+  0x3418361A:  68C0         LDR        R0, [R0, #12]
+  0x3418361C:  F5B0 1F00    CMP.W      R0, #0x200000
+  0x34183620:  D018         BEQ        46L20                     ; 0x34183654
+  0x34183622:  9802         LDR        R0, [SP, #8]
+  0x34183624:  68C0         LDR        R0, [R0, #12]
+  0x34183626:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x3418362A:  D013         BEQ        46L20                     ; 0x34183654
+  0x3418362C:  9802         LDR        R0, [SP, #8]
+  0x3418362E:  68C0         LDR        R0, [R0, #12]
+  0x34183630:  F5B0 0F80    CMP.W      R0, #0x400000
+  0x34183634:  D00E         BEQ        46L20                     ; 0x34183654
+  0x34183636:  9802         LDR        R0, [SP, #8]
+  0x34183638:  68C0         LDR        R0, [R0, #12]
+  0x3418363A:  F5B0 0FA0    CMP.W      R0, #0x500000
+  0x3418363E:  D009         BEQ        46L20                     ; 0x34183654
+  0x34183640:  9802         LDR        R0, [SP, #8]
+  0x34183642:  68C0         LDR        R0, [R0, #12]
+  0x34183644:  F5B0 0FC0    CMP.W      R0, #0x600000
+  0x34183648:  D004         BEQ        46L20                     ; 0x34183654
+  0x3418364A:  9802         LDR        R0, [SP, #8]
+  0x3418364C:  68C0         LDR        R0, [R0, #12]
+  0x3418364E:  F5B0 0FE0    CMP.W      R0, #0x700000
+  0x34183652:  D100         BNE        46L21                     ; 0x34183656
+
.L20:
+  0x34183654:  E007         B          46L22                     ; 0x34183666
+
.L21:
+  0x34183656:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x3418365A:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418365E:  F240 31C5    MOVW       R1, #0x03C5
+  0x34183662:  F7FE FBEB    BL         assert_failed            ; 0x34181E3C
+
.L22:
+  0x34183666:  9802         LDR        R0, [SP, #8]
+  0x34183668:  68C0         LDR        R0, [R0, #12]
+  0x3418366A:  F248 0124    MOVW       R1, #0x8024
+  0x3418366E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183672:  6809         LDR        R1, [R1]
+  0x34183674:  F401 01E0    AND        R1, R1, #0x700000
+  0x34183678:  4288         CMP        R0, R1
+  0x3418367A:  D90A         BLS        46L23                     ; 0x34183692
+  0x3418367C:  F248 0124    MOVW       R1, #0x8024
+  0x34183680:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183684:  6808         LDR        R0, [R1]
+  0x34183686:  F420 00E0    BIC        R0, R0, #0x700000
+  0x3418368A:  9A02         LDR        R2, [SP, #8]
+  0x3418368C:  68D2         LDR        R2, [R2, #12]
+  0x3418368E:  4310         ORRS       R0, R2
+  0x34183690:  6008         STR        R0, [R1]
+
.L23:
+  0x34183692:  9802         LDR        R0, [SP, #8]
+  0x34183694:  7800         LDRB       R0, [R0]
+  0x34183696:  07C0         LSLS       R0, R0, #31
+  0x34183698:  2800         CMP        R0, #0
+  0x3418369A:  F000 80B3    BEQ.W      46L42                     ; 0x34183804
+  0x3418369E:  9802         LDR        R0, [SP, #8]
+  0x341836A0:  6840         LDR        R0, [R0, #4]
+  0x341836A2:  B170         CBZ        R0, .L24                 ; 0x341836C2
+  0x341836A4:  9802         LDR        R0, [SP, #8]
+  0x341836A6:  6840         LDR        R0, [R0, #4]
+  0x341836A8:  F5B0 3F80    CMP.W      R0, #0x010000
+  0x341836AC:  D009         BEQ        46L24                     ; 0x341836C2
+  0x341836AE:  9802         LDR        R0, [SP, #8]
+  0x341836B0:  6840         LDR        R0, [R0, #4]
+  0x341836B2:  F5B0 3F00    CMP.W      R0, #0x020000
+  0x341836B6:  D004         BEQ        46L24                     ; 0x341836C2
+  0x341836B8:  9802         LDR        R0, [SP, #8]
+  0x341836BA:  6840         LDR        R0, [R0, #4]
+  0x341836BC:  F5B0 3F40    CMP.W      R0, #0x030000
+  0x341836C0:  D100         BNE        46L25                     ; 0x341836C4
+
.L24:
+  0x341836C2:  E007         B          46L26                     ; 0x341836D4
+
.L25:
+  0x341836C4:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341836C8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341836CC:  F44F 7174    MOV.W      R1, #0x03D0
+  0x341836D0:  F7FE FBB4    BL         assert_failed            ; 0x34181E3C
+
.L26:
+  0x341836D4:  9802         LDR        R0, [SP, #8]
+  0x341836D6:  6840         LDR        R0, [R0, #4]
+  0x341836D8:  F5B0 3F00    CMP.W      R0, #0x020000
+  0x341836DC:  D107         BNE        46L28                     ; 0x341836EE
+  0x341836DE:  F7FD FF49    BL         LL_RCC_HSE_IsReady       ; 0x34181574
+  0x341836E2:  B918         CBNZ       R0, .L27                 ; 0x341836EC
+  0x341836E4:  2001         MOVS       R0, #1
+  0x341836E6:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341836EA:  E334         B          46L93                     ; 0x34183D56
+
.L27:
+  0x341836EC:  E061         B          46L38                     ; 0x341837B2
+
.L28:
+  0x341836EE:  9802         LDR        R0, [SP, #8]
+  0x341836F0:  6840         LDR        R0, [R0, #4]
+  0x341836F2:  F5B0 3F40    CMP.W      R0, #0x030000
+  0x341836F6:  D148         BNE        46L35                     ; 0x3418378A
+  0x341836F8:  9802         LDR        R0, [SP, #8]
+  0x341836FA:  6A00         LDR        R0, [R0, #32]
+  0x341836FC:  B170         CBZ        R0, .L29                 ; 0x3418371C
+  0x341836FE:  9802         LDR        R0, [SP, #8]
+  0x34183700:  6A00         LDR        R0, [R0, #32]
+  0x34183702:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34183706:  D009         BEQ        46L29                     ; 0x3418371C
+  0x34183708:  9802         LDR        R0, [SP, #8]
+  0x3418370A:  6A00         LDR        R0, [R0, #32]
+  0x3418370C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34183710:  D004         BEQ        46L29                     ; 0x3418371C
+  0x34183712:  9802         LDR        R0, [SP, #8]
+  0x34183714:  6A00         LDR        R0, [R0, #32]
+  0x34183716:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x3418371A:  D100         BNE        46L30                     ; 0x3418371E
+
.L29:
+  0x3418371C:  E007         B          46L31                     ; 0x3418372E
+
.L30:
+  0x3418371E:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183722:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183726:  F240 31DF    MOVW       R1, #0x03DF
+  0x3418372A:  F7FE FB87    BL         assert_failed            ; 0x34181E3C
+
.L31:
+  0x3418372E:  9802         LDR        R0, [SP, #8]
+  0x34183730:  6A40         LDR        R0, [R0, #36]
+  0x34183732:  B128         CBZ        R0, .L32                 ; 0x34183740
+  0x34183734:  9802         LDR        R0, [SP, #8]
+  0x34183736:  6A40         LDR        R0, [R0, #36]
+  0x34183738:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x3418373C:  D800         BHI        46L32                     ; 0x34183740
+  0x3418373E:  E007         B          46L33                     ; 0x34183750
+
.L32:
+  0x34183740:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183744:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183748:  F44F 7178    MOV.W      R1, #0x03E0
+  0x3418374C:  F7FE FB76    BL         assert_failed            ; 0x34181E3C
+
.L33:
+  0x34183750:  F7FD FEAE    BL         LL_RCC_IC1_GetSource     ; 0x341814B0
+  0x34183754:  9902         LDR        R1, [SP, #8]
+  0x34183756:  6A09         LDR        R1, [R1, #32]
+  0x34183758:  F000 FB02    BL         RCC_IC_CheckPLLSources   ; 0x34183D60
+  0x3418375C:  2801         CMP        R0, #1
+  0x3418375E:  D003         BEQ        46L34                     ; 0x34183768
+  0x34183760:  2001         MOVS       R0, #1
+  0x34183762:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x34183766:  E2F6         B          46L93                     ; 0x34183D56
+
.L34:
+  0x34183768:  9902         LDR        R1, [SP, #8]
+  0x3418376A:  6A08         LDR        R0, [R1, #32]
+  0x3418376C:  6A4A         LDR        R2, [R1, #36]
+  0x3418376E:  2100         MOVS       R1, #0
+  0x34183770:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x34183774:  EB01 4102    ADD.W      R1, R1, R2, LSL #16
+  0x34183778:  4308         ORRS       R0, R1
+  0x3418377A:  F248 01C4    MOVW       R1, #0x80C4
+  0x3418377E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183782:  6008         STR        R0, [R1]
+  0x34183784:  F000 FB62    BL         LL_RCC_IC1_Enable        ; 0x34183E4C
+  0x34183788:  E013         B          46L38                     ; 0x341837B2
+
.L35:
+  0x3418378A:  9802         LDR        R0, [SP, #8]
+  0x3418378C:  6840         LDR        R0, [R0, #4]
+  0x3418378E:  F5B0 3F80    CMP.W      R0, #0x010000
+  0x34183792:  D107         BNE        46L37                     ; 0x341837A4
+  0x34183794:  F7FD FE6C    BL         LL_RCC_MSI_IsReady       ; 0x34181470
+  0x34183798:  B918         CBNZ       R0, .L36                 ; 0x341837A2
+  0x3418379A:  2001         MOVS       R0, #1
+  0x3418379C:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341837A0:  E2D9         B          46L93                     ; 0x34183D56
+
.L36:
+  0x341837A2:  E006         B          46L38                     ; 0x341837B2
+
.L37:
+  0x341837A4:  F7FD FE1E    BL         LL_RCC_HSI_IsReady       ; 0x341813E4
+  0x341837A8:  B918         CBNZ       R0, .L38                 ; 0x341837B2
+  0x341837AA:  2001         MOVS       R0, #1
+  0x341837AC:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341837B0:  E2D1         B          46L93                     ; 0x34183D56
+
.L38:
+  0x341837B2:  F248 0120    MOVW       R1, #0x8020
+  0x341837B6:  F2C5 6102    MOVT       R1, #0x5602
+  0x341837BA:  6808         LDR        R0, [R1]
+  0x341837BC:  F420 3040    BIC        R0, R0, #0x030000
+  0x341837C0:  9A02         LDR        R2, [SP, #8]
+  0x341837C2:  6852         LDR        R2, [R2, #4]
+  0x341837C4:  4310         ORRS       R0, R2
+  0x341837C6:  6008         STR        R0, [R1]
+  0x341837C8:  F7FD F980    BL         HAL_GetTick              ; 0x34180ACC
+  0x341837CC:  9001         STR        R0, [SP, #4]
+
.L39:
+  0x341837CE:  F7FD FE11    BL         LL_RCC_GetCpuClkSource   ; 0x341813F4
+  0x341837D2:  9902         LDR        R1, [SP, #8]
+  0x341837D4:  6849         LDR        R1, [R1, #4]
+  0x341837D6:  0109         LSLS       R1, R1, #4
+  0x341837D8:  4288         CMP        R0, R1
+  0x341837DA:  D00C         BEQ        46L41                     ; 0x341837F6
+  0x341837DC:  F7FD F976    BL         HAL_GetTick              ; 0x34180ACC
+  0x341837E0:  9901         LDR        R1, [SP, #4]
+  0x341837E2:  1A40         SUBS       R0, R0, R1
+  0x341837E4:  F241 3189    MOVW       R1, #0x1389
+  0x341837E8:  4288         CMP        R0, R1
+  0x341837EA:  D303         BCC        46L40                     ; 0x341837F4
+  0x341837EC:  2003         MOVS       R0, #3
+  0x341837EE:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341837F2:  E2B0         B          46L93                     ; 0x34183D56
+
.L40:
+  0x341837F4:  E7EB         B          46L39                     ; 0x341837CE
+
.L41:
+  0x341837F6:  F000 FB31    BL         HAL_RCC_GetCpuClockFreq  ; 0x34183E5C
+  0x341837FA:  F244 4148    MOVW       R1, #0x4448              ; 0x34184448 = SystemCoreClock
+  0x341837FE:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34184448 = SystemCoreClock
+  0x34183802:  6008         STR        R0, [R1]
+
.L42:
+  0x34183804:  9802         LDR        R0, [SP, #8]
+  0x34183806:  7800         LDRB       R0, [R0]
+  0x34183808:  0780         LSLS       R0, R0, #30
+  0x3418380A:  2800         CMP        R0, #0
+  0x3418380C:  F140 8136    BPL.W      46L72                     ; 0x34183A7C
+  0x34183810:  9802         LDR        R0, [SP, #8]
+  0x34183812:  6880         LDR        R0, [R0, #8]
+  0x34183814:  B170         CBZ        R0, .L43                 ; 0x34183834
+  0x34183816:  9802         LDR        R0, [SP, #8]
+  0x34183818:  6880         LDR        R0, [R0, #8]
+  0x3418381A:  F1B0 7F80    CMP.W      R0, #0x01000000
+  0x3418381E:  D009         BEQ        46L43                     ; 0x34183834
+  0x34183820:  9802         LDR        R0, [SP, #8]
+  0x34183822:  6880         LDR        R0, [R0, #8]
+  0x34183824:  F1B0 7F00    CMP.W      R0, #0x02000000
+  0x34183828:  D004         BEQ        46L43                     ; 0x34183834
+  0x3418382A:  9802         LDR        R0, [SP, #8]
+  0x3418382C:  6880         LDR        R0, [R0, #8]
+  0x3418382E:  F1B0 7F40    CMP.W      R0, #0x03000000
+  0x34183832:  D100         BNE        46L44                     ; 0x34183836
+
.L43:
+  0x34183834:  E007         B          46L45                     ; 0x34183846
+
.L44:
+  0x34183836:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x3418383A:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418383E:  F240 4119    MOVW       R1, #0x0419
+  0x34183842:  F7FE FAFB    BL         assert_failed            ; 0x34181E3C
+
.L45:
+  0x34183846:  9802         LDR        R0, [SP, #8]
+  0x34183848:  6880         LDR        R0, [R0, #8]
+  0x3418384A:  F1B0 7F00    CMP.W      R0, #0x02000000
+  0x3418384E:  D107         BNE        46L47                     ; 0x34183860
+  0x34183850:  F7FD FE90    BL         LL_RCC_HSE_IsReady       ; 0x34181574
+  0x34183854:  B918         CBNZ       R0, .L46                 ; 0x3418385E
+  0x34183856:  2001         MOVS       R0, #1
+  0x34183858:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x3418385C:  E27B         B          46L93                     ; 0x34183D56
+
.L46:
+  0x3418385E:  E0EB         B          46L69                     ; 0x34183A38
+
.L47:
+  0x34183860:  9802         LDR        R0, [SP, #8]
+  0x34183862:  6880         LDR        R0, [R0, #8]
+  0x34183864:  F1B0 7F40    CMP.W      R0, #0x03000000
+  0x34183868:  F040 80D4    BNE.W      46L66                     ; 0x34183A14
+  0x3418386C:  9802         LDR        R0, [SP, #8]
+  0x3418386E:  6A80         LDR        R0, [R0, #40]
+  0x34183870:  B170         CBZ        R0, .L48                 ; 0x34183890
+  0x34183872:  9802         LDR        R0, [SP, #8]
+  0x34183874:  6A80         LDR        R0, [R0, #40]
+  0x34183876:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x3418387A:  D009         BEQ        46L48                     ; 0x34183890
+  0x3418387C:  9802         LDR        R0, [SP, #8]
+  0x3418387E:  6A80         LDR        R0, [R0, #40]
+  0x34183880:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34183884:  D004         BEQ        46L48                     ; 0x34183890
+  0x34183886:  9802         LDR        R0, [SP, #8]
+  0x34183888:  6A80         LDR        R0, [R0, #40]
+  0x3418388A:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x3418388E:  D100         BNE        46L49                     ; 0x34183892
+
.L48:
+  0x34183890:  E007         B          46L50                     ; 0x341838A2
+
.L49:
+  0x34183892:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183896:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418389A:  F44F 6185    MOV.W      R1, #0x0428
+  0x3418389E:  F7FE FACD    BL         assert_failed            ; 0x34181E3C
+
.L50:
+  0x341838A2:  9802         LDR        R0, [SP, #8]
+  0x341838A4:  6AC0         LDR        R0, [R0, #44]
+  0x341838A6:  B128         CBZ        R0, .L51                 ; 0x341838B4
+  0x341838A8:  9802         LDR        R0, [SP, #8]
+  0x341838AA:  6AC0         LDR        R0, [R0, #44]
+  0x341838AC:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x341838B0:  D800         BHI        46L51                     ; 0x341838B4
+  0x341838B2:  E007         B          46L52                     ; 0x341838C4
+
.L51:
+  0x341838B4:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341838B8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341838BC:  F240 4129    MOVW       R1, #0x0429
+  0x341838C0:  F7FE FABC    BL         assert_failed            ; 0x34181E3C
+
.L52:
+  0x341838C4:  9802         LDR        R0, [SP, #8]
+  0x341838C6:  6B00         LDR        R0, [R0, #48]
+  0x341838C8:  B170         CBZ        R0, .L53                 ; 0x341838E8
+  0x341838CA:  9802         LDR        R0, [SP, #8]
+  0x341838CC:  6B00         LDR        R0, [R0, #48]
+  0x341838CE:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x341838D2:  D009         BEQ        46L53                     ; 0x341838E8
+  0x341838D4:  9802         LDR        R0, [SP, #8]
+  0x341838D6:  6B00         LDR        R0, [R0, #48]
+  0x341838D8:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x341838DC:  D004         BEQ        46L53                     ; 0x341838E8
+  0x341838DE:  9802         LDR        R0, [SP, #8]
+  0x341838E0:  6B00         LDR        R0, [R0, #48]
+  0x341838E2:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x341838E6:  D100         BNE        46L54                     ; 0x341838EA
+
.L53:
+  0x341838E8:  E007         B          46L55                     ; 0x341838FA
+
.L54:
+  0x341838EA:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x341838EE:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x341838F2:  F240 412A    MOVW       R1, #0x042A
+  0x341838F6:  F7FE FAA1    BL         assert_failed            ; 0x34181E3C
+
.L55:
+  0x341838FA:  9802         LDR        R0, [SP, #8]
+  0x341838FC:  6B40         LDR        R0, [R0, #52]
+  0x341838FE:  B128         CBZ        R0, .L56                 ; 0x3418390C
+  0x34183900:  9802         LDR        R0, [SP, #8]
+  0x34183902:  6B40         LDR        R0, [R0, #52]
+  0x34183904:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x34183908:  D800         BHI        46L56                     ; 0x3418390C
+  0x3418390A:  E007         B          46L57                     ; 0x3418391C
+
.L56:
+  0x3418390C:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183910:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183914:  F240 412B    MOVW       R1, #0x042B
+  0x34183918:  F7FE FA90    BL         assert_failed            ; 0x34181E3C
+
.L57:
+  0x3418391C:  9802         LDR        R0, [SP, #8]
+  0x3418391E:  6B80         LDR        R0, [R0, #56]
+  0x34183920:  B170         CBZ        R0, .L58                 ; 0x34183940
+  0x34183922:  9802         LDR        R0, [SP, #8]
+  0x34183924:  6B80         LDR        R0, [R0, #56]
+  0x34183926:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x3418392A:  D009         BEQ        46L58                     ; 0x34183940
+  0x3418392C:  9802         LDR        R0, [SP, #8]
+  0x3418392E:  6B80         LDR        R0, [R0, #56]
+  0x34183930:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34183934:  D004         BEQ        46L58                     ; 0x34183940
+  0x34183936:  9802         LDR        R0, [SP, #8]
+  0x34183938:  6B80         LDR        R0, [R0, #56]
+  0x3418393A:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x3418393E:  D100         BNE        46L59                     ; 0x34183942
+
.L58:
+  0x34183940:  E007         B          46L60                     ; 0x34183952
+
.L59:
+  0x34183942:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183946:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418394A:  F240 412C    MOVW       R1, #0x042C
+  0x3418394E:  F7FE FA75    BL         assert_failed            ; 0x34181E3C
+
.L60:
+  0x34183952:  9802         LDR        R0, [SP, #8]
+  0x34183954:  6BC0         LDR        R0, [R0, #60]
+  0x34183956:  B128         CBZ        R0, .L61                 ; 0x34183964
+  0x34183958:  9802         LDR        R0, [SP, #8]
+  0x3418395A:  6BC0         LDR        R0, [R0, #60]
+  0x3418395C:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x34183960:  D800         BHI        46L61                     ; 0x34183964
+  0x34183962:  E007         B          46L62                     ; 0x34183974
+
.L61:
+  0x34183964:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183968:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x3418396C:  F240 412D    MOVW       R1, #0x042D
+  0x34183970:  F7FE FA64    BL         assert_failed            ; 0x34181E3C
+
.L62:
+  0x34183974:  F7FD FDA4    BL         LL_RCC_IC2_GetSource     ; 0x341814C0
+  0x34183978:  9902         LDR        R1, [SP, #8]
+  0x3418397A:  6A89         LDR        R1, [R1, #40]
+  0x3418397C:  F000 F9F0    BL         RCC_IC_CheckPLLSources   ; 0x34183D60
+  0x34183980:  2801         CMP        R0, #1
+  0x34183982:  D003         BEQ        46L63                     ; 0x3418398C
+  0x34183984:  2001         MOVS       R0, #1
+  0x34183986:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x3418398A:  E1E4         B          46L93                     ; 0x34183D56
+
.L63:
+  0x3418398C:  F7FD FDA0    BL         LL_RCC_IC6_GetSource     ; 0x341814D0
+  0x34183990:  9902         LDR        R1, [SP, #8]
+  0x34183992:  6B09         LDR        R1, [R1, #48]
+  0x34183994:  F000 F9E4    BL         RCC_IC_CheckPLLSources   ; 0x34183D60
+  0x34183998:  2801         CMP        R0, #1
+  0x3418399A:  D003         BEQ        46L64                     ; 0x341839A4
+  0x3418399C:  2001         MOVS       R0, #1
+  0x3418399E:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341839A2:  E1D8         B          46L93                     ; 0x34183D56
+
.L64:
+  0x341839A4:  F7FD FD9C    BL         LL_RCC_IC11_GetSource    ; 0x341814E0
+  0x341839A8:  9902         LDR        R1, [SP, #8]
+  0x341839AA:  6B89         LDR        R1, [R1, #56]
+  0x341839AC:  F000 F9D8    BL         RCC_IC_CheckPLLSources   ; 0x34183D60
+  0x341839B0:  2801         CMP        R0, #1
+  0x341839B2:  D003         BEQ        46L65                     ; 0x341839BC
+  0x341839B4:  2001         MOVS       R0, #1
+  0x341839B6:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x341839BA:  E1CC         B          46L93                     ; 0x34183D56
+
.L65:
+  0x341839BC:  9902         LDR        R1, [SP, #8]
+  0x341839BE:  6A88         LDR        R0, [R1, #40]
+  0x341839C0:  6ACA         LDR        R2, [R1, #44]
+  0x341839C2:  2100         MOVS       R1, #0
+  0x341839C4:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x341839C8:  EB01 4202    ADD.W      R2, R1, R2, LSL #16
+  0x341839CC:  4310         ORRS       R0, R2
+  0x341839CE:  F248 02C8    MOVW       R2, #0x80C8
+  0x341839D2:  F2C5 6202    MOVT       R2, #0x5602
+  0x341839D6:  6010         STR        R0, [R2]
+  0x341839D8:  9A02         LDR        R2, [SP, #8]
+  0x341839DA:  6B10         LDR        R0, [R2, #48]
+  0x341839DC:  6B52         LDR        R2, [R2, #52]
+  0x341839DE:  EB01 4202    ADD.W      R2, R1, R2, LSL #16
+  0x341839E2:  4310         ORRS       R0, R2
+  0x341839E4:  F248 02D8    MOVW       R2, #0x80D8
+  0x341839E8:  F2C5 6202    MOVT       R2, #0x5602
+  0x341839EC:  6010         STR        R0, [R2]
+  0x341839EE:  9A02         LDR        R2, [SP, #8]
+  0x341839F0:  6B90         LDR        R0, [R2, #56]
+  0x341839F2:  6BD2         LDR        R2, [R2, #60]
+  0x341839F4:  EB01 4102    ADD.W      R1, R1, R2, LSL #16
+  0x341839F8:  4308         ORRS       R0, R1
+  0x341839FA:  F248 01EC    MOVW       R1, #0x80EC
+  0x341839FE:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183A02:  6008         STR        R0, [R1]
+  0x34183A04:  F648 2140    MOVW       R1, #0x8A40
+  0x34183A08:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183A0C:  F240 4022    MOVW       R0, #0x0422
+  0x34183A10:  6008         STR        R0, [R1]
+  0x34183A12:  E011         B          46L69                     ; 0x34183A38
+
.L66:
+  0x34183A14:  9802         LDR        R0, [SP, #8]
+  0x34183A16:  6880         LDR        R0, [R0, #8]
+  0x34183A18:  B938         CBNZ       R0, .L68                 ; 0x34183A2A
+  0x34183A1A:  F7FD FCE3    BL         LL_RCC_HSI_IsReady       ; 0x341813E4
+  0x34183A1E:  B918         CBNZ       R0, .L67                 ; 0x34183A28
+  0x34183A20:  2001         MOVS       R0, #1
+  0x34183A22:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x34183A26:  E196         B          46L93                     ; 0x34183D56
+
.L67:
+  0x34183A28:  E006         B          46L69                     ; 0x34183A38
+
.L68:
+  0x34183A2A:  F7FD FD21    BL         LL_RCC_MSI_IsReady       ; 0x34181470
+  0x34183A2E:  B918         CBNZ       R0, .L69                 ; 0x34183A38
+  0x34183A30:  2001         MOVS       R0, #1
+  0x34183A32:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x34183A36:  E18E         B          46L93                     ; 0x34183D56
+
.L69:
+  0x34183A38:  F248 0120    MOVW       R1, #0x8020
+  0x34183A3C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183A40:  6808         LDR        R0, [R1]
+  0x34183A42:  F020 7040    BIC        R0, R0, #0x03000000
+  0x34183A46:  9A02         LDR        R2, [SP, #8]
+  0x34183A48:  6892         LDR        R2, [R2, #8]
+  0x34183A4A:  4310         ORRS       R0, R2
+  0x34183A4C:  6008         STR        R0, [R1]
+  0x34183A4E:  F7FD F83D    BL         HAL_GetTick              ; 0x34180ACC
+  0x34183A52:  9001         STR        R0, [SP, #4]
+
.L70:
+  0x34183A54:  F7FD FCD6    BL         LL_RCC_GetSysClkSource   ; 0x34181404
+  0x34183A58:  9902         LDR        R1, [SP, #8]
+  0x34183A5A:  6889         LDR        R1, [R1, #8]
+  0x34183A5C:  0109         LSLS       R1, R1, #4
+  0x34183A5E:  4288         CMP        R0, R1
+  0x34183A60:  D00C         BEQ        46L72                     ; 0x34183A7C
+  0x34183A62:  F7FD F833    BL         HAL_GetTick              ; 0x34180ACC
+  0x34183A66:  9901         LDR        R1, [SP, #4]
+  0x34183A68:  1A40         SUBS       R0, R0, R1
+  0x34183A6A:  F241 3189    MOVW       R1, #0x1389
+  0x34183A6E:  4288         CMP        R0, R1
+  0x34183A70:  D303         BCC        46L71                     ; 0x34183A7A
+  0x34183A72:  2003         MOVS       R0, #3
+  0x34183A74:  F88D 000F    STRB.W     R0, [SP, #15]
+  0x34183A78:  E16D         B          46L93                     ; 0x34183D56
+
.L71:
+  0x34183A7A:  E7EB         B          46L70                     ; 0x34183A54
+
.L72:
+  0x34183A7C:  9802         LDR        R0, [SP, #8]
+  0x34183A7E:  7800         LDRB       R0, [R0]
+  0x34183A80:  0740         LSLS       R0, R0, #29
+  0x34183A82:  2800         CMP        R0, #0
+  0x34183A84:  D544         BPL        46L76                     ; 0x34183B10
+  0x34183A86:  9802         LDR        R0, [SP, #8]
+  0x34183A88:  68C0         LDR        R0, [R0, #12]
+  0x34183A8A:  B310         CBZ        R0, .L73                 ; 0x34183AD2
+  0x34183A8C:  9802         LDR        R0, [SP, #8]
+  0x34183A8E:  68C0         LDR        R0, [R0, #12]
+  0x34183A90:  F5B0 1F80    CMP.W      R0, #0x100000
+  0x34183A94:  D01D         BEQ        46L73                     ; 0x34183AD2
+  0x34183A96:  9802         LDR        R0, [SP, #8]
+  0x34183A98:  68C0         LDR        R0, [R0, #12]
+  0x34183A9A:  F5B0 1F00    CMP.W      R0, #0x200000
+  0x34183A9E:  D018         BEQ        46L73                     ; 0x34183AD2
+  0x34183AA0:  9802         LDR        R0, [SP, #8]
+  0x34183AA2:  68C0         LDR        R0, [R0, #12]
+  0x34183AA4:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x34183AA8:  D013         BEQ        46L73                     ; 0x34183AD2
+  0x34183AAA:  9802         LDR        R0, [SP, #8]
+  0x34183AAC:  68C0         LDR        R0, [R0, #12]
+  0x34183AAE:  F5B0 0F80    CMP.W      R0, #0x400000
+  0x34183AB2:  D00E         BEQ        46L73                     ; 0x34183AD2
+  0x34183AB4:  9802         LDR        R0, [SP, #8]
+  0x34183AB6:  68C0         LDR        R0, [R0, #12]
+  0x34183AB8:  F5B0 0FA0    CMP.W      R0, #0x500000
+  0x34183ABC:  D009         BEQ        46L73                     ; 0x34183AD2
+  0x34183ABE:  9802         LDR        R0, [SP, #8]
+  0x34183AC0:  68C0         LDR        R0, [R0, #12]
+  0x34183AC2:  F5B0 0FC0    CMP.W      R0, #0x600000
+  0x34183AC6:  D004         BEQ        46L73                     ; 0x34183AD2
+  0x34183AC8:  9802         LDR        R0, [SP, #8]
+  0x34183ACA:  68C0         LDR        R0, [R0, #12]
+  0x34183ACC:  F5B0 0FE0    CMP.W      R0, #0x700000
+  0x34183AD0:  D100         BNE        46L74                     ; 0x34183AD4
+
.L73:
+  0x34183AD2:  E007         B          46L75                     ; 0x34183AE4
+
.L74:
+  0x34183AD4:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183AD8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183ADC:  F44F 618E    MOV.W      R1, #0x0470
+  0x34183AE0:  F7FE F9AC    BL         assert_failed            ; 0x34181E3C
+
.L75:
+  0x34183AE4:  9802         LDR        R0, [SP, #8]
+  0x34183AE6:  68C0         LDR        R0, [R0, #12]
+  0x34183AE8:  F248 0124    MOVW       R1, #0x8024
+  0x34183AEC:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183AF0:  6809         LDR        R1, [R1]
+  0x34183AF2:  F401 01E0    AND        R1, R1, #0x700000
+  0x34183AF6:  4288         CMP        R0, R1
+  0x34183AF8:  D20A         BCS        46L76                     ; 0x34183B10
+  0x34183AFA:  F248 0124    MOVW       R1, #0x8024
+  0x34183AFE:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183B02:  6808         LDR        R0, [R1]
+  0x34183B04:  F420 00E0    BIC        R0, R0, #0x700000
+  0x34183B08:  9A02         LDR        R2, [SP, #8]
+  0x34183B0A:  68D2         LDR        R2, [R2, #12]
+  0x34183B0C:  4310         ORRS       R0, R2
+  0x34183B0E:  6008         STR        R0, [R1]
+
.L76:
+  0x34183B10:  9802         LDR        R0, [SP, #8]
+  0x34183B12:  7800         LDRB       R0, [R0]
+  0x34183B14:  0700         LSLS       R0, R0, #28
+  0x34183B16:  2800         CMP        R0, #0
+  0x34183B18:  D53D         BPL        46L80                     ; 0x34183B96
+  0x34183B1A:  9802         LDR        R0, [SP, #8]
+  0x34183B1C:  6900         LDR        R0, [R0, #16]
+  0x34183B1E:  B1D8         CBZ        R0, .L77                 ; 0x34183B58
+  0x34183B20:  9802         LDR        R0, [SP, #8]
+  0x34183B22:  6900         LDR        R0, [R0, #16]
+  0x34183B24:  2801         CMP        R0, #1
+  0x34183B26:  D017         BEQ        46L77                     ; 0x34183B58
+  0x34183B28:  9802         LDR        R0, [SP, #8]
+  0x34183B2A:  6900         LDR        R0, [R0, #16]
+  0x34183B2C:  2802         CMP        R0, #2
+  0x34183B2E:  D013         BEQ        46L77                     ; 0x34183B58
+  0x34183B30:  9802         LDR        R0, [SP, #8]
+  0x34183B32:  6900         LDR        R0, [R0, #16]
+  0x34183B34:  2803         CMP        R0, #3
+  0x34183B36:  D00F         BEQ        46L77                     ; 0x34183B58
+  0x34183B38:  9802         LDR        R0, [SP, #8]
+  0x34183B3A:  6900         LDR        R0, [R0, #16]
+  0x34183B3C:  2804         CMP        R0, #4
+  0x34183B3E:  D00B         BEQ        46L77                     ; 0x34183B58
+  0x34183B40:  9802         LDR        R0, [SP, #8]
+  0x34183B42:  6900         LDR        R0, [R0, #16]
+  0x34183B44:  2805         CMP        R0, #5
+  0x34183B46:  D007         BEQ        46L77                     ; 0x34183B58
+  0x34183B48:  9802         LDR        R0, [SP, #8]
+  0x34183B4A:  6900         LDR        R0, [R0, #16]
+  0x34183B4C:  2806         CMP        R0, #6
+  0x34183B4E:  D003         BEQ        46L77                     ; 0x34183B58
+  0x34183B50:  9802         LDR        R0, [SP, #8]
+  0x34183B52:  6900         LDR        R0, [R0, #16]
+  0x34183B54:  2807         CMP        R0, #7
+  0x34183B56:  D100         BNE        46L78                     ; 0x34183B5A
+
.L77:
+  0x34183B58:  E007         B          46L79                     ; 0x34183B6A
+
.L78:
+  0x34183B5A:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183B5E:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183B62:  F240 417B    MOVW       R1, #0x047B
+  0x34183B66:  F7FE F969    BL         assert_failed            ; 0x34181E3C
+
.L79:
+  0x34183B6A:  9802         LDR        R0, [SP, #8]
+  0x34183B6C:  6900         LDR        R0, [R0, #16]
+  0x34183B6E:  F248 0124    MOVW       R1, #0x8024
+  0x34183B72:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183B76:  6809         LDR        R1, [R1]
+  0x34183B78:  F001 0107    AND        R1, R1, #7
+  0x34183B7C:  4288         CMP        R0, R1
+  0x34183B7E:  D20A         BCS        46L80                     ; 0x34183B96
+  0x34183B80:  F248 0124    MOVW       R1, #0x8024
+  0x34183B84:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183B88:  6808         LDR        R0, [R1]
+  0x34183B8A:  F020 0007    BIC        R0, R0, #7
+  0x34183B8E:  9A02         LDR        R2, [SP, #8]
+  0x34183B90:  6912         LDR        R2, [R2, #16]
+  0x34183B92:  4310         ORRS       R0, R2
+  0x34183B94:  6008         STR        R0, [R1]
+
.L80:
+  0x34183B96:  9802         LDR        R0, [SP, #8]
+  0x34183B98:  7800         LDRB       R0, [R0]
+  0x34183B9A:  06C0         LSLS       R0, R0, #27
+  0x34183B9C:  2800         CMP        R0, #0
+  0x34183B9E:  D53D         BPL        46L84                     ; 0x34183C1C
+  0x34183BA0:  9802         LDR        R0, [SP, #8]
+  0x34183BA2:  6940         LDR        R0, [R0, #20]
+  0x34183BA4:  B1D8         CBZ        R0, .L81                 ; 0x34183BDE
+  0x34183BA6:  9802         LDR        R0, [SP, #8]
+  0x34183BA8:  6940         LDR        R0, [R0, #20]
+  0x34183BAA:  2810         CMP        R0, #16
+  0x34183BAC:  D017         BEQ        46L81                     ; 0x34183BDE
+  0x34183BAE:  9802         LDR        R0, [SP, #8]
+  0x34183BB0:  6940         LDR        R0, [R0, #20]
+  0x34183BB2:  2820         CMP        R0, #32
+  0x34183BB4:  D013         BEQ        46L81                     ; 0x34183BDE
+  0x34183BB6:  9802         LDR        R0, [SP, #8]
+  0x34183BB8:  6940         LDR        R0, [R0, #20]
+  0x34183BBA:  2830         CMP        R0, #48
+  0x34183BBC:  D00F         BEQ        46L81                     ; 0x34183BDE
+  0x34183BBE:  9802         LDR        R0, [SP, #8]
+  0x34183BC0:  6940         LDR        R0, [R0, #20]
+  0x34183BC2:  2840         CMP        R0, #64
+  0x34183BC4:  D00B         BEQ        46L81                     ; 0x34183BDE
+  0x34183BC6:  9802         LDR        R0, [SP, #8]
+  0x34183BC8:  6940         LDR        R0, [R0, #20]
+  0x34183BCA:  2850         CMP        R0, #80
+  0x34183BCC:  D007         BEQ        46L81                     ; 0x34183BDE
+  0x34183BCE:  9802         LDR        R0, [SP, #8]
+  0x34183BD0:  6940         LDR        R0, [R0, #20]
+  0x34183BD2:  2860         CMP        R0, #96
+  0x34183BD4:  D003         BEQ        46L81                     ; 0x34183BDE
+  0x34183BD6:  9802         LDR        R0, [SP, #8]
+  0x34183BD8:  6940         LDR        R0, [R0, #20]
+  0x34183BDA:  2870         CMP        R0, #112
+  0x34183BDC:  D100         BNE        46L82                     ; 0x34183BE0
+
.L81:
+  0x34183BDE:  E007         B          46L83                     ; 0x34183BF0
+
.L82:
+  0x34183BE0:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183BE4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183BE8:  F240 4185    MOVW       R1, #0x0485
+  0x34183BEC:  F7FE F926    BL         assert_failed            ; 0x34181E3C
+
.L83:
+  0x34183BF0:  9802         LDR        R0, [SP, #8]
+  0x34183BF2:  6940         LDR        R0, [R0, #20]
+  0x34183BF4:  F248 0124    MOVW       R1, #0x8024
+  0x34183BF8:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183BFC:  6809         LDR        R1, [R1]
+  0x34183BFE:  F001 0170    AND        R1, R1, #112
+  0x34183C02:  4288         CMP        R0, R1
+  0x34183C04:  D20A         BCS        46L84                     ; 0x34183C1C
+  0x34183C06:  F248 0124    MOVW       R1, #0x8024
+  0x34183C0A:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183C0E:  6808         LDR        R0, [R1]
+  0x34183C10:  F020 0070    BIC        R0, R0, #112
+  0x34183C14:  9A02         LDR        R2, [SP, #8]
+  0x34183C16:  6952         LDR        R2, [R2, #20]
+  0x34183C18:  4310         ORRS       R0, R2
+  0x34183C1A:  6008         STR        R0, [R1]
+
.L84:
+  0x34183C1C:  9802         LDR        R0, [SP, #8]
+  0x34183C1E:  7800         LDRB       R0, [R0]
+  0x34183C20:  0680         LSLS       R0, R0, #26
+  0x34183C22:  2800         CMP        R0, #0
+  0x34183C24:  D544         BPL        46L88                     ; 0x34183CB0
+  0x34183C26:  9802         LDR        R0, [SP, #8]
+  0x34183C28:  6980         LDR        R0, [R0, #24]
+  0x34183C2A:  B310         CBZ        R0, .L85                 ; 0x34183C72
+  0x34183C2C:  9802         LDR        R0, [SP, #8]
+  0x34183C2E:  6980         LDR        R0, [R0, #24]
+  0x34183C30:  F5B0 5F80    CMP.W      R0, #0x1000
+  0x34183C34:  D01D         BEQ        46L85                     ; 0x34183C72
+  0x34183C36:  9802         LDR        R0, [SP, #8]
+  0x34183C38:  6980         LDR        R0, [R0, #24]
+  0x34183C3A:  F5B0 5F00    CMP.W      R0, #0x2000
+  0x34183C3E:  D018         BEQ        46L85                     ; 0x34183C72
+  0x34183C40:  9802         LDR        R0, [SP, #8]
+  0x34183C42:  6980         LDR        R0, [R0, #24]
+  0x34183C44:  F5B0 5F40    CMP.W      R0, #0x3000
+  0x34183C48:  D013         BEQ        46L85                     ; 0x34183C72
+  0x34183C4A:  9802         LDR        R0, [SP, #8]
+  0x34183C4C:  6980         LDR        R0, [R0, #24]
+  0x34183C4E:  F5B0 4F80    CMP.W      R0, #0x4000
+  0x34183C52:  D00E         BEQ        46L85                     ; 0x34183C72
+  0x34183C54:  9802         LDR        R0, [SP, #8]
+  0x34183C56:  6980         LDR        R0, [R0, #24]
+  0x34183C58:  F5B0 4FA0    CMP.W      R0, #0x5000
+  0x34183C5C:  D009         BEQ        46L85                     ; 0x34183C72
+  0x34183C5E:  9802         LDR        R0, [SP, #8]
+  0x34183C60:  6980         LDR        R0, [R0, #24]
+  0x34183C62:  F5B0 4FC0    CMP.W      R0, #0x6000
+  0x34183C66:  D004         BEQ        46L85                     ; 0x34183C72
+  0x34183C68:  9802         LDR        R0, [SP, #8]
+  0x34183C6A:  6980         LDR        R0, [R0, #24]
+  0x34183C6C:  F5B0 4FE0    CMP.W      R0, #0x7000
+  0x34183C70:  D100         BNE        46L86                     ; 0x34183C74
+
.L85:
+  0x34183C72:  E007         B          46L87                     ; 0x34183C84
+
.L86:
+  0x34183C74:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183C78:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183C7C:  F240 418F    MOVW       R1, #0x048F
+  0x34183C80:  F7FE F8DC    BL         assert_failed            ; 0x34181E3C
+
.L87:
+  0x34183C84:  9802         LDR        R0, [SP, #8]
+  0x34183C86:  6980         LDR        R0, [R0, #24]
+  0x34183C88:  F248 0124    MOVW       R1, #0x8024
+  0x34183C8C:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183C90:  6809         LDR        R1, [R1]
+  0x34183C92:  F401 41E0    AND        R1, R1, #0x7000
+  0x34183C96:  4288         CMP        R0, R1
+  0x34183C98:  D20A         BCS        46L88                     ; 0x34183CB0
+  0x34183C9A:  F248 0124    MOVW       R1, #0x8024
+  0x34183C9E:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183CA2:  6808         LDR        R0, [R1]
+  0x34183CA4:  F420 40E0    BIC        R0, R0, #0x7000
+  0x34183CA8:  9A02         LDR        R2, [SP, #8]
+  0x34183CAA:  6992         LDR        R2, [R2, #24]
+  0x34183CAC:  4310         ORRS       R0, R2
+  0x34183CAE:  6008         STR        R0, [R1]
+
.L88:
+  0x34183CB0:  9802         LDR        R0, [SP, #8]
+  0x34183CB2:  7800         LDRB       R0, [R0]
+  0x34183CB4:  0640         LSLS       R0, R0, #25
+  0x34183CB6:  2800         CMP        R0, #0
+  0x34183CB8:  D544         BPL        46L92                     ; 0x34183D44
+  0x34183CBA:  9802         LDR        R0, [SP, #8]
+  0x34183CBC:  69C0         LDR        R0, [R0, #28]
+  0x34183CBE:  B310         CBZ        R0, .L89                 ; 0x34183D06
+  0x34183CC0:  9802         LDR        R0, [SP, #8]
+  0x34183CC2:  69C0         LDR        R0, [R0, #28]
+  0x34183CC4:  F5B0 3F80    CMP.W      R0, #0x010000
+  0x34183CC8:  D01D         BEQ        46L89                     ; 0x34183D06
+  0x34183CCA:  9802         LDR        R0, [SP, #8]
+  0x34183CCC:  69C0         LDR        R0, [R0, #28]
+  0x34183CCE:  F5B0 3F00    CMP.W      R0, #0x020000
+  0x34183CD2:  D018         BEQ        46L89                     ; 0x34183D06
+  0x34183CD4:  9802         LDR        R0, [SP, #8]
+  0x34183CD6:  69C0         LDR        R0, [R0, #28]
+  0x34183CD8:  F5B0 3F40    CMP.W      R0, #0x030000
+  0x34183CDC:  D013         BEQ        46L89                     ; 0x34183D06
+  0x34183CDE:  9802         LDR        R0, [SP, #8]
+  0x34183CE0:  69C0         LDR        R0, [R0, #28]
+  0x34183CE2:  F5B0 2F80    CMP.W      R0, #0x040000
+  0x34183CE6:  D00E         BEQ        46L89                     ; 0x34183D06
+  0x34183CE8:  9802         LDR        R0, [SP, #8]
+  0x34183CEA:  69C0         LDR        R0, [R0, #28]
+  0x34183CEC:  F5B0 2FA0    CMP.W      R0, #0x050000
+  0x34183CF0:  D009         BEQ        46L89                     ; 0x34183D06
+  0x34183CF2:  9802         LDR        R0, [SP, #8]
+  0x34183CF4:  69C0         LDR        R0, [R0, #28]
+  0x34183CF6:  F5B0 2FC0    CMP.W      R0, #0x060000
+  0x34183CFA:  D004         BEQ        46L89                     ; 0x34183D06
+  0x34183CFC:  9802         LDR        R0, [SP, #8]
+  0x34183CFE:  69C0         LDR        R0, [R0, #28]
+  0x34183D00:  F5B0 2FE0    CMP.W      R0, #0x070000
+  0x34183D04:  D100         BNE        46L90                     ; 0x34183D08
+
.L89:
+  0x34183D06:  E007         B          46L91                     ; 0x34183D18
+
.L90:
+  0x34183D08:  F244 20F8    MOVW       R0, #0x42F8              ; 0x341842F8 = .rodata..L.str.35
+  0x34183D0C:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341842F8 = .rodata..L.str.35
+  0x34183D10:  F240 4199    MOVW       R1, #0x0499
+  0x34183D14:  F7FE F892    BL         assert_failed            ; 0x34181E3C
+
.L91:
+  0x34183D18:  9802         LDR        R0, [SP, #8]
+  0x34183D1A:  69C0         LDR        R0, [R0, #28]
+  0x34183D1C:  F248 0124    MOVW       R1, #0x8024
+  0x34183D20:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183D24:  6809         LDR        R1, [R1]
+  0x34183D26:  F401 21E0    AND        R1, R1, #0x070000
+  0x34183D2A:  4288         CMP        R0, R1
+  0x34183D2C:  D20A         BCS        46L92                     ; 0x34183D44
+  0x34183D2E:  F248 0124    MOVW       R1, #0x8024
+  0x34183D32:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183D36:  6808         LDR        R0, [R1]
+  0x34183D38:  F420 20E0    BIC        R0, R0, #0x070000
+  0x34183D3C:  9A02         LDR        R2, [SP, #8]
+  0x34183D3E:  69D2         LDR        R2, [R2, #28]
+  0x34183D40:  4310         ORRS       R0, R2
+  0x34183D42:  6008         STR        R0, [R1]
+
.L92:
+  0x34183D44:  F244 4044    MOVW       R0, #0x4444              ; 0x34184444 = uwTickPrio
+  0x34183D48:  F2C3 4018    MOVT       R0, #0x3418              ; 0x34184444 = uwTickPrio
+  0x34183D4C:  6800         LDR        R0, [R0]
+  0x34183D4E:  F7FE F98B    BL         HAL_InitTick             ; 0x34182068
+  0x34183D52:  F88D 000F    STRB.W     R0, [SP, #15]
+
.L93:
+  0x34183D56:  F89D 000F    LDRB.W     R0, [SP, #15]
+  0x34183D5A:  B004         ADD        SP, SP, #16
+  0x34183D5C:  BD80         POP        123R7, PC}
+
+

Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RNG_IRQHandler:
+  0x34183D5E:  E7FE         B          RNG_IRQHandler           ; 0x34183D5E
+
+

Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=234, align=4

+ +
+
RCC_IC_CheckPLLSources:
+  0x34183D60:  B580         PUSH       123R7, LR}
+  0x34183D62:  B086         SUB        SP, SP, #24
+  0x34183D64:  9005         STR        R0, [SP, #20]
+  0x34183D66:  9104         STR        R1, [SP, #16]
+  0x34183D68:  2001         MOVS       R0, #1
+  0x34183D6A:  9003         STR        R0, [SP, #12]
+  0x34183D6C:  9805         LDR        R0, [SP, #20]
+  0x34183D6E:  9002         STR        R0, [SP, #8]
+  0x34183D70:  B160         CBZ        R0, .L1                  ; 0x34183D8C
+  0x34183D72:  9802         LDR        R0, [SP, #8]
+  0x34183D74:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34183D78:  D011         BEQ        46L3                      ; 0x34183D9E
+  0x34183D7A:  9802         LDR        R0, [SP, #8]
+  0x34183D7C:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34183D80:  D016         BEQ        46L5                      ; 0x34183DB0
+  0x34183D82:  9802         LDR        R0, [SP, #8]
+  0x34183D84:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34183D88:  D01B         BEQ        46L7                      ; 0x34183DC2
+  0x34183D8A:  E023         B          46L9                      ; 0x34183DD4
+
.L1:
+  0x34183D8C:  F7FD FB88    BL         LL_RCC_PLL1_IsReady      ; 0x341814A0
+  0x34183D90:  B920         CBNZ       R0, .L2                  ; 0x34183D9C
+  0x34183D92:  F7FD FBFF    BL         LL_RCC_PLL1_IsEnabledBypass ; 0x34181594
+  0x34183D96:  B908         CBNZ       R0, .L2                  ; 0x34183D9C
+  0x34183D98:  2000         MOVS       R0, #0
+  0x34183D9A:  9003         STR        R0, [SP, #12]
+
.L2:
+  0x34183D9C:  E01C         B          46L10                     ; 0x34183DD8
+
.L3:
+  0x34183D9E:  F7FD FBA7    BL         LL_RCC_PLL2_IsReady      ; 0x341814F0
+  0x34183DA2:  B920         CBNZ       R0, .L4                  ; 0x34183DAE
+  0x34183DA4:  F7FD FBFE    BL         LL_RCC_PLL2_IsEnabledBypass ; 0x341815A4
+  0x34183DA8:  B908         CBNZ       R0, .L4                  ; 0x34183DAE
+  0x34183DAA:  2000         MOVS       R0, #0
+  0x34183DAC:  9003         STR        R0, [SP, #12]
+
.L4:
+  0x34183DAE:  E013         B          46L10                     ; 0x34183DD8
+
.L5:
+  0x34183DB0:  F7FD FBA6    BL         LL_RCC_PLL3_IsReady      ; 0x34181500
+  0x34183DB4:  B920         CBNZ       R0, .L6                  ; 0x34183DC0
+  0x34183DB6:  F7FD FBFD    BL         LL_RCC_PLL3_IsEnabledBypass ; 0x341815B4
+  0x34183DBA:  B908         CBNZ       R0, .L6                  ; 0x34183DC0
+  0x34183DBC:  2000         MOVS       R0, #0
+  0x34183DBE:  9003         STR        R0, [SP, #12]
+
.L6:
+  0x34183DC0:  E00A         B          46L10                     ; 0x34183DD8
+
.L7:
+  0x34183DC2:  F7FD FBA5    BL         LL_RCC_PLL4_IsReady      ; 0x34181510
+  0x34183DC6:  B920         CBNZ       R0, .L8                  ; 0x34183DD2
+  0x34183DC8:  F7FD FBFC    BL         LL_RCC_PLL4_IsEnabledBypass ; 0x341815C4
+  0x34183DCC:  B908         CBNZ       R0, .L8                  ; 0x34183DD2
+  0x34183DCE:  2000         MOVS       R0, #0
+  0x34183DD0:  9003         STR        R0, [SP, #12]
+
.L8:
+  0x34183DD2:  E001         B          46L10                     ; 0x34183DD8
+
.L9:
+  0x34183DD4:  2000         MOVS       R0, #0
+  0x34183DD6:  9003         STR        R0, [SP, #12]
+
.L10:
+  0x34183DD8:  9804         LDR        R0, [SP, #16]
+  0x34183DDA:  9001         STR        R0, [SP, #4]
+  0x34183DDC:  B160         CBZ        R0, .L11                 ; 0x34183DF8
+  0x34183DDE:  9801         LDR        R0, [SP, #4]
+  0x34183DE0:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34183DE4:  D011         BEQ        46L13                     ; 0x34183E0A
+  0x34183DE6:  9801         LDR        R0, [SP, #4]
+  0x34183DE8:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34183DEC:  D016         BEQ        46L15                     ; 0x34183E1C
+  0x34183DEE:  9801         LDR        R0, [SP, #4]
+  0x34183DF0:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34183DF4:  D01B         BEQ        46L17                     ; 0x34183E2E
+  0x34183DF6:  E023         B          46L19                     ; 0x34183E40
+
.L11:
+  0x34183DF8:  F7FD FB52    BL         LL_RCC_PLL1_IsReady      ; 0x341814A0
+  0x34183DFC:  B920         CBNZ       R0, .L12                 ; 0x34183E08
+  0x34183DFE:  F7FD FBC9    BL         LL_RCC_PLL1_IsEnabledBypass ; 0x34181594
+  0x34183E02:  B908         CBNZ       R0, .L12                 ; 0x34183E08
+  0x34183E04:  2000         MOVS       R0, #0
+  0x34183E06:  9003         STR        R0, [SP, #12]
+
.L12:
+  0x34183E08:  E01C         B          46L20                     ; 0x34183E44
+
.L13:
+  0x34183E0A:  F7FD FB71    BL         LL_RCC_PLL2_IsReady      ; 0x341814F0
+  0x34183E0E:  B920         CBNZ       R0, .L14                 ; 0x34183E1A
+  0x34183E10:  F7FD FBC8    BL         LL_RCC_PLL2_IsEnabledBypass ; 0x341815A4
+  0x34183E14:  B908         CBNZ       R0, .L14                 ; 0x34183E1A
+  0x34183E16:  2000         MOVS       R0, #0
+  0x34183E18:  9003         STR        R0, [SP, #12]
+
.L14:
+  0x34183E1A:  E013         B          46L20                     ; 0x34183E44
+
.L15:
+  0x34183E1C:  F7FD FB70    BL         LL_RCC_PLL3_IsReady      ; 0x34181500
+  0x34183E20:  B920         CBNZ       R0, .L16                 ; 0x34183E2C
+  0x34183E22:  F7FD FBC7    BL         LL_RCC_PLL3_IsEnabledBypass ; 0x341815B4
+  0x34183E26:  B908         CBNZ       R0, .L16                 ; 0x34183E2C
+  0x34183E28:  2000         MOVS       R0, #0
+  0x34183E2A:  9003         STR        R0, [SP, #12]
+
.L16:
+  0x34183E2C:  E00A         B          46L20                     ; 0x34183E44
+
.L17:
+  0x34183E2E:  F7FD FB6F    BL         LL_RCC_PLL4_IsReady      ; 0x34181510
+  0x34183E32:  B920         CBNZ       R0, .L18                 ; 0x34183E3E
+  0x34183E34:  F7FD FBC6    BL         LL_RCC_PLL4_IsEnabledBypass ; 0x341815C4
+  0x34183E38:  B908         CBNZ       R0, .L18                 ; 0x34183E3E
+  0x34183E3A:  2000         MOVS       R0, #0
+  0x34183E3C:  9003         STR        R0, [SP, #12]
+
.L18:
+  0x34183E3E:  E001         B          46L20                     ; 0x34183E44
+
.L19:
+  0x34183E40:  2000         MOVS       R0, #0
+  0x34183E42:  9003         STR        R0, [SP, #12]
+
.L20:
+  0x34183E44:  9803         LDR        R0, [SP, #12]
+  0x34183E46:  B006         ADD        SP, SP, #24
+  0x34183E48:  BD80         POP        123R7, PC}
+
+

Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE1_IRQHandler:
+  0x34183E4A:  E7FE         B          MCE1_IRQHandler          ; 0x34183E4A
+
+

Section .text.LL_RCC_IC1_Enable from blto2_FSBL_lto.o, size=14, align=4

+ +
+
LL_RCC_IC1_Enable:
+  0x34183E4C:  F648 2140    MOVW       R1, #0x8A40
+  0x34183E50:  F2C5 6102    MOVT       R1, #0x5602
+  0x34183E54:  2001         MOVS       R0, #1
+  0x34183E56:  6008         STR        R0, [R1]
+  0x34183E58:  4770         BX         LR
+
+

Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE2_IRQHandler:
+  0x34183E5A:  E7FE         B          MCE2_IRQHandler          ; 0x34183E5A
+
+

Section .text.HAL_RCC_GetCpuClockFreq from blto2_FSBL_lto.o, size=238, align=4

+ +
+
HAL_RCC_GetCpuClockFreq:
+  0x34183E5C:  B580         PUSH       123R7, LR}
+  0x34183E5E:  B084         SUB        SP, SP, #16
+  0x34183E60:  2000         MOVS       R0, #0
+  0x34183E62:  9003         STR        R0, [SP, #12]
+  0x34183E64:  F7FD FAC6    BL         LL_RCC_GetCpuClkSource   ; 0x341813F4
+  0x34183E68:  4601         MOV        R1, R0
+  0x34183E6A:  9101         STR        R1, [SP, #4]
+  0x34183E6C:  B160         CBZ        R0, .L1                  ; 0x34183E88
+  0x34183E6E:  9801         LDR        R0, [SP, #4]
+  0x34183E70:  F5B0 1F80    CMP.W      R0, #0x100000
+  0x34183E74:  D012         BEQ        46L2                      ; 0x34183E9C
+  0x34183E76:  9801         LDR        R0, [SP, #4]
+  0x34183E78:  F5B0 1F00    CMP.W      R0, #0x200000
+  0x34183E7C:  D022         BEQ        46L3                      ; 0x34183EC4
+  0x34183E7E:  9801         LDR        R0, [SP, #4]
+  0x34183E80:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x34183E84:  D024         BEQ        46L4                      ; 0x34183ED0
+  0x34183E86:  E05D         B          46L10                     ; 0x34183F44
+
.L1:
+  0x34183E88:  F7FD FB7C    BL         LL_RCC_HSI_GetDivider    ; 0x34181584
+  0x34183E8C:  09C1         LSRS       R1, R0, #7
+  0x34183E8E:  F249 0000    MOVW       R0, #0x9000
+  0x34183E92:  F2C0 30D0    MOVT       R0, #0x03D0
+  0x34183E96:  40C8         LSRS       R0, R1
+  0x34183E98:  9003         STR        R0, [SP, #12]
+  0x34183E9A:  E053         B          46L10                     ; 0x34183F44
+
.L2:
+  0x34183E9C:  F248 0044    MOVW       R0, #0x8044
+  0x34183EA0:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183EA4:  6800         LDR        R0, [R0]
+  0x34183EA6:  F400 7000    AND        R0, R0, #0x0200
+  0x34183EAA:  F5B0 7F00    CMP.W      R0, #0x0200
+  0x34183EAE:  F640 1000    MOVW       R0, #0x0900
+  0x34183EB2:  F2C0 003D    MOVT       R0, #61
+  0x34183EB6:  BF04         ITT        EQ
+  0x34183EB8:  F242 4000    MOVWEQ     R0, #0x2400
+  0x34183EBC:  F2C0 00F4    MOVTEQ     R0, #244
+  0x34183EC0:  9003         STR        R0, [SP, #12]
+  0x34183EC2:  E03F         B          46L10                     ; 0x34183F44
+
.L3:
+  0x34183EC4:  F646 4000    MOVW       R0, #0x6C00
+  0x34183EC8:  F2C0 20DC    MOVT       R0, #0x02DC
+  0x34183ECC:  9003         STR        R0, [SP, #12]
+  0x34183ECE:  E039         B          46L10                     ; 0x34183F44
+
.L4:
+  0x34183ED0:  F000 F83C    BL         LL_RCC_IC1_GetDivider    ; 0x34183F4C
+  0x34183ED4:  9002         STR        R0, [SP, #8]
+  0x34183ED6:  F7FD FAEB    BL         LL_RCC_IC1_GetSource     ; 0x341814B0
+  0x34183EDA:  4601         MOV        R1, R0
+  0x34183EDC:  9100         STR        R1, [SP, #0]
+  0x34183EDE:  B160         CBZ        R0, .L5                  ; 0x34183EFA
+  0x34183EE0:  9800         LDR        R0, [SP, #0]
+  0x34183EE2:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34183EE6:  D011         BEQ        46L6                      ; 0x34183F0C
+  0x34183EE8:  9800         LDR        R0, [SP, #0]
+  0x34183EEA:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34183EEE:  D016         BEQ        46L7                      ; 0x34183F1E
+  0x34183EF0:  9800         LDR        R0, [SP, #0]
+  0x34183EF2:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34183EF6:  D01B         BEQ        46L8                      ; 0x34183F30
+  0x34183EF8:  E023         B          46L9                      ; 0x34183F42
+
.L5:
+  0x34183EFA:  F000 F833    BL         HAL_RCCEx_GetPLL1CLKFreq ; 0x34183F64
+  0x34183EFE:  9003         STR        R0, [SP, #12]
+  0x34183F00:  9803         LDR        R0, [SP, #12]
+  0x34183F02:  9902         LDR        R1, [SP, #8]
+  0x34183F04:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34183F08:  9003         STR        R0, [SP, #12]
+  0x34183F0A:  E01A         B          46L9                      ; 0x34183F42
+
.L6:
+  0x34183F0C:  F000 F86C    BL         HAL_RCCEx_GetPLL2CLKFreq ; 0x34183FE8
+  0x34183F10:  9003         STR        R0, [SP, #12]
+  0x34183F12:  9803         LDR        R0, [SP, #12]
+  0x34183F14:  9902         LDR        R1, [SP, #8]
+  0x34183F16:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34183F1A:  9003         STR        R0, [SP, #12]
+  0x34183F1C:  E011         B          46L9                      ; 0x34183F42
+
.L7:
+  0x34183F1E:  F000 F8A5    BL         HAL_RCCEx_GetPLL3CLKFreq ; 0x3418406C
+  0x34183F22:  9003         STR        R0, [SP, #12]
+  0x34183F24:  9803         LDR        R0, [SP, #12]
+  0x34183F26:  9902         LDR        R1, [SP, #8]
+  0x34183F28:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34183F2C:  9003         STR        R0, [SP, #12]
+  0x34183F2E:  E008         B          46L9                      ; 0x34183F42
+
.L8:
+  0x34183F30:  F000 F8DE    BL         HAL_RCCEx_GetPLL4CLKFreq ; 0x341840F0
+  0x34183F34:  9003         STR        R0, [SP, #12]
+  0x34183F36:  9803         LDR        R0, [SP, #12]
+  0x34183F38:  9902         LDR        R1, [SP, #8]
+  0x34183F3A:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34183F3E:  9003         STR        R0, [SP, #12]
+  0x34183F40:  E7FF         B          46L9                      ; 0x34183F42
+
.L9:
+  0x34183F42:  E7FF         B          46L10                     ; 0x34183F44
+
.L10:
+  0x34183F44:  9803         LDR        R0, [SP, #12]
+  0x34183F46:  B004         ADD        SP, SP, #16
+  0x34183F48:  BD80         POP        123R7, PC}
+
+

Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE3_IRQHandler:
+  0x34183F4A:  E7FE         B          MCE3_IRQHandler          ; 0x34183F4A
+
+

Section .text.LL_RCC_IC1_GetDivider from blto2_FSBL_lto.o, size=22, align=4

+ +
+
LL_RCC_IC1_GetDivider:
+  0x34183F4C:  F248 00C4    MOVW       R0, #0x80C4
+  0x34183F50:  F2C5 6002    MOVT       R0, #0x5602
+  0x34183F54:  6800         LDR        R0, [R0]
+  0x34183F56:  F400 017F    AND        R1, R0, #0xFF0000
+  0x34183F5A:  2001         MOVS       R0, #1
+  0x34183F5C:  EB00 4011    ADD.W      R0, R0, R1, LSR #16
+  0x34183F60:  4770         BX         LR
+
+

Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE4_IRQHandler:
+  0x34183F62:  E7FE         B          MCE4_IRQHandler          ; 0x34183F62
+
+

Section .text.HAL_RCCEx_GetPLL1CLKFreq from blto2_FSBL_lto.o, size=130, align=4

+ +
+
HAL_RCCEx_GetPLL1CLKFreq:
+  0x34183F64:  B510         PUSH       123R4, LR}
+  0x34183F66:  B08A         SUB        SP, SP, #40
+  0x34183F68:  2000         MOVS       R0, #0
+  0x34183F6A:  9009         STR        R0, [SP, #36]
+  0x34183F6C:  F7FD FD34    BL         LL_RCC_PLL1_IsReady.70   ; 0x341819D8
+  0x34183F70:  B368         CBZ        R0, .L2                  ; 0x34183FCE
+  0x34183F72:  F7FD FD39    BL         LL_RCC_PLL1P_IsEnabled   ; 0x341819E8
+  0x34183F76:  B348         CBZ        R0, .L1                  ; 0x34183FCC
+  0x34183F78:  F7FD FD3E    BL         LL_RCC_PLL1_GetSource.71 ; 0x341819F8
+  0x34183F7C:  F7FD FBBA    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x34183F80:  9007         STR        R0, [SP, #28]
+  0x34183F82:  9807         LDR        R0, [SP, #28]
+  0x34183F84:  B310         CBZ        R0, .L1                  ; 0x34183FCC
+  0x34183F86:  F7FD FD3F    BL         LL_RCC_PLL1_GetM         ; 0x34181A08
+  0x34183F8A:  9008         STR        R0, [SP, #32]
+  0x34183F8C:  9808         LDR        R0, [SP, #32]
+  0x34183F8E:  B1E8         CBZ        R0, .L1                  ; 0x34183FCC
+  0x34183F90:  9807         LDR        R0, [SP, #28]
+  0x34183F92:  9006         STR        R0, [SP, #24]
+  0x34183F94:  9808         LDR        R0, [SP, #32]
+  0x34183F96:  9003         STR        R0, [SP, #12]
+  0x34183F98:  F7FD FD3E    BL         LL_RCC_PLL1_GetN         ; 0x34181A18
+  0x34183F9C:  9004         STR        R0, [SP, #16]
+  0x34183F9E:  F7FD FD43    BL         LL_RCC_PLL1_GetFRACN     ; 0x34181A28
+  0x34183FA2:  9005         STR        R0, [SP, #20]
+  0x34183FA4:  F7FD FD48    BL         LL_RCC_PLL1_GetP1        ; 0x34181A38
+  0x34183FA8:  9002         STR        R0, [SP, #8]
+  0x34183FAA:  F7FD FD4D    BL         LL_RCC_PLL1_GetP2        ; 0x34181A48
+  0x34183FAE:  F8DD C008    LDR.W      R12, [SP, #8]
+  0x34183FB2:  9903         LDR        R1, [SP, #12]
+  0x34183FB4:  9A04         LDR        R2, [SP, #16]
+  0x34183FB6:  9B05         LDR        R3, [SP, #20]
+  0x34183FB8:  4604         MOV        R4, R0
+  0x34183FBA:  9806         LDR        R0, [SP, #24]
+  0x34183FBC:  46EE         MOV        LR, SP
+  0x34183FBE:  F8CE 4004    STR.W      R4, [LR, #4]
+  0x34183FC2:  F8CE C000    STR.W      R12, [LR]
+  0x34183FC6:  F7FD FC03    BL         RCCEx_CalcPLLFreq        ; 0x341817D0
+  0x34183FCA:  9009         STR        R0, [SP, #36]
+
.L1:
+  0x34183FCC:  E008         B          46L3                      ; 0x34183FE0
+
.L2:
+  0x34183FCE:  F7FD FD43    BL         LL_RCC_PLL1_IsEnabledBypass.72 ; 0x34181A58
+  0x34183FD2:  B128         CBZ        R0, .L3                  ; 0x34183FE0
+  0x34183FD4:  F7FD FD10    BL         LL_RCC_PLL1_GetSource.71 ; 0x341819F8
+  0x34183FD8:  F7FD FB8C    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x34183FDC:  9009         STR        R0, [SP, #36]
+  0x34183FDE:  E7FF         B          46L3                      ; 0x34183FE0
+
.L3:
+  0x34183FE0:  9809         LDR        R0, [SP, #36]
+  0x34183FE2:  B00A         ADD        SP, SP, #40
+  0x34183FE4:  BD10         POP        123R4, PC}
+
+

Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ADC1_2_IRQHandler:
+  0x34183FE6:  E7FE         B          ADC1_2_IRQHandler        ; 0x34183FE6
+
+

Section .text.HAL_RCCEx_GetPLL2CLKFreq from blto2_FSBL_lto.o, size=130, align=4

+ +
+
HAL_RCCEx_GetPLL2CLKFreq:
+  0x34183FE8:  B510         PUSH       123R4, LR}
+  0x34183FEA:  B08A         SUB        SP, SP, #40
+  0x34183FEC:  2000         MOVS       R0, #0
+  0x34183FEE:  9009         STR        R0, [SP, #36]
+  0x34183FF0:  F7FD FCAA    BL         LL_RCC_PLL2_IsReady.67   ; 0x34181948
+  0x34183FF4:  B368         CBZ        R0, .L2                  ; 0x34184052
+  0x34183FF6:  F7FD FCAF    BL         LL_RCC_PLL2P_IsEnabled   ; 0x34181958
+  0x34183FFA:  B348         CBZ        R0, .L1                  ; 0x34184050
+  0x34183FFC:  F7FD FCB4    BL         LL_RCC_PLL2_GetSource.68 ; 0x34181968
+  0x34184000:  F7FD FB78    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x34184004:  9007         STR        R0, [SP, #28]
+  0x34184006:  9807         LDR        R0, [SP, #28]
+  0x34184008:  B310         CBZ        R0, .L1                  ; 0x34184050
+  0x3418400A:  F7FD FCB5    BL         LL_RCC_PLL2_GetM         ; 0x34181978
+  0x3418400E:  9008         STR        R0, [SP, #32]
+  0x34184010:  9808         LDR        R0, [SP, #32]
+  0x34184012:  B1E8         CBZ        R0, .L1                  ; 0x34184050
+  0x34184014:  9807         LDR        R0, [SP, #28]
+  0x34184016:  9006         STR        R0, [SP, #24]
+  0x34184018:  9808         LDR        R0, [SP, #32]
+  0x3418401A:  9003         STR        R0, [SP, #12]
+  0x3418401C:  F7FD FCB4    BL         LL_RCC_PLL2_GetN         ; 0x34181988
+  0x34184020:  9004         STR        R0, [SP, #16]
+  0x34184022:  F7FD FCB9    BL         LL_RCC_PLL2_GetFRACN     ; 0x34181998
+  0x34184026:  9005         STR        R0, [SP, #20]
+  0x34184028:  F7FD FCBE    BL         LL_RCC_PLL2_GetP1        ; 0x341819A8
+  0x3418402C:  9002         STR        R0, [SP, #8]
+  0x3418402E:  F7FD FCC3    BL         LL_RCC_PLL2_GetP2        ; 0x341819B8
+  0x34184032:  F8DD C008    LDR.W      R12, [SP, #8]
+  0x34184036:  9903         LDR        R1, [SP, #12]
+  0x34184038:  9A04         LDR        R2, [SP, #16]
+  0x3418403A:  9B05         LDR        R3, [SP, #20]
+  0x3418403C:  4604         MOV        R4, R0
+  0x3418403E:  9806         LDR        R0, [SP, #24]
+  0x34184040:  46EE         MOV        LR, SP
+  0x34184042:  F8CE 4004    STR.W      R4, [LR, #4]
+  0x34184046:  F8CE C000    STR.W      R12, [LR]
+  0x3418404A:  F7FD FBC1    BL         RCCEx_CalcPLLFreq        ; 0x341817D0
+  0x3418404E:  9009         STR        R0, [SP, #36]
+
.L1:
+  0x34184050:  E008         B          46L3                      ; 0x34184064
+
.L2:
+  0x34184052:  F7FD FCB9    BL         LL_RCC_PLL2_IsEnabledBypass.69 ; 0x341819C8
+  0x34184056:  B128         CBZ        R0, .L3                  ; 0x34184064
+  0x34184058:  F7FD FC86    BL         LL_RCC_PLL2_GetSource.68 ; 0x34181968
+  0x3418405C:  F7FD FB4A    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x34184060:  9009         STR        R0, [SP, #36]
+  0x34184062:  E7FF         B          46L3                      ; 0x34184064
+
.L3:
+  0x34184064:  9809         LDR        R0, [SP, #36]
+  0x34184066:  B00A         ADD        SP, SP, #40
+  0x34184068:  BD10         POP        123R4, PC}
+
+

Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CSI_IRQHandler:
+  0x3418406A:  E7FE         B          CSI_IRQHandler           ; 0x3418406A
+
+

Section .text.HAL_RCCEx_GetPLL3CLKFreq from blto2_FSBL_lto.o, size=130, align=4

+ +
+
HAL_RCCEx_GetPLL3CLKFreq:
+  0x3418406C:  B510         PUSH       123R4, LR}
+  0x3418406E:  B08A         SUB        SP, SP, #40
+  0x34184070:  2000         MOVS       R0, #0
+  0x34184072:  9009         STR        R0, [SP, #36]
+  0x34184074:  F7FD FC20    BL         LL_RCC_PLL3_IsReady.64   ; 0x341818B8
+  0x34184078:  B368         CBZ        R0, .L2                  ; 0x341840D6
+  0x3418407A:  F7FD FC25    BL         LL_RCC_PLL3P_IsEnabled   ; 0x341818C8
+  0x3418407E:  B348         CBZ        R0, .L1                  ; 0x341840D4
+  0x34184080:  F7FD FC2A    BL         LL_RCC_PLL3_GetSource.65 ; 0x341818D8
+  0x34184084:  F7FD FB36    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x34184088:  9007         STR        R0, [SP, #28]
+  0x3418408A:  9807         LDR        R0, [SP, #28]
+  0x3418408C:  B310         CBZ        R0, .L1                  ; 0x341840D4
+  0x3418408E:  F7FD FC2B    BL         LL_RCC_PLL3_GetM         ; 0x341818E8
+  0x34184092:  9008         STR        R0, [SP, #32]
+  0x34184094:  9808         LDR        R0, [SP, #32]
+  0x34184096:  B1E8         CBZ        R0, .L1                  ; 0x341840D4
+  0x34184098:  9807         LDR        R0, [SP, #28]
+  0x3418409A:  9006         STR        R0, [SP, #24]
+  0x3418409C:  9808         LDR        R0, [SP, #32]
+  0x3418409E:  9003         STR        R0, [SP, #12]
+  0x341840A0:  F7FD FC2A    BL         LL_RCC_PLL3_GetN         ; 0x341818F8
+  0x341840A4:  9004         STR        R0, [SP, #16]
+  0x341840A6:  F7FD FC2F    BL         LL_RCC_PLL3_GetFRACN     ; 0x34181908
+  0x341840AA:  9005         STR        R0, [SP, #20]
+  0x341840AC:  F7FD FC34    BL         LL_RCC_PLL3_GetP1        ; 0x34181918
+  0x341840B0:  9002         STR        R0, [SP, #8]
+  0x341840B2:  F7FD FC39    BL         LL_RCC_PLL3_GetP2        ; 0x34181928
+  0x341840B6:  F8DD C008    LDR.W      R12, [SP, #8]
+  0x341840BA:  9903         LDR        R1, [SP, #12]
+  0x341840BC:  9A04         LDR        R2, [SP, #16]
+  0x341840BE:  9B05         LDR        R3, [SP, #20]
+  0x341840C0:  4604         MOV        R4, R0
+  0x341840C2:  9806         LDR        R0, [SP, #24]
+  0x341840C4:  46EE         MOV        LR, SP
+  0x341840C6:  F8CE 4004    STR.W      R4, [LR, #4]
+  0x341840CA:  F8CE C000    STR.W      R12, [LR]
+  0x341840CE:  F7FD FB7F    BL         RCCEx_CalcPLLFreq        ; 0x341817D0
+  0x341840D2:  9009         STR        R0, [SP, #36]
+
.L1:
+  0x341840D4:  E008         B          46L3                      ; 0x341840E8
+
.L2:
+  0x341840D6:  F7FD FC2F    BL         LL_RCC_PLL3_IsEnabledBypass.66 ; 0x34181938
+  0x341840DA:  B128         CBZ        R0, .L3                  ; 0x341840E8
+  0x341840DC:  F7FD FBFC    BL         LL_RCC_PLL3_GetSource.65 ; 0x341818D8
+  0x341840E0:  F7FD FB08    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x341840E4:  9009         STR        R0, [SP, #36]
+  0x341840E6:  E7FF         B          46L3                      ; 0x341840E8
+
.L3:
+  0x341840E8:  9809         LDR        R0, [SP, #36]
+  0x341840EA:  B00A         ADD        SP, SP, #40
+  0x341840EC:  BD10         POP        123R4, PC}
+
+

Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DCMIPP_IRQHandler:
+  0x341840EE:  E7FE         B          DCMIPP_IRQHandler        ; 0x341840EE
+
+

Section .text.HAL_RCCEx_GetPLL4CLKFreq from blto2_FSBL_lto.o, size=130, align=4

+ +
+
HAL_RCCEx_GetPLL4CLKFreq:
+  0x341840F0:  B510         PUSH       123R4, LR}
+  0x341840F2:  B08A         SUB        SP, SP, #40
+  0x341840F4:  2000         MOVS       R0, #0
+  0x341840F6:  9009         STR        R0, [SP, #36]
+  0x341840F8:  F7FD FAE4    BL         LL_RCC_PLL4_IsReady.57   ; 0x341816C4
+  0x341840FC:  B368         CBZ        R0, .L2                  ; 0x3418415A
+  0x341840FE:  F7FD FAE9    BL         LL_RCC_PLL4P_IsEnabled   ; 0x341816D4
+  0x34184102:  B348         CBZ        R0, .L1                  ; 0x34184158
+  0x34184104:  F7FD FAEE    BL         LL_RCC_PLL4_GetSource.58 ; 0x341816E4
+  0x34184108:  F7FD FAF4    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x3418410C:  9007         STR        R0, [SP, #28]
+  0x3418410E:  9807         LDR        R0, [SP, #28]
+  0x34184110:  B310         CBZ        R0, .L1                  ; 0x34184158
+  0x34184112:  F7FD FB35    BL         LL_RCC_PLL4_GetM         ; 0x34181780
+  0x34184116:  9008         STR        R0, [SP, #32]
+  0x34184118:  9808         LDR        R0, [SP, #32]
+  0x3418411A:  B1E8         CBZ        R0, .L1                  ; 0x34184158
+  0x3418411C:  9807         LDR        R0, [SP, #28]
+  0x3418411E:  9006         STR        R0, [SP, #24]
+  0x34184120:  9808         LDR        R0, [SP, #32]
+  0x34184122:  9003         STR        R0, [SP, #12]
+  0x34184124:  F7FD FB34    BL         LL_RCC_PLL4_GetN         ; 0x34181790
+  0x34184128:  9004         STR        R0, [SP, #16]
+  0x3418412A:  F7FD FB39    BL         LL_RCC_PLL4_GetFRACN     ; 0x341817A0
+  0x3418412E:  9005         STR        R0, [SP, #20]
+  0x34184130:  F7FD FB3E    BL         LL_RCC_PLL4_GetP1        ; 0x341817B0
+  0x34184134:  9002         STR        R0, [SP, #8]
+  0x34184136:  F7FD FB43    BL         LL_RCC_PLL4_GetP2        ; 0x341817C0
+  0x3418413A:  F8DD C008    LDR.W      R12, [SP, #8]
+  0x3418413E:  9903         LDR        R1, [SP, #12]
+  0x34184140:  9A04         LDR        R2, [SP, #16]
+  0x34184142:  9B05         LDR        R3, [SP, #20]
+  0x34184144:  4604         MOV        R4, R0
+  0x34184146:  9806         LDR        R0, [SP, #24]
+  0x34184148:  46EE         MOV        LR, SP
+  0x3418414A:  F8CE 4004    STR.W      R4, [LR, #4]
+  0x3418414E:  F8CE C000    STR.W      R12, [LR]
+  0x34184152:  F7FD FB3D    BL         RCCEx_CalcPLLFreq        ; 0x341817D0
+  0x34184156:  9009         STR        R0, [SP, #36]
+
.L1:
+  0x34184158:  E008         B          46L3                      ; 0x3418416C
+
.L2:
+  0x3418415A:  F7FD FB7D    BL         LL_RCC_PLL4_IsEnabledBypass.59 ; 0x34181858
+  0x3418415E:  B128         CBZ        R0, .L3                  ; 0x3418416C
+  0x34184160:  F7FD FAC0    BL         LL_RCC_PLL4_GetSource.58 ; 0x341816E4
+  0x34184164:  F7FD FAC6    BL         RCCEx_GetPLLSourceFreq   ; 0x341816F4
+  0x34184168:  9009         STR        R0, [SP, #36]
+  0x3418416A:  E7FF         B          46L3                      ; 0x3418416C
+
.L3:
+  0x3418416C:  9809         LDR        R0, [SP, #36]
+  0x3418416E:  B00A         ADD        SP, SP, #40
+  0x34184170:  BD10         POP        123R4, PC}
+
+

Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
PAHB_ERR_IRQHandler:
+  0x34184172:  E7FE         B          PAHB_ERR_IRQHandler      ; 0x34184172
+
+

Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU0_IRQHandler:
+  0x34184174:  E7FE         B          NPU0_IRQHandler          ; 0x34184174
+
+

Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU1_IRQHandler:
+  0x34184176:  E7FE         B          NPU1_IRQHandler          ; 0x34184176
+
+

Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU2_IRQHandler:
+  0x34184178:  E7FE         B          NPU2_IRQHandler          ; 0x34184178
+
+

Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU3_IRQHandler:
+  0x3418417A:  E7FE         B          NPU3_IRQHandler          ; 0x3418417A
+
+

Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CACHEAXI_IRQHandler:
+  0x3418417C:  E7FE         B          CACHEAXI_IRQHandler      ; 0x3418417C
+
+

Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_LO_IRQHandler:
+  0x3418417E:  E7FE         B          LTDC_LO_IRQHandler       ; 0x3418417E
+
+

Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_LO_ERR_IRQHandler:
+  0x34184180:  E7FE         B          LTDC_LO_ERR_IRQHandler   ; 0x34184180
+
+

Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DMA2D_IRQHandler:
+  0x34184182:  E7FE         B          DMA2D_IRQHandler         ; 0x34184182
+
+

Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
JPEG_IRQHandler:
+  0x34184184:  E7FE         B          JPEG_IRQHandler          ; 0x34184184
+
+

Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
VENC_IRQHandler:
+  0x34184186:  E7FE         B          VENC_IRQHandler          ; 0x34184186
+
+

Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GFXMMU_IRQHandler:
+  0x34184188:  E7FE         B          GFXMMU_IRQHandler        ; 0x34184188
+
+

Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GFXTIM_IRQHandler:
+  0x3418418A:  E7FE         B          GFXTIM_IRQHandler        ; 0x3418418A
+
+

Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPU2D_IRQHandler:
+  0x3418418C:  E7FE         B          GPU2D_IRQHandler         ; 0x3418418C
+
+

Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPU2D_ER_IRQHandler:
+  0x3418418E:  E7FE         B          GPU2D_ER_IRQHandler      ; 0x3418418E
+
+

Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ICACHE_IRQHandler:
+  0x34184190:  E7FE         B          ICACHE_IRQHandler        ; 0x34184190
+
+

Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel0_IRQHandler:
+  0x34184192:  E7FE         B          HPDMA1_Channel0_IRQHandler ; 0x34184192
+
+

Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel1_IRQHandler:
+  0x34184194:  E7FE         B          HPDMA1_Channel1_IRQHandler ; 0x34184194
+
+

Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel2_IRQHandler:
+  0x34184196:  E7FE         B          HPDMA1_Channel2_IRQHandler ; 0x34184196
+
+

Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel3_IRQHandler:
+  0x34184198:  E7FE         B          HPDMA1_Channel3_IRQHandler ; 0x34184198
+
+

Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel4_IRQHandler:
+  0x3418419A:  E7FE         B          HPDMA1_Channel4_IRQHandler ; 0x3418419A
+
+

Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel5_IRQHandler:
+  0x3418419C:  E7FE         B          HPDMA1_Channel5_IRQHandler ; 0x3418419C
+
+

Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel6_IRQHandler:
+  0x3418419E:  E7FE         B          HPDMA1_Channel6_IRQHandler ; 0x3418419E
+
+

Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel7_IRQHandler:
+  0x341841A0:  E7FE         B          HPDMA1_Channel7_IRQHandler ; 0x341841A0
+
+

Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel8_IRQHandler:
+  0x341841A2:  E7FE         B          HPDMA1_Channel8_IRQHandler ; 0x341841A2
+
+

Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel9_IRQHandler:
+  0x341841A4:  E7FE         B          HPDMA1_Channel9_IRQHandler ; 0x341841A4
+
+

Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel10_IRQHandler:
+  0x341841A6:  E7FE         B          HPDMA1_Channel10_IRQHandler ; 0x341841A6
+
+

Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel11_IRQHandler:
+  0x341841A8:  E7FE         B          HPDMA1_Channel11_IRQHandler ; 0x341841A8
+
+

Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel12_IRQHandler:
+  0x341841AA:  E7FE         B          HPDMA1_Channel12_IRQHandler ; 0x341841AA
+
+

Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel13_IRQHandler:
+  0x341841AC:  E7FE         B          HPDMA1_Channel13_IRQHandler ; 0x341841AC
+
+

Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel14_IRQHandler:
+  0x341841AE:  E7FE         B          HPDMA1_Channel14_IRQHandler ; 0x341841AE
+
+

Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel15_IRQHandler:
+  0x341841B0:  E7FE         B          HPDMA1_Channel15_IRQHandler ; 0x341841B0
+
+

Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel0_IRQHandler:
+  0x341841B2:  E7FE         B          GPDMA1_Channel0_IRQHandler ; 0x341841B2
+
+

Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel1_IRQHandler:
+  0x341841B4:  E7FE         B          GPDMA1_Channel1_IRQHandler ; 0x341841B4
+
+

Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel2_IRQHandler:
+  0x341841B6:  E7FE         B          GPDMA1_Channel2_IRQHandler ; 0x341841B6
+
+

Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel3_IRQHandler:
+  0x341841B8:  E7FE         B          GPDMA1_Channel3_IRQHandler ; 0x341841B8
+
+

Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel4_IRQHandler:
+  0x341841BA:  E7FE         B          GPDMA1_Channel4_IRQHandler ; 0x341841BA
+
+

Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel5_IRQHandler:
+  0x341841BC:  E7FE         B          GPDMA1_Channel5_IRQHandler ; 0x341841BC
+
+

Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel6_IRQHandler:
+  0x341841BE:  E7FE         B          GPDMA1_Channel6_IRQHandler ; 0x341841BE
+
+

Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel7_IRQHandler:
+  0x341841C0:  E7FE         B          GPDMA1_Channel7_IRQHandler ; 0x341841C0
+
+

Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel8_IRQHandler:
+  0x341841C2:  E7FE         B          GPDMA1_Channel8_IRQHandler ; 0x341841C2
+
+

Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel9_IRQHandler:
+  0x341841C4:  E7FE         B          GPDMA1_Channel9_IRQHandler ; 0x341841C4
+
+

Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel10_IRQHandler:
+  0x341841C6:  E7FE         B          GPDMA1_Channel10_IRQHandler ; 0x341841C6
+
+

Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel11_IRQHandler:
+  0x341841C8:  E7FE         B          GPDMA1_Channel11_IRQHandler ; 0x341841C8
+
+

Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel12_IRQHandler:
+  0x341841CA:  E7FE         B          GPDMA1_Channel12_IRQHandler ; 0x341841CA
+
+

Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel13_IRQHandler:
+  0x341841CC:  E7FE         B          GPDMA1_Channel13_IRQHandler ; 0x341841CC
+
+

Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel14_IRQHandler:
+  0x341841CE:  E7FE         B          GPDMA1_Channel14_IRQHandler ; 0x341841CE
+
+

Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel15_IRQHandler:
+  0x341841D0:  E7FE         B          GPDMA1_Channel15_IRQHandler ; 0x341841D0
+
+

Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C1_EV_IRQHandler:
+  0x341841D2:  E7FE         B          I2C1_EV_IRQHandler       ; 0x341841D2
+
+

Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C1_ER_IRQHandler:
+  0x341841D4:  E7FE         B          I2C1_ER_IRQHandler       ; 0x341841D4
+
+

Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C2_EV_IRQHandler:
+  0x341841D6:  E7FE         B          I2C2_EV_IRQHandler       ; 0x341841D6
+
+

Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C2_ER_IRQHandler:
+  0x341841D8:  E7FE         B          I2C2_ER_IRQHandler       ; 0x341841D8
+
+

Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C3_EV_IRQHandler:
+  0x341841DA:  E7FE         B          I2C3_EV_IRQHandler       ; 0x341841DA
+
+

Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C3_ER_IRQHandler:
+  0x341841DC:  E7FE         B          I2C3_ER_IRQHandler       ; 0x341841DC
+
+

Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C4_EV_IRQHandler:
+  0x341841DE:  E7FE         B          I2C4_EV_IRQHandler       ; 0x341841DE
+
+

Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C4_ER_IRQHandler:
+  0x341841E0:  E7FE         B          I2C4_ER_IRQHandler       ; 0x341841E0
+
+

Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C1_EV_IRQHandler:
+  0x341841E2:  E7FE         B          I3C1_EV_IRQHandler       ; 0x341841E2
+
+

Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C1_ER_IRQHandler:
+  0x341841E4:  E7FE         B          I3C1_ER_IRQHandler       ; 0x341841E4
+
+

Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C2_EV_IRQHandler:
+  0x341841E6:  E7FE         B          I3C2_EV_IRQHandler       ; 0x341841E6
+
+

Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C2_ER_IRQHandler:
+  0x341841E8:  E7FE         B          I3C2_ER_IRQHandler       ; 0x341841E8
+
+

Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_BRK_IRQHandler:
+  0x341841EA:  E7FE         B          TIM1_BRK_IRQHandler      ; 0x341841EA
+
+

Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_UP_IRQHandler:
+  0x341841EC:  E7FE         B          TIM1_UP_IRQHandler       ; 0x341841EC
+
+

Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_TRG_CCU_IRQHandler:
+  0x341841EE:  E7FE         B          TIM1_TRG_CCU_IRQHandler  ; 0x341841EE
+
+

Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_CC_IRQHandler:
+  0x341841F0:  E7FE         B          TIM1_CC_IRQHandler       ; 0x341841F0
+
+

Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM2_IRQHandler:
+  0x341841F2:  E7FE         B          TIM2_IRQHandler          ; 0x341841F2
+
+

Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM3_IRQHandler:
+  0x341841F4:  E7FE         B          TIM3_IRQHandler          ; 0x341841F4
+
+

Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM4_IRQHandler:
+  0x341841F6:  E7FE         B          TIM4_IRQHandler          ; 0x341841F6
+
+

Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM5_IRQHandler:
+  0x341841F8:  E7FE         B          TIM5_IRQHandler          ; 0x341841F8
+
+

Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM6_IRQHandler:
+  0x341841FA:  E7FE         B          TIM6_IRQHandler          ; 0x341841FA
+
+

Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM7_IRQHandler:
+  0x341841FC:  E7FE         B          TIM7_IRQHandler          ; 0x341841FC
+
+

Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_BRK_IRQHandler:
+  0x341841FE:  E7FE         B          TIM8_BRK_IRQHandler      ; 0x341841FE
+
+

Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_UP_IRQHandler:
+  0x34184200:  E7FE         B          TIM8_UP_IRQHandler       ; 0x34184200
+
+

Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_TRG_CCU_IRQHandler:
+  0x34184202:  E7FE         B          TIM8_TRG_CCU_IRQHandler  ; 0x34184202
+
+

Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_CC_IRQHandler:
+  0x34184204:  E7FE         B          TIM8_CC_IRQHandler       ; 0x34184204
+
+

Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM9_IRQHandler:
+  0x34184206:  E7FE         B          TIM9_IRQHandler          ; 0x34184206
+
+

Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM10_IRQHandler:
+  0x34184208:  E7FE         B          TIM10_IRQHandler         ; 0x34184208
+
+

Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM11_IRQHandler:
+  0x3418420A:  E7FE         B          TIM11_IRQHandler         ; 0x3418420A
+
+

Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM12_IRQHandler:
+  0x3418420C:  E7FE         B          TIM12_IRQHandler         ; 0x3418420C
+
+

Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM13_IRQHandler:
+  0x3418420E:  E7FE         B          TIM13_IRQHandler         ; 0x3418420E
+
+

Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM14_IRQHandler:
+  0x34184210:  E7FE         B          TIM14_IRQHandler         ; 0x34184210
+
+

Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM15_IRQHandler:
+  0x34184212:  E7FE         B          TIM15_IRQHandler         ; 0x34184212
+
+

Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM16_IRQHandler:
+  0x34184214:  E7FE         B          TIM16_IRQHandler         ; 0x34184214
+
+

Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM17_IRQHandler:
+  0x34184216:  E7FE         B          TIM17_IRQHandler         ; 0x34184216
+
+

Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM18_IRQHandler:
+  0x34184218:  E7FE         B          TIM18_IRQHandler         ; 0x34184218
+
+

Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM1_IRQHandler:
+  0x3418421A:  E7FE         B          LPTIM1_IRQHandler        ; 0x3418421A
+
+

Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM2_IRQHandler:
+  0x3418421C:  E7FE         B          LPTIM2_IRQHandler        ; 0x3418421C
+
+

Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM3_IRQHandler:
+  0x3418421E:  E7FE         B          LPTIM3_IRQHandler        ; 0x3418421E
+
+

Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM4_IRQHandler:
+  0x34184220:  E7FE         B          LPTIM4_IRQHandler        ; 0x34184220
+
+

Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM5_IRQHandler:
+  0x34184222:  E7FE         B          LPTIM5_IRQHandler        ; 0x34184222
+
+

Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ADF1_FLT0_IRQHandler:
+  0x34184224:  E7FE         B          ADF1_FLT0_IRQHandler     ; 0x34184224
+
+

Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT0_IRQHandler:
+  0x34184226:  E7FE         B          MDF1_FLT0_IRQHandler     ; 0x34184226
+
+

Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT1_IRQHandler:
+  0x34184228:  E7FE         B          MDF1_FLT1_IRQHandler     ; 0x34184228
+
+

Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT2_IRQHandler:
+  0x3418422A:  E7FE         B          MDF1_FLT2_IRQHandler     ; 0x3418422A
+
+

Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT3_IRQHandler:
+  0x3418422C:  E7FE         B          MDF1_FLT3_IRQHandler     ; 0x3418422C
+
+

Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT4_IRQHandler:
+  0x3418422E:  E7FE         B          MDF1_FLT4_IRQHandler     ; 0x3418422E
+
+

Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT5_IRQHandler:
+  0x34184230:  E7FE         B          MDF1_FLT5_IRQHandler     ; 0x34184230
+
+

Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI1_A_IRQHandler:
+  0x34184232:  E7FE         B          SAI1_A_IRQHandler        ; 0x34184232
+
+

Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI1_B_IRQHandler:
+  0x34184234:  E7FE         B          SAI1_B_IRQHandler        ; 0x34184234
+
+

Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI2_A_IRQHandler:
+  0x34184236:  E7FE         B          SAI2_A_IRQHandler        ; 0x34184236
+
+

Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI2_B_IRQHandler:
+  0x34184238:  E7FE         B          SAI2_B_IRQHandler        ; 0x34184238
+
+

Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPDIFRX_IRQHandler:
+  0x3418423A:  E7FE         B          SPDIFRX_IRQHandler       ; 0x3418423A
+
+

Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI1_IRQHandler:
+  0x3418423C:  E7FE         B          SPI1_IRQHandler          ; 0x3418423C
+
+

Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI2_IRQHandler:
+  0x3418423E:  E7FE         B          SPI2_IRQHandler          ; 0x3418423E
+
+

Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI3_IRQHandler:
+  0x34184240:  E7FE         B          SPI3_IRQHandler          ; 0x34184240
+
+

Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI4_IRQHandler:
+  0x34184242:  E7FE         B          SPI4_IRQHandler          ; 0x34184242
+
+

Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI5_IRQHandler:
+  0x34184244:  E7FE         B          SPI5_IRQHandler          ; 0x34184244
+
+

Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI6_IRQHandler:
+  0x34184246:  E7FE         B          SPI6_IRQHandler          ; 0x34184246
+
+

Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART1_IRQHandler:
+  0x34184248:  E7FE         B          USART1_IRQHandler        ; 0x34184248
+
+

Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART2_IRQHandler:
+  0x3418424A:  E7FE         B          USART2_IRQHandler        ; 0x3418424A
+
+

Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART3_IRQHandler:
+  0x3418424C:  E7FE         B          USART3_IRQHandler        ; 0x3418424C
+
+

Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART4_IRQHandler:
+  0x3418424E:  E7FE         B          UART4_IRQHandler         ; 0x3418424E
+
+

Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART5_IRQHandler:
+  0x34184250:  E7FE         B          UART5_IRQHandler         ; 0x34184250
+
+

Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART6_IRQHandler:
+  0x34184252:  E7FE         B          USART6_IRQHandler        ; 0x34184252
+
+

Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART7_IRQHandler:
+  0x34184254:  E7FE         B          UART7_IRQHandler         ; 0x34184254
+
+

Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART8_IRQHandler:
+  0x34184256:  E7FE         B          UART8_IRQHandler         ; 0x34184256
+
+

Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART9_IRQHandler:
+  0x34184258:  E7FE         B          UART9_IRQHandler         ; 0x34184258
+
+

Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART10_IRQHandler:
+  0x3418425A:  E7FE         B          USART10_IRQHandler       ; 0x3418425A
+
+

Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPUART1_IRQHandler:
+  0x3418425C:  E7FE         B          LPUART1_IRQHandler       ; 0x3418425C
+
+

Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
XSPI1_IRQHandler:
+  0x3418425E:  E7FE         B          XSPI1_IRQHandler         ; 0x3418425E
+
+

Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
XSPI2_IRQHandler:
+  0x34184260:  E7FE         B          XSPI2_IRQHandler         ; 0x34184260
+
+

Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
XSPI3_IRQHandler:
+  0x34184262:  E7FE         B          XSPI3_IRQHandler         ; 0x34184262
+
+

Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FMC_IRQHandler:
+  0x34184264:  E7FE         B          FMC_IRQHandler           ; 0x34184264
+
+

Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SDMMC1_IRQHandler:
+  0x34184266:  E7FE         B          SDMMC1_IRQHandler        ; 0x34184266
+
+

Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SDMMC2_IRQHandler:
+  0x34184268:  E7FE         B          SDMMC2_IRQHandler        ; 0x34184268
+
+

Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UCPD1_IRQHandler:
+  0x3418426A:  E7FE         B          UCPD1_IRQHandler         ; 0x3418426A
+
+

Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USB1_OTG_HS_IRQHandler:
+  0x3418426C:  E7FE         B          USB1_OTG_HS_IRQHandler   ; 0x3418426C
+
+

Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USB2_OTG_HS_IRQHandler:
+  0x3418426E:  E7FE         B          USB2_OTG_HS_IRQHandler   ; 0x3418426E
+
+

Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ETH1_IRQHandler:
+  0x34184270:  E7FE         B          ETH1_IRQHandler          ; 0x34184270
+
+

Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN1_IT0_IRQHandler:
+  0x34184272:  E7FE         B          FDCAN1_IT0_IRQHandler    ; 0x34184272
+
+

Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN1_IT1_IRQHandler:
+  0x34184274:  E7FE         B          FDCAN1_IT1_IRQHandler    ; 0x34184274
+
+

Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN2_IT0_IRQHandler:
+  0x34184276:  E7FE         B          FDCAN2_IT0_IRQHandler    ; 0x34184276
+
+

Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN2_IT1_IRQHandler:
+  0x34184278:  E7FE         B          FDCAN2_IT1_IRQHandler    ; 0x34184278
+
+

Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN3_IT0_IRQHandler:
+  0x3418427A:  E7FE         B          FDCAN3_IT0_IRQHandler    ; 0x3418427A
+
+

Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN3_IT1_IRQHandler:
+  0x3418427C:  E7FE         B          FDCAN3_IT1_IRQHandler    ; 0x3418427C
+
+

Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN_CU_IRQHandler:
+  0x3418427E:  E7FE         B          FDCAN_CU_IRQHandler      ; 0x3418427E
+
+

Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDIOS_IRQHandler:
+  0x34184280:  E7FE         B          MDIOS_IRQHandler         ; 0x34184280
+
+

Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DCMI_PSSI_IRQHandler:
+  0x34184282:  E7FE         B          DCMI_PSSI_IRQHandler     ; 0x34184282
+
+

Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
WAKEUP_PIN_IRQHandler:
+  0x34184284:  E7FE         B          WAKEUP_PIN_IRQHandler    ; 0x34184284
+
+

Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CTI_INT0_IRQHandler:
+  0x34184286:  E7FE         B          CTI_INT0_IRQHandler      ; 0x34184286
+
+

Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CTI_INT1_IRQHandler:
+  0x34184288:  E7FE         B          CTI_INT1_IRQHandler      ; 0x34184288
+
+

Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_UP_IRQHandler:
+  0x3418428A:  E7FE         B          LTDC_UP_IRQHandler       ; 0x3418428A
+
+

Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_UP_ERR_IRQHandler:
+  0x3418428C:  E7FE         B          LTDC_UP_ERR_IRQHandler   ; 0x3418428C
+
+

Section .rodata..L.str.20 from blto2_FSBL_lto.o, size=106, align=1

+ +
+  0x3418428E:  44           DC.B       0x44                     ; 'D'
+  0x3418428F:  3A           DC.B       0x3A                     ; ':'
+  0x34184290:  5C           DC.B       0x5C                     ; '\\'
+  0x34184291:  50           DC.B       0x50                     ; 'P'
+  0x34184292:  72           DC.B       0x72                     ; 'r'
+  0x34184293:  6F           DC.B       0x6F                     ; 'o'
+  0x34184294:  6A           DC.B       0x6A                     ; 'j'
+  0x34184295:  65           DC.B       0x65                     ; 'e'
+  0x34184296:  6B           DC.B       0x6B                     ; 'k'
+  0x34184297:  74           DC.B       0x74                     ; 't'
+  0x34184298:  65           DC.B       0x65                     ; 'e'
+  0x34184299:  5C           DC.B       0x5C                     ; '\\'
+  0x3418429A:  68           DC.B       0x68                     ; 'h'
+  0x3418429B:  61           DC.B       0x61                     ; 'a'
+  0x3418429C:  64           DC.B       0x64                     ; 'd'
+  0x3418429D:  65           DC.B       0x65                     ; 'e'
+  0x3418429E:  77           DC.B       0x77                     ; 'w'
+  0x3418429F:  65           DC.B       0x65                     ; 'e'
+  0x341842A0:  5F           DC.B       0x5F                     ; '_'
+  0x341842A1:  62           DC.B       0x62                     ; 'b'
+  0x341842A2:  6C           DC.B       0x6C                     ; 'l'
+  0x341842A3:  74           DC.B       0x74                     ; 't'
+  0x341842A4:  6F           DC.B       0x6F                     ; 'o'
+  0x341842A5:  32           DC.B       0x32                     ; '2'
+  0x341842A6:  5C           DC.B       0x5C                     ; '\\'
+  0x341842A7:  74           DC.B       0x74                     ; 't'
+  0x341842A8:  72           DC.B       0x72                     ; 'r'
+  0x341842A9:  75           DC.B       0x75                     ; 'u'
+  0x341842AA:  6E           DC.B       0x6E                     ; 'n'
+  0x341842AB:  6B           DC.B       0x6B                     ; 'k'
+  0x341842AC:  5C           DC.B       0x5C                     ; '\\'
+  0x341842AD:  66           DC.B       0x66                     ; 'f'
+  0x341842AE:  69           DC.B       0x69                     ; 'i'
+  0x341842AF:  72           DC.B       0x72                     ; 'r'
+  0x341842B0:  6D           DC.B       0x6D                     ; 'm'
+  0x341842B1:  77           DC.B       0x77                     ; 'w'
+  0x341842B2:  61           DC.B       0x61                     ; 'a'
+  0x341842B3:  72           DC.B       0x72                     ; 'r'
+  0x341842B4:  65           DC.B       0x65                     ; 'e'
+  0x341842B5:  5C           DC.B       0x5C                     ; '\\'
+  0x341842B6:  46           DC.B       0x46                     ; 'F'
+  0x341842B7:  53           DC.B       0x53                     ; 'S'
+  0x341842B8:  42           DC.B       0x42                     ; 'B'
+  0x341842B9:  4C           DC.B       0x4C                     ; 'L'
+  0x341842BA:  5C           DC.B       0x5C                     ; '\\'
+  0x341842BB:  43           DC.B       0x43                     ; 'C'
+  0x341842BC:  75           DC.B       0x75                     ; 'u'
+  0x341842BD:  62           DC.B       0x62                     ; 'b'
+  0x341842BE:  65           DC.B       0x65                     ; 'e'
+  0x341842BF:  4D           DC.B       0x4D                     ; 'M'
+  0x341842C0:  58           DC.B       0x58                     ; 'X'
+  0x341842C1:  5C           DC.B       0x5C                     ; '\\'
+  0x341842C2:  44           DC.B       0x44                     ; 'D'
+  0x341842C3:  72           DC.B       0x72                     ; 'r'
+  0x341842C4:  69           DC.B       0x69                     ; 'i'
+  0x341842C5:  76           DC.B       0x76                     ; 'v'
+  0x341842C6:  65           DC.B       0x65                     ; 'e'
+  0x341842C7:  72           DC.B       0x72                     ; 'r'
+  0x341842C8:  73           DC.B       0x73                     ; 's'
+  0x341842C9:  5C           DC.B       0x5C                     ; '\\'
+  0x341842CA:  53           DC.B       0x53                     ; 'S'
+  0x341842CB:  54           DC.B       0x54                     ; 'T'
+  0x341842CC:  4D           DC.B       0x4D                     ; 'M'
+  0x341842CD:  33           DC.B       0x33                     ; '3'
+  0x341842CE:  32           DC.B       0x32                     ; '2'
+  0x341842CF:  4E           DC.B       0x4E                     ; 'N'
+  0x341842D0:  36           DC.B       0x36                     ; '6'
+  0x341842D1:  78           DC.B       0x78                     ; 'x'
+  0x341842D2:  78           DC.B       0x78                     ; 'x'
+  0x341842D3:  5F           DC.B       0x5F                     ; '_'
+  0x341842D4:  48           DC.B       0x48                     ; 'H'
+  0x341842D5:  41           DC.B       0x41                     ; 'A'
+  0x341842D6:  4C           DC.B       0x4C                     ; 'L'
+  0x341842D7:  5F           DC.B       0x5F                     ; '_'
+  0x341842D8:  44           DC.B       0x44                     ; 'D'
+  0x341842D9:  72           DC.B       0x72                     ; 'r'
+  0x341842DA:  69           DC.B       0x69                     ; 'i'
+  0x341842DB:  76           DC.B       0x76                     ; 'v'
+  0x341842DC:  65           DC.B       0x65                     ; 'e'
+  0x341842DD:  72           DC.B       0x72                     ; 'r'
+  0x341842DE:  5C           DC.B       0x5C                     ; '\\'
+  0x341842DF:  53           DC.B       0x53                     ; 'S'
+  0x341842E0:  72           DC.B       0x72                     ; 'r'
+  0x341842E1:  63           DC.B       0x63                     ; 'c'
+  0x341842E2:  5C           DC.B       0x5C                     ; '\\'
+  0x341842E3:  73           DC.B       0x73                     ; 's'
+  0x341842E4:  74           DC.B       0x74                     ; 't'
+  0x341842E5:  6D           DC.B       0x6D                     ; 'm'
+  0x341842E6:  33           DC.B       0x33                     ; '3'
+  0x341842E7:  32           DC.B       0x32                     ; '2'
+  0x341842E8:  6E           DC.B       0x6E                     ; 'n'
+  0x341842E9:  36           DC.B       0x36                     ; '6'
+  0x341842EA:  78           DC.B       0x78                     ; 'x'
+  0x341842EB:  78           DC.B       0x78                     ; 'x'
+  0x341842EC:  5F           DC.B       0x5F                     ; '_'
+  0x341842ED:  68           DC.B       0x68                     ; 'h'
+  0x341842EE:  61           DC.B       0x61                     ; 'a'
+  0x341842EF:  6C           DC.B       0x6C                     ; 'l'
+  0x341842F0:  5F           DC.B       0x5F                     ; '_'
+  0x341842F1:  67           DC.B       0x67                     ; 'g'
+  0x341842F2:  70           DC.B       0x70                     ; 'p'
+  0x341842F3:  69           DC.B       0x69                     ; 'i'
+  0x341842F4:  6F           DC.B       0x6F                     ; 'o'
+  0x341842F5:  2E           DC.B       0x2E                     ; '.'
+  0x341842F6:  63           DC.B       0x63                     ; 'c'
+  0x341842F7:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.35 from blto2_FSBL_lto.o, size=105, align=1

+ +
+  0x341842F8:  44           DC.B       0x44                     ; 'D'
+  0x341842F9:  3A           DC.B       0x3A                     ; ':'
+  0x341842FA:  5C           DC.B       0x5C                     ; '\\'
+  0x341842FB:  50           DC.B       0x50                     ; 'P'
+  0x341842FC:  72           DC.B       0x72                     ; 'r'
+  0x341842FD:  6F           DC.B       0x6F                     ; 'o'
+  0x341842FE:  6A           DC.B       0x6A                     ; 'j'
+  0x341842FF:  65           DC.B       0x65                     ; 'e'
+  0x34184300:  6B           DC.B       0x6B                     ; 'k'
+  0x34184301:  74           DC.B       0x74                     ; 't'
+  0x34184302:  65           DC.B       0x65                     ; 'e'
+  0x34184303:  5C           DC.B       0x5C                     ; '\\'
+  0x34184304:  68           DC.B       0x68                     ; 'h'
+  0x34184305:  61           DC.B       0x61                     ; 'a'
+  0x34184306:  64           DC.B       0x64                     ; 'd'
+  0x34184307:  65           DC.B       0x65                     ; 'e'
+  0x34184308:  77           DC.B       0x77                     ; 'w'
+  0x34184309:  65           DC.B       0x65                     ; 'e'
+  0x3418430A:  5F           DC.B       0x5F                     ; '_'
+  0x3418430B:  62           DC.B       0x62                     ; 'b'
+  0x3418430C:  6C           DC.B       0x6C                     ; 'l'
+  0x3418430D:  74           DC.B       0x74                     ; 't'
+  0x3418430E:  6F           DC.B       0x6F                     ; 'o'
+  0x3418430F:  32           DC.B       0x32                     ; '2'
+  0x34184310:  5C           DC.B       0x5C                     ; '\\'
+  0x34184311:  74           DC.B       0x74                     ; 't'
+  0x34184312:  72           DC.B       0x72                     ; 'r'
+  0x34184313:  75           DC.B       0x75                     ; 'u'
+  0x34184314:  6E           DC.B       0x6E                     ; 'n'
+  0x34184315:  6B           DC.B       0x6B                     ; 'k'
+  0x34184316:  5C           DC.B       0x5C                     ; '\\'
+  0x34184317:  66           DC.B       0x66                     ; 'f'
+  0x34184318:  69           DC.B       0x69                     ; 'i'
+  0x34184319:  72           DC.B       0x72                     ; 'r'
+  0x3418431A:  6D           DC.B       0x6D                     ; 'm'
+  0x3418431B:  77           DC.B       0x77                     ; 'w'
+  0x3418431C:  61           DC.B       0x61                     ; 'a'
+  0x3418431D:  72           DC.B       0x72                     ; 'r'
+  0x3418431E:  65           DC.B       0x65                     ; 'e'
+  0x3418431F:  5C           DC.B       0x5C                     ; '\\'
+  0x34184320:  46           DC.B       0x46                     ; 'F'
+  0x34184321:  53           DC.B       0x53                     ; 'S'
+  0x34184322:  42           DC.B       0x42                     ; 'B'
+  0x34184323:  4C           DC.B       0x4C                     ; 'L'
+  0x34184324:  5C           DC.B       0x5C                     ; '\\'
+  0x34184325:  43           DC.B       0x43                     ; 'C'
+  0x34184326:  75           DC.B       0x75                     ; 'u'
+  0x34184327:  62           DC.B       0x62                     ; 'b'
+  0x34184328:  65           DC.B       0x65                     ; 'e'
+  0x34184329:  4D           DC.B       0x4D                     ; 'M'
+  0x3418432A:  58           DC.B       0x58                     ; 'X'
+  0x3418432B:  5C           DC.B       0x5C                     ; '\\'
+  0x3418432C:  44           DC.B       0x44                     ; 'D'
+  0x3418432D:  72           DC.B       0x72                     ; 'r'
+  0x3418432E:  69           DC.B       0x69                     ; 'i'
+  0x3418432F:  76           DC.B       0x76                     ; 'v'
+  0x34184330:  65           DC.B       0x65                     ; 'e'
+  0x34184331:  72           DC.B       0x72                     ; 'r'
+  0x34184332:  73           DC.B       0x73                     ; 's'
+  0x34184333:  5C           DC.B       0x5C                     ; '\\'
+  0x34184334:  53           DC.B       0x53                     ; 'S'
+  0x34184335:  54           DC.B       0x54                     ; 'T'
+  0x34184336:  4D           DC.B       0x4D                     ; 'M'
+  0x34184337:  33           DC.B       0x33                     ; '3'
+  0x34184338:  32           DC.B       0x32                     ; '2'
+  0x34184339:  4E           DC.B       0x4E                     ; 'N'
+  0x3418433A:  36           DC.B       0x36                     ; '6'
+  0x3418433B:  78           DC.B       0x78                     ; 'x'
+  0x3418433C:  78           DC.B       0x78                     ; 'x'
+  0x3418433D:  5F           DC.B       0x5F                     ; '_'
+  0x3418433E:  48           DC.B       0x48                     ; 'H'
+  0x3418433F:  41           DC.B       0x41                     ; 'A'
+  0x34184340:  4C           DC.B       0x4C                     ; 'L'
+  0x34184341:  5F           DC.B       0x5F                     ; '_'
+  0x34184342:  44           DC.B       0x44                     ; 'D'
+  0x34184343:  72           DC.B       0x72                     ; 'r'
+  0x34184344:  69           DC.B       0x69                     ; 'i'
+  0x34184345:  76           DC.B       0x76                     ; 'v'
+  0x34184346:  65           DC.B       0x65                     ; 'e'
+  0x34184347:  72           DC.B       0x72                     ; 'r'
+  0x34184348:  5C           DC.B       0x5C                     ; '\\'
+  0x34184349:  53           DC.B       0x53                     ; 'S'
+  0x3418434A:  72           DC.B       0x72                     ; 'r'
+  0x3418434B:  63           DC.B       0x63                     ; 'c'
+  0x3418434C:  5C           DC.B       0x5C                     ; '\\'
+  0x3418434D:  73           DC.B       0x73                     ; 's'
+  0x3418434E:  74           DC.B       0x74                     ; 't'
+  0x3418434F:  6D           DC.B       0x6D                     ; 'm'
+  0x34184350:  33           DC.B       0x33                     ; '3'
+  0x34184351:  32           DC.B       0x32                     ; '2'
+  0x34184352:  6E           DC.B       0x6E                     ; 'n'
+  0x34184353:  36           DC.B       0x36                     ; '6'
+  0x34184354:  78           DC.B       0x78                     ; 'x'
+  0x34184355:  78           DC.B       0x78                     ; 'x'
+  0x34184356:  5F           DC.B       0x5F                     ; '_'
+  0x34184357:  68           DC.B       0x68                     ; 'h'
+  0x34184358:  61           DC.B       0x61                     ; 'a'
+  0x34184359:  6C           DC.B       0x6C                     ; 'l'
+  0x3418435A:  5F           DC.B       0x5F                     ; '_'
+  0x3418435B:  72           DC.B       0x72                     ; 'r'
+  0x3418435C:  63           DC.B       0x63                     ; 'c'
+  0x3418435D:  63           DC.B       0x63                     ; 'c'
+  0x3418435E:  2E           DC.B       0x2E                     ; '.'
+  0x3418435F:  63           DC.B       0x63                     ; 'c'
+  0x34184360:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.uwTickFreq from blto2_FSBL_lto.o, size=1, align=1

+ +
+
uwTickFreq:
+  0x34184361:  01           DC.B       0x01                     ; '\x01'
+
+

Section .init_array from STM32N6xx_Startup.o, size=4, align=4

+ +
+  0x34184364:  34180761     DC.W       SystemCoreClockUpdate
+
+

Section .rodata..L.str.10 from blto2_FSBL_lto.o, size=108, align=1

+ +
+  0x34184368:  44           DC.B       0x44                     ; 'D'
+  0x34184369:  3A           DC.B       0x3A                     ; ':'
+  0x3418436A:  5C           DC.B       0x5C                     ; '\\'
+  0x3418436B:  50           DC.B       0x50                     ; 'P'
+  0x3418436C:  72           DC.B       0x72                     ; 'r'
+  0x3418436D:  6F           DC.B       0x6F                     ; 'o'
+  0x3418436E:  6A           DC.B       0x6A                     ; 'j'
+  0x3418436F:  65           DC.B       0x65                     ; 'e'
+  0x34184370:  6B           DC.B       0x6B                     ; 'k'
+  0x34184371:  74           DC.B       0x74                     ; 't'
+  0x34184372:  65           DC.B       0x65                     ; 'e'
+  0x34184373:  5C           DC.B       0x5C                     ; '\\'
+  0x34184374:  68           DC.B       0x68                     ; 'h'
+  0x34184375:  61           DC.B       0x61                     ; 'a'
+  0x34184376:  64           DC.B       0x64                     ; 'd'
+  0x34184377:  65           DC.B       0x65                     ; 'e'
+  0x34184378:  77           DC.B       0x77                     ; 'w'
+  0x34184379:  65           DC.B       0x65                     ; 'e'
+  0x3418437A:  5F           DC.B       0x5F                     ; '_'
+  0x3418437B:  62           DC.B       0x62                     ; 'b'
+  0x3418437C:  6C           DC.B       0x6C                     ; 'l'
+  0x3418437D:  74           DC.B       0x74                     ; 't'
+  0x3418437E:  6F           DC.B       0x6F                     ; 'o'
+  0x3418437F:  32           DC.B       0x32                     ; '2'
+  0x34184380:  5C           DC.B       0x5C                     ; '\\'
+  0x34184381:  74           DC.B       0x74                     ; 't'
+  0x34184382:  72           DC.B       0x72                     ; 'r'
+  0x34184383:  75           DC.B       0x75                     ; 'u'
+  0x34184384:  6E           DC.B       0x6E                     ; 'n'
+  0x34184385:  6B           DC.B       0x6B                     ; 'k'
+  0x34184386:  5C           DC.B       0x5C                     ; '\\'
+  0x34184387:  66           DC.B       0x66                     ; 'f'
+  0x34184388:  69           DC.B       0x69                     ; 'i'
+  0x34184389:  72           DC.B       0x72                     ; 'r'
+  0x3418438A:  6D           DC.B       0x6D                     ; 'm'
+  0x3418438B:  77           DC.B       0x77                     ; 'w'
+  0x3418438C:  61           DC.B       0x61                     ; 'a'
+  0x3418438D:  72           DC.B       0x72                     ; 'r'
+  0x3418438E:  65           DC.B       0x65                     ; 'e'
+  0x3418438F:  5C           DC.B       0x5C                     ; '\\'
+  0x34184390:  46           DC.B       0x46                     ; 'F'
+  0x34184391:  53           DC.B       0x53                     ; 'S'
+  0x34184392:  42           DC.B       0x42                     ; 'B'
+  0x34184393:  4C           DC.B       0x4C                     ; 'L'
+  0x34184394:  5C           DC.B       0x5C                     ; '\\'
+  0x34184395:  43           DC.B       0x43                     ; 'C'
+  0x34184396:  75           DC.B       0x75                     ; 'u'
+  0x34184397:  62           DC.B       0x62                     ; 'b'
+  0x34184398:  65           DC.B       0x65                     ; 'e'
+  0x34184399:  4D           DC.B       0x4D                     ; 'M'
+  0x3418439A:  58           DC.B       0x58                     ; 'X'
+  0x3418439B:  5C           DC.B       0x5C                     ; '\\'
+  0x3418439C:  44           DC.B       0x44                     ; 'D'
+  0x3418439D:  72           DC.B       0x72                     ; 'r'
+  0x3418439E:  69           DC.B       0x69                     ; 'i'
+  0x3418439F:  76           DC.B       0x76                     ; 'v'
+  0x341843A0:  65           DC.B       0x65                     ; 'e'
+  0x341843A1:  72           DC.B       0x72                     ; 'r'
+  0x341843A2:  73           DC.B       0x73                     ; 's'
+  0x341843A3:  5C           DC.B       0x5C                     ; '\\'
+  0x341843A4:  53           DC.B       0x53                     ; 'S'
+  0x341843A5:  54           DC.B       0x54                     ; 'T'
+  0x341843A6:  4D           DC.B       0x4D                     ; 'M'
+  0x341843A7:  33           DC.B       0x33                     ; '3'
+  0x341843A8:  32           DC.B       0x32                     ; '2'
+  0x341843A9:  4E           DC.B       0x4E                     ; 'N'
+  0x341843AA:  36           DC.B       0x36                     ; '6'
+  0x341843AB:  78           DC.B       0x78                     ; 'x'
+  0x341843AC:  78           DC.B       0x78                     ; 'x'
+  0x341843AD:  5F           DC.B       0x5F                     ; '_'
+  0x341843AE:  48           DC.B       0x48                     ; 'H'
+  0x341843AF:  41           DC.B       0x41                     ; 'A'
+  0x341843B0:  4C           DC.B       0x4C                     ; 'L'
+  0x341843B1:  5F           DC.B       0x5F                     ; '_'
+  0x341843B2:  44           DC.B       0x44                     ; 'D'
+  0x341843B3:  72           DC.B       0x72                     ; 'r'
+  0x341843B4:  69           DC.B       0x69                     ; 'i'
+  0x341843B5:  76           DC.B       0x76                     ; 'v'
+  0x341843B6:  65           DC.B       0x65                     ; 'e'
+  0x341843B7:  72           DC.B       0x72                     ; 'r'
+  0x341843B8:  5C           DC.B       0x5C                     ; '\\'
+  0x341843B9:  53           DC.B       0x53                     ; 'S'
+  0x341843BA:  72           DC.B       0x72                     ; 'r'
+  0x341843BB:  63           DC.B       0x63                     ; 'c'
+  0x341843BC:  5C           DC.B       0x5C                     ; '\\'
+  0x341843BD:  73           DC.B       0x73                     ; 's'
+  0x341843BE:  74           DC.B       0x74                     ; 't'
+  0x341843BF:  6D           DC.B       0x6D                     ; 'm'
+  0x341843C0:  33           DC.B       0x33                     ; '3'
+  0x341843C1:  32           DC.B       0x32                     ; '2'
+  0x341843C2:  6E           DC.B       0x6E                     ; 'n'
+  0x341843C3:  36           DC.B       0x36                     ; '6'
+  0x341843C4:  78           DC.B       0x78                     ; 'x'
+  0x341843C5:  78           DC.B       0x78                     ; 'x'
+  0x341843C6:  5F           DC.B       0x5F                     ; '_'
+  0x341843C7:  68           DC.B       0x68                     ; 'h'
+  0x341843C8:  61           DC.B       0x61                     ; 'a'
+  0x341843C9:  6C           DC.B       0x6C                     ; 'l'
+  0x341843CA:  5F           DC.B       0x5F                     ; '_'
+  0x341843CB:  63           DC.B       0x63                     ; 'c'
+  0x341843CC:  6F           DC.B       0x6F                     ; 'o'
+  0x341843CD:  72           DC.B       0x72                     ; 'r'
+  0x341843CE:  74           DC.B       0x74                     ; 't'
+  0x341843CF:  65           DC.B       0x65                     ; 'e'
+  0x341843D0:  78           DC.B       0x78                     ; 'x'
+  0x341843D1:  2E           DC.B       0x2E                     ; '.'
+  0x341843D2:  63           DC.B       0x63                     ; 'c'
+  0x341843D3:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..L.str.28 from blto2_FSBL_lto.o, size=108, align=1

+ +
+  0x341843D4:  44           DC.B       0x44                     ; 'D'
+  0x341843D5:  3A           DC.B       0x3A                     ; ':'
+  0x341843D6:  5C           DC.B       0x5C                     ; '\\'
+  0x341843D7:  50           DC.B       0x50                     ; 'P'
+  0x341843D8:  72           DC.B       0x72                     ; 'r'
+  0x341843D9:  6F           DC.B       0x6F                     ; 'o'
+  0x341843DA:  6A           DC.B       0x6A                     ; 'j'
+  0x341843DB:  65           DC.B       0x65                     ; 'e'
+  0x341843DC:  6B           DC.B       0x6B                     ; 'k'
+  0x341843DD:  74           DC.B       0x74                     ; 't'
+  0x341843DE:  65           DC.B       0x65                     ; 'e'
+  0x341843DF:  5C           DC.B       0x5C                     ; '\\'
+  0x341843E0:  68           DC.B       0x68                     ; 'h'
+  0x341843E1:  61           DC.B       0x61                     ; 'a'
+  0x341843E2:  64           DC.B       0x64                     ; 'd'
+  0x341843E3:  65           DC.B       0x65                     ; 'e'
+  0x341843E4:  77           DC.B       0x77                     ; 'w'
+  0x341843E5:  65           DC.B       0x65                     ; 'e'
+  0x341843E6:  5F           DC.B       0x5F                     ; '_'
+  0x341843E7:  62           DC.B       0x62                     ; 'b'
+  0x341843E8:  6C           DC.B       0x6C                     ; 'l'
+  0x341843E9:  74           DC.B       0x74                     ; 't'
+  0x341843EA:  6F           DC.B       0x6F                     ; 'o'
+  0x341843EB:  32           DC.B       0x32                     ; '2'
+  0x341843EC:  5C           DC.B       0x5C                     ; '\\'
+  0x341843ED:  74           DC.B       0x74                     ; 't'
+  0x341843EE:  72           DC.B       0x72                     ; 'r'
+  0x341843EF:  75           DC.B       0x75                     ; 'u'
+  0x341843F0:  6E           DC.B       0x6E                     ; 'n'
+  0x341843F1:  6B           DC.B       0x6B                     ; 'k'
+  0x341843F2:  5C           DC.B       0x5C                     ; '\\'
+  0x341843F3:  66           DC.B       0x66                     ; 'f'
+  0x341843F4:  69           DC.B       0x69                     ; 'i'
+  0x341843F5:  72           DC.B       0x72                     ; 'r'
+  0x341843F6:  6D           DC.B       0x6D                     ; 'm'
+  0x341843F7:  77           DC.B       0x77                     ; 'w'
+  0x341843F8:  61           DC.B       0x61                     ; 'a'
+  0x341843F9:  72           DC.B       0x72                     ; 'r'
+  0x341843FA:  65           DC.B       0x65                     ; 'e'
+  0x341843FB:  5C           DC.B       0x5C                     ; '\\'
+  0x341843FC:  46           DC.B       0x46                     ; 'F'
+  0x341843FD:  53           DC.B       0x53                     ; 'S'
+  0x341843FE:  42           DC.B       0x42                     ; 'B'
+  0x341843FF:  4C           DC.B       0x4C                     ; 'L'
+  0x34184400:  5C           DC.B       0x5C                     ; '\\'
+  0x34184401:  43           DC.B       0x43                     ; 'C'
+  0x34184402:  75           DC.B       0x75                     ; 'u'
+  0x34184403:  62           DC.B       0x62                     ; 'b'
+  0x34184404:  65           DC.B       0x65                     ; 'e'
+  0x34184405:  4D           DC.B       0x4D                     ; 'M'
+  0x34184406:  58           DC.B       0x58                     ; 'X'
+  0x34184407:  5C           DC.B       0x5C                     ; '\\'
+  0x34184408:  44           DC.B       0x44                     ; 'D'
+  0x34184409:  72           DC.B       0x72                     ; 'r'
+  0x3418440A:  69           DC.B       0x69                     ; 'i'
+  0x3418440B:  76           DC.B       0x76                     ; 'v'
+  0x3418440C:  65           DC.B       0x65                     ; 'e'
+  0x3418440D:  72           DC.B       0x72                     ; 'r'
+  0x3418440E:  73           DC.B       0x73                     ; 's'
+  0x3418440F:  5C           DC.B       0x5C                     ; '\\'
+  0x34184410:  53           DC.B       0x53                     ; 'S'
+  0x34184411:  54           DC.B       0x54                     ; 'T'
+  0x34184412:  4D           DC.B       0x4D                     ; 'M'
+  0x34184413:  33           DC.B       0x33                     ; '3'
+  0x34184414:  32           DC.B       0x32                     ; '2'
+  0x34184415:  4E           DC.B       0x4E                     ; 'N'
+  0x34184416:  36           DC.B       0x36                     ; '6'
+  0x34184417:  78           DC.B       0x78                     ; 'x'
+  0x34184418:  78           DC.B       0x78                     ; 'x'
+  0x34184419:  5F           DC.B       0x5F                     ; '_'
+  0x3418441A:  48           DC.B       0x48                     ; 'H'
+  0x3418441B:  41           DC.B       0x41                     ; 'A'
+  0x3418441C:  4C           DC.B       0x4C                     ; 'L'
+  0x3418441D:  5F           DC.B       0x5F                     ; '_'
+  0x3418441E:  44           DC.B       0x44                     ; 'D'
+  0x3418441F:  72           DC.B       0x72                     ; 'r'
+  0x34184420:  69           DC.B       0x69                     ; 'i'
+  0x34184421:  76           DC.B       0x76                     ; 'v'
+  0x34184422:  65           DC.B       0x65                     ; 'e'
+  0x34184423:  72           DC.B       0x72                     ; 'r'
+  0x34184424:  5C           DC.B       0x5C                     ; '\\'
+  0x34184425:  53           DC.B       0x53                     ; 'S'
+  0x34184426:  72           DC.B       0x72                     ; 'r'
+  0x34184427:  63           DC.B       0x63                     ; 'c'
+  0x34184428:  5C           DC.B       0x5C                     ; '\\'
+  0x34184429:  73           DC.B       0x73                     ; 's'
+  0x3418442A:  74           DC.B       0x74                     ; 't'
+  0x3418442B:  6D           DC.B       0x6D                     ; 'm'
+  0x3418442C:  33           DC.B       0x33                     ; '3'
+  0x3418442D:  32           DC.B       0x32                     ; '2'
+  0x3418442E:  6E           DC.B       0x6E                     ; 'n'
+  0x3418442F:  36           DC.B       0x36                     ; '6'
+  0x34184430:  78           DC.B       0x78                     ; 'x'
+  0x34184431:  78           DC.B       0x78                     ; 'x'
+  0x34184432:  5F           DC.B       0x5F                     ; '_'
+  0x34184433:  68           DC.B       0x68                     ; 'h'
+  0x34184434:  61           DC.B       0x61                     ; 'a'
+  0x34184435:  6C           DC.B       0x6C                     ; 'l'
+  0x34184436:  5F           DC.B       0x5F                     ; '_'
+  0x34184437:  70           DC.B       0x70                     ; 'p'
+  0x34184438:  77           DC.B       0x77                     ; 'w'
+  0x34184439:  72           DC.B       0x72                     ; 'r'
+  0x3418443A:  5F           DC.B       0x5F                     ; '_'
+  0x3418443B:  65           DC.B       0x65                     ; 'e'
+  0x3418443C:  78           DC.B       0x78                     ; 'x'
+  0x3418443D:  2E           DC.B       0x2E                     ; '.'
+  0x3418443E:  63           DC.B       0x63                     ; 'c'
+  0x3418443F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4

+ +
+
uwTick:
+  0x34184440:  44           DC.B       0x44                     ; 'D'
+  0x34184441:  3A           DC.B       0x3A                     ; ':'
+  0x34184442:  5C           DC.B       0x5C                     ; '\\'
+  0x34184443:  50           DC.B       0x50                     ; 'P'
+
+

Section .data.uwTickPrio from blto2_FSBL_lto.o, size=4, align=4

+ +
+
uwTickPrio:
+  0x34184444:  10           DC.B       0x10                     ; '\x10'
+  0x34184445:  00           DC.B       0x00                     ; '\0'
+  0x34184446:  00           DC.B       0x00                     ; '\0'
+  0x34184447:  00           DC.B       0x00                     ; '\0'
+
+

Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4

+ +
+
SystemCoreClock:
+  0x34184448:  00           DC.B       0x00                     ; '\0'
+  0x34184449:  90           DC.B       0x90                     ; '\x90'
+  0x3418444A:  D0           DC.B       0xD0                     ; '\xD0'
+  0x3418444B:  03           DC.B       0x03                     ; '\x03'
+
+

Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4

+ +
+
__SEGGER_init_ctors:
+  0x3418444C:  B500         PUSH       123LR}
+  0x3418444E:  4806         LDR        R0, =0x34184364          ; [PC, #24] [0x34184468] 
+  0x34184450:  4906         LDR        R1, =0x34184368          ; [PC, #24] [0x3418446C] 
+
.L1:
+  0x34184452:  4288         CMP        R0, R1
+  0x34184454:  D005         BEQ        46L2                      ; 0x34184462
+  0x34184456:  6802         LDR        R2, [R0]
+  0x34184458:  3004         ADDS       R0, #4
+  0x3418445A:  B403         PUSH       123R0-R1}
+  0x3418445C:  4790         BLX        R2
+  0x3418445E:  BC03         POP        123R0-R1}
+  0x34184460:  E7F7         B          46L1                      ; 0x34184452
+
.L2:
+  0x34184462:  BC08         POP        123R3}
+  0x34184464:  4718         BX         R3
+  0x34184466:  0000         NOP
+  0x34184468:  34184364     DC.W       34184364               ; R_ARM_ABS32
+  0x3418446C:  34184368     DC.W       34184368               ; R_ARM_ABS32
+
+

Section .segger.init.table from [ Linker created ], size=52, align=4

+ +
+  0x34184470:  341844B1     DC.W       __SEGGER_init_zero
+  0x34184474:  40           DC.B       0x40                     ; '@'
+  0x34184475:  44           DC.B       0x44                     ; 'D'
+  0x34184476:  18           DC.B       0x18                     ; '\x18'
+  0x34184477:  34           DC.B       0x34                     ; '4'
+  0x34184478:  04           DC.B       0x04                     ; '\x04'
+  0x34184479:  00           DC.B       0x00                     ; '\0'
+  0x3418447A:  00           DC.B       0x00                     ; '\0'
+  0x3418447B:  00           DC.B       0x00                     ; '\0'
+  0x3418447C:  341844C3     DC.W       __SEGGER_init_copy
+  0x34184480:  61           DC.B       0x61                     ; 'a'
+  0x34184481:  43           DC.B       0x43                     ; 'C'
+  0x34184482:  18           DC.B       0x18                     ; '\x18'
+  0x34184483:  34           DC.B       0x34                     ; '4'
+  0x34184484:  341844A4     DC.W       341844A4               ; R_ARM_ABS32
+  0x34184488:  01           DC.B       0x01                     ; '\x01'
+  0x34184489:  00           DC.B       0x00                     ; '\0'
+  0x3418448A:  00           DC.B       0x00                     ; '\0'
+  0x3418448B:  00           DC.B       0x00                     ; '\0'
+  0x3418448C:  341844C3     DC.W       __SEGGER_init_copy
+  0x34184490:  44           DC.B       0x44                     ; 'D'
+  0x34184491:  44           DC.B       0x44                     ; 'D'
+  0x34184492:  18           DC.B       0x18                     ; '\x18'
+  0x34184493:  34           DC.B       0x34                     ; '4'
+  0x34184494:  341844A5     DC.W       341844A5               ; R_ARM_ABS32
+  0x34184498:  08           DC.B       0x08                     ; '\b'
+  0x34184499:  00           DC.B       0x00                     ; '\0'
+  0x3418449A:  00           DC.B       0x00                     ; '\0'
+  0x3418449B:  00           DC.B       0x00                     ; '\0'
+  0x3418449C:  3418444D     DC.W       __SEGGER_init_ctors
+  0x341844A0:  34181A73     DC.W       __SEGGER_init_done
+
+

Section .segger.init.data from [ Linker created ], size=12, align=4

+ +
+  0x341844A4:  01           DC.B       0x01                     ; '\x01'
+  0x341844A5:  10           DC.B       0x10                     ; '\x10'
+  0x341844A6:  00           DC.B       0x00                     ; '\0'
+  0x341844A7:  00           DC.B       0x00                     ; '\0'
+  0x341844A8:  00           DC.B       0x00                     ; '\0'
+  0x341844A9:  00           DC.B       0x00                     ; '\0'
+  0x341844AA:  90           DC.B       0x90                     ; '\x90'
+  0x341844AB:  D0           DC.B       0xD0                     ; '\xD0'
+  0x341844AC:  03           DC.B       0x03                     ; '\x03'
+  0x341844AD:  00           DC.B       0x00                     ; '\0'
+  0x341844AE:  00           DC.B       0x00                     ; '\0'
+  0x341844AF:  00           DC.B       0x00                     ; '\0'
+
+

Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2

+ +
+
__SEGGER_init_zero:
+  0x341844B0:  6820         LDR        R0, [R4]
+  0x341844B2:  6861         LDR        R1, [R4, #4]
+  0x341844B4:  3408         ADDS       R4, #8
+  0x341844B6:  2200         MOVS       R2, #0
+  0x341844B8:  E000         B          46L2                      ; 0x341844BC
+
.L1:
+  0x341844BA:  5442         STRB       R2, [R0, R1]
+
.L2:
+  0x341844BC:  1E49         SUBS       R1, R1, #1
+  0x341844BE:  D5FC         BPL        46L1                      ; 0x341844BA
+  0x341844C0:  4770         BX         LR
+
+

Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2

+ +
+
__SEGGER_init_copy:
+  0x341844C2:  6820         LDR        R0, [R4]
+  0x341844C4:  6861         LDR        R1, [R4, #4]
+  0x341844C6:  68A2         LDR        R2, [R4, #8]
+  0x341844C8:  340C         ADDS       R4, #12
+  0x341844CA:  E001         B          46L2                      ; 0x341844D0
+
.L1:
+  0x341844CC:  5C8B         LDRB       R3, [R1, R2]
+  0x341844CE:  5483         STRB       R3, [R0, R2]
+
.L2:
+  0x341844D0:  1E52         SUBS       R2, R2, #1
+  0x341844D2:  D5FB         BPL        46L1                      ; 0x341844CC
+  0x341844D4:  4770         BX         LR
+
+

Section .bss.block.stack from [ Linker created ], size=16384, align=8

+ +
+(341FC000-341FFFFF excluded)
+
+

LINK SUMMARY

+ + +
+ 16 088 bytes read-only  code    + 
+    491 bytes read-only  data    =  16 579 bytes read-only (total)
+ 16 397 bytes read-write data
+
+ + + + + + + + + + + + + + + + + + + +
NameRangeSizeUsedUnusedAlignment Loss
AXI_RAM234180400-341FFFFF523 26432 980 6.30490 284 93.700 0.00
+ + +
+Link complete: 0 errors.
+
+ Index: trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.htm =================================================================== --- trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.htm (revision 16) +++ trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.htm (revision 16) @@ -0,0 +1,18837 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ + +
+SEGGER ARM Linker 4.44.5 compiled Aug  7 2026 18:47:09
+Copyright (c) 2017-2026 SEGGER Microcontroller GmbH    www.segger.com
+
+ + +
+--add-region:ITCM_RAM=0x00010000@0x10000000
+--add-region:DTCM_RAM=0x00020000@0x30000000
+--add-region:FLEX_RAM=0x00064000@0x34000000
+--add-region:AXI_RAM1=0x0009c000@0x34064000
+--add-region:AXI_RAM2=0x0007fc00@0x34180400
+--add-region:AXI_RAM3=0x00070000@0x34200000
+--add-region:AXI_RAM4=0x00070000@0x34270000
+--add-region:AXI_RAM5=0x00070000@0x342e0000
+--add-region:AXI_RAM6=0x00070000@0x34350000
+--add-region:AXI_RAM7=0x00040000@0x343c0000
+--add-region:AXI_RAM8=0x00020000@0x34400000
+--add-region:AHB_RAM1=0x00004000@0x38000000
+--add-region:AHB_RAM2=0x00004000@0x38004000
+--add-region:BKP_RAM=0x00002000@0x3c000000
+--full-section-headers
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Production/Exe/blto2_FSBL.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=8.1-M.main
+--silent
+-TD:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf
+--defsym=__STACKSIZE__=8192
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=256
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_short_float_long_long
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Production/Exe/blto2_FSBL.elf
+D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Production/Obj/blto2_FSBL_lto.o
+Output/Production/Obj/SEGGER_THUMB_Startup.o
+Output/Production/Obj/stm32n657xx_Vectors.o
+Output/Production/Obj/STM32N6xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/libc_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/prinops_rtt_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_disable_interrupts_locking_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/mbops_timeops_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf'

+ +
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32N6xx_RAM.icf
+Purpose : STM32N6xx linker script for application placement in RAM
+          (to be copied to RAM by bootloader or debugger)
+          for use with the SEGGER Linker.
+Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
+          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
+          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
+          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
+          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
+          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region RAM   = AXI_RAM2;
+
+//
+// Block definitions
+//
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { section .vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in RAMn
+//
+place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
+place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
+place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
+place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
+place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
+place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
+place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.*  };  // This region may be deactivated and not accessible
+place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
+place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
+place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
+
+//
+// RAM Placement
+//
+place at start of RAM                       { section .vectors };                                   // Vector table section
+place in RAM with minimum size order        { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x34180400

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x341804008441024stm32n657xx_Vectors.o
+

place at 0x34200000

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x341FE0008 1928[ Linker created ]
+

"<#14> at line 120, col 45": place in [0x34180400 to 0x341FFFFF] with maximum packing

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
mainCode0x3418074C1 1844blto2_FSBL_lto.o
SysTick_HandlerCode0x34180BEC164blto2_FSBL_lto.o
SystemCoreClockUpdateCode0x34180BFC4004blto2_FSBL_lto.o
HAL_RCC_ClockConfigCode0x34180D8C1 4724blto2_FSBL_lto.o
RCC_IC_CheckPLLSourcesCode0x3418134C1484blto2_FSBL_lto.o
RCCEx_GetPLLSourceFreqCode0x341813E01284blto2_FSBL_lto.o
[.rodata..Lswitch.table.HAL_GPIO_DeInit]Cnst0x34181460644blto2_FSBL_lto.o
[.rodata..Lswitch.table.RCC_PLL_Config]Cnst0x341814A0124blto2_FSBL_lto.o
_startCode0x341814AC204SEGGER_THUMB_Startup.o
reset_handlerCode0x341814C0444STM32N6xx_Startup.o
__aeabi_memclrCode0x341814EC1044strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
NMI_HandlerCode0x3418155424blto2_FSBL_lto.o
PVD_PVM_IRQHandlerCode0x3418155622stm32n657xx_Vectors.o
HardFault_HandlerCode0x3418155824blto2_FSBL_lto.o
DTS_IRQHandlerCode0x3418155A22stm32n657xx_Vectors.o
MemManage_HandlerCode0x3418155C24blto2_FSBL_lto.o
RCC_IRQHandlerCode0x3418155E22stm32n657xx_Vectors.o
BusFault_HandlerCode0x3418156024blto2_FSBL_lto.o
LOCKUP_IRQHandlerCode0x3418156222stm32n657xx_Vectors.o
UsageFault_HandlerCode0x3418156424blto2_FSBL_lto.o
CACHE_ECC_IRQHandlerCode0x3418156622stm32n657xx_Vectors.o
SVC_HandlerCode0x3418156824blto2_FSBL_lto.o
TCM_ECC_IRQHandlerCode0x3418156A22stm32n657xx_Vectors.o
DebugMon_HandlerCode0x3418156C24blto2_FSBL_lto.o
BCK_ECC_IRQHandlerCode0x3418156E22stm32n657xx_Vectors.o
PendSV_HandlerCode0x3418157024blto2_FSBL_lto.o
FPU_IRQHandlerCode0x3418157222stm32n657xx_Vectors.o
SystemInitCode0x341815743024blto2_FSBL_lto.o
RTC_S_IRQHandlerCode0x341816A222stm32n657xx_Vectors.o
HAL_GPIO_InitCode0x341816A44184blto2_FSBL_lto.o
TAMP_IRQHandlerCode0x3418184622stm32n657xx_Vectors.o
HAL_RCC_OscConfigCode0x341818481 7144blto2_FSBL_lto.o
RIFSC_TAMPER_IRQHandlerCode0x34181EFA22stm32n657xx_Vectors.o
RCC_PLL_IsNewConfigCode0x34181EFC1344blto2_FSBL_lto.o
IAC_IRQHandlerCode0x34181F8222stm32n657xx_Vectors.o
RCC_PLL_ConfigCode0x34181F844464blto2_FSBL_lto.o
RCC_S_IRQHandlerCode0x3418214222stm32n657xx_Vectors.o
RTC_IRQHandlerCode0x3418214422stm32n657xx_Vectors.o
IWDG_IRQHandlerCode0x3418214622stm32n657xx_Vectors.o
WWDG_IRQHandlerCode0x3418214822stm32n657xx_Vectors.o
EXTI0_IRQHandlerCode0x3418214A22stm32n657xx_Vectors.o
EXTI1_IRQHandlerCode0x3418214C22stm32n657xx_Vectors.o
EXTI2_IRQHandlerCode0x3418214E22stm32n657xx_Vectors.o
EXTI3_IRQHandlerCode0x3418215022stm32n657xx_Vectors.o
EXTI4_IRQHandlerCode0x3418215222stm32n657xx_Vectors.o
EXTI5_IRQHandlerCode0x3418215422stm32n657xx_Vectors.o
EXTI6_IRQHandlerCode0x3418215622stm32n657xx_Vectors.o
EXTI7_IRQHandlerCode0x3418215822stm32n657xx_Vectors.o
EXTI8_IRQHandlerCode0x3418215A22stm32n657xx_Vectors.o
EXTI9_IRQHandlerCode0x3418215C22stm32n657xx_Vectors.o
EXTI10_IRQHandlerCode0x3418215E22stm32n657xx_Vectors.o
EXTI11_IRQHandlerCode0x3418216022stm32n657xx_Vectors.o
EXTI12_IRQHandlerCode0x3418216222stm32n657xx_Vectors.o
EXTI13_IRQHandlerCode0x3418216422stm32n657xx_Vectors.o
EXTI14_IRQHandlerCode0x3418216622stm32n657xx_Vectors.o
EXTI15_IRQHandlerCode0x3418216822stm32n657xx_Vectors.o
SAES_IRQHandlerCode0x3418216A22stm32n657xx_Vectors.o
CRYP_IRQHandlerCode0x3418216C22stm32n657xx_Vectors.o
PKA_IRQHandlerCode0x3418216E22stm32n657xx_Vectors.o
HASH_IRQHandlerCode0x3418217022stm32n657xx_Vectors.o
RNG_IRQHandlerCode0x3418217222stm32n657xx_Vectors.o
MCE1_IRQHandlerCode0x3418217422stm32n657xx_Vectors.o
MCE2_IRQHandlerCode0x3418217622stm32n657xx_Vectors.o
MCE3_IRQHandlerCode0x3418217822stm32n657xx_Vectors.o
MCE4_IRQHandlerCode0x3418217A22stm32n657xx_Vectors.o
ADC1_2_IRQHandlerCode0x3418217C22stm32n657xx_Vectors.o
CSI_IRQHandlerCode0x3418217E22stm32n657xx_Vectors.o
DCMIPP_IRQHandlerCode0x3418218022stm32n657xx_Vectors.o
PAHB_ERR_IRQHandlerCode0x3418218222stm32n657xx_Vectors.o
NPU0_IRQHandlerCode0x3418218422stm32n657xx_Vectors.o
NPU1_IRQHandlerCode0x3418218622stm32n657xx_Vectors.o
NPU2_IRQHandlerCode0x3418218822stm32n657xx_Vectors.o
NPU3_IRQHandlerCode0x3418218A22stm32n657xx_Vectors.o
CACHEAXI_IRQHandlerCode0x3418218C22stm32n657xx_Vectors.o
LTDC_LO_IRQHandlerCode0x3418218E22stm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandlerCode0x3418219022stm32n657xx_Vectors.o
DMA2D_IRQHandlerCode0x3418219222stm32n657xx_Vectors.o
JPEG_IRQHandlerCode0x3418219422stm32n657xx_Vectors.o
VENC_IRQHandlerCode0x3418219622stm32n657xx_Vectors.o
GFXMMU_IRQHandlerCode0x3418219822stm32n657xx_Vectors.o
GFXTIM_IRQHandlerCode0x3418219A22stm32n657xx_Vectors.o
GPU2D_IRQHandlerCode0x3418219C22stm32n657xx_Vectors.o
GPU2D_ER_IRQHandlerCode0x3418219E22stm32n657xx_Vectors.o
ICACHE_IRQHandlerCode0x341821A022stm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandlerCode0x341821A222stm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandlerCode0x341821A422stm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandlerCode0x341821A622stm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandlerCode0x341821A822stm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandlerCode0x341821AA22stm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandlerCode0x341821AC22stm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandlerCode0x341821AE22stm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandlerCode0x341821B022stm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandlerCode0x341821B222stm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandlerCode0x341821B422stm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandlerCode0x341821B622stm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandlerCode0x341821B822stm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandlerCode0x341821BA22stm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandlerCode0x341821BC22stm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandlerCode0x341821BE22stm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandlerCode0x341821C022stm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandlerCode0x341821C222stm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandlerCode0x341821C422stm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandlerCode0x341821C622stm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandlerCode0x341821C822stm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandlerCode0x341821CA22stm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandlerCode0x341821CC22stm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandlerCode0x341821CE22stm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandlerCode0x341821D022stm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandlerCode0x341821D222stm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandlerCode0x341821D422stm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandlerCode0x341821D622stm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandlerCode0x341821D822stm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandlerCode0x341821DA22stm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandlerCode0x341821DC22stm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandlerCode0x341821DE22stm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandlerCode0x341821E022stm32n657xx_Vectors.o
I2C1_EV_IRQHandlerCode0x341821E222stm32n657xx_Vectors.o
I2C1_ER_IRQHandlerCode0x341821E422stm32n657xx_Vectors.o
I2C2_EV_IRQHandlerCode0x341821E622stm32n657xx_Vectors.o
I2C2_ER_IRQHandlerCode0x341821E822stm32n657xx_Vectors.o
I2C3_EV_IRQHandlerCode0x341821EA22stm32n657xx_Vectors.o
I2C3_ER_IRQHandlerCode0x341821EC22stm32n657xx_Vectors.o
I2C4_EV_IRQHandlerCode0x341821EE22stm32n657xx_Vectors.o
I2C4_ER_IRQHandlerCode0x341821F022stm32n657xx_Vectors.o
I3C1_EV_IRQHandlerCode0x341821F222stm32n657xx_Vectors.o
I3C1_ER_IRQHandlerCode0x341821F422stm32n657xx_Vectors.o
I3C2_EV_IRQHandlerCode0x341821F622stm32n657xx_Vectors.o
I3C2_ER_IRQHandlerCode0x341821F822stm32n657xx_Vectors.o
TIM1_BRK_IRQHandlerCode0x341821FA22stm32n657xx_Vectors.o
TIM1_UP_IRQHandlerCode0x341821FC22stm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandlerCode0x341821FE22stm32n657xx_Vectors.o
TIM1_CC_IRQHandlerCode0x3418220022stm32n657xx_Vectors.o
TIM2_IRQHandlerCode0x3418220222stm32n657xx_Vectors.o
TIM3_IRQHandlerCode0x3418220422stm32n657xx_Vectors.o
TIM4_IRQHandlerCode0x3418220622stm32n657xx_Vectors.o
TIM5_IRQHandlerCode0x3418220822stm32n657xx_Vectors.o
TIM6_IRQHandlerCode0x3418220A22stm32n657xx_Vectors.o
TIM7_IRQHandlerCode0x3418220C22stm32n657xx_Vectors.o
TIM8_BRK_IRQHandlerCode0x3418220E22stm32n657xx_Vectors.o
TIM8_UP_IRQHandlerCode0x3418221022stm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandlerCode0x3418221222stm32n657xx_Vectors.o
TIM8_CC_IRQHandlerCode0x3418221422stm32n657xx_Vectors.o
TIM9_IRQHandlerCode0x3418221622stm32n657xx_Vectors.o
TIM10_IRQHandlerCode0x3418221822stm32n657xx_Vectors.o
TIM11_IRQHandlerCode0x3418221A22stm32n657xx_Vectors.o
TIM12_IRQHandlerCode0x3418221C22stm32n657xx_Vectors.o
TIM13_IRQHandlerCode0x3418221E22stm32n657xx_Vectors.o
TIM14_IRQHandlerCode0x3418222022stm32n657xx_Vectors.o
TIM15_IRQHandlerCode0x3418222222stm32n657xx_Vectors.o
TIM16_IRQHandlerCode0x3418222422stm32n657xx_Vectors.o
TIM17_IRQHandlerCode0x3418222622stm32n657xx_Vectors.o
TIM18_IRQHandlerCode0x3418222822stm32n657xx_Vectors.o
LPTIM1_IRQHandlerCode0x3418222A22stm32n657xx_Vectors.o
LPTIM2_IRQHandlerCode0x3418222C22stm32n657xx_Vectors.o
LPTIM3_IRQHandlerCode0x3418222E22stm32n657xx_Vectors.o
LPTIM4_IRQHandlerCode0x3418223022stm32n657xx_Vectors.o
LPTIM5_IRQHandlerCode0x3418223222stm32n657xx_Vectors.o
ADF1_FLT0_IRQHandlerCode0x3418223422stm32n657xx_Vectors.o
MDF1_FLT0_IRQHandlerCode0x3418223622stm32n657xx_Vectors.o
MDF1_FLT1_IRQHandlerCode0x3418223822stm32n657xx_Vectors.o
MDF1_FLT2_IRQHandlerCode0x3418223A22stm32n657xx_Vectors.o
MDF1_FLT3_IRQHandlerCode0x3418223C22stm32n657xx_Vectors.o
MDF1_FLT4_IRQHandlerCode0x3418223E22stm32n657xx_Vectors.o
MDF1_FLT5_IRQHandlerCode0x3418224022stm32n657xx_Vectors.o
SAI1_A_IRQHandlerCode0x3418224222stm32n657xx_Vectors.o
SAI1_B_IRQHandlerCode0x3418224422stm32n657xx_Vectors.o
SAI2_A_IRQHandlerCode0x3418224622stm32n657xx_Vectors.o
SAI2_B_IRQHandlerCode0x3418224822stm32n657xx_Vectors.o
SPDIFRX_IRQHandlerCode0x3418224A22stm32n657xx_Vectors.o
SPI1_IRQHandlerCode0x3418224C22stm32n657xx_Vectors.o
SPI2_IRQHandlerCode0x3418224E22stm32n657xx_Vectors.o
SPI3_IRQHandlerCode0x3418225022stm32n657xx_Vectors.o
SPI4_IRQHandlerCode0x3418225222stm32n657xx_Vectors.o
SPI5_IRQHandlerCode0x3418225422stm32n657xx_Vectors.o
SPI6_IRQHandlerCode0x3418225622stm32n657xx_Vectors.o
USART1_IRQHandlerCode0x3418225822stm32n657xx_Vectors.o
USART2_IRQHandlerCode0x3418225A22stm32n657xx_Vectors.o
USART3_IRQHandlerCode0x3418225C22stm32n657xx_Vectors.o
UART4_IRQHandlerCode0x3418225E22stm32n657xx_Vectors.o
UART5_IRQHandlerCode0x3418226022stm32n657xx_Vectors.o
USART6_IRQHandlerCode0x3418226222stm32n657xx_Vectors.o
UART7_IRQHandlerCode0x3418226422stm32n657xx_Vectors.o
UART8_IRQHandlerCode0x3418226622stm32n657xx_Vectors.o
UART9_IRQHandlerCode0x3418226822stm32n657xx_Vectors.o
USART10_IRQHandlerCode0x3418226A22stm32n657xx_Vectors.o
LPUART1_IRQHandlerCode0x3418226C22stm32n657xx_Vectors.o
XSPI1_IRQHandlerCode0x3418226E22stm32n657xx_Vectors.o
XSPI2_IRQHandlerCode0x3418227022stm32n657xx_Vectors.o
XSPI3_IRQHandlerCode0x3418227222stm32n657xx_Vectors.o
FMC_IRQHandlerCode0x3418227422stm32n657xx_Vectors.o
SDMMC1_IRQHandlerCode0x3418227622stm32n657xx_Vectors.o
SDMMC2_IRQHandlerCode0x3418227822stm32n657xx_Vectors.o
UCPD1_IRQHandlerCode0x3418227A22stm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandlerCode0x3418227C22stm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandlerCode0x3418227E22stm32n657xx_Vectors.o
ETH1_IRQHandlerCode0x3418228022stm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandlerCode0x3418228222stm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandlerCode0x3418228422stm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandlerCode0x3418228622stm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandlerCode0x3418228822stm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandlerCode0x3418228A22stm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandlerCode0x3418228C22stm32n657xx_Vectors.o
FDCAN_CU_IRQHandlerCode0x3418228E22stm32n657xx_Vectors.o
MDIOS_IRQHandlerCode0x3418229022stm32n657xx_Vectors.o
DCMI_PSSI_IRQHandlerCode0x3418229222stm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandlerCode0x3418229422stm32n657xx_Vectors.o
CTI_INT0_IRQHandlerCode0x3418229622stm32n657xx_Vectors.o
CTI_INT1_IRQHandlerCode0x3418229822stm32n657xx_Vectors.o
LTDC_UP_IRQHandlerCode0x3418229A22stm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandlerCode0x3418229C22stm32n657xx_Vectors.o
[.rodata.block.tdata.copy]Cnst0x3418229E1[ Linker created ]
[.init_array]----0x341822A044STM32N6xx_Startup.o
__SEGGER_init_ctorsCode0x341822B0364SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_table__Cnst0x341822D4364[ Linker created ]
__SEGGER_init_data__Cnst0x341822F844[ Linker created ]
__SEGGER_init_zeroCode0x341822FC182SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_copyCode0x3418230E202SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
+

"<#16> at line 128, col 45": place in [0x34180400 to 0x341FFFFF] with auto order

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x341822A08[ Linker created ]
uwTickZero0x341822A444blto2_FSBL_lto.o
uwTickPrioZero0x341822A814blto2_FSBL_lto.o
SystemCoreClockInit0x341822AC44blto2_FSBL_lto.o
[.bss.block.stack]None0x341FE0008 1928[ Linker created ]
+

"<#17> at line 132, col 45": place in [0x34180400 to 0x341FFFFF] with auto order

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x341822A08[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
blto2_FSBL_lto.o6 3787645
SEGGER_THUMB_Startup.o20
stm32n657xx_Vectors.o1 216
STM32N6xx_Startup.o44
Subtotal (4 objects)7 6587645
SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a74
strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a104
Subtotal (2archives)178
Linker created (shared data, fills, blocks):408 192
Total:7 83611648 197
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)74
strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)104
Subtotal (2 members from 2 archives)178
Objects (4 files)7 6587645
Linker created (shared data, fills, blocks):408 192
Total:7 83611648 197
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table40
Memory for block 'stack'8 192
Subtotal (linker created):408 192
Objects (4 files)7 6587645
Archives (2 files)178
Total:7 83611648 197
+

MODULE DETAIL

+

Module blto2_FSBL_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_RCC_OscConfig1 714
HAL_RCC_ClockConfig1 472
main1 184
RCC_PLL_Config446
HAL_GPIO_Init418
SystemCoreClockUpdate400
SystemInit302
RCC_IC_CheckPLLSources148
RCC_PLL_IsNewConfig134
RCCEx_GetPLLSourceFreq128
SysTick_Handler16
NMI_Handler2
HardFault_Handler2
MemManage_Handler2
BusFault_Handler2
UsageFault_Handler2
SVC_Handler2
DebugMon_Handler2
PendSV_Handler2
[.rodata..Lswitch.table.HAL_GPIO_DeInit]64
[.rodata..Lswitch.table.RCC_PLL_Config]12
SystemCoreClock4
uwTick4
uwTickPrio1
Total:6 3787645
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32n657xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors844
PVD_PVM_IRQHandler2
DTS_IRQHandler2
RCC_IRQHandler2
LOCKUP_IRQHandler2
CACHE_ECC_IRQHandler2
TCM_ECC_IRQHandler2
BCK_ECC_IRQHandler2
FPU_IRQHandler2
RTC_S_IRQHandler2
TAMP_IRQHandler2
RIFSC_TAMPER_IRQHandler2
IAC_IRQHandler2
RCC_S_IRQHandler2
RTC_IRQHandler2
IWDG_IRQHandler2
WWDG_IRQHandler2
EXTI0_IRQHandler2
EXTI1_IRQHandler2
EXTI2_IRQHandler2
EXTI3_IRQHandler2
EXTI4_IRQHandler2
EXTI5_IRQHandler2
EXTI6_IRQHandler2
EXTI7_IRQHandler2
EXTI8_IRQHandler2
EXTI9_IRQHandler2
EXTI10_IRQHandler2
EXTI11_IRQHandler2
EXTI12_IRQHandler2
EXTI13_IRQHandler2
EXTI14_IRQHandler2
EXTI15_IRQHandler2
SAES_IRQHandler2
CRYP_IRQHandler2
PKA_IRQHandler2
HASH_IRQHandler2
RNG_IRQHandler2
MCE1_IRQHandler2
MCE2_IRQHandler2
MCE3_IRQHandler2
MCE4_IRQHandler2
ADC1_2_IRQHandler2
CSI_IRQHandler2
DCMIPP_IRQHandler2
PAHB_ERR_IRQHandler2
NPU0_IRQHandler2
NPU1_IRQHandler2
NPU2_IRQHandler2
NPU3_IRQHandler2
CACHEAXI_IRQHandler2
LTDC_LO_IRQHandler2
LTDC_LO_ERR_IRQHandler2
DMA2D_IRQHandler2
JPEG_IRQHandler2
VENC_IRQHandler2
GFXMMU_IRQHandler2
GFXTIM_IRQHandler2
GPU2D_IRQHandler2
GPU2D_ER_IRQHandler2
ICACHE_IRQHandler2
HPDMA1_Channel0_IRQHandler2
HPDMA1_Channel1_IRQHandler2
HPDMA1_Channel2_IRQHandler2
HPDMA1_Channel3_IRQHandler2
HPDMA1_Channel4_IRQHandler2
HPDMA1_Channel5_IRQHandler2
HPDMA1_Channel6_IRQHandler2
HPDMA1_Channel7_IRQHandler2
HPDMA1_Channel8_IRQHandler2
HPDMA1_Channel9_IRQHandler2
HPDMA1_Channel10_IRQHandler2
HPDMA1_Channel11_IRQHandler2
HPDMA1_Channel12_IRQHandler2
HPDMA1_Channel13_IRQHandler2
HPDMA1_Channel14_IRQHandler2
HPDMA1_Channel15_IRQHandler2
GPDMA1_Channel0_IRQHandler2
GPDMA1_Channel1_IRQHandler2
GPDMA1_Channel2_IRQHandler2
GPDMA1_Channel3_IRQHandler2
GPDMA1_Channel4_IRQHandler2
GPDMA1_Channel5_IRQHandler2
GPDMA1_Channel6_IRQHandler2
GPDMA1_Channel7_IRQHandler2
GPDMA1_Channel8_IRQHandler2
GPDMA1_Channel9_IRQHandler2
GPDMA1_Channel10_IRQHandler2
GPDMA1_Channel11_IRQHandler2
GPDMA1_Channel12_IRQHandler2
GPDMA1_Channel13_IRQHandler2
GPDMA1_Channel14_IRQHandler2
GPDMA1_Channel15_IRQHandler2
I2C1_EV_IRQHandler2
I2C1_ER_IRQHandler2
I2C2_EV_IRQHandler2
I2C2_ER_IRQHandler2
I2C3_EV_IRQHandler2
I2C3_ER_IRQHandler2
I2C4_EV_IRQHandler2
I2C4_ER_IRQHandler2
I3C1_EV_IRQHandler2
I3C1_ER_IRQHandler2
I3C2_EV_IRQHandler2
I3C2_ER_IRQHandler2
TIM1_BRK_IRQHandler2
TIM1_UP_IRQHandler2
TIM1_TRG_CCU_IRQHandler2
TIM1_CC_IRQHandler2
TIM2_IRQHandler2
TIM3_IRQHandler2
TIM4_IRQHandler2
TIM5_IRQHandler2
TIM6_IRQHandler2
TIM7_IRQHandler2
TIM8_BRK_IRQHandler2
TIM8_UP_IRQHandler2
TIM8_TRG_CCU_IRQHandler2
TIM8_CC_IRQHandler2
TIM9_IRQHandler2
TIM10_IRQHandler2
TIM11_IRQHandler2
TIM12_IRQHandler2
TIM13_IRQHandler2
TIM14_IRQHandler2
TIM15_IRQHandler2
TIM16_IRQHandler2
TIM17_IRQHandler2
TIM18_IRQHandler2
LPTIM1_IRQHandler2
LPTIM2_IRQHandler2
LPTIM3_IRQHandler2
LPTIM4_IRQHandler2
LPTIM5_IRQHandler2
ADF1_FLT0_IRQHandler2
MDF1_FLT0_IRQHandler2
MDF1_FLT1_IRQHandler2
MDF1_FLT2_IRQHandler2
MDF1_FLT3_IRQHandler2
MDF1_FLT4_IRQHandler2
MDF1_FLT5_IRQHandler2
SAI1_A_IRQHandler2
SAI1_B_IRQHandler2
SAI2_A_IRQHandler2
SAI2_B_IRQHandler2
SPDIFRX_IRQHandler2
SPI1_IRQHandler2
SPI2_IRQHandler2
SPI3_IRQHandler2
SPI4_IRQHandler2
SPI5_IRQHandler2
SPI6_IRQHandler2
USART1_IRQHandler2
USART2_IRQHandler2
USART3_IRQHandler2
UART4_IRQHandler2
UART5_IRQHandler2
USART6_IRQHandler2
UART7_IRQHandler2
UART8_IRQHandler2
UART9_IRQHandler2
USART10_IRQHandler2
LPUART1_IRQHandler2
XSPI1_IRQHandler2
XSPI2_IRQHandler2
XSPI3_IRQHandler2
FMC_IRQHandler2
SDMMC1_IRQHandler2
SDMMC2_IRQHandler2
UCPD1_IRQHandler2
USB1_OTG_HS_IRQHandler2
USB2_OTG_HS_IRQHandler2
ETH1_IRQHandler2
FDCAN1_IT0_IRQHandler2
FDCAN1_IT1_IRQHandler2
FDCAN2_IT0_IRQHandler2
FDCAN2_IT1_IRQHandler2
FDCAN3_IT0_IRQHandler2
FDCAN3_IT1_IRQHandler2
FDCAN_CU_IRQHandler2
MDIOS_IRQHandler2
DCMI_PSSI_IRQHandler2
WAKEUP_PIN_IRQHandler2
CTI_INT0_IRQHandler2
CTI_INT1_IRQHandler2
LTDC_UP_IRQHandler2
LTDC_UP_ERR_IRQHandler2
Total:1 216
+

Module STM32N6xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler44
Total:44
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr104
Total:104
+

All modules

+ + + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:7 8367645
+

SECTION DETAIL

+

Sections by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSymbol or [section] NameSizeAlInitAcObject File
34180400-3418074B_vectors8441024CodeRXstm32n657xx_Vectors.o
3418074C-34180BEBmain1 1844CodeRXblto2_FSBL_lto.o
34180BEC-34180BFBSysTick_Handler164CodeRXblto2_FSBL_lto.o
34180BFC-34180D8BSystemCoreClockUpdate4004CodeRXblto2_FSBL_lto.o
34180D8C-3418134BHAL_RCC_ClockConfig1 4724CodeRXblto2_FSBL_lto.o
3418134C-341813DFRCC_IC_CheckPLLSources1484CodeRXblto2_FSBL_lto.o
341813E0-3418145FRCCEx_GetPLLSourceFreq1284CodeRXblto2_FSBL_lto.o
34181460-3418149F[.rodata..Lswitch.table.HAL_GPIO_DeInit]644CnstROblto2_FSBL_lto.o
341814A0-341814AB[.rodata..Lswitch.table.RCC_PLL_Config]124CnstROblto2_FSBL_lto.o
341814AC-341814BF_start204CodeRXSEGGER_THUMB_Startup.o
341814C0-341814EBreset_handler444CodeRXSTM32N6xx_Startup.o
341814EC-34181553__aeabi_memclr1044CodeRXstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
34181554-34181555NMI_Handler24CodeRXblto2_FSBL_lto.o
34181556-34181557PVD_PVM_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181558-34181559HardFault_Handler24CodeRXblto2_FSBL_lto.o
3418155A-3418155BDTS_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418155C-3418155DMemManage_Handler24CodeRXblto2_FSBL_lto.o
3418155E-3418155FRCC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181560-34181561BusFault_Handler24CodeRXblto2_FSBL_lto.o
34181562-34181563LOCKUP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181564-34181565UsageFault_Handler24CodeRXblto2_FSBL_lto.o
34181566-34181567CACHE_ECC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181568-34181569SVC_Handler24CodeRXblto2_FSBL_lto.o
3418156A-3418156BTCM_ECC_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418156C-3418156DDebugMon_Handler24CodeRXblto2_FSBL_lto.o
3418156E-3418156FBCK_ECC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181570-34181571PendSV_Handler24CodeRXblto2_FSBL_lto.o
34181572-34181573FPU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181574-341816A1SystemInit3024CodeRXblto2_FSBL_lto.o
341816A2-341816A3RTC_S_IRQHandler22CodeRXstm32n657xx_Vectors.o
341816A4-34181845HAL_GPIO_Init4184CodeRXblto2_FSBL_lto.o
34181846-34181847TAMP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181848-34181EF9HAL_RCC_OscConfig1 7144CodeRXblto2_FSBL_lto.o
34181EFA-34181EFBRIFSC_TAMPER_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181EFC-34181F81RCC_PLL_IsNewConfig1344CodeRXblto2_FSBL_lto.o
34181F82-34181F83IAC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34181F84-34182141RCC_PLL_Config4464CodeRXblto2_FSBL_lto.o
34182142-34182143RCC_S_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182144-34182145RTC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182146-34182147IWDG_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182148-34182149WWDG_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418214A-3418214BEXTI0_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418214C-3418214DEXTI1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418214E-3418214FEXTI2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182150-34182151EXTI3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182152-34182153EXTI4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182154-34182155EXTI5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182156-34182157EXTI6_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182158-34182159EXTI7_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418215A-3418215BEXTI8_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418215C-3418215DEXTI9_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418215E-3418215FEXTI10_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182160-34182161EXTI11_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182162-34182163EXTI12_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182164-34182165EXTI13_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182166-34182167EXTI14_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182168-34182169EXTI15_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418216A-3418216BSAES_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418216C-3418216DCRYP_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418216E-3418216FPKA_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182170-34182171HASH_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182172-34182173RNG_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182174-34182175MCE1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182176-34182177MCE2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182178-34182179MCE3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418217A-3418217BMCE4_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418217C-3418217DADC1_2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418217E-3418217FCSI_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182180-34182181DCMIPP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182182-34182183PAHB_ERR_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182184-34182185NPU0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182186-34182187NPU1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182188-34182189NPU2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418218A-3418218BNPU3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418218C-3418218DCACHEAXI_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418218E-3418218FLTDC_LO_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182190-34182191LTDC_LO_ERR_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182192-34182193DMA2D_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182194-34182195JPEG_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182196-34182197VENC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182198-34182199GFXMMU_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418219A-3418219BGFXTIM_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418219C-3418219DGPU2D_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418219E-3418219FGPU2D_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821A0-341821A1ICACHE_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821A2-341821A3HPDMA1_Channel0_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821A4-341821A5HPDMA1_Channel1_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821A6-341821A7HPDMA1_Channel2_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821A8-341821A9HPDMA1_Channel3_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821AA-341821ABHPDMA1_Channel4_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821AC-341821ADHPDMA1_Channel5_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821AE-341821AFHPDMA1_Channel6_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821B0-341821B1HPDMA1_Channel7_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821B2-341821B3HPDMA1_Channel8_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821B4-341821B5HPDMA1_Channel9_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821B6-341821B7HPDMA1_Channel10_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821B8-341821B9HPDMA1_Channel11_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821BA-341821BBHPDMA1_Channel12_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821BC-341821BDHPDMA1_Channel13_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821BE-341821BFHPDMA1_Channel14_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821C0-341821C1HPDMA1_Channel15_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821C2-341821C3GPDMA1_Channel0_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821C4-341821C5GPDMA1_Channel1_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821C6-341821C7GPDMA1_Channel2_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821C8-341821C9GPDMA1_Channel3_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821CA-341821CBGPDMA1_Channel4_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821CC-341821CDGPDMA1_Channel5_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821CE-341821CFGPDMA1_Channel6_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821D0-341821D1GPDMA1_Channel7_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821D2-341821D3GPDMA1_Channel8_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821D4-341821D5GPDMA1_Channel9_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821D6-341821D7GPDMA1_Channel10_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821D8-341821D9GPDMA1_Channel11_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821DA-341821DBGPDMA1_Channel12_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821DC-341821DDGPDMA1_Channel13_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821DE-341821DFGPDMA1_Channel14_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821E0-341821E1GPDMA1_Channel15_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821E2-341821E3I2C1_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821E4-341821E5I2C1_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821E6-341821E7I2C2_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821E8-341821E9I2C2_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821EA-341821EBI2C3_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821EC-341821EDI2C3_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821EE-341821EFI2C4_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821F0-341821F1I2C4_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821F2-341821F3I3C1_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821F4-341821F5I3C1_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821F6-341821F7I3C2_EV_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821F8-341821F9I3C2_ER_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821FA-341821FBTIM1_BRK_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821FC-341821FDTIM1_UP_IRQHandler22CodeRXstm32n657xx_Vectors.o
341821FE-341821FFTIM1_TRG_CCU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182200-34182201TIM1_CC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182202-34182203TIM2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182204-34182205TIM3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182206-34182207TIM4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182208-34182209TIM5_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418220A-3418220BTIM6_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418220C-3418220DTIM7_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418220E-3418220FTIM8_BRK_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182210-34182211TIM8_UP_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182212-34182213TIM8_TRG_CCU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182214-34182215TIM8_CC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182216-34182217TIM9_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182218-34182219TIM10_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418221A-3418221BTIM11_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418221C-3418221DTIM12_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418221E-3418221FTIM13_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182220-34182221TIM14_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182222-34182223TIM15_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182224-34182225TIM16_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182226-34182227TIM17_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182228-34182229TIM18_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418222A-3418222BLPTIM1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418222C-3418222DLPTIM2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418222E-3418222FLPTIM3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182230-34182231LPTIM4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182232-34182233LPTIM5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182234-34182235ADF1_FLT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182236-34182237MDF1_FLT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182238-34182239MDF1_FLT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418223A-3418223BMDF1_FLT2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418223C-3418223DMDF1_FLT3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418223E-3418223FMDF1_FLT4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182240-34182241MDF1_FLT5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182242-34182243SAI1_A_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182244-34182245SAI1_B_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182246-34182247SAI2_A_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182248-34182249SAI2_B_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418224A-3418224BSPDIFRX_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418224C-3418224DSPI1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418224E-3418224FSPI2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182250-34182251SPI3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182252-34182253SPI4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182254-34182255SPI5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182256-34182257SPI6_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182258-34182259USART1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418225A-3418225BUSART2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418225C-3418225DUSART3_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418225E-3418225FUART4_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182260-34182261UART5_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182262-34182263USART6_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182264-34182265UART7_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182266-34182267UART8_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182268-34182269UART9_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418226A-3418226BUSART10_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418226C-3418226DLPUART1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418226E-3418226FXSPI1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182270-34182271XSPI2_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182272-34182273XSPI3_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182274-34182275FMC_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182276-34182277SDMMC1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182278-34182279SDMMC2_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418227A-3418227BUCPD1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418227C-3418227DUSB1_OTG_HS_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418227E-3418227FUSB2_OTG_HS_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182280-34182281ETH1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182282-34182283FDCAN1_IT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182284-34182285FDCAN1_IT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182286-34182287FDCAN2_IT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182288-34182289FDCAN2_IT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418228A-3418228BFDCAN3_IT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418228C-3418228DFDCAN3_IT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418228E-3418228FFDCAN_CU_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182290-34182291MDIOS_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182292-34182293DCMI_PSSI_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182294-34182295WAKEUP_PIN_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182296-34182297CTI_INT0_IRQHandler22CodeRXstm32n657xx_Vectors.o
34182298-34182299CTI_INT1_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418229A-3418229BLTDC_UP_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418229C-3418229DLTDC_UP_ERR_IRQHandler22CodeRXstm32n657xx_Vectors.o
3418229E-3418229F( UNUSED .=.+2 )2-------
341822A0-341822A3[.init_array]44------STM32N6xx_Startup.o
341822A4-341822A7uwTick44ZeroZIblto2_FSBL_lto.o
341822A8-341822A8uwTickPrio14ZeroZIblto2_FSBL_lto.o
341822A9-341822AB( ALIGN .=.+3 )3-------
341822AC-341822AFSystemCoreClock44InitRWblto2_FSBL_lto.o
341822B0-341822D3__SEGGER_init_ctors364CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
341822D4-341822F7__SEGGER_init_table__364CnstRO[ Linker created ]
341822F8-341822FB__SEGGER_init_data__44CnstRO[ Linker created ]
341822FC-3418230D__SEGGER_init_zero182CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
3418230E-34182321__SEGGER_init_copy202CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
34182322-341FDFFF( UNUSED .=.+507102 )507 102-------
341FE000-341FFFFF[.bss.block.stack]8 1928NoneZI[ Linker created ]
+

UNUSED MEMORY SUMMARY

+

Detail

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeReason
3418229E-3418229F2Unused memory between sections '.init.LTDC_UP_ERR_IRQHandler' and '.init_array'
341822A9-341822AB3Filler between sections '.bss.uwTickPrio' and '.data.SystemCoreClock' as align=4
NOTE: section '.bss.uwTickPrio' has size 1 that is not a multiple of its alignment 4
34182322-341FDFFF507 102Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.block.stack'
+

INITIALIZATION TABLE

+

Constructor list

+ + + + + + + + + + + + +
Table
Address		Called
Address		Called
Symbol or [section] name
0x341822A00x34180BFDSystemCoreClockUpdate
+

Initialize by zero

+ + + + + + + + + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+ +
RangeSizeSymbol or [section] name
341822A4-341822A74uwTick
341822A8-341822A81uwTickPrio
341822A4-341822A85Total (2 sections)
+ + + + + + + + + + + + + + + + +

Summary

+ +
RangeSizeSymbol or [section] name
341822AC-341822AF4SystemCoreClock
341822AC-341822AF4Total (1 sections)
+ + + + + + + + + + + + + + + + + + + + +
DescriptionSize
Initialization table36 bytes
Source image4 bytes
Destination image9 bytes
Saving-31 bytes
+

LINKER-CREATED VENEERS

+

Arm-Arm range extension veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Thumb range extension veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Arm-Thumb mode switch veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Arm mode switch veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
Veneer TypeSize
Thumb-Arm mode switch0
Arm-Thumb mode switch0
Thumb-Thumb range extension0
Arm-Arm range extension0
Total:0
+

SYMBOL LIST

+

Function symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
ADC1_2_IRQHandler0x3418217D2CodeWkstm32n657xx_Vectors.o
ADF1_FLT0_IRQHandler0x341822352CodeWkstm32n657xx_Vectors.o
BCK_ECC_IRQHandler0x3418156F2CodeWkstm32n657xx_Vectors.o
BusFault_Handler0x3418156124CodeGbblto2_FSBL_lto.o
CACHEAXI_IRQHandler0x3418218D2CodeWkstm32n657xx_Vectors.o
CACHE_ECC_IRQHandler0x341815672CodeWkstm32n657xx_Vectors.o
CRYP_IRQHandler0x3418216D2CodeWkstm32n657xx_Vectors.o
CSI_IRQHandler0x3418217F2CodeWkstm32n657xx_Vectors.o
CTI_INT0_IRQHandler0x341822972CodeWkstm32n657xx_Vectors.o
CTI_INT1_IRQHandler0x341822992CodeWkstm32n657xx_Vectors.o
DCMIPP_IRQHandler0x341821812CodeWkstm32n657xx_Vectors.o
DCMI_PSSI_IRQHandler0x341822932CodeWkstm32n657xx_Vectors.o
DMA2D_IRQHandler0x341821932CodeWkstm32n657xx_Vectors.o
DTS_IRQHandler0x3418155B2CodeWkstm32n657xx_Vectors.o
DebugMon_Handler0x3418156D24CodeGbblto2_FSBL_lto.o
ETH1_IRQHandler0x341822812CodeWkstm32n657xx_Vectors.o
EXTI0_IRQHandler0x3418214B2CodeWkstm32n657xx_Vectors.o
EXTI10_IRQHandler0x3418215F2CodeWkstm32n657xx_Vectors.o
EXTI11_IRQHandler0x341821612CodeWkstm32n657xx_Vectors.o
EXTI12_IRQHandler0x341821632CodeWkstm32n657xx_Vectors.o
EXTI13_IRQHandler0x341821652CodeWkstm32n657xx_Vectors.o
EXTI14_IRQHandler0x341821672CodeWkstm32n657xx_Vectors.o
EXTI15_IRQHandler0x341821692CodeWkstm32n657xx_Vectors.o
EXTI1_IRQHandler0x3418214D2CodeWkstm32n657xx_Vectors.o
EXTI2_IRQHandler0x3418214F2CodeWkstm32n657xx_Vectors.o
EXTI3_IRQHandler0x341821512CodeWkstm32n657xx_Vectors.o
EXTI4_IRQHandler0x341821532CodeWkstm32n657xx_Vectors.o
EXTI5_IRQHandler0x341821552CodeWkstm32n657xx_Vectors.o
EXTI6_IRQHandler0x341821572CodeWkstm32n657xx_Vectors.o
EXTI7_IRQHandler0x341821592CodeWkstm32n657xx_Vectors.o
EXTI8_IRQHandler0x3418215B2CodeWkstm32n657xx_Vectors.o
EXTI9_IRQHandler0x3418215D2CodeWkstm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandler0x341822832CodeWkstm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandler0x341822852CodeWkstm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandler0x341822872CodeWkstm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandler0x341822892CodeWkstm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandler0x3418228B2CodeWkstm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandler0x3418228D2CodeWkstm32n657xx_Vectors.o
FDCAN_CU_IRQHandler0x3418228F2CodeWkstm32n657xx_Vectors.o
FMC_IRQHandler0x341822752CodeWkstm32n657xx_Vectors.o
FPU_IRQHandler0x341815732CodeWkstm32n657xx_Vectors.o
GFXMMU_IRQHandler0x341821992CodeWkstm32n657xx_Vectors.o
GFXTIM_IRQHandler0x3418219B2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandler0x341821C32CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandler0x341821D72CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandler0x341821D92CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandler0x341821DB2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandler0x341821DD2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandler0x341821DF2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandler0x341821E12CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandler0x341821C52CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandler0x341821C72CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandler0x341821C92CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandler0x341821CB2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandler0x341821CD2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandler0x341821CF2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandler0x341821D12CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandler0x341821D32CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandler0x341821D52CodeWkstm32n657xx_Vectors.o
GPU2D_ER_IRQHandler0x3418219F2CodeWkstm32n657xx_Vectors.o
GPU2D_IRQHandler0x3418219D2CodeWkstm32n657xx_Vectors.o
HAL_GPIO_Init0x341816A54184CodeLcblto2_FSBL_lto.o
HAL_RCC_ClockConfig0x34180D8D1 4724CodeLcblto2_FSBL_lto.o
HAL_RCC_OscConfig0x341818491 7144CodeLcblto2_FSBL_lto.o
HASH_IRQHandler0x341821712CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandler0x341821A32CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandler0x341821B72CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandler0x341821B92CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandler0x341821BB2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandler0x341821BD2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandler0x341821BF2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandler0x341821C12CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandler0x341821A52CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandler0x341821A72CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandler0x341821A92CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandler0x341821AB2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandler0x341821AD2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandler0x341821AF2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandler0x341821B12CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandler0x341821B32CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandler0x341821B52CodeWkstm32n657xx_Vectors.o
HardFault_Handler0x3418155924CodeGbblto2_FSBL_lto.o
I2C1_ER_IRQHandler0x341821E52CodeWkstm32n657xx_Vectors.o
I2C1_EV_IRQHandler0x341821E32CodeWkstm32n657xx_Vectors.o
I2C2_ER_IRQHandler0x341821E92CodeWkstm32n657xx_Vectors.o
I2C2_EV_IRQHandler0x341821E72CodeWkstm32n657xx_Vectors.o
I2C3_ER_IRQHandler0x341821ED2CodeWkstm32n657xx_Vectors.o
I2C3_EV_IRQHandler0x341821EB2CodeWkstm32n657xx_Vectors.o
I2C4_ER_IRQHandler0x341821F12CodeWkstm32n657xx_Vectors.o
I2C4_EV_IRQHandler0x341821EF2CodeWkstm32n657xx_Vectors.o
I3C1_ER_IRQHandler0x341821F52CodeWkstm32n657xx_Vectors.o
I3C1_EV_IRQHandler0x341821F32CodeWkstm32n657xx_Vectors.o
I3C2_ER_IRQHandler0x341821F92CodeWkstm32n657xx_Vectors.o
I3C2_EV_IRQHandler0x341821F72CodeWkstm32n657xx_Vectors.o
IAC_IRQHandler0x34181F832CodeWkstm32n657xx_Vectors.o
ICACHE_IRQHandler0x341821A12CodeWkstm32n657xx_Vectors.o
IWDG_IRQHandler0x341821472CodeWkstm32n657xx_Vectors.o
JPEG_IRQHandler0x341821952CodeWkstm32n657xx_Vectors.o
LOCKUP_IRQHandler0x341815632CodeWkstm32n657xx_Vectors.o
LPTIM1_IRQHandler0x3418222B2CodeWkstm32n657xx_Vectors.o
LPTIM2_IRQHandler0x3418222D2CodeWkstm32n657xx_Vectors.o
LPTIM3_IRQHandler0x3418222F2CodeWkstm32n657xx_Vectors.o
LPTIM4_IRQHandler0x341822312CodeWkstm32n657xx_Vectors.o
LPTIM5_IRQHandler0x341822332CodeWkstm32n657xx_Vectors.o
LPUART1_IRQHandler0x3418226D2CodeWkstm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandler0x341821912CodeWkstm32n657xx_Vectors.o
LTDC_LO_IRQHandler0x3418218F2CodeWkstm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandler0x3418229D2CodeWkstm32n657xx_Vectors.o
LTDC_UP_IRQHandler0x3418229B2CodeWkstm32n657xx_Vectors.o
MCE1_IRQHandler0x341821752CodeWkstm32n657xx_Vectors.o
MCE2_IRQHandler0x341821772CodeWkstm32n657xx_Vectors.o
MCE3_IRQHandler0x341821792CodeWkstm32n657xx_Vectors.o
MCE4_IRQHandler0x3418217B2CodeWkstm32n657xx_Vectors.o
MDF1_FLT0_IRQHandler0x341822372CodeWkstm32n657xx_Vectors.o
MDF1_FLT1_IRQHandler0x341822392CodeWkstm32n657xx_Vectors.o
MDF1_FLT2_IRQHandler0x3418223B2CodeWkstm32n657xx_Vectors.o
MDF1_FLT3_IRQHandler0x3418223D2CodeWkstm32n657xx_Vectors.o
MDF1_FLT4_IRQHandler0x3418223F2CodeWkstm32n657xx_Vectors.o
MDF1_FLT5_IRQHandler0x341822412CodeWkstm32n657xx_Vectors.o
MDIOS_IRQHandler0x341822912CodeWkstm32n657xx_Vectors.o
MemManage_Handler0x3418155D24CodeGbblto2_FSBL_lto.o
NMI_Handler0x3418155524CodeGbblto2_FSBL_lto.o
NPU0_IRQHandler0x341821852CodeWkstm32n657xx_Vectors.o
NPU1_IRQHandler0x341821872CodeWkstm32n657xx_Vectors.o
NPU2_IRQHandler0x341821892CodeWkstm32n657xx_Vectors.o
NPU3_IRQHandler0x3418218B2CodeWkstm32n657xx_Vectors.o
PAHB_ERR_IRQHandler0x341821832CodeWkstm32n657xx_Vectors.o
PKA_IRQHandler0x3418216F2CodeWkstm32n657xx_Vectors.o
PVD_PVM_IRQHandler0x341815572CodeWkstm32n657xx_Vectors.o
PendSV_Handler0x3418157124CodeGbblto2_FSBL_lto.o
RCCEx_GetPLLSourceFreq0x341813E11284CodeLcblto2_FSBL_lto.o
RCC_IC_CheckPLLSources0x3418134D1484CodeLcblto2_FSBL_lto.o
RCC_IRQHandler0x3418155F2CodeWkstm32n657xx_Vectors.o
RCC_PLL_Config0x34181F854464CodeLcblto2_FSBL_lto.o
RCC_PLL_IsNewConfig0x34181EFD1344CodeLcblto2_FSBL_lto.o
RCC_S_IRQHandler0x341821432CodeWkstm32n657xx_Vectors.o
RIFSC_TAMPER_IRQHandler0x34181EFB2CodeWkstm32n657xx_Vectors.o
RNG_IRQHandler0x341821732CodeWkstm32n657xx_Vectors.o
RTC_IRQHandler0x341821452CodeWkstm32n657xx_Vectors.o
RTC_S_IRQHandler0x341816A32CodeWkstm32n657xx_Vectors.o
Reset_Handler0x341814C14CodeGbSTM32N6xx_Startup.o
SAES_IRQHandler0x3418216B2CodeWkstm32n657xx_Vectors.o
SAI1_A_IRQHandler0x341822432CodeWkstm32n657xx_Vectors.o
SAI1_B_IRQHandler0x341822452CodeWkstm32n657xx_Vectors.o
SAI2_A_IRQHandler0x341822472CodeWkstm32n657xx_Vectors.o
SAI2_B_IRQHandler0x341822492CodeWkstm32n657xx_Vectors.o
SDMMC1_IRQHandler0x341822772CodeWkstm32n657xx_Vectors.o
SDMMC2_IRQHandler0x341822792CodeWkstm32n657xx_Vectors.o
SPDIFRX_IRQHandler0x3418224B2CodeWkstm32n657xx_Vectors.o
SPI1_IRQHandler0x3418224D2CodeWkstm32n657xx_Vectors.o
SPI2_IRQHandler0x3418224F2CodeWkstm32n657xx_Vectors.o
SPI3_IRQHandler0x341822512CodeWkstm32n657xx_Vectors.o
SPI4_IRQHandler0x341822532CodeWkstm32n657xx_Vectors.o
SPI5_IRQHandler0x341822552CodeWkstm32n657xx_Vectors.o
SPI6_IRQHandler0x341822572CodeWkstm32n657xx_Vectors.o
SVC_Handler0x3418156924CodeGbblto2_FSBL_lto.o
SysTick_Handler0x34180BED164CodeGbblto2_FSBL_lto.o
SystemCoreClockUpdate0x34180BFD4004CodeGbblto2_FSBL_lto.o
SystemInit0x341815753024CodeGbblto2_FSBL_lto.o
TAMP_IRQHandler0x341818472CodeWkstm32n657xx_Vectors.o
TCM_ECC_IRQHandler0x3418156B2CodeWkstm32n657xx_Vectors.o
TIM10_IRQHandler0x341822192CodeWkstm32n657xx_Vectors.o
TIM11_IRQHandler0x3418221B2CodeWkstm32n657xx_Vectors.o
TIM12_IRQHandler0x3418221D2CodeWkstm32n657xx_Vectors.o
TIM13_IRQHandler0x3418221F2CodeWkstm32n657xx_Vectors.o
TIM14_IRQHandler0x341822212CodeWkstm32n657xx_Vectors.o
TIM15_IRQHandler0x341822232CodeWkstm32n657xx_Vectors.o
TIM16_IRQHandler0x341822252CodeWkstm32n657xx_Vectors.o
TIM17_IRQHandler0x341822272CodeWkstm32n657xx_Vectors.o
TIM18_IRQHandler0x341822292CodeWkstm32n657xx_Vectors.o
TIM1_BRK_IRQHandler0x341821FB2CodeWkstm32n657xx_Vectors.o
TIM1_CC_IRQHandler0x341822012CodeWkstm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandler0x341821FF2CodeWkstm32n657xx_Vectors.o
TIM1_UP_IRQHandler0x341821FD2CodeWkstm32n657xx_Vectors.o
TIM2_IRQHandler0x341822032CodeWkstm32n657xx_Vectors.o
TIM3_IRQHandler0x341822052CodeWkstm32n657xx_Vectors.o
TIM4_IRQHandler0x341822072CodeWkstm32n657xx_Vectors.o
TIM5_IRQHandler0x341822092CodeWkstm32n657xx_Vectors.o
TIM6_IRQHandler0x3418220B2CodeWkstm32n657xx_Vectors.o
TIM7_IRQHandler0x3418220D2CodeWkstm32n657xx_Vectors.o
TIM8_BRK_IRQHandler0x3418220F2CodeWkstm32n657xx_Vectors.o
TIM8_CC_IRQHandler0x341822152CodeWkstm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandler0x341822132CodeWkstm32n657xx_Vectors.o
TIM8_UP_IRQHandler0x341822112CodeWkstm32n657xx_Vectors.o
TIM9_IRQHandler0x341822172CodeWkstm32n657xx_Vectors.o
UART4_IRQHandler0x3418225F2CodeWkstm32n657xx_Vectors.o
UART5_IRQHandler0x341822612CodeWkstm32n657xx_Vectors.o
UART7_IRQHandler0x341822652CodeWkstm32n657xx_Vectors.o
UART8_IRQHandler0x341822672CodeWkstm32n657xx_Vectors.o
UART9_IRQHandler0x341822692CodeWkstm32n657xx_Vectors.o
UCPD1_IRQHandler0x3418227B2CodeWkstm32n657xx_Vectors.o
USART10_IRQHandler0x3418226B2CodeWkstm32n657xx_Vectors.o
USART1_IRQHandler0x341822592CodeWkstm32n657xx_Vectors.o
USART2_IRQHandler0x3418225B2CodeWkstm32n657xx_Vectors.o
USART3_IRQHandler0x3418225D2CodeWkstm32n657xx_Vectors.o
USART6_IRQHandler0x341822632CodeWkstm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandler0x3418227D2CodeWkstm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandler0x3418227F2CodeWkstm32n657xx_Vectors.o
UsageFault_Handler0x3418156524CodeGbblto2_FSBL_lto.o
VENC_IRQHandler0x341821972CodeWkstm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandler0x341822952CodeWkstm32n657xx_Vectors.o
WWDG_IRQHandler0x341821492CodeWkstm32n657xx_Vectors.o
XSPI1_IRQHandler0x3418226F2CodeWkstm32n657xx_Vectors.o
XSPI2_IRQHandler0x341822712CodeWkstm32n657xx_Vectors.o
XSPI3_IRQHandler0x341822732CodeWkstm32n657xx_Vectors.o
__SEGGER_init_copy0x3418230F202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_ctors0x341822B1264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_done0x341814B74CodeGbSEGGER_THUMB_Startup.o
__SEGGER_init_zero0x341822FD182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr0x341814ED1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr40x341814ED4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr80x341814ED4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset0x341814EF4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset40x341814EF4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset80x341814EF4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__startup_complete0x341814B74CodeGbSEGGER_THUMB_Startup.o
_start0x341814AD144CodeGbSEGGER_THUMB_Startup.o
exit0x341814BB24CodeGbSEGGER_THUMB_Startup.o
main0x3418074D1 1844CodeGbblto2_FSBL_lto.o
memset0x341814F54CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
reset_handler0x341814C14CodeGbSTM32N6xx_Startup.o
+

Function symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
0x3418074Dmain1 1844CodeGbblto2_FSBL_lto.o
0x34180BEDSysTick_Handler164CodeGbblto2_FSBL_lto.o
0x34180BFDSystemCoreClockUpdate4004CodeGbblto2_FSBL_lto.o
0x34180D8DHAL_RCC_ClockConfig1 4724CodeLcblto2_FSBL_lto.o
0x3418134DRCC_IC_CheckPLLSources1484CodeLcblto2_FSBL_lto.o
0x341813E1RCCEx_GetPLLSourceFreq1284CodeLcblto2_FSBL_lto.o
0x341814AD_start144CodeGbSEGGER_THUMB_Startup.o
0x341814B7__startup_complete4CodeGbSEGGER_THUMB_Startup.o
0x341814B7__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
0x341814BBexit24CodeGbSEGGER_THUMB_Startup.o
0x341814C1reset_handler4CodeGbSTM32N6xx_Startup.o
0x341814C1Reset_Handler4CodeGbSTM32N6xx_Startup.o
0x341814ED__aeabi_memclr84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814ED__aeabi_memclr44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814ED__aeabi_memclr1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814EF__aeabi_memset84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814EF__aeabi_memset44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814EF__aeabi_memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814F5memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181555NMI_Handler24CodeGbblto2_FSBL_lto.o
0x34181557PVD_PVM_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181559HardFault_Handler24CodeGbblto2_FSBL_lto.o
0x3418155BDTS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418155DMemManage_Handler24CodeGbblto2_FSBL_lto.o
0x3418155FRCC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181561BusFault_Handler24CodeGbblto2_FSBL_lto.o
0x34181563LOCKUP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181565UsageFault_Handler24CodeGbblto2_FSBL_lto.o
0x34181567CACHE_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181569SVC_Handler24CodeGbblto2_FSBL_lto.o
0x3418156BTCM_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418156DDebugMon_Handler24CodeGbblto2_FSBL_lto.o
0x3418156FBCK_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181571PendSV_Handler24CodeGbblto2_FSBL_lto.o
0x34181573FPU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181575SystemInit3024CodeGbblto2_FSBL_lto.o
0x341816A3RTC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341816A5HAL_GPIO_Init4184CodeLcblto2_FSBL_lto.o
0x34181847TAMP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181849HAL_RCC_OscConfig1 7144CodeLcblto2_FSBL_lto.o
0x34181EFBRIFSC_TAMPER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181EFDRCC_PLL_IsNewConfig1344CodeLcblto2_FSBL_lto.o
0x34181F83IAC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34181F85RCC_PLL_Config4464CodeLcblto2_FSBL_lto.o
0x34182143RCC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182145RTC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182147IWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182149WWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418214BEXTI0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418214DEXTI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418214FEXTI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182151EXTI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182153EXTI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182155EXTI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182157EXTI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182159EXTI7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418215BEXTI8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418215DEXTI9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418215FEXTI10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182161EXTI11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182163EXTI12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182165EXTI13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182167EXTI14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182169EXTI15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418216BSAES_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418216DCRYP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418216FPKA_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182171HASH_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182173RNG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182175MCE1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182177MCE2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182179MCE3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418217BMCE4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418217DADC1_2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418217FCSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182181DCMIPP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182183PAHB_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182185NPU0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182187NPU1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182189NPU2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418218BNPU3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418218DCACHEAXI_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418218FLTDC_LO_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182191LTDC_LO_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182193DMA2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182195JPEG_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182197VENC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182199GFXMMU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418219BGFXTIM_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418219DGPU2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418219FGPU2D_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821A1ICACHE_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821A3HPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821A5HPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821A7HPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821A9HPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821ABHPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821ADHPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821AFHPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821B1HPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821B3HPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821B5HPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821B7HPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821B9HPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821BBHPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821BDHPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821BFHPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821C1HPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821C3GPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821C5GPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821C7GPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821C9GPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821CBGPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821CDGPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821CFGPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821D1GPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821D3GPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821D5GPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821D7GPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821D9GPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821DBGPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821DDGPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821DFGPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821E1GPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821E3I2C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821E5I2C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821E7I2C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821E9I2C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821EBI2C3_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821EDI2C3_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821EFI2C4_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821F1I2C4_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821F3I3C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821F5I3C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821F7I3C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821F9I3C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821FBTIM1_BRK_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821FDTIM1_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341821FFTIM1_TRG_CCU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182201TIM1_CC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182203TIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182205TIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182207TIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182209TIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418220BTIM6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418220DTIM7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418220FTIM8_BRK_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182211TIM8_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182213TIM8_TRG_CCU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182215TIM8_CC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182217TIM9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182219TIM10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418221BTIM11_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418221DTIM12_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418221FTIM13_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182221TIM14_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182223TIM15_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182225TIM16_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182227TIM17_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182229TIM18_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418222BLPTIM1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418222DLPTIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418222FLPTIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182231LPTIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182233LPTIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182235ADF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182237MDF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182239MDF1_FLT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418223BMDF1_FLT2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418223DMDF1_FLT3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418223FMDF1_FLT4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182241MDF1_FLT5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182243SAI1_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182245SAI1_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182247SAI2_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182249SAI2_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418224BSPDIFRX_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418224DSPI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418224FSPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182251SPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182253SPI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182255SPI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182257SPI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182259USART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418225BUSART2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418225DUSART3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418225FUART4_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182261UART5_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182263USART6_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182265UART7_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182267UART8_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182269UART9_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418226BUSART10_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418226DLPUART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418226FXSPI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182271XSPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182273XSPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182275FMC_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182277SDMMC1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182279SDMMC2_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418227BUCPD1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418227DUSB1_OTG_HS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418227FUSB2_OTG_HS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182281ETH1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182283FDCAN1_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182285FDCAN1_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182287FDCAN2_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182289FDCAN2_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418228BFDCAN3_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418228DFDCAN3_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418228FFDCAN_CU_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182291MDIOS_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182293DCMI_PSSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182295WAKEUP_PIN_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182297CTI_INT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x34182299CTI_INT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418229BLTDC_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x3418229DLTDC_UP_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
0x341822B1__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341822FD__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x3418230F__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
+

Function symbols by descending size

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameSizeAlignTypeBdObject File
HAL_RCC_OscConfig1 7144CodeLcblto2_FSBL_lto.o
HAL_RCC_ClockConfig1 4724CodeLcblto2_FSBL_lto.o
main1 1844CodeGbblto2_FSBL_lto.o
RCC_PLL_Config4464CodeLcblto2_FSBL_lto.o
HAL_GPIO_Init4184CodeLcblto2_FSBL_lto.o
SystemCoreClockUpdate4004CodeGbblto2_FSBL_lto.o
SystemInit3024CodeGbblto2_FSBL_lto.o
RCC_IC_CheckPLLSources1484CodeLcblto2_FSBL_lto.o
RCC_PLL_IsNewConfig1344CodeLcblto2_FSBL_lto.o
RCCEx_GetPLLSourceFreq1284CodeLcblto2_FSBL_lto.o
__aeabi_memclr1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
SysTick_Handler164CodeGbblto2_FSBL_lto.o
_start144CodeGbSEGGER_THUMB_Startup.o
BusFault_Handler24CodeGbblto2_FSBL_lto.o
DebugMon_Handler24CodeGbblto2_FSBL_lto.o
HardFault_Handler24CodeGbblto2_FSBL_lto.o
MemManage_Handler24CodeGbblto2_FSBL_lto.o
NMI_Handler24CodeGbblto2_FSBL_lto.o
PendSV_Handler24CodeGbblto2_FSBL_lto.o
SVC_Handler24CodeGbblto2_FSBL_lto.o
UsageFault_Handler24CodeGbblto2_FSBL_lto.o
exit24CodeGbSEGGER_THUMB_Startup.o
ADC1_2_IRQHandler2CodeWkstm32n657xx_Vectors.o
ADF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
BCK_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
CACHEAXI_IRQHandler2CodeWkstm32n657xx_Vectors.o
CACHE_ECC_IRQHandler2CodeWkstm32n657xx_Vectors.o
CRYP_IRQHandler2CodeWkstm32n657xx_Vectors.o
CSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
CTI_INT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
CTI_INT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
DCMIPP_IRQHandler2CodeWkstm32n657xx_Vectors.o
DCMI_PSSI_IRQHandler2CodeWkstm32n657xx_Vectors.o
DMA2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
DTS_IRQHandler2CodeWkstm32n657xx_Vectors.o
ETH1_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI0_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI10_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI11_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI12_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI13_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI14_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI15_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI1_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI7_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI8_IRQHandler2CodeWkstm32n657xx_Vectors.o
EXTI9_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
FDCAN_CU_IRQHandler2CodeWkstm32n657xx_Vectors.o
FMC_IRQHandler2CodeWkstm32n657xx_Vectors.o
FPU_IRQHandler2CodeWkstm32n657xx_Vectors.o
GFXMMU_IRQHandler2CodeWkstm32n657xx_Vectors.o
GFXTIM_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
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GPU2D_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
GPU2D_IRQHandler2CodeWkstm32n657xx_Vectors.o
HASH_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandler2CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C3_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C3_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C4_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I2C4_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C1_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C1_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C2_ER_IRQHandler2CodeWkstm32n657xx_Vectors.o
I3C2_EV_IRQHandler2CodeWkstm32n657xx_Vectors.o
IAC_IRQHandler2CodeWkstm32n657xx_Vectors.o
ICACHE_IRQHandler2CodeWkstm32n657xx_Vectors.o
IWDG_IRQHandler2CodeWkstm32n657xx_Vectors.o
JPEG_IRQHandler2CodeWkstm32n657xx_Vectors.o
LOCKUP_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM1_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM2_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM3_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM4_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPTIM5_IRQHandler2CodeWkstm32n657xx_Vectors.o
LPUART1_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_LO_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
LTDC_UP_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE1_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE2_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE3_IRQHandler2CodeWkstm32n657xx_Vectors.o
MCE4_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT0_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT1_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT2_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT3_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT4_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDF1_FLT5_IRQHandler2CodeWkstm32n657xx_Vectors.o
MDIOS_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU0_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU1_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU2_IRQHandler2CodeWkstm32n657xx_Vectors.o
NPU3_IRQHandler2CodeWkstm32n657xx_Vectors.o
PAHB_ERR_IRQHandler2CodeWkstm32n657xx_Vectors.o
PKA_IRQHandler2CodeWkstm32n657xx_Vectors.o
PVD_PVM_IRQHandler2CodeWkstm32n657xx_Vectors.o
RCC_IRQHandler2CodeWkstm32n657xx_Vectors.o
RCC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
RIFSC_TAMPER_IRQHandler2CodeWkstm32n657xx_Vectors.o
RNG_IRQHandler2CodeWkstm32n657xx_Vectors.o
RTC_IRQHandler2CodeWkstm32n657xx_Vectors.o
RTC_S_IRQHandler2CodeWkstm32n657xx_Vectors.o
Reset_Handler4CodeGbSTM32N6xx_Startup.o
SAES_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI1_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI1_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI2_A_IRQHandler2CodeWkstm32n657xx_Vectors.o
SAI2_B_IRQHandler2CodeWkstm32n657xx_Vectors.o
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SPI2_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI3_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI4_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI5_IRQHandler2CodeWkstm32n657xx_Vectors.o
SPI6_IRQHandler2CodeWkstm32n657xx_Vectors.o
TAMP_IRQHandler2CodeWkstm32n657xx_Vectors.o
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TIM11_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM12_IRQHandler2CodeWkstm32n657xx_Vectors.o
TIM13_IRQHandler2CodeWkstm32n657xx_Vectors.o
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TIM15_IRQHandler2CodeWkstm32n657xx_Vectors.o
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TIM18_IRQHandler2CodeWkstm32n657xx_Vectors.o
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Untyped symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ValueSymbol nameSizeAlignTypeBdObject File
0x00000000__thread_pointer$----Gb[ Linker created ]
0x00000000__STACKSIZE_PROCESS__----Gb[ Linker created ]
0x00000000__ITCM_RAM_segment_used_size__----Gb[ Linker created ]
0x00000000__FLEX_RAM_segment_used_size__----Gb[ Linker created ]
0x00000000__DTCM_RAM_segment_used_size__----Gb[ Linker created ]
0x00000000__BKP_RAM_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM8_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM7_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM6_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM5_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM4_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM3_segment_used_size__----Gb[ Linker created ]
0x00000000__AXI_RAM1_segment_used_size__----Gb[ Linker created ]
0x00000000__AHB_RAM2_segment_used_size__----Gb[ Linker created ]
0x00000000__AHB_RAM1_segment_used_size__----Gb[ Linker created ]
0x00000100__HEAPSIZE__----Gb[ Linker created ]
0x00002000__STACKSIZE__----Gb[ Linker created ]
0x00002000__BKP_RAM_segment_size__----Gb[ Linker created ]
0x00004000__AHB_RAM2_segment_size__----Gb[ Linker created ]
0x00004000__AHB_RAM1_segment_size__----Gb[ Linker created ]
0x00010000__ITCM_RAM_segment_size__----Gb[ Linker created ]
0x00020000__DTCM_RAM_segment_size__----Gb[ Linker created ]
0x00020000__AXI_RAM8_segment_size__----Gb[ Linker created ]
0x00040000__AXI_RAM7_segment_size__----Gb[ Linker created ]
0x00064000__FLEX_RAM_segment_size__----Gb[ Linker created ]
0x00070000__AXI_RAM6_segment_size__----Gb[ Linker created ]
0x00070000__AXI_RAM5_segment_size__----Gb[ Linker created ]
0x00070000__AXI_RAM4_segment_size__----Gb[ Linker created ]
0x00070000__AXI_RAM3_segment_size__----Gb[ Linker created ]
0x0007FC00__RAM_segment_used_size__----Gb[ Linker created ]
0x0007FC00__RAM_segment_size__----Gb[ Linker created ]
0x0007FC00__AXI_RAM2_segment_used_size__----Gb[ Linker created ]
0x0007FC00__AXI_RAM2_segment_size__----Gb[ Linker created ]
0x0009C000__AXI_RAM1_segment_size__----Gb[ Linker created ]
0x10000000__ITCM_RAM_segment_used_start__----Gb[ Linker created ]
0x10000000__ITCM_RAM_segment_used_end__----Gb[ Linker created ]
0x10000000__ITCM_RAM_segment_start__----Gb[ Linker created ]
0x10010000__ITCM_RAM_segment_end__----Gb[ Linker created ]
0x30000000__DTCM_RAM_segment_used_start__----Gb[ Linker created ]
0x30000000__DTCM_RAM_segment_used_end__----Gb[ Linker created ]
0x30000000__DTCM_RAM_segment_start__----Gb[ Linker created ]
0x30020000__DTCM_RAM_segment_end__----Gb[ Linker created ]
0x34000000__FLEX_RAM_segment_used_start__----Gb[ Linker created ]
0x34000000__FLEX_RAM_segment_used_end__----Gb[ Linker created ]
0x34000000__FLEX_RAM_segment_start__----Gb[ Linker created ]
0x34064000__FLEX_RAM_segment_end__----Gb[ Linker created ]
0x34064000__AXI_RAM1_segment_used_start__----Gb[ Linker created ]
0x34064000__AXI_RAM1_segment_used_end__----Gb[ Linker created ]
0x34064000__AXI_RAM1_segment_start__----Gb[ Linker created ]
0x34100000__AXI_RAM1_segment_end__----Gb[ Linker created ]
0x34180400g_pfnVectors[844]1024CodeGbstm32n657xx_Vectors.o
0x34180400_vectors[844]1024CodeGbstm32n657xx_Vectors.o
0x34180400__RAM_segment_used_start__----Gb[ Linker created ]
0x34180400__RAM_segment_start__----Gb[ Linker created ]
0x34180400__AXI_RAM2_segment_used_start__----Gb[ Linker created ]
0x34180400__AXI_RAM2_segment_start__----Gb[ Linker created ]
0x3418074C_vectors_end1024CodeLcstm32n657xx_Vectors.o
0x341822A0__ctors_start__----Gb[ Linker created ]
0x341822A4__ctors_end__----Gb[ Linker created ]
0x341FE000__stack_start__----Gb[ Linker created ]
0x34200000__stack_end__----Gb[ Linker created ]
0x34200000__RAM_segment_used_end__----Gb[ Linker created ]
0x34200000__RAM_segment_end__----Gb[ Linker created ]
0x34200000__AXI_RAM3_segment_used_start__----Gb[ Linker created ]
0x34200000__AXI_RAM3_segment_used_end__----Gb[ Linker created ]
0x34200000__AXI_RAM3_segment_start__----Gb[ Linker created ]
0x34200000__AXI_RAM2_segment_used_end__----Gb[ Linker created ]
0x34200000__AXI_RAM2_segment_end__----Gb[ Linker created ]
0x34270000__AXI_RAM4_segment_used_start__----Gb[ Linker created ]
0x34270000__AXI_RAM4_segment_used_end__----Gb[ Linker created ]
0x34270000__AXI_RAM4_segment_start__----Gb[ Linker created ]
0x34270000__AXI_RAM3_segment_end__----Gb[ Linker created ]
0x342E0000__AXI_RAM5_segment_used_start__----Gb[ Linker created ]
0x342E0000__AXI_RAM5_segment_used_end__----Gb[ Linker created ]
0x342E0000__AXI_RAM5_segment_start__----Gb[ Linker created ]
0x342E0000__AXI_RAM4_segment_end__----Gb[ Linker created ]
0x34350000__AXI_RAM6_segment_used_start__----Gb[ Linker created ]
0x34350000__AXI_RAM6_segment_used_end__----Gb[ Linker created ]
0x34350000__AXI_RAM6_segment_start__----Gb[ Linker created ]
0x34350000__AXI_RAM5_segment_end__----Gb[ Linker created ]
0x343C0000__AXI_RAM7_segment_used_start__----Gb[ Linker created ]
0x343C0000__AXI_RAM7_segment_used_end__----Gb[ Linker created ]
0x343C0000__AXI_RAM7_segment_start__----Gb[ Linker created ]
0x343C0000__AXI_RAM6_segment_end__----Gb[ Linker created ]
0x34400000__AXI_RAM8_segment_used_start__----Gb[ Linker created ]
0x34400000__AXI_RAM8_segment_used_end__----Gb[ Linker created ]
0x34400000__AXI_RAM8_segment_start__----Gb[ Linker created ]
0x34400000__AXI_RAM7_segment_end__----Gb[ Linker created ]
0x34420000__AXI_RAM8_segment_end__----Gb[ Linker created ]
0x38000000__AHB_RAM1_segment_used_start__----Gb[ Linker created ]
0x38000000__AHB_RAM1_segment_used_end__----Gb[ Linker created ]
0x38000000__AHB_RAM1_segment_start__----Gb[ Linker created ]
0x38004000__AHB_RAM2_segment_used_start__----Gb[ Linker created ]
0x38004000__AHB_RAM2_segment_used_end__----Gb[ Linker created ]
0x38004000__AHB_RAM2_segment_start__----Gb[ Linker created ]
0x38004000__AHB_RAM1_segment_end__----Gb[ Linker created ]
0x38008000__AHB_RAM2_segment_end__----Gb[ Linker created ]
0x3C000000__BKP_RAM_segment_used_start__----Gb[ Linker created ]
0x3C000000__BKP_RAM_segment_used_end__----Gb[ Linker created ]
0x3C000000__BKP_RAM_segment_start__----Gb[ Linker created ]
0x3C002000__BKP_RAM_segment_end__----Gb[ Linker created ]
+

REGION LIST

+

Regions by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSize
AHB_RAM138000000-38003FFF16 384
AHB_RAM238004000-38007FFF16 384
AXI_RAM134064000-340FFFFF638 976
AXI_RAM234180400-341FFFFF523 264
AXI_RAM334200000-3426FFFF458 752
AXI_RAM434270000-342DFFFF458 752
AXI_RAM5342E0000-3434FFFF458 752
AXI_RAM634350000-343BFFFF458 752
AXI_RAM7343C0000-343FFFFF262 144
AXI_RAM834400000-3441FFFF131 072
BKP_RAM3C000000-3C001FFF8 192
DTCM_RAM30000000-3001FFFF131 072
FLEX_RAM34000000-34063FFF409 600
ITCM_RAM10000000-1000FFFF65 536
RAM34180400-341FFFFF523 264
+

Analysis

+ +AXI_RAM2: + Identical to region RAM + +RAM: + Identical to region AXI_RAM2 +

BLOCK LIST

+

Blocks by name

+ + + + + + + + + + + + + + + + + + + + +
NameRangeSizeOrdering
ctors341822A0-341822A34Auto
stack341FE000-341FFFFF8 192Auto
+

Blocks by address

+ + + + + + + + + + + + + + + + + + + + +
RangeSizeNameOrdering
341822A0-341822A34ctorsAuto
341FE000-341FFFFF8 192stackAuto
+

STACK SIZES

+

Functions by stack size

+ + + + + + + +
Function nameStackObject File
+

Functions without stack size information

+ + HAL_RCC_OscConfig + HAL_RCC_ClockConfig + HAL_GPIO_Init + RCC_PLL_IsNewConfig + RCC_PLL_Config + RCC_IC_CheckPLLSources + RCCEx_GetPLLSourceFreq + main + SystemCoreClockUpdate + NMI_Handler + HardFault_Handler + MemManage_Handler + BusFault_Handler + UsageFault_Handler + SVC_Handler + DebugMon_Handler + PendSV_Handler + SysTick_Handler + SystemInit + _start + __SEGGER_init_done + __startup_complete + exit + PVD_PVM_IRQHandler + DTS_IRQHandler + RCC_IRQHandler + LOCKUP_IRQHandler + CACHE_ECC_IRQHandler + TCM_ECC_IRQHandler + BCK_ECC_IRQHandler + FPU_IRQHandler + RTC_S_IRQHandler + TAMP_IRQHandler + RIFSC_TAMPER_IRQHandler + IAC_IRQHandler + RCC_S_IRQHandler + RTC_IRQHandler + IWDG_IRQHandler + WWDG_IRQHandler + EXTI0_IRQHandler + EXTI1_IRQHandler + EXTI2_IRQHandler + EXTI3_IRQHandler + EXTI4_IRQHandler + EXTI5_IRQHandler + EXTI6_IRQHandler + EXTI7_IRQHandler + EXTI8_IRQHandler + EXTI9_IRQHandler + EXTI10_IRQHandler + EXTI11_IRQHandler + EXTI12_IRQHandler + EXTI13_IRQHandler + EXTI14_IRQHandler + EXTI15_IRQHandler + SAES_IRQHandler + CRYP_IRQHandler + PKA_IRQHandler + HASH_IRQHandler + RNG_IRQHandler + MCE1_IRQHandler + MCE2_IRQHandler + MCE3_IRQHandler + MCE4_IRQHandler + ADC1_2_IRQHandler + CSI_IRQHandler + DCMIPP_IRQHandler + PAHB_ERR_IRQHandler + NPU0_IRQHandler + NPU1_IRQHandler + NPU2_IRQHandler + NPU3_IRQHandler + CACHEAXI_IRQHandler + LTDC_LO_IRQHandler + LTDC_LO_ERR_IRQHandler + DMA2D_IRQHandler + JPEG_IRQHandler + VENC_IRQHandler + GFXMMU_IRQHandler + GFXTIM_IRQHandler + GPU2D_IRQHandler + GPU2D_ER_IRQHandler + ICACHE_IRQHandler + HPDMA1_Channel0_IRQHandler + HPDMA1_Channel1_IRQHandler + HPDMA1_Channel2_IRQHandler + HPDMA1_Channel3_IRQHandler + HPDMA1_Channel4_IRQHandler + HPDMA1_Channel5_IRQHandler + HPDMA1_Channel6_IRQHandler + HPDMA1_Channel7_IRQHandler + HPDMA1_Channel8_IRQHandler + HPDMA1_Channel9_IRQHandler + HPDMA1_Channel10_IRQHandler + HPDMA1_Channel11_IRQHandler + HPDMA1_Channel12_IRQHandler + HPDMA1_Channel13_IRQHandler + HPDMA1_Channel14_IRQHandler + HPDMA1_Channel15_IRQHandler + GPDMA1_Channel0_IRQHandler + GPDMA1_Channel1_IRQHandler + GPDMA1_Channel2_IRQHandler + GPDMA1_Channel3_IRQHandler + GPDMA1_Channel4_IRQHandler + GPDMA1_Channel5_IRQHandler + GPDMA1_Channel6_IRQHandler + GPDMA1_Channel7_IRQHandler + GPDMA1_Channel8_IRQHandler + GPDMA1_Channel9_IRQHandler + GPDMA1_Channel10_IRQHandler + GPDMA1_Channel11_IRQHandler + GPDMA1_Channel12_IRQHandler + GPDMA1_Channel13_IRQHandler + GPDMA1_Channel14_IRQHandler + GPDMA1_Channel15_IRQHandler + I2C1_EV_IRQHandler + I2C1_ER_IRQHandler + I2C2_EV_IRQHandler + I2C2_ER_IRQHandler + I2C3_EV_IRQHandler + I2C3_ER_IRQHandler + I2C4_EV_IRQHandler + I2C4_ER_IRQHandler + I3C1_EV_IRQHandler + I3C1_ER_IRQHandler + I3C2_EV_IRQHandler + I3C2_ER_IRQHandler + TIM1_BRK_IRQHandler + TIM1_UP_IRQHandler + TIM1_TRG_CCU_IRQHandler + TIM1_CC_IRQHandler + TIM2_IRQHandler + TIM3_IRQHandler + TIM4_IRQHandler + TIM5_IRQHandler + TIM6_IRQHandler + TIM7_IRQHandler + TIM8_BRK_IRQHandler + TIM8_UP_IRQHandler + TIM8_TRG_CCU_IRQHandler + TIM8_CC_IRQHandler + TIM9_IRQHandler + TIM10_IRQHandler + TIM11_IRQHandler + TIM12_IRQHandler + TIM13_IRQHandler + TIM14_IRQHandler + TIM15_IRQHandler + TIM16_IRQHandler + TIM17_IRQHandler + TIM18_IRQHandler + LPTIM1_IRQHandler + LPTIM2_IRQHandler + LPTIM3_IRQHandler + LPTIM4_IRQHandler + LPTIM5_IRQHandler + ADF1_FLT0_IRQHandler + MDF1_FLT0_IRQHandler + MDF1_FLT1_IRQHandler + MDF1_FLT2_IRQHandler + MDF1_FLT3_IRQHandler + MDF1_FLT4_IRQHandler + MDF1_FLT5_IRQHandler + SAI1_A_IRQHandler + SAI1_B_IRQHandler + SAI2_A_IRQHandler + SAI2_B_IRQHandler + SPDIFRX_IRQHandler + SPI1_IRQHandler + SPI2_IRQHandler + SPI3_IRQHandler + SPI4_IRQHandler + SPI5_IRQHandler + SPI6_IRQHandler + USART1_IRQHandler + USART2_IRQHandler + USART3_IRQHandler + UART4_IRQHandler + UART5_IRQHandler + USART6_IRQHandler + UART7_IRQHandler + UART8_IRQHandler + UART9_IRQHandler + USART10_IRQHandler + LPUART1_IRQHandler + XSPI1_IRQHandler + XSPI2_IRQHandler + XSPI3_IRQHandler + FMC_IRQHandler + SDMMC1_IRQHandler + SDMMC2_IRQHandler + UCPD1_IRQHandler + USB1_OTG_HS_IRQHandler + USB2_OTG_HS_IRQHandler + ETH1_IRQHandler + FDCAN1_IT0_IRQHandler + FDCAN1_IT1_IRQHandler + FDCAN2_IT0_IRQHandler + FDCAN2_IT1_IRQHandler + FDCAN3_IT0_IRQHandler + FDCAN3_IT1_IRQHandler + FDCAN_CU_IRQHandler + MDIOS_IRQHandler + DCMI_PSSI_IRQHandler + WAKEUP_PIN_IRQHandler + CTI_INT0_IRQHandler + CTI_INT1_IRQHandler + LTDC_UP_IRQHandler + LTDC_UP_ERR_IRQHandler + reset_handler + Reset_Handler + __SEGGER_init_zero + __SEGGER_init_copy + __SEGGER_init_ctors + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset +

UNUSED INPUTS

+

Unused object files

+ +No unused object files +

ABSOLUTE LISTING

+

Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024

+ +
+
_vectors:
+g_pfnVectors:
+  0x34180400:  34200000     DC.W       34200000               ; R_ARM_ABS32
+  0x34180404:  341814C1     DC.W       reset_handler
+  0x34180408:  34181555     DC.W       NMI_Handler
+  0x3418040C:  34181559     DC.W       HardFault_Handler
+  0x34180410:  3418155D     DC.W       MemManage_Handler
+  0x34180414:  34181561     DC.W       BusFault_Handler
+  0x34180418:  34181565     DC.W       UsageFault_Handler
+  0x3418041C:  00           DC.B       0x00                     ; '\0'
+  0x3418041D:  00           DC.B       0x00                     ; '\0'
+  0x3418041E:  00           DC.B       0x00                     ; '\0'
+  0x3418041F:  00           DC.B       0x00                     ; '\0'
+  0x34180420:  00           DC.B       0x00                     ; '\0'
+  0x34180421:  00           DC.B       0x00                     ; '\0'
+  0x34180422:  00           DC.B       0x00                     ; '\0'
+  0x34180423:  00           DC.B       0x00                     ; '\0'
+  0x34180424:  00           DC.B       0x00                     ; '\0'
+  0x34180425:  00           DC.B       0x00                     ; '\0'
+  0x34180426:  00           DC.B       0x00                     ; '\0'
+  0x34180427:  00           DC.B       0x00                     ; '\0'
+  0x34180428:  00           DC.B       0x00                     ; '\0'
+  0x34180429:  00           DC.B       0x00                     ; '\0'
+  0x3418042A:  00           DC.B       0x00                     ; '\0'
+  0x3418042B:  00           DC.B       0x00                     ; '\0'
+  0x3418042C:  34181569     DC.W       SVC_Handler
+  0x34180430:  3418156D     DC.W       DebugMon_Handler
+  0x34180434:  00           DC.B       0x00                     ; '\0'
+  0x34180435:  00           DC.B       0x00                     ; '\0'
+  0x34180436:  00           DC.B       0x00                     ; '\0'
+  0x34180437:  00           DC.B       0x00                     ; '\0'
+  0x34180438:  34181571     DC.W       PendSV_Handler
+  0x3418043C:  34180BED     DC.W       SysTick_Handler
+  0x34180440:  34181557     DC.W       PVD_PVM_IRQHandler
+  0x34180444:  00           DC.B       0x00                     ; '\0'
+  0x34180445:  00           DC.B       0x00                     ; '\0'
+  0x34180446:  00           DC.B       0x00                     ; '\0'
+  0x34180447:  00           DC.B       0x00                     ; '\0'
+  0x34180448:  3418155B     DC.W       DTS_IRQHandler
+  0x3418044C:  3418155F     DC.W       RCC_IRQHandler
+  0x34180450:  34181563     DC.W       LOCKUP_IRQHandler
+  0x34180454:  34181567     DC.W       CACHE_ECC_IRQHandler
+  0x34180458:  3418156B     DC.W       TCM_ECC_IRQHandler
+  0x3418045C:  3418156F     DC.W       BCK_ECC_IRQHandler
+  0x34180460:  34181573     DC.W       FPU_IRQHandler
+  0x34180464:  00           DC.B       0x00                     ; '\0'
+  0x34180465:  00           DC.B       0x00                     ; '\0'
+  0x34180466:  00           DC.B       0x00                     ; '\0'
+  0x34180467:  00           DC.B       0x00                     ; '\0'
+  0x34180468:  341816A3     DC.W       RTC_S_IRQHandler
+  0x3418046C:  34181847     DC.W       TAMP_IRQHandler
+  0x34180470:  34181EFB     DC.W       RIFSC_TAMPER_IRQHandler
+  0x34180474:  34181F83     DC.W       IAC_IRQHandler
+  0x34180478:  34182143     DC.W       RCC_S_IRQHandler
+  0x3418047C:  00           DC.B       0x00                     ; '\0'
+  0x3418047D:  00           DC.B       0x00                     ; '\0'
+  0x3418047E:  00           DC.B       0x00                     ; '\0'
+  0x3418047F:  00           DC.B       0x00                     ; '\0'
+  0x34180480:  34182145     DC.W       RTC_IRQHandler
+  0x34180484:  00           DC.B       0x00                     ; '\0'
+  0x34180485:  00           DC.B       0x00                     ; '\0'
+  0x34180486:  00           DC.B       0x00                     ; '\0'
+  0x34180487:  00           DC.B       0x00                     ; '\0'
+  0x34180488:  34182147     DC.W       IWDG_IRQHandler
+  0x3418048C:  34182149     DC.W       WWDG_IRQHandler
+  0x34180490:  3418214B     DC.W       EXTI0_IRQHandler
+  0x34180494:  3418214D     DC.W       EXTI1_IRQHandler
+  0x34180498:  3418214F     DC.W       EXTI2_IRQHandler
+  0x3418049C:  34182151     DC.W       EXTI3_IRQHandler
+  0x341804A0:  34182153     DC.W       EXTI4_IRQHandler
+  0x341804A4:  34182155     DC.W       EXTI5_IRQHandler
+  0x341804A8:  34182157     DC.W       EXTI6_IRQHandler
+  0x341804AC:  34182159     DC.W       EXTI7_IRQHandler
+  0x341804B0:  3418215B     DC.W       EXTI8_IRQHandler
+  0x341804B4:  3418215D     DC.W       EXTI9_IRQHandler
+  0x341804B8:  3418215F     DC.W       EXTI10_IRQHandler
+  0x341804BC:  34182161     DC.W       EXTI11_IRQHandler
+  0x341804C0:  34182163     DC.W       EXTI12_IRQHandler
+  0x341804C4:  34182165     DC.W       EXTI13_IRQHandler
+  0x341804C8:  34182167     DC.W       EXTI14_IRQHandler
+  0x341804CC:  34182169     DC.W       EXTI15_IRQHandler
+  0x341804D0:  3418216B     DC.W       SAES_IRQHandler
+  0x341804D4:  3418216D     DC.W       CRYP_IRQHandler
+  0x341804D8:  3418216F     DC.W       PKA_IRQHandler
+  0x341804DC:  34182171     DC.W       HASH_IRQHandler
+  0x341804E0:  34182173     DC.W       RNG_IRQHandler
+  0x341804E4:  00           DC.B       0x00                     ; '\0'
+  0x341804E5:  00           DC.B       0x00                     ; '\0'
+  0x341804E6:  00           DC.B       0x00                     ; '\0'
+  0x341804E7:  00           DC.B       0x00                     ; '\0'
+  0x341804E8:  34182175     DC.W       MCE1_IRQHandler
+  0x341804EC:  34182177     DC.W       MCE2_IRQHandler
+  0x341804F0:  34182179     DC.W       MCE3_IRQHandler
+  0x341804F4:  3418217B     DC.W       MCE4_IRQHandler
+  0x341804F8:  3418217D     DC.W       ADC1_2_IRQHandler
+  0x341804FC:  3418217F     DC.W       CSI_IRQHandler
+  0x34180500:  34182181     DC.W       DCMIPP_IRQHandler
+  0x34180504:  00           DC.B       0x00                     ; '\0'
+  0x34180505:  00           DC.B       0x00                     ; '\0'
+  0x34180506:  00           DC.B       0x00                     ; '\0'
+  0x34180507:  00           DC.B       0x00                     ; '\0'
+  0x34180508:  00           DC.B       0x00                     ; '\0'
+  0x34180509:  00           DC.B       0x00                     ; '\0'
+  0x3418050A:  00           DC.B       0x00                     ; '\0'
+  0x3418050B:  00           DC.B       0x00                     ; '\0'
+  0x3418050C:  00           DC.B       0x00                     ; '\0'
+  0x3418050D:  00           DC.B       0x00                     ; '\0'
+  0x3418050E:  00           DC.B       0x00                     ; '\0'
+  0x3418050F:  00           DC.B       0x00                     ; '\0'
+  0x34180510:  34182183     DC.W       PAHB_ERR_IRQHandler
+  0x34180514:  34182185     DC.W       NPU0_IRQHandler
+  0x34180518:  34182187     DC.W       NPU1_IRQHandler
+  0x3418051C:  34182189     DC.W       NPU2_IRQHandler
+  0x34180520:  3418218B     DC.W       NPU3_IRQHandler
+  0x34180524:  3418218D     DC.W       CACHEAXI_IRQHandler
+  0x34180528:  3418218F     DC.W       LTDC_LO_IRQHandler
+  0x3418052C:  34182191     DC.W       LTDC_LO_ERR_IRQHandler
+  0x34180530:  34182193     DC.W       DMA2D_IRQHandler
+  0x34180534:  34182195     DC.W       JPEG_IRQHandler
+  0x34180538:  34182197     DC.W       VENC_IRQHandler
+  0x3418053C:  34182199     DC.W       GFXMMU_IRQHandler
+  0x34180540:  3418219B     DC.W       GFXTIM_IRQHandler
+  0x34180544:  3418219D     DC.W       GPU2D_IRQHandler
+  0x34180548:  3418219F     DC.W       GPU2D_ER_IRQHandler
+  0x3418054C:  341821A1     DC.W       ICACHE_IRQHandler
+  0x34180550:  341821A3     DC.W       HPDMA1_Channel0_IRQHandler
+  0x34180554:  341821A5     DC.W       HPDMA1_Channel1_IRQHandler
+  0x34180558:  341821A7     DC.W       HPDMA1_Channel2_IRQHandler
+  0x3418055C:  341821A9     DC.W       HPDMA1_Channel3_IRQHandler
+  0x34180560:  341821AB     DC.W       HPDMA1_Channel4_IRQHandler
+  0x34180564:  341821AD     DC.W       HPDMA1_Channel5_IRQHandler
+  0x34180568:  341821AF     DC.W       HPDMA1_Channel6_IRQHandler
+  0x3418056C:  341821B1     DC.W       HPDMA1_Channel7_IRQHandler
+  0x34180570:  341821B3     DC.W       HPDMA1_Channel8_IRQHandler
+  0x34180574:  341821B5     DC.W       HPDMA1_Channel9_IRQHandler
+  0x34180578:  341821B7     DC.W       HPDMA1_Channel10_IRQHandler
+  0x3418057C:  341821B9     DC.W       HPDMA1_Channel11_IRQHandler
+  0x34180580:  341821BB     DC.W       HPDMA1_Channel12_IRQHandler
+  0x34180584:  341821BD     DC.W       HPDMA1_Channel13_IRQHandler
+  0x34180588:  341821BF     DC.W       HPDMA1_Channel14_IRQHandler
+  0x3418058C:  341821C1     DC.W       HPDMA1_Channel15_IRQHandler
+  0x34180590:  341821C3     DC.W       GPDMA1_Channel0_IRQHandler
+  0x34180594:  341821C5     DC.W       GPDMA1_Channel1_IRQHandler
+  0x34180598:  341821C7     DC.W       GPDMA1_Channel2_IRQHandler
+  0x3418059C:  341821C9     DC.W       GPDMA1_Channel3_IRQHandler
+  0x341805A0:  341821CB     DC.W       GPDMA1_Channel4_IRQHandler
+  0x341805A4:  341821CD     DC.W       GPDMA1_Channel5_IRQHandler
+  0x341805A8:  341821CF     DC.W       GPDMA1_Channel6_IRQHandler
+  0x341805AC:  341821D1     DC.W       GPDMA1_Channel7_IRQHandler
+  0x341805B0:  341821D3     DC.W       GPDMA1_Channel8_IRQHandler
+  0x341805B4:  341821D5     DC.W       GPDMA1_Channel9_IRQHandler
+  0x341805B8:  341821D7     DC.W       GPDMA1_Channel10_IRQHandler
+  0x341805BC:  341821D9     DC.W       GPDMA1_Channel11_IRQHandler
+  0x341805C0:  341821DB     DC.W       GPDMA1_Channel12_IRQHandler
+  0x341805C4:  341821DD     DC.W       GPDMA1_Channel13_IRQHandler
+  0x341805C8:  341821DF     DC.W       GPDMA1_Channel14_IRQHandler
+  0x341805CC:  341821E1     DC.W       GPDMA1_Channel15_IRQHandler
+  0x341805D0:  341821E3     DC.W       I2C1_EV_IRQHandler
+  0x341805D4:  341821E5     DC.W       I2C1_ER_IRQHandler
+  0x341805D8:  341821E7     DC.W       I2C2_EV_IRQHandler
+  0x341805DC:  341821E9     DC.W       I2C2_ER_IRQHandler
+  0x341805E0:  341821EB     DC.W       I2C3_EV_IRQHandler
+  0x341805E4:  341821ED     DC.W       I2C3_ER_IRQHandler
+  0x341805E8:  341821EF     DC.W       I2C4_EV_IRQHandler
+  0x341805EC:  341821F1     DC.W       I2C4_ER_IRQHandler
+  0x341805F0:  341821F3     DC.W       I3C1_EV_IRQHandler
+  0x341805F4:  341821F5     DC.W       I3C1_ER_IRQHandler
+  0x341805F8:  341821F7     DC.W       I3C2_EV_IRQHandler
+  0x341805FC:  341821F9     DC.W       I3C2_ER_IRQHandler
+  0x34180600:  341821FB     DC.W       TIM1_BRK_IRQHandler
+  0x34180604:  341821FD     DC.W       TIM1_UP_IRQHandler
+  0x34180608:  341821FF     DC.W       TIM1_TRG_CCU_IRQHandler
+  0x3418060C:  34182201     DC.W       TIM1_CC_IRQHandler
+  0x34180610:  34182203     DC.W       TIM2_IRQHandler
+  0x34180614:  34182205     DC.W       TIM3_IRQHandler
+  0x34180618:  34182207     DC.W       TIM4_IRQHandler
+  0x3418061C:  34182209     DC.W       TIM5_IRQHandler
+  0x34180620:  3418220B     DC.W       TIM6_IRQHandler
+  0x34180624:  3418220D     DC.W       TIM7_IRQHandler
+  0x34180628:  3418220F     DC.W       TIM8_BRK_IRQHandler
+  0x3418062C:  34182211     DC.W       TIM8_UP_IRQHandler
+  0x34180630:  34182213     DC.W       TIM8_TRG_CCU_IRQHandler
+  0x34180634:  34182215     DC.W       TIM8_CC_IRQHandler
+  0x34180638:  34182217     DC.W       TIM9_IRQHandler
+  0x3418063C:  34182219     DC.W       TIM10_IRQHandler
+  0x34180640:  3418221B     DC.W       TIM11_IRQHandler
+  0x34180644:  3418221D     DC.W       TIM12_IRQHandler
+  0x34180648:  3418221F     DC.W       TIM13_IRQHandler
+  0x3418064C:  34182221     DC.W       TIM14_IRQHandler
+  0x34180650:  34182223     DC.W       TIM15_IRQHandler
+  0x34180654:  34182225     DC.W       TIM16_IRQHandler
+  0x34180658:  34182227     DC.W       TIM17_IRQHandler
+  0x3418065C:  34182229     DC.W       TIM18_IRQHandler
+  0x34180660:  3418222B     DC.W       LPTIM1_IRQHandler
+  0x34180664:  3418222D     DC.W       LPTIM2_IRQHandler
+  0x34180668:  3418222F     DC.W       LPTIM3_IRQHandler
+  0x3418066C:  34182231     DC.W       LPTIM4_IRQHandler
+  0x34180670:  34182233     DC.W       LPTIM5_IRQHandler
+  0x34180674:  34182235     DC.W       ADF1_FLT0_IRQHandler
+  0x34180678:  34182237     DC.W       MDF1_FLT0_IRQHandler
+  0x3418067C:  34182239     DC.W       MDF1_FLT1_IRQHandler
+  0x34180680:  3418223B     DC.W       MDF1_FLT2_IRQHandler
+  0x34180684:  3418223D     DC.W       MDF1_FLT3_IRQHandler
+  0x34180688:  3418223F     DC.W       MDF1_FLT4_IRQHandler
+  0x3418068C:  34182241     DC.W       MDF1_FLT5_IRQHandler
+  0x34180690:  34182243     DC.W       SAI1_A_IRQHandler
+  0x34180694:  34182245     DC.W       SAI1_B_IRQHandler
+  0x34180698:  34182247     DC.W       SAI2_A_IRQHandler
+  0x3418069C:  34182249     DC.W       SAI2_B_IRQHandler
+  0x341806A0:  3418224B     DC.W       SPDIFRX_IRQHandler
+  0x341806A4:  3418224D     DC.W       SPI1_IRQHandler
+  0x341806A8:  3418224F     DC.W       SPI2_IRQHandler
+  0x341806AC:  34182251     DC.W       SPI3_IRQHandler
+  0x341806B0:  34182253     DC.W       SPI4_IRQHandler
+  0x341806B4:  34182255     DC.W       SPI5_IRQHandler
+  0x341806B8:  34182257     DC.W       SPI6_IRQHandler
+  0x341806BC:  34182259     DC.W       USART1_IRQHandler
+  0x341806C0:  3418225B     DC.W       USART2_IRQHandler
+  0x341806C4:  3418225D     DC.W       USART3_IRQHandler
+  0x341806C8:  3418225F     DC.W       UART4_IRQHandler
+  0x341806CC:  34182261     DC.W       UART5_IRQHandler
+  0x341806D0:  34182263     DC.W       USART6_IRQHandler
+  0x341806D4:  34182265     DC.W       UART7_IRQHandler
+  0x341806D8:  34182267     DC.W       UART8_IRQHandler
+  0x341806DC:  34182269     DC.W       UART9_IRQHandler
+  0x341806E0:  3418226B     DC.W       USART10_IRQHandler
+  0x341806E4:  3418226D     DC.W       LPUART1_IRQHandler
+  0x341806E8:  3418226F     DC.W       XSPI1_IRQHandler
+  0x341806EC:  34182271     DC.W       XSPI2_IRQHandler
+  0x341806F0:  34182273     DC.W       XSPI3_IRQHandler
+  0x341806F4:  34182275     DC.W       FMC_IRQHandler
+  0x341806F8:  34182277     DC.W       SDMMC1_IRQHandler
+  0x341806FC:  34182279     DC.W       SDMMC2_IRQHandler
+  0x34180700:  3418227B     DC.W       UCPD1_IRQHandler
+  0x34180704:  3418227D     DC.W       USB1_OTG_HS_IRQHandler
+  0x34180708:  3418227F     DC.W       USB2_OTG_HS_IRQHandler
+  0x3418070C:  34182281     DC.W       ETH1_IRQHandler
+  0x34180710:  34182283     DC.W       FDCAN1_IT0_IRQHandler
+  0x34180714:  34182285     DC.W       FDCAN1_IT1_IRQHandler
+  0x34180718:  34182287     DC.W       FDCAN2_IT0_IRQHandler
+  0x3418071C:  34182289     DC.W       FDCAN2_IT1_IRQHandler
+  0x34180720:  3418228B     DC.W       FDCAN3_IT0_IRQHandler
+  0x34180724:  3418228D     DC.W       FDCAN3_IT1_IRQHandler
+  0x34180728:  3418228F     DC.W       FDCAN_CU_IRQHandler
+  0x3418072C:  34182291     DC.W       MDIOS_IRQHandler
+  0x34180730:  34182293     DC.W       DCMI_PSSI_IRQHandler
+  0x34180734:  34182295     DC.W       WAKEUP_PIN_IRQHandler
+  0x34180738:  34182297     DC.W       CTI_INT0_IRQHandler
+  0x3418073C:  34182299     DC.W       CTI_INT1_IRQHandler
+  0x34180740:  00           DC.B       0x00                     ; '\0'
+  0x34180741:  00           DC.B       0x00                     ; '\0'
+  0x34180742:  00           DC.B       0x00                     ; '\0'
+  0x34180743:  00           DC.B       0x00                     ; '\0'
+  0x34180744:  3418229B     DC.W       LTDC_UP_IRQHandler
+  0x34180748:  3418229D     DC.W       LTDC_UP_ERR_IRQHandler
+
+

Section .text.main from blto2_FSBL_lto.o, size=1184, align=4

+ +
+
main:
+_vectors_end:
+  0x3418074C:  B0B6         SUB        SP, SP, #216
+  0x3418074E:  F64E 5414    MOVW       R4, #0xED14
+  0x34180752:  F2CE 0400    MOVT       R4, #0xE000
+  0x34180756:  6820         LDR        R0, [R4]
+  0x34180758:  0380         LSLS       R0, R0, #14
+  0x3418075A:  D412         BMI        46L1                      ; 0x34180782
+  0x3418075C:  F3BF 8F4F    DSB        SY
+  0x34180760:  2000         MOVS       R0, #0
+  0x34180762:  F3BF 8F6F    ISB        SY
+  0x34180766:  F8C4 023C    STR.W      R0, [R4, #0x023C]
+  0x3418076A:  F3BF 8F4F    DSB        SY
+  0x3418076E:  F3BF 8F6F    ISB        SY
+  0x34180772:  6820         LDR        R0, [R4]
+  0x34180774:  F440 3000    ORR        R0, R0, #0x020000
+  0x34180778:  6020         STR        R0, [R4]
+  0x3418077A:  F3BF 8F4F    DSB        SY
+  0x3418077E:  F3BF 8F6F    ISB        SY
+
.L1:
+  0x34180782:  6820         LDR        R0, [R4]
+  0x34180784:  03C0         LSLS       R0, R0, #15
+  0x34180786:  D426         BMI        46L4                      ; 0x341807D6
+  0x34180788:  2000         MOVS       R0, #0
+  0x3418078A:  F643 72E0    MOVW       R2, #0x3FE0
+  0x3418078E:  6720         STR        R0, [R4, #112]
+  0x34180790:  F3BF 8F4F    DSB        SY
+  0x34180794:  6EE1         LDR        R1, [R4, #108]
+  0x34180796:  F3C1 06C9    UBFX       R6, R1, #3, #10
+  0x3418079A:  F3C1 304E    UBFX       R0, R1, #13, #15
+  0x3418079E:  F106 0A01    ADD.W      R10, R6, #1
+  0x341807A2:  BF00         NOP
+
.L2:
+  0x341807A4:  F04A E001    DLS        LR, R10
+  0x341807A8:  4631         MOV        R1, R6
+  0x341807AA:  EA02 1340    AND.W      R3, R2, R0, LSL #5
+  0x341807AE:  BF00         NOP
+
.L3:
+  0x341807B0:  EA43 7581    ORR.W      R5, R3, R1, LSL #30
+  0x341807B4:  3901         SUBS       R1, #1
+  0x341807B6:  F8C4 524C    STR.W      R5, [R4, #0x024C]
+  0x341807BA:  F00F C807    LE         LR, .L3                  ; 0x341807B0
+  0x341807BE:  3801         SUBS       R0, #1
+  0x341807C0:  D2F0         BCS        46L2                      ; 0x341807A4
+  0x341807C2:  F3BF 8F4F    DSB        SY
+  0x341807C6:  6820         LDR        R0, [R4]
+  0x341807C8:  F440 3080    ORR        R0, R0, #0x010000
+  0x341807CC:  6020         STR        R0, [R4]
+  0x341807CE:  F3BF 8F4F    DSB        SY
+  0x341807D2:  F3BF 8F6F    ISB        SY
+
.L4:
+  0x341807D6:  F854 0C08    LDR        R0, [R4, #-8]
+  0x341807DA:  F64F 01FF    MOVW       R1, #0xF8FF
+  0x341807DE:  F644 0520    MOVW       R5, #0x4820
+  0x341807E2:  4008         ANDS       R0, R1
+  0x341807E4:  F240 3100    MOVW       R1, #0x0300
+  0x341807E8:  F2C0 51FA    MOVT       R1, #0x05FA
+  0x341807EC:  4308         ORRS       R0, R1
+  0x341807EE:  F844 0C08    STR        R0, [R4, #-8]
+  0x341807F2:  F2C5 6502    MOVT       R5, #0x5602
+  0x341807F6:  F000 FA01    BL         SystemCoreClockUpdate    ; 0x34180BFC
+  0x341807FA:  F242 20AC    MOVW       R0, #0x22AC              ; 0x341822AC = SystemCoreClock
+  0x341807FE:  F644 51D3    MOVW       R1, #0x4DD3
+  0x34180802:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822AC = SystemCoreClock
+  0x34180806:  6800         LDR        R0, [R0]
+  0x34180808:  F2C1 0162    MOVT       R1, #0x1062
+  0x3418080C:  FBA0 0101    UMULL      R0, R1, R0, R1
+  0x34180810:  F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+  0x34180814:  EB00 1191    ADD.W      R1, R0, R1, LSR #6
+  0x34180818:  0E0A         LSRS       R2, R1, #24
+  0x3418081A:  D124         BNE        46L5                      ; 0x34180866
+  0x3418081C:  F24E 0210    MOVW       R2, #0xE010
+  0x34180820:  F2CE 0200    MOVT       R2, #0xE000
+  0x34180824:  6051         STR        R1, [R2, #4]
+  0x34180826:  21F0         MOVS       R1, #240
+  0x34180828:  73E1         STRB       R1, [R4, #15]
+  0x3418082A:  2100         MOVS       R1, #0
+  0x3418082C:  6091         STR        R1, [R2, #8]
+  0x3418082E:  2107         MOVS       R1, #7
+  0x34180830:  6011         STR        R1, [R2]
+  0x34180832:  F854 1C08    LDR        R1, [R4, #-8]
+  0x34180836:  F3C1 2102    UBFX       R1, R1, #8, #3
+  0x3418083A:  F081 0207    EOR        R2, R1, #7
+  0x3418083E:  2A04         CMP        R2, #4
+  0x34180840:  BF28         IT         CS
+  0x34180842:  2204         MOVCS      R2, #4
+  0x34180844:  4090         LSLS       R0, R2
+  0x34180846:  43C0         MVNS       R0, R0
+  0x34180848:  3903         SUBS       R1, #3
+  0x3418084A:  BF28         IT         CS
+  0x3418084C:  4088         LSLCS      R0, R1
+  0x3418084E:  2101         MOVS       R1, #1
+  0x34180850:  0100         LSLS       R0, R0, #4
+  0x34180852:  73E0         STRB       R0, [R4, #15]
+  0x34180854:  F242 20A8    MOVW       R0, #0x22A8              ; 0x341822A8 = uwTickPrio
+  0x34180858:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A8 = uwTickPrio
+  0x3418085C:  7001         STRB       R1, [R0]
+  0x3418085E:  69E8         LDR        R0, [R5, #28]
+  0x34180860:  F440 7000    ORR        R0, R0, #0x0200
+  0x34180864:  61E8         STR        R0, [R5, #28]
+
.L5:
+  0x34180866:  A811         ADD        R0, SP, #68
+  0x34180868:  2194         MOVS       R1, #148
+  0x3418086A:  F000 FE3F    BL         __aeabi_memclr           ; 0x341814EC
+  0x3418086E:  4668         MOV        R0, SP
+  0x34180870:  2140         MOVS       R1, #64
+  0x34180872:  F000 FE3B    BL         __aeabi_memclr           ; 0x341814EC
+  0x34180876:  F855 0C20    LDR        R0, [R5, #-32]
+  0x3418087A:  F242 2AA4    MOVW       R10, #0x22A4             ; 0x341822A4 = uwTick
+  0x3418087E:  F2C3 4A18    MOVT       R10, #0x3418             ; 0x341822A4 = uwTick
+  0x34180882:  F020 0004    BIC        R0, R0, #4
+  0x34180886:  F845 0C20    STR        R0, [R5, #-32]
+  0x3418088A:  F8DA 0000    LDR.W      R0, [R10]
+  0x3418088E:  BF00         NOP
+
.L6:
+  0x34180890:  6829         LDR        R1, [R5]
+  0x34180892:  0389         LSLS       R1, R1, #14
+  0x34180894:  D407         BMI        46L8                      ; 0x341808A6
+  0x34180896:  F8DA 1000    LDR.W      R1, [R10]
+  0x3418089A:  1A09         SUBS       R1, R1, R0
+  0x3418089C:  F5B1 7F7A    CMP.W      R1, #0x03E8
+  0x341808A0:  D9F6         BLS        46L6                      ; 0x34180890
+  0x341808A2:  B672         CPSID      i
+
.L7:
+  0x341808A4:  E7FE         B          46L7                      ; 0x341808A4
+
.L8:
+  0x341808A6:  6828         LDR        R0, [R5]
+  0x341808A8:  F020 0001    BIC        R0, R0, #1
+  0x341808AC:  6028         STR        R0, [R5]
+  0x341808AE:  F8DA 0000    LDR.W      R0, [R10]
+  0x341808B2:  BF00         NOP
+
.L9:
+  0x341808B4:  6829         LDR        R1, [R5]
+  0x341808B6:  0789         LSLS       R1, R1, #30
+  0x341808B8:  D407         BMI        46L11                     ; 0x341808CA
+  0x341808BA:  F8DA 1000    LDR.W      R1, [R10]
+  0x341808BE:  1A09         SUBS       R1, R1, R0
+  0x341808C0:  F5B1 7F7A    CMP.W      R1, #0x03E8
+  0x341808C4:  D9F6         BLS        46L9                      ; 0x341808B4
+  0x341808C6:  B672         CPSID      i
+
.L10:
+  0x341808C8:  E7FE         B          46L10                     ; 0x341808C8
+
.L11:
+  0x341808CA:  2002         MOVS       R0, #2
+  0x341808CC:  9010         STR        R0, [SP, #64]
+  0x341808CE:  2008         MOVS       R0, #8
+  0x341808D0:  9013         STR        R0, [SP, #76]
+  0x341808D2:  2000         MOVS       R0, #0
+  0x341808D4:  E9CD 0014    STRD       R0, R0, [SP, #80]
+  0x341808D8:  901A         STR        R0, [SP, #104]
+  0x341808DA:  9021         STR        R0, [SP, #132]
+  0x341808DC:  9028         STR        R0, [SP, #160]
+  0x341808DE:  902F         STR        R0, [SP, #188]
+  0x341808E0:  A810         ADD        R0, SP, #64
+  0x341808E2:  F000 FFB1    BL         HAL_RCC_OscConfig        ; 0x34181848
+  0x341808E6:  B110         CBZ        R0, .L13                 ; 0x341808EE
+  0x341808E8:  B672         CPSID      i
+  0x341808EA:  BF00         NOP
+
.L12:
+  0x341808EC:  E7FE         B          46L12                     ; 0x341808EC
+
.L13:
+  0x341808EE:  207F         MOVS       R0, #127
+  0x341808F0:  F248 265C    MOVW       R6, #0x825C
+  0x341808F4:  9000         STR        R0, [SP, #0]
+  0x341808F6:  F64F 50C4    MOVW       R0, #0xFDC4
+  0x341808FA:  F2C5 6602    MOVT       R6, #0x5602
+  0x341808FE:  F44F 3140    MOV.W      R1, #0x030000
+  0x34180902:  F6CF 70FF    MOVT       R0, #0xFFFF
+  0x34180906:  5830         LDR        R0, [R6, R0]
+  0x34180908:  EA01 1110    AND.W      R1, R1, R0, LSR #4
+  0x3418090C:  9101         STR        R1, [SP, #4]
+  0x3418090E:  F5B1 3F40    CMP.W      R1, #0x030000
+  0x34180912:  F04F 7140    MOV.W      R1, #0x03000000
+  0x34180916:  EA01 1010    AND.W      R0, R1, R0, LSR #4
+  0x3418091A:  F64F 51C8    MOVW       R1, #0xFDC8
+  0x3418091E:  9002         STR        R0, [SP, #8]
+  0x34180920:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x34180924:  5871         LDR        R1, [R6, R1]
+  0x34180926:  F401 02E0    AND        R2, R1, #0x700000
+  0x3418092A:  9203         STR        R2, [SP, #12]
+  0x3418092C:  F001 0207    AND        R2, R1, #7
+  0x34180930:  9204         STR        R2, [SP, #16]
+  0x34180932:  F001 0270    AND        R2, R1, #112
+  0x34180936:  9205         STR        R2, [SP, #20]
+  0x34180938:  F401 42E0    AND        R2, R1, #0x7000
+  0x3418093C:  F401 21E0    AND        R1, R1, #0x070000
+  0x34180940:  E9CD 2106    STRD       R2, R1, [SP, #24]
+  0x34180944:  F64F 6168    MOVW       R1, #0xFE68
+  0x34180948:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x3418094C:  5871         LDR        R1, [R6, R1]
+  0x3418094E:  F001 5240    AND        R2, R1, #0x30000000
+  0x34180952:  9208         STR        R2, [SP, #32]
+  0x34180954:  F04F 0201    MOV.W      R2, #1
+  0x34180958:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x3418095C:  9109         STR        R1, [SP, #36]
+  0x3418095E:  F64F 616C    MOVW       R1, #0xFE6C
+  0x34180962:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x34180966:  5871         LDR        R1, [R6, R1]
+  0x34180968:  F001 5340    AND        R3, R1, #0x30000000
+  0x3418096C:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x34180970:  E9CD 310A    STRD       R3, R1, [SP, #40]
+  0x34180974:  F64F 617C    MOVW       R1, #0xFE7C
+  0x34180978:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x3418097C:  5871         LDR        R1, [R6, R1]
+  0x3418097E:  F001 5340    AND        R3, R1, #0x30000000
+  0x34180982:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x34180986:  E9CD 310C    STRD       R3, R1, [SP, #48]
+  0x3418098A:  F64F 6190    MOVW       R1, #0xFE90
+  0x3418098E:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x34180992:  5871         LDR        R1, [R6, R1]
+  0x34180994:  FA52 F2A1    UXTAB      R2, R2, R1, ROR #16
+  0x34180998:  F001 5140    AND        R1, R1, #0x30000000
+  0x3418099C:  E9CD 120E    STRD       R1, R2, [SP, #56]
+  0x341809A0:  BF18         IT         NE
+  0x341809A2:  F1B0 7F40    CMPNE.W    R0, #0x03000000
+  0x341809A6:  D10A         BNE        46L15                     ; 0x341809BE
+  0x341809A8:  2003         MOVS       R0, #3
+  0x341809AA:  9000         STR        R0, [SP, #0]
+  0x341809AC:  2000         MOVS       R0, #0
+  0x341809AE:  E9CD 0001    STRD       R0, R0, [SP, #4]
+  0x341809B2:  4668         MOV        R0, SP
+  0x341809B4:  F000 F9EA    BL         HAL_RCC_ClockConfig      ; 0x34180D8C
+  0x341809B8:  B108         CBZ        R0, .L15                 ; 0x341809BE
+  0x341809BA:  B672         CPSID      i
+
.L14:
+  0x341809BC:  E7FE         B          46L14                     ; 0x341809BC
+
.L15:
+  0x341809BE:  2500         MOVS       R5, #0
+  0x341809C0:  204B         MOVS       R0, #75
+  0x341809C2:  E9CD 501D    STRD       R5, R0, [SP, #116]
+  0x341809C6:  2001         MOVS       R0, #1
+  0x341809C8:  F04F 0902    MOV.W      R9, #2
+  0x341809CC:  F04F 0804    MOV.W      R8, #4
+  0x341809D0:  9510         STR        R5, [SP, #64]
+  0x341809D2:  E9CD 001F    STRD       R0, R0, [SP, #124]
+  0x341809D6:  A810         ADD        R0, SP, #64
+  0x341809D8:  F8CD 8070    STR.W      R8, [SP, #112]
+  0x341809DC:  E9CD 951A    STRD       R9, R5, [SP, #104]
+  0x341809E0:  9521         STR        R5, [SP, #132]
+  0x341809E2:  9528         STR        R5, [SP, #160]
+  0x341809E4:  952F         STR        R5, [SP, #188]
+  0x341809E6:  F000 FF2F    BL         HAL_RCC_OscConfig        ; 0x34181848
+  0x341809EA:  B110         CBZ        R0, .L17                 ; 0x341809F2
+  0x341809EC:  B672         CPSID      i
+  0x341809EE:  BF00         NOP
+
.L16:
+  0x341809F0:  E7FE         B          46L16                     ; 0x341809F0
+
.L17:
+  0x341809F2:  207F         MOVS       R0, #127
+  0x341809F4:  2703         MOVS       R7, #3
+  0x341809F6:  9000         STR        R0, [SP, #0]
+  0x341809F8:  F44F 3040    MOV.W      R0, #0x030000
+  0x341809FC:  9001         STR        R0, [SP, #4]
+  0x341809FE:  F04F 7040    MOV.W      R0, #0x03000000
+  0x34180A02:  9002         STR        R0, [SP, #8]
+  0x34180A04:  F44F 1080    MOV.W      R0, #0x100000
+  0x34180A08:  E9CD 0503    STRD       R0, R5, [SP, #12]
+  0x34180A0C:  4668         MOV        R0, SP
+  0x34180A0E:  970F         STR        R7, [SP, #60]
+  0x34180A10:  E9CD 5505    STRD       R5, R5, [SP, #20]
+  0x34180A14:  E9CD 5507    STRD       R5, R5, [SP, #28]
+  0x34180A18:  E9CD 9509    STRD       R9, R5, [SP, #36]
+  0x34180A1C:  E9CD 750B    STRD       R7, R5, [SP, #44]
+  0x34180A20:  E9CD 850D    STRD       R8, R5, [SP, #52]
+  0x34180A24:  F000 F9B2    BL         HAL_RCC_ClockConfig      ; 0x34180D8C
+  0x34180A28:  B108         CBZ        R0, .L19                 ; 0x34180A2E
+  0x34180A2A:  B672         CPSID      i
+
.L18:
+  0x34180A2C:  E7FE         B          46L18                     ; 0x34180A2C
+
.L19:
+  0x34180A2E:  F04F 0B00    MOV.W      R11, #0
+  0x34180A32:  F506 6000    ADD.W      R0, R6, #0x0800
+  0x34180A36:  F44F 3180    MOV.W      R1, #0x010000
+  0x34180A3A:  F641 0528    MOVW       R5, #0x1828
+  0x34180A3E:  E9CD BB13    STRD       R11, R11, [SP, #76]
+  0x34180A42:  6001         STR        R1, [R0]
+  0x34180A44:  6831         LDR        R1, [R6]
+  0x34180A46:  F2C5 6502    MOVT       R5, #0x5602
+  0x34180A4A:  9100         STR        R1, [SP, #0]
+  0x34180A4C:  9900         LDR        R1, [SP, #0]
+  0x34180A4E:  F8C0 8000    STR.W      R8, [R0]
+  0x34180A52:  F04F 0801    MOV.W      R8, #1
+  0x34180A56:  6831         LDR        R1, [R6]
+  0x34180A58:  9100         STR        R1, [SP, #0]
+  0x34180A5A:  9900         LDR        R1, [SP, #0]
+  0x34180A5C:  2110         MOVS       R1, #16
+  0x34180A5E:  6001         STR        R1, [R0]
+  0x34180A60:  6831         LDR        R1, [R6]
+  0x34180A62:  9100         STR        R1, [SP, #0]
+  0x34180A64:  9900         LDR        R1, [SP, #0]
+  0x34180A66:  2108         MOVS       R1, #8
+  0x34180A68:  6001         STR        R1, [R0]
+  0x34180A6A:  6831         LDR        R1, [R6]
+  0x34180A6C:  9100         STR        R1, [SP, #0]
+  0x34180A6E:  9900         LDR        R1, [SP, #0]
+  0x34180A70:  2180         MOVS       R1, #128
+  0x34180A72:  6001         STR        R1, [R0]
+  0x34180A74:  6831         LDR        R1, [R6]
+  0x34180A76:  9100         STR        R1, [SP, #0]
+  0x34180A78:  9900         LDR        R1, [SP, #0]
+  0x34180A7A:  F8C0 9000    STR.W      R9, [R0]
+  0x34180A7E:  6831         LDR        R1, [R6]
+  0x34180A80:  9100         STR        R1, [SP, #0]
+  0x34180A82:  9900         LDR        R1, [SP, #0]
+  0x34180A84:  F44F 4100    MOV.W      R1, #0x8000
+  0x34180A88:  6001         STR        R1, [R0]
+  0x34180A8A:  6831         LDR        R1, [R6]
+  0x34180A8C:  9100         STR        R1, [SP, #0]
+  0x34180A8E:  9900         LDR        R1, [SP, #0]
+  0x34180A90:  F44F 4180    MOV.W      R1, #0x4000
+  0x34180A94:  6001         STR        R1, [R0]
+  0x34180A96:  6831         LDR        R1, [R6]
+  0x34180A98:  9100         STR        R1, [SP, #0]
+  0x34180A9A:  9900         LDR        R1, [SP, #0]
+  0x34180A9C:  2140         MOVS       R1, #64
+  0x34180A9E:  6001         STR        R1, [R0]
+  0x34180AA0:  6831         LDR        R1, [R6]
+  0x34180AA2:  9100         STR        R1, [SP, #0]
+  0x34180AA4:  9900         LDR        R1, [SP, #0]
+  0x34180AA6:  2120         MOVS       R1, #32
+  0x34180AA8:  6001         STR        R1, [R0]
+  0x34180AAA:  6831         LDR        R1, [R6]
+  0x34180AAC:  9100         STR        R1, [SP, #0]
+  0x34180AAE:  9900         LDR        R1, [SP, #0]
+  0x34180AB0:  F44F 5100    MOV.W      R1, #0x2000
+  0x34180AB4:  6001         STR        R1, [R0]
+  0x34180AB6:  6831         LDR        R1, [R6]
+  0x34180AB8:  9100         STR        R1, [SP, #0]
+  0x34180ABA:  9900         LDR        R1, [SP, #0]
+  0x34180ABC:  F8C0 8000    STR.W      R8, [R0]
+  0x34180AC0:  A910         ADD        R1, SP, #64
+  0x34180AC2:  6830         LDR        R0, [R6]
+  0x34180AC4:  9000         STR        R0, [SP, #0]
+  0x34180AC6:  9800         LDR        R0, [SP, #0]
+  0x34180AC8:  20FF         MOVS       R0, #255
+  0x34180ACA:  F8C5 8000    STR.W      R8, [R5]
+  0x34180ACE:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180AD2:  A910         ADD        R1, SP, #64
+  0x34180AD4:  F244 0000    MOVW       R0, #0x4000
+  0x34180AD8:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180ADC:  F000 FDE2    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180AE0:  F643 70FF    MOVW       R0, #0x3FFF
+  0x34180AE4:  A910         ADD        R1, SP, #64
+  0x34180AE6:  F1A5 0928    SUB.W      R9, R5, #40
+  0x34180AEA:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180AEE:  F5A9 5080    SUB.W      R0, R9, #0x1000
+  0x34180AF2:  A910         ADD        R1, SP, #64
+  0x34180AF4:  F000 FDD6    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180AF8:  F64F 76FF    MOVW       R6, #0xFFFF
+  0x34180AFC:  A810         ADD        R0, SP, #64
+  0x34180AFE:  E880 08C0    STM.W      R0, {R6-R7, R11}
+  0x34180B02:  F5A9 6000    SUB.W      R0, R9, #0x0800
+  0x34180B06:  A910         ADD        R1, SP, #64
+  0x34180B08:  F000 FDCC    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B0C:  A810         ADD        R0, SP, #64
+  0x34180B0E:  A910         ADD        R1, SP, #64
+  0x34180B10:  E880 08C0    STM.W      R0, {R6-R7, R11}
+  0x34180B14:  F5A9 6040    SUB.W      R0, R9, #0x0C00
+  0x34180B18:  F000 FDC4    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B1C:  F44F 707F    MOV.W      R0, #0x03FC
+  0x34180B20:  A910         ADD        R1, SP, #64
+  0x34180B22:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180B26:  F505 7076    ADD.W      R0, R5, #0x03D8
+  0x34180B2A:  A910         ADD        R1, SP, #64
+  0x34180B2C:  F000 FDBA    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B30:  A810         ADD        R0, SP, #64
+  0x34180B32:  A910         ADD        R1, SP, #64
+  0x34180B34:  E880 08C0    STM.W      R0, {R6-R7, R11}
+  0x34180B38:  F5A9 50A0    SUB.W      R0, R9, #0x1400
+  0x34180B3C:  F000 FDB2    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B40:  A810         ADD        R0, SP, #64
+  0x34180B42:  A910         ADD        R1, SP, #64
+  0x34180B44:  E880 08C0    STM.W      R0, {R6-R7, R11}
+  0x34180B48:  F509 56E0    ADD.W      R6, R9, #0x1C00
+  0x34180B4C:  F506 6000    ADD.W      R0, R6, #0x0800
+  0x34180B50:  F000 FDA8    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B54:  203F         MOVS       R0, #63
+  0x34180B56:  A910         ADD        R1, SP, #64
+  0x34180B58:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180B5C:  F506 6080    ADD.W      R0, R6, #0x0400
+  0x34180B60:  A910         ADD        R1, SP, #64
+  0x34180B62:  F000 FD9F    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B66:  F64F 30FE    MOVW       R0, #0xFBFE
+  0x34180B6A:  A910         ADD        R1, SP, #64
+  0x34180B6C:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180B70:  4648         MOV        R0, R9
+  0x34180B72:  A910         ADD        R1, SP, #64
+  0x34180B74:  F000 FD96    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B78:  F64F 70FF    MOVW       R0, #0xFFFF
+  0x34180B7C:  A910         ADD        R1, SP, #64
+  0x34180B7E:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180B82:  F5A9 6080    SUB.W      R0, R9, #0x0400
+  0x34180B86:  A910         ADD        R1, SP, #64
+  0x34180B88:  F000 FD8C    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180B8C:  F649 70FF    MOVW       R0, #0x9FFF
+  0x34180B90:  A910         ADD        R1, SP, #64
+  0x34180B92:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180B96:  F5A9 50C0    SUB.W      R0, R9, #0x1800
+  0x34180B9A:  A910         ADD        R1, SP, #64
+  0x34180B9C:  F000 FD82    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180BA0:  F44F 5084    MOV.W      R0, #0x1080
+  0x34180BA4:  A910         ADD        R1, SP, #64
+  0x34180BA6:  E881 0881    STM.W      R1, {R0, R7, R11}
+  0x34180BAA:  4630         MOV        R0, R6
+  0x34180BAC:  A910         ADD        R1, SP, #64
+  0x34180BAE:  F000 FD79    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180BB2:  4648         MOV        R0, R9
+  0x34180BB4:  A910         ADD        R1, SP, #64
+  0x34180BB6:  E9CD 8810    STRD       R8, R8, [SP, #64]
+  0x34180BBA:  E9CD BB12    STRD       R11, R11, [SP, #72]
+  0x34180BBE:  F000 FD71    BL         HAL_GPIO_Init            ; 0x341816A4
+  0x34180BC2:  BF00         NOP
+
.L20:
+  0x34180BC4:  F845 8C10    STR        R8, [R5, #-16]
+  0x34180BC8:  F8DA 0000    LDR.W      R0, [R10]
+
.L21:
+  0x34180BCC:  F8DA 1000    LDR.W      R1, [R10]
+  0x34180BD0:  1A09         SUBS       R1, R1, R0
+  0x34180BD2:  29FB         CMP        R1, #251
+  0x34180BD4:  D3FA         BCC        46L21                     ; 0x34180BCC
+  0x34180BD6:  F8C5 8000    STR.W      R8, [R5]
+  0x34180BDA:  F8DA 0000    LDR.W      R0, [R10]
+  0x34180BDE:  BF00         NOP
+
.L22:
+  0x34180BE0:  F8DA 1000    LDR.W      R1, [R10]
+  0x34180BE4:  1A09         SUBS       R1, R1, R0
+  0x34180BE6:  29FB         CMP        R1, #251
+  0x34180BE8:  D3FA         BCC        46L22                     ; 0x34180BE0
+  0x34180BEA:  E7EB         B          46L20                     ; 0x34180BC4
+
+

Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=16, align=4

+ +
+
SysTick_Handler:
+  0x34180BEC:  F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
+  0x34180BF0:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
+  0x34180BF4:  6801         LDR        R1, [R0]
+  0x34180BF6:  3101         ADDS       R1, #1
+  0x34180BF8:  6001         STR        R1, [R0]
+  0x34180BFA:  4770         BX         LR
+
+

Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=400, align=4

+ +
+
SystemCoreClockUpdate:
+  0x34180BFC:  F248 0144    MOVW       R1, #0x8044
+  0x34180C00:  F646 4000    MOVW       R0, #0x6C00
+  0x34180C04:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180C08:  F851 2C24    LDR        R2, [R1, #-36]
+  0x34180C0C:  F3C2 5201    UBFX       R2, R2, #20, #2
+  0x34180C10:  F2C0 20DC    MOVT       R0, #0x02DC
+  0x34180C14:  E8DF F002    TBB        91PC, R2]
+  0x34180C18:  02           DC.B       0x02                     ; '\x02'
+  0x34180C19:  0C           DC.B       0x0C                     ; '\x0C'
+  0x34180C1A:  AB           DC.B       0xAB                     ; '\xAB'
+  0x34180C1B:  19           DC.B       0x19                     ; '\x19'
+  0x34180C1C:  6848         LDR        R0, [R1, #4]
+  0x34180C1E:  F249 0100    MOVW       R1, #0x9000
+  0x34180C22:  F2C0 31D0    MOVT       R1, #0x03D0
+  0x34180C26:  F3C0 10C1    UBFX       R0, R0, #7, #2
+  0x34180C2A:  FA21 F000    LSR.W      R0, R1, R0
+  0x34180C2E:  E09E         B          46L6                      ; 0x34180D6E
+  0x34180C30:  6808         LDR        R0, [R1]
+  0x34180C32:  0580         LSLS       R0, R0, #22
+  0x34180C34:  F242 4000    MOVW       R0, #0x2400
+  0x34180C38:  F2C0 00F4    MOVT       R0, #244
+  0x34180C3C:  F100 8097    BMI.W      46L6                      ; 0x34180D6E
+  0x34180C40:  F640 1000    MOVW       R0, #0x0900
+  0x34180C44:  F2C0 003D    MOVT       R0, #61
+  0x34180C48:  E091         B          46L6                      ; 0x34180D6E
+  0x34180C4A:  F8D1 2080    LDR.W      R2, [R1, #128]
+  0x34180C4E:  F3C2 7201    UBFX       R2, R2, #28, #2
+  0x34180C52:  B530         PUSH       123R4-R5, LR}
+  0x34180C54:  E8DF F002    TBB        91PC, R2]
+  0x34180C58:  02           DC.B       0x02                     ; '\x02'
+  0x34180C59:  1A           DC.B       0x1A                     ; '\x1A'
+  0x34180C5A:  0A           DC.B       0x0A                     ; '\n'
+  0x34180C5B:  12           DC.B       0x12                     ; '\x12'
+  0x34180C5C:  6BCD         LDR        R5, [R1, #60]
+  0x34180C5E:  012B         LSLS       R3, R5, #4
+  0x34180C60:  D442         BMI        46L2                      ; 0x34180CE8
+  0x34180C62:  F101 0C40    ADD.W      R12, R1, #64
+  0x34180C66:  F101 0E44    ADD.W      LR, R1, #68
+  0x34180C6A:  E016         B          46L1                      ; 0x34180C9A
+  0x34180C6C:  6DCD         LDR        R5, [R1, #92]
+  0x34180C6E:  012B         LSLS       R3, R5, #4
+  0x34180C70:  D43A         BMI        46L2                      ; 0x34180CE8
+  0x34180C72:  F101 0C60    ADD.W      R12, R1, #96
+  0x34180C76:  F101 0E64    ADD.W      LR, R1, #100
+  0x34180C7A:  E00E         B          46L1                      ; 0x34180C9A
+  0x34180C7C:  6ECD         LDR        R5, [R1, #108]
+  0x34180C7E:  012B         LSLS       R3, R5, #4
+  0x34180C80:  D432         BMI        46L2                      ; 0x34180CE8
+  0x34180C82:  F101 0C70    ADD.W      R12, R1, #112
+  0x34180C86:  F101 0E74    ADD.W      LR, R1, #116
+  0x34180C8A:  E006         B          46L1                      ; 0x34180C9A
+  0x34180C8C:  6CCD         LDR        R5, [R1, #76]
+  0x34180C8E:  012B         LSLS       R3, R5, #4
+  0x34180C90:  D42A         BMI        46L2                      ; 0x34180CE8
+  0x34180C92:  F101 0C50    ADD.W      R12, R1, #80
+  0x34180C96:  F101 0E54    ADD.W      LR, R1, #84
+
.L1:
+  0x34180C9A:  F8DC 3000    LDR.W      R3, [R12]
+  0x34180C9E:  F3C5 240B    UBFX       R4, R5, #8, #12
+  0x34180CA2:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x34180CA6:  EE01 3A10    VMOV       S2, R3
+  0x34180CAA:  F8DE 2000    LDR.W      R2, [LR]
+  0x34180CAE:  EE00 4A10    VMOV       S0, R4
+  0x34180CB2:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180CB6:  ED9F 2A34    VLDR       S4, =0x33800000          ; [PC, #208] [0x34180D88]
+  0x34180CBA:  F3C5 5305    UBFX       R3, R5, #20, #6
+  0x34180CBE:  F3C2 64C2    UBFX       R4, R2, #27, #3
+  0x34180CC2:  F3C2 6202    UBFX       R2, R2, #24, #3
+  0x34180CC6:  EEB8 0A40    VCVT.F32.U32 S0, S0
+  0x34180CCA:  EE21 1A02    VMUL.F32   S2, S2, S4
+  0x34180CCE:  4362         MULS       R2, R4, R2
+  0x34180CD0:  EE31 0A00    VADD.F32   S0, S2, S0
+  0x34180CD4:  EE01 3A10    VMOV       S2, R3
+  0x34180CD8:  2301         MOVS       R3, #1
+  0x34180CDA:  EEB8 2A41    VCVT.F32.U32 S4, S2
+  0x34180CDE:  EE01 2A10    VMOV       S2, R2
+  0x34180CE2:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180CE6:  E006         B          46L3                      ; 0x34180CF6
+
.L2:
+  0x34180CE8:  ED9F 0A26    VLDR       S0, =0x00000000          ; [PC, #152] [0x34180D84]
+  0x34180CEC:  2300         MOVS       R3, #0
+  0x34180CEE:  EEB0 1A40    VMOV.F32   S2, S0
+  0x34180CF2:  EEB0 2A40    VMOV.F32   S4, S0
+
.L3:
+  0x34180CF6:  F3C5 7202    UBFX       R2, R5, #28, #3
+  0x34180CFA:  2A03         CMP        R2, #3
+  0x34180CFC:  D83D         BHI        46L7                      ; 0x34180D7A
+  0x34180CFE:  E8DF F002    TBB        91PC, R2]
+  0x34180D02:  02           DC.B       0x02                     ; '\x02'
+  0x34180D03:  0D           DC.B       0x0D                     ; '\r'
+  0x34180D04:  1E           DC.B       0x1E                     ; '\x1E'
+  0x34180D05:  1A           DC.B       0x1A                     ; '\x1A'
+  0x34180D06:  6848         LDR        R0, [R1, #4]
+  0x34180D08:  F249 0200    MOVW       R2, #0x9000
+  0x34180D0C:  F2C0 32D0    MOVT       R2, #0x03D0
+  0x34180D10:  F3C0 10C1    UBFX       R0, R0, #7, #2
+  0x34180D14:  FA22 F000    LSR.W      R0, R2, R0
+  0x34180D18:  B993         CBNZ       R3, .L4                  ; 0x34180D40
+  0x34180D1A:  E01F         B          46L5                      ; 0x34180D5C
+  0x34180D1C:  6808         LDR        R0, [R1]
+  0x34180D1E:  0580         LSLS       R0, R0, #22
+  0x34180D20:  F242 4000    MOVW       R0, #0x2400
+  0x34180D24:  F2C0 00F4    MOVT       R0, #244
+  0x34180D28:  BF5C         ITT        PL
+  0x34180D2A:  F640 1000    MOVWPL     R0, #0x0900
+  0x34180D2E:  F2C0 003D    MOVTPL     R0, #61
+  0x34180D32:  B92B         CBNZ       R3, .L4                  ; 0x34180D40
+  0x34180D34:  E012         B          46L5                      ; 0x34180D5C
+  0x34180D36:  F248 0000    MOVW       R0, #0x8000
+  0x34180D3A:  F2C0 00BB    MOVT       R0, #187
+  0x34180D3E:  B16B         CBZ        R3, .L5                  ; 0x34180D5C
+
.L4:
+  0x34180D40:  EE03 0A10    VMOV       S6, R0
+  0x34180D44:  EEB8 3A43    VCVT.F32.U32 S6, S6
+  0x34180D48:  EE20 0A03    VMUL.F32   S0, S0, S6
+  0x34180D4C:  EE80 0A02    VDIV.F32   S0, S0, S4
+  0x34180D50:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34180D54:  EEBC 0AC0    VCVT.U32.F32 S0, S0
+  0x34180D58:  EE10 0A10    VMOV       R0, S0
+
.L5:
+  0x34180D5C:  F8D1 1080    LDR.W      R1, [R1, #128]
+  0x34180D60:  2201         MOVS       R2, #1
+  0x34180D62:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x34180D66:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34180D6A:  E8BD 4030    POP.W      123R4-R5, LR}
+
.L6:
+  0x34180D6E:  F242 21AC    MOVW       R1, #0x22AC              ; 0x341822AC = SystemCoreClock
+  0x34180D72:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822AC = SystemCoreClock
+  0x34180D76:  6008         STR        R0, [R1]
+  0x34180D78:  4770         BX         LR
+
.L7:
+  0x34180D7A:  2000         MOVS       R0, #0
+  0x34180D7C:  2B00         CMP        R3, #0
+  0x34180D7E:  D1DF         BNE        46L4                      ; 0x34180D40
+  0x34180D80:  E7EC         B          46L5                      ; 0x34180D5C
+  0x34180D82:  BF00         NOP
+  0x34180D84:  00000000     DC.W       0x00000000
+  0x34180D88:  33800000     DC.W       0x33800000
+
+

Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=1472, align=4

+ +
+
HAL_RCC_ClockConfig:
+  0x34180D8C:  B570         PUSH       123R4-R6, LR}
+  0x34180D8E:  6801         LDR        R1, [R0]
+  0x34180D90:  F248 0424    MOVW       R4, #0x8024
+  0x34180D94:  F2C5 6402    MOVT       R4, #0x5602
+  0x34180D98:  070A         LSLS       R2, R1, #28
+  0x34180D9A:  D46A         BMI        46L13                     ; 0x34180E72
+  0x34180D9C:  06CA         LSLS       R2, R1, #27
+  0x34180D9E:  D475         BMI        46L14                     ; 0x34180E8C
+
.L1:
+  0x34180DA0:  068A         LSLS       R2, R1, #26
+  0x34180DA2:  F100 8081    BMI.W      46L15                     ; 0x34180EA8
+
.L2:
+  0x34180DA6:  064A         LSLS       R2, R1, #25
+  0x34180DA8:  F100 808C    BMI.W      46L16                     ; 0x34180EC4
+
.L3:
+  0x34180DAC:  074A         LSLS       R2, R1, #29
+  0x34180DAE:  F100 8097    BMI.W      46L17                     ; 0x34180EE0
+
.L4:
+  0x34180DB2:  07CA         LSLS       R2, R1, #31
+  0x34180DB4:  F040 80A2    BNE.W      46L18                     ; 0x34180EFC
+
.L5:
+  0x34180DB8:  078A         LSLS       R2, R1, #30
+  0x34180DBA:  F100 8216    BMI.W      46L39                     ; 0x341811EA
+
.L6:
+  0x34180DBE:  074A         LSLS       R2, R1, #29
+  0x34180DC0:  F100 8241    BMI.W      46L43                     ; 0x34181246
+
.L7:
+  0x34180DC4:  070A         LSLS       R2, R1, #28
+  0x34180DC6:  F100 824C    BMI.W      46L44                     ; 0x34181262
+
.L8:
+  0x34180DCA:  06CA         LSLS       R2, R1, #27
+  0x34180DCC:  F100 8257    BMI.W      46L45                     ; 0x3418127E
+
.L9:
+  0x34180DD0:  068A         LSLS       R2, R1, #26
+  0x34180DD2:  F100 8262    BMI.W      46L46                     ; 0x3418129A
+
.L10:
+  0x34180DD6:  0649         LSLS       R1, R1, #25
+  0x34180DD8:  D50A         BPL        46L12                     ; 0x34180DF0
+
.L11:
+  0x34180DDA:  69C0         LDR        R0, [R0, #28]
+  0x34180DDC:  6821         LDR        R1, [R4]
+  0x34180DDE:  F401 21E0    AND        R1, R1, #0x070000
+  0x34180DE2:  4288         CMP        R0, R1
+  0x34180DE4:  BF3F         ITTTT      CC
+  0x34180DE6:  6821         LDRCC      R1, [R4]
+  0x34180DE8:  F421 21E0    BICCC      R1, R1, #0x070000
+  0x34180DEC:  4308         ORRCC      R0, R1
+  0x34180DEE:  6020         STRCC      R0, [R4]
+
.L12:
+  0x34180DF0:  F242 20AC    MOVW       R0, #0x22AC              ; 0x341822AC = SystemCoreClock
+  0x34180DF4:  F644 51D3    MOVW       R1, #0x4DD3
+  0x34180DF8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822AC = SystemCoreClock
+  0x34180DFC:  6800         LDR        R0, [R0]
+  0x34180DFE:  F2C1 0162    MOVT       R1, #0x1062
+  0x34180E02:  FBA0 0101    UMULL      R0, R1, R0, R1
+  0x34180E06:  F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+  0x34180E0A:  EB00 1091    ADD.W      R0, R0, R1, LSR #6
+  0x34180E0E:  0E01         LSRS       R1, R0, #24
+  0x34180E10:  F040 81DA    BNE.W      46L34                     ; 0x341811C8
+  0x34180E14:  F242 21A8    MOVW       R1, #0x22A8              ; 0x341822A8 = uwTickPrio
+  0x34180E18:  F24E 0310    MOVW       R3, #0xE010
+  0x34180E1C:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A8 = uwTickPrio
+  0x34180E20:  780A         LDRB       R2, [R1]
+  0x34180E22:  F2CE 0300    MOVT       R3, #0xE000
+  0x34180E26:  6058         STR        R0, [R3, #4]
+  0x34180E28:  20F0         MOVS       R0, #240
+  0x34180E2A:  2A01         CMP        R2, #1
+  0x34180E2C:  F603 5213    ADDW       R2, R3, #0x0D13
+  0x34180E30:  7010         STRB       R0, [R2]
+  0x34180E32:  F04F 0000    MOV.W      R0, #0
+  0x34180E36:  6098         STR        R0, [R3, #8]
+  0x34180E38:  F04F 0007    MOV.W      R0, #7
+  0x34180E3C:  6018         STR        R0, [R3]
+  0x34180E3E:  F04F 0001    MOV.W      R0, #1
+  0x34180E42:  F040 808A    BNE.W      46L20                     ; 0x34180F5A
+  0x34180E46:  F852 3C17    LDR        R3, [R2, #-23]
+  0x34180E4A:  F04F 35FF    MOV.W      R5, #0xFFFFFFFF
+  0x34180E4E:  F3C3 2302    UBFX       R3, R3, #8, #3
+  0x34180E52:  F083 0607    EOR        R6, R3, #7
+  0x34180E56:  2E04         CMP        R6, #4
+  0x34180E58:  BF28         IT         CS
+  0x34180E5A:  2604         MOVCS      R6, #4
+  0x34180E5C:  FA05 F606    LSL.W      R6, R5, R6
+  0x34180E60:  43F6         MVNS       R6, R6
+  0x34180E62:  3B03         SUBS       R3, #3
+  0x34180E64:  BF28         IT         CS
+  0x34180E66:  409E         LSLCS      R6, R3
+  0x34180E68:  0133         LSLS       R3, R6, #4
+  0x34180E6A:  7013         STRB       R3, [R2]
+  0x34180E6C:  7008         STRB       R0, [R1]
+  0x34180E6E:  2000         MOVS       R0, #0
+  0x34180E70:  BD70         POP        123R4-R6, PC}
+
.L13:
+  0x34180E72:  6902         LDR        R2, [R0, #16]
+  0x34180E74:  6823         LDR        R3, [R4]
+  0x34180E76:  F003 0307    AND        R3, R3, #7
+  0x34180E7A:  429A         CMP        R2, R3
+  0x34180E7C:  BF81         ITTTT      HI
+  0x34180E7E:  6823         LDRHI      R3, [R4]
+  0x34180E80:  F023 0307    BICHI      R3, R3, #7
+  0x34180E84:  431A         ORRHI      R2, R3
+  0x34180E86:  6022         STRHI      R2, [R4]
+  0x34180E88:  06CA         LSLS       R2, R1, #27
+  0x34180E8A:  D589         BPL        46L1                      ; 0x34180DA0
+
.L14:
+  0x34180E8C:  6942         LDR        R2, [R0, #20]
+  0x34180E8E:  6823         LDR        R3, [R4]
+  0x34180E90:  F003 0370    AND        R3, R3, #112
+  0x34180E94:  429A         CMP        R2, R3
+  0x34180E96:  BF81         ITTTT      HI
+  0x34180E98:  6823         LDRHI      R3, [R4]
+  0x34180E9A:  F023 0370    BICHI      R3, R3, #112
+  0x34180E9E:  431A         ORRHI      R2, R3
+  0x34180EA0:  6022         STRHI      R2, [R4]
+  0x34180EA2:  068A         LSLS       R2, R1, #26
+  0x34180EA4:  F57F AF7F    BPL.W      46L2                      ; 0x34180DA6
+
.L15:
+  0x34180EA8:  6982         LDR        R2, [R0, #24]
+  0x34180EAA:  6823         LDR        R3, [R4]
+  0x34180EAC:  F403 43E0    AND        R3, R3, #0x7000
+  0x34180EB0:  429A         CMP        R2, R3
+  0x34180EB2:  BF81         ITTTT      HI
+  0x34180EB4:  6823         LDRHI      R3, [R4]
+  0x34180EB6:  F423 43E0    BICHI      R3, R3, #0x7000
+  0x34180EBA:  431A         ORRHI      R2, R3
+  0x34180EBC:  6022         STRHI      R2, [R4]
+  0x34180EBE:  064A         LSLS       R2, R1, #25
+  0x34180EC0:  F57F AF74    BPL.W      46L3                      ; 0x34180DAC
+
.L16:
+  0x34180EC4:  69C2         LDR        R2, [R0, #28]
+  0x34180EC6:  6823         LDR        R3, [R4]
+  0x34180EC8:  F403 23E0    AND        R3, R3, #0x070000
+  0x34180ECC:  429A         CMP        R2, R3
+  0x34180ECE:  BF81         ITTTT      HI
+  0x34180ED0:  6823         LDRHI      R3, [R4]
+  0x34180ED2:  F423 23E0    BICHI      R3, R3, #0x070000
+  0x34180ED6:  431A         ORRHI      R2, R3
+  0x34180ED8:  6022         STRHI      R2, [R4]
+  0x34180EDA:  074A         LSLS       R2, R1, #29
+  0x34180EDC:  F57F AF69    BPL.W      46L4                      ; 0x34180DB2
+
.L17:
+  0x34180EE0:  68C2         LDR        R2, [R0, #12]
+  0x34180EE2:  6823         LDR        R3, [R4]
+  0x34180EE4:  F403 03E0    AND        R3, R3, #0x700000
+  0x34180EE8:  429A         CMP        R2, R3
+  0x34180EEA:  BF81         ITTTT      HI
+  0x34180EEC:  6823         LDRHI      R3, [R4]
+  0x34180EEE:  F423 03E0    BICHI      R3, R3, #0x700000
+  0x34180EF2:  431A         ORRHI      R2, R3
+  0x34180EF4:  6022         STRHI      R2, [R4]
+  0x34180EF6:  07CA         LSLS       R2, R1, #31
+  0x34180EF8:  F43F AF5E    BEQ.W      46L5                      ; 0x34180DB8
+
.L18:
+  0x34180EFC:  6841         LDR        R1, [R0, #4]
+  0x34180EFE:  F5B1 3F80    CMP.W      R1, #0x010000
+  0x34180F02:  D02B         BEQ        46L21                     ; 0x34180F5C
+  0x34180F04:  F5B1 3F40    CMP.W      R1, #0x030000
+  0x34180F08:  D00A         BEQ        46L19                     ; 0x34180F20
+  0x34180F0A:  F854 2C20    LDR        R2, [R4, #-32]
+  0x34180F0E:  F5B1 3F00    CMP.W      R1, #0x020000
+  0x34180F12:  D12B         BNE        46L22                     ; 0x34180F6C
+  0x34180F14:  06D1         LSLS       R1, R2, #27
+  0x34180F16:  F140 8157    BPL.W      46L34                     ; 0x341811C8
+  0x34180F1A:  F44F 3100    MOV.W      R1, #0x020000
+  0x34180F1E:  E028         B          46L23                     ; 0x34180F72
+
.L19:
+  0x34180F20:  4605         MOV        R5, R0
+  0x34180F22:  6A01         LDR        R1, [R0, #32]
+  0x34180F24:  F8D4 00A0    LDR.W      R0, [R4, #160]
+  0x34180F28:  F000 5040    AND        R0, R0, #0x30000000
+  0x34180F2C:  F000 FA0E    BL         RCC_IC_CheckPLLSources   ; 0x3418134C
+  0x34180F30:  2800         CMP        R0, #0
+  0x34180F32:  F04F 0001    MOV.W      R0, #1
+  0x34180F36:  D010         BEQ        46L20                     ; 0x34180F5A
+  0x34180F38:  E9D5 1308    LDRD       R1, R3, [R5, #32]
+  0x34180F3C:  2600         MOVS       R6, #0
+  0x34180F3E:  F6CF 76FF    MOVT       R6, #0xFFFF
+  0x34180F42:  2201         MOVS       R2, #1
+  0x34180F44:  4628         MOV        R0, R5
+  0x34180F46:  EB06 4303    ADD.W      R3, R6, R3, LSL #16
+  0x34180F4A:  430B         ORRS       R3, R1
+  0x34180F4C:  6869         LDR        R1, [R5, #4]
+  0x34180F4E:  F8C4 30A0    STR.W      R3, [R4, #160]
+  0x34180F52:  F604 231C    ADDW       R3, R4, #0x0A1C
+  0x34180F56:  601A         STR        R2, [R3]
+  0x34180F58:  E00B         B          46L23                     ; 0x34180F72
+
.L20:
+  0x34180F5A:  BD70         POP        123R4-R6, PC}
+
.L21:
+  0x34180F5C:  F854 1C20    LDR        R1, [R4, #-32]
+  0x34180F60:  0749         LSLS       R1, R1, #29
+  0x34180F62:  F140 8131    BPL.W      46L34                     ; 0x341811C8
+  0x34180F66:  F44F 3180    MOV.W      R1, #0x010000
+  0x34180F6A:  E002         B          46L23                     ; 0x34180F72
+
.L22:
+  0x34180F6C:  0712         LSLS       R2, R2, #28
+  0x34180F6E:  F140 812B    BPL.W      46L34                     ; 0x341811C8
+
.L23:
+  0x34180F72:  F854 2C04    LDR        R2, [R4, #-4]
+  0x34180F76:  F241 3688    MOVW       R6, #0x1388
+  0x34180F7A:  F422 3240    BIC        R2, R2, #0x030000
+  0x34180F7E:  430A         ORRS       R2, R1
+  0x34180F80:  F844 2C04    STR        R2, [R4, #-4]
+  0x34180F84:  F242 22A4    MOVW       R2, #0x22A4              ; 0x341822A4 = uwTick
+  0x34180F88:  F2C3 4218    MOVT       R2, #0x3418              ; 0x341822A4 = uwTick
+  0x34180F8C:  6813         LDR        R3, [R2]
+  0x34180F8E:  BF00         NOP
+
.L24:
+  0x34180F90:  F854 5C04    LDR        R5, [R4, #-4]
+  0x34180F94:  F405 1540    AND        R5, R5, #0x300000
+  0x34180F98:  EBB5 1F01    CMP.W      R5, R1, LSL #4
+  0x34180F9C:  D005         BEQ        46L25                     ; 0x34180FAA
+  0x34180F9E:  6815         LDR        R5, [R2]
+  0x34180FA0:  1AED         SUBS       R5, R5, R3
+  0x34180FA2:  42B5         CMP        R5, R6
+  0x34180FA4:  D9F4         BLS        46L24                     ; 0x34180F90
+  0x34180FA6:  2003         MOVS       R0, #3
+  0x34180FA8:  BD70         POP        123R4-R6, PC}
+
.L25:
+  0x34180FAA:  F854 1C04    LDR        R1, [R4, #-4]
+  0x34180FAE:  F3C1 5201    UBFX       R2, R1, #20, #2
+  0x34180FB2:  F646 4100    MOVW       R1, #0x6C00
+  0x34180FB6:  F2C0 21DC    MOVT       R1, #0x02DC
+  0x34180FBA:  E8DF F012    TBH        91PC, R2, LSL #1]
+  0x34180FBE:  04           DC.B       0x04                     ; '\x04'
+  0x34180FBF:  00           DC.B       0x00                     ; '\0'
+  0x34180FC0:  0E           DC.B       0x0E                     ; '\x0E'
+  0x34180FC1:  00           DC.B       0x00                     ; '\0'
+  0x34180FC2:  0D           DC.B       0x0D                     ; '\r'
+  0x34180FC3:  01           DC.B       0x01                     ; '\x01'
+  0x34180FC4:  1B           DC.B       0x1B                     ; '\x1B'
+  0x34180FC5:  00           DC.B       0x00                     ; '\0'
+  0x34180FC6:  6A61         LDR        R1, [R4, #36]
+  0x34180FC8:  F249 0200    MOVW       R2, #0x9000
+  0x34180FCC:  F2C0 32D0    MOVT       R2, #0x03D0
+  0x34180FD0:  F3C1 11C1    UBFX       R1, R1, #7, #2
+  0x34180FD4:  FA22 F101    LSR.W      R1, R2, R1
+  0x34180FD8:  E0FE         B          46L38                     ; 0x341811D8
+  0x34180FDA:  6A21         LDR        R1, [R4, #32]
+  0x34180FDC:  0589         LSLS       R1, R1, #22
+  0x34180FDE:  F242 4100    MOVW       R1, #0x2400
+  0x34180FE2:  F2C0 01F4    MOVT       R1, #244
+  0x34180FE6:  F100 80F7    BMI.W      46L38                     ; 0x341811D8
+  0x34180FEA:  F640 1100    MOVW       R1, #0x0900
+  0x34180FEE:  F2C0 013D    MOVT       R1, #61
+  0x34180FF2:  E0F1         B          46L38                     ; 0x341811D8
+  0x34180FF4:  F8D4 10A0    LDR.W      R1, [R4, #160]
+  0x34180FF8:  2201         MOVS       R2, #1
+  0x34180FFA:  FA52 F5A1    UXTAB      R5, R2, R1, ROR #16
+  0x34180FFE:  F8D4 10A0    LDR.W      R1, [R4, #160]
+  0x34181002:  F3C1 7201    UBFX       R2, R1, #28, #2
+  0x34181006:  F854 1C20    LDR        R1, [R4, #-32]
+  0x3418100A:  E8DF F002    TBB        91PC, R2]
+  0x3418100E:  02           DC.B       0x02                     ; '\x02'
+  0x3418100F:  1C           DC.B       0x1C                     ; '\x1C'
+  0x34181010:  0A           DC.B       0x0A                     ; '\n'
+  0x34181011:  12           DC.B       0x12                     ; '\x12'
+  0x34181012:  05C9         LSLS       R1, R1, #23
+  0x34181014:  D475         BMI        46L30                     ; 0x34181102
+  0x34181016:  6DE1         LDR        R1, [R4, #92]
+  0x34181018:  0109         LSLS       R1, R1, #4
+  0x3418101A:  F140 80DA    BPL.W      46L36                     ; 0x341811D2
+  0x3418101E:  6DE1         LDR        R1, [R4, #92]
+  0x34181020:  E019         B          46L26                     ; 0x34181056
+  0x34181022:  0549         LSLS       R1, R1, #21
+  0x34181024:  D41F         BMI        46L28                     ; 0x34181066
+  0x34181026:  6FE1         LDR        R1, [R4, #124]
+  0x34181028:  0109         LSLS       R1, R1, #4
+  0x3418102A:  F140 80D2    BPL.W      46L36                     ; 0x341811D2
+  0x3418102E:  6FE1         LDR        R1, [R4, #124]
+  0x34181030:  E011         B          46L26                     ; 0x34181056
+  0x34181032:  0509         LSLS       R1, R1, #20
+  0x34181034:  D43D         BMI        46L29                     ; 0x341810B2
+  0x34181036:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x3418103A:  0109         LSLS       R1, R1, #4
+  0x3418103C:  F140 80C9    BPL.W      46L36                     ; 0x341811D2
+  0x34181040:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x34181044:  E007         B          46L26                     ; 0x34181056
+  0x34181046:  0589         LSLS       R1, R1, #22
+  0x34181048:  F100 80C0    BMI.W      46L35                     ; 0x341811CC
+  0x3418104C:  6EE1         LDR        R1, [R4, #108]
+  0x3418104E:  0109         LSLS       R1, R1, #4
+  0x34181050:  F140 80BF    BPL.W      46L36                     ; 0x341811D2
+  0x34181054:  6EE1         LDR        R1, [R4, #108]
+
.L26:
+  0x34181056:  4606         MOV        R6, R0
+  0x34181058:  F001 40E0    AND        R0, R1, #0x70000000
+  0x3418105C:  F000 F9C0    BL         RCCEx_GetPLLSourceFreq   ; 0x341813E0
+  0x34181060:  4601         MOV        R1, R0
+
.L27:
+  0x34181062:  4630         MOV        R0, R6
+  0x34181064:  E0B6         B          46L37                     ; 0x341811D4
+
.L28:
+  0x34181066:  F8D4 1084    LDR.W      R1, [R4, #132]
+  0x3418106A:  0049         LSLS       R1, R1, #1
+  0x3418106C:  F140 80B1    BPL.W      46L36                     ; 0x341811D2
+  0x34181070:  4606         MOV        R6, R0
+  0x34181072:  6FE0         LDR        R0, [R4, #124]
+  0x34181074:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181078:  F000 F9B2    BL         RCCEx_GetPLLSourceFreq   ; 0x341813E0
+  0x3418107C:  0001         MOVS       R1, R0
+  0x3418107E:  D0F0         BEQ        46L27                     ; 0x34181062
+  0x34181080:  6FE0         LDR        R0, [R4, #124]
+  0x34181082:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x34181086:  4630         MOV        R0, R6
+  0x34181088:  2A00         CMP        R2, #0
+  0x3418108A:  F000 80A2    BEQ.W      46L36                     ; 0x341811D2
+  0x3418108E:  EE00 1A10    VMOV       S0, R1
+  0x34181092:  6FE1         LDR        R1, [R4, #124]
+  0x34181094:  F8D4 3080    LDR.W      R3, [R4, #128]
+  0x34181098:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x3418109C:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x341810A0:  EE01 1A10    VMOV       S2, R1
+  0x341810A4:  F8D4 1084    LDR.W      R1, [R4, #132]
+  0x341810A8:  EE02 3A10    VMOV       S4, R3
+  0x341810AC:  F8D4 3084    LDR.W      R3, [R4, #132]
+  0x341810B0:  E120         B          46L48                     ; 0x341812F4
+
.L29:
+  0x341810B2:  F8D4 1094    LDR.W      R1, [R4, #148]
+  0x341810B6:  0049         LSLS       R1, R1, #1
+  0x341810B8:  F140 808B    BPL.W      46L36                     ; 0x341811D2
+  0x341810BC:  4606         MOV        R6, R0
+  0x341810BE:  F8D4 008C    LDR.W      R0, [R4, #140]
+  0x341810C2:  F000 40E0    AND        R0, R0, #0x70000000
+  0x341810C6:  F000 F98B    BL         RCCEx_GetPLLSourceFreq   ; 0x341813E0
+  0x341810CA:  0001         MOVS       R1, R0
+  0x341810CC:  D0C9         BEQ        46L27                     ; 0x34181062
+  0x341810CE:  F8D4 008C    LDR.W      R0, [R4, #140]
+  0x341810D2:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x341810D6:  4630         MOV        R0, R6
+  0x341810D8:  2A00         CMP        R2, #0
+  0x341810DA:  D07A         BEQ        46L36                     ; 0x341811D2
+  0x341810DC:  EE00 1A10    VMOV       S0, R1
+  0x341810E0:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x341810E4:  F8D4 3090    LDR.W      R3, [R4, #144]
+  0x341810E8:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x341810EC:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x341810F0:  EE01 1A10    VMOV       S2, R1
+  0x341810F4:  F8D4 1094    LDR.W      R1, [R4, #148]
+  0x341810F8:  EE02 3A10    VMOV       S4, R3
+  0x341810FC:  F8D4 3094    LDR.W      R3, [R4, #148]
+  0x34181100:  E0F8         B          46L48                     ; 0x341812F4
+
.L30:
+  0x34181102:  6E61         LDR        R1, [R4, #100]
+  0x34181104:  0049         LSLS       R1, R1, #1
+  0x34181106:  D564         BPL        46L36                     ; 0x341811D2
+  0x34181108:  4606         MOV        R6, R0
+  0x3418110A:  6DE0         LDR        R0, [R4, #92]
+  0x3418110C:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181110:  F000 F966    BL         RCCEx_GetPLLSourceFreq   ; 0x341813E0
+  0x34181114:  0001         MOVS       R1, R0
+  0x34181116:  D0A4         BEQ        46L27                     ; 0x34181062
+  0x34181118:  6DE0         LDR        R0, [R4, #92]
+  0x3418111A:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x3418111E:  4630         MOV        R0, R6
+  0x34181120:  2A00         CMP        R2, #0
+  0x34181122:  D056         BEQ        46L36                     ; 0x341811D2
+  0x34181124:  EE00 1A10    VMOV       S0, R1
+  0x34181128:  6DE1         LDR        R1, [R4, #92]
+  0x3418112A:  6E23         LDR        R3, [R4, #96]
+  0x3418112C:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x34181130:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x34181134:  EE01 1A10    VMOV       S2, R1
+  0x34181138:  6E61         LDR        R1, [R4, #100]
+  0x3418113A:  EE02 3A10    VMOV       S4, R3
+  0x3418113E:  6E63         LDR        R3, [R4, #100]
+  0x34181140:  E0D8         B          46L48                     ; 0x341812F4
+
.L31:
+  0x34181142:  4605         MOV        R5, R0
+  0x34181144:  6A81         LDR        R1, [R0, #40]
+  0x34181146:  F8D4 00A4    LDR.W      R0, [R4, #164]
+  0x3418114A:  F000 5040    AND        R0, R0, #0x30000000
+  0x3418114E:  F000 F8FD    BL         RCC_IC_CheckPLLSources   ; 0x3418134C
+  0x34181152:  B3C8         CBZ        R0, .L34                 ; 0x341811C8
+  0x34181154:  F8D4 00B4    LDR.W      R0, [R4, #180]
+  0x34181158:  6B29         LDR        R1, [R5, #48]
+  0x3418115A:  F000 5040    AND        R0, R0, #0x30000000
+  0x3418115E:  F000 F8F5    BL         RCC_IC_CheckPLLSources   ; 0x3418134C
+  0x34181162:  B388         CBZ        R0, .L34                 ; 0x341811C8
+  0x34181164:  F8D4 00C8    LDR.W      R0, [R4, #200]
+  0x34181168:  6BA9         LDR        R1, [R5, #56]
+  0x3418116A:  F000 5040    AND        R0, R0, #0x30000000
+  0x3418116E:  F000 F8ED    BL         RCC_IC_CheckPLLSources   ; 0x3418134C
+  0x34181172:  B348         CBZ        R0, .L34                 ; 0x341811C8
+  0x34181174:  E9D5 210A    LDRD       R2, R1, [R5, #40]
+  0x34181178:  2300         MOVS       R3, #0
+  0x3418117A:  F6CF 73FF    MOVT       R3, #0xFFFF
+  0x3418117E:  4628         MOV        R0, R5
+  0x34181180:  6B2E         LDR        R6, [R5, #48]
+  0x34181182:  EB03 4101    ADD.W      R1, R3, R1, LSL #16
+  0x34181186:  430A         ORRS       R2, R1
+  0x34181188:  68A9         LDR        R1, [R5, #8]
+  0x3418118A:  F8C4 20A4    STR.W      R2, [R4, #164]
+  0x3418118E:  6B6A         LDR        R2, [R5, #52]
+  0x34181190:  EB03 4202    ADD.W      R2, R3, R2, LSL #16
+  0x34181194:  4332         ORRS       R2, R6
+  0x34181196:  F8C4 20B4    STR.W      R2, [R4, #180]
+  0x3418119A:  6BEA         LDR        R2, [R5, #60]
+  0x3418119C:  EB03 4202    ADD.W      R2, R3, R2, LSL #16
+  0x341811A0:  6BAB         LDR        R3, [R5, #56]
+  0x341811A2:  431A         ORRS       R2, R3
+  0x341811A4:  F240 4322    MOVW       R3, #0x0422
+  0x341811A8:  F8C4 20C8    STR.W      R2, [R4, #200]
+  0x341811AC:  F648 2240    MOVW       R2, #0x8A40
+  0x341811B0:  F2C5 6202    MOVT       R2, #0x5602
+  0x341811B4:  6013         STR        R3, [R2]
+  0x341811B6:  E027         B          46L40                     ; 0x34181208
+
.L32:
+  0x341811B8:  F854 1C20    LDR        R1, [R4, #-32]
+  0x341811BC:  0709         LSLS       R1, R1, #28
+  0x341811BE:  D503         BPL        46L34                     ; 0x341811C8
+  0x341811C0:  2100         MOVS       R1, #0
+  0x341811C2:  E021         B          46L40                     ; 0x34181208
+
.L33:
+  0x341811C4:  0752         LSLS       R2, R2, #29
+  0x341811C6:  D41F         BMI        46L40                     ; 0x34181208
+
.L34:
+  0x341811C8:  2001         MOVS       R0, #1
+  0x341811CA:  BD70         POP        123R4-R6, PC}
+
.L35:
+  0x341811CC:  6F61         LDR        R1, [R4, #116]
+  0x341811CE:  0049         LSLS       R1, R1, #1
+  0x341811D0:  D472         BMI        46L47                     ; 0x341812B8
+
.L36:
+  0x341811D2:  2100         MOVS       R1, #0
+
.L37:
+  0x341811D4:  FBB1 F1F5    UDIV       R1, R1, R5
+
.L38:
+  0x341811D8:  F242 22AC    MOVW       R2, #0x22AC              ; 0x341822AC = SystemCoreClock
+  0x341811DC:  F2C3 4218    MOVT       R2, #0x3418              ; 0x341822AC = SystemCoreClock
+  0x341811E0:  6011         STR        R1, [R2]
+  0x341811E2:  6801         LDR        R1, [R0]
+  0x341811E4:  078A         LSLS       R2, R1, #30
+  0x341811E6:  F57F ADEA    BPL.W      46L6                      ; 0x34180DBE
+
.L39:
+  0x341811EA:  6881         LDR        R1, [R0, #8]
+  0x341811EC:  2900         CMP        R1, #0
+  0x341811EE:  D0E3         BEQ        46L32                     ; 0x341811B8
+  0x341811F0:  F1B1 7F40    CMP.W      R1, #0x03000000
+  0x341811F4:  D0A5         BEQ        46L31                     ; 0x34181142
+  0x341811F6:  F854 2C20    LDR        R2, [R4, #-32]
+  0x341811FA:  F1B1 7F00    CMP.W      R1, #0x02000000
+  0x341811FE:  D1E1         BNE        46L33                     ; 0x341811C4
+  0x34181200:  06D1         LSLS       R1, R2, #27
+  0x34181202:  D5E1         BPL        46L34                     ; 0x341811C8
+  0x34181204:  F04F 7100    MOV.W      R1, #0x02000000
+
.L40:
+  0x34181208:  F854 2C04    LDR        R2, [R4, #-4]
+  0x3418120C:  F241 3688    MOVW       R6, #0x1388
+  0x34181210:  F022 7240    BIC        R2, R2, #0x03000000
+  0x34181214:  430A         ORRS       R2, R1
+  0x34181216:  F844 2C04    STR        R2, [R4, #-4]
+  0x3418121A:  F242 22A4    MOVW       R2, #0x22A4              ; 0x341822A4 = uwTick
+  0x3418121E:  F2C3 4218    MOVT       R2, #0x3418              ; 0x341822A4 = uwTick
+  0x34181222:  6813         LDR        R3, [R2]
+
.L41:
+  0x34181224:  F854 5C04    LDR        R5, [R4, #-4]
+  0x34181228:  F005 5540    AND        R5, R5, #0x30000000
+  0x3418122C:  EBB5 1F01    CMP.W      R5, R1, LSL #4
+  0x34181230:  D005         BEQ        46L42                     ; 0x3418123E
+  0x34181232:  6815         LDR        R5, [R2]
+  0x34181234:  1AED         SUBS       R5, R5, R3
+  0x34181236:  42B5         CMP        R5, R6
+  0x34181238:  D9F4         BLS        46L41                     ; 0x34181224
+  0x3418123A:  2003         MOVS       R0, #3
+  0x3418123C:  BD70         POP        123R4-R6, PC}
+
.L42:
+  0x3418123E:  6801         LDR        R1, [R0]
+  0x34181240:  074A         LSLS       R2, R1, #29
+  0x34181242:  F57F ADBF    BPL.W      46L7                      ; 0x34180DC4
+
.L43:
+  0x34181246:  68C2         LDR        R2, [R0, #12]
+  0x34181248:  6823         LDR        R3, [R4]
+  0x3418124A:  F403 03E0    AND        R3, R3, #0x700000
+  0x3418124E:  429A         CMP        R2, R3
+  0x34181250:  BF3F         ITTTT      CC
+  0x34181252:  6823         LDRCC      R3, [R4]
+  0x34181254:  F423 03E0    BICCC      R3, R3, #0x700000
+  0x34181258:  431A         ORRCC      R2, R3
+  0x3418125A:  6022         STRCC      R2, [R4]
+  0x3418125C:  070A         LSLS       R2, R1, #28
+  0x3418125E:  F57F ADB4    BPL.W      46L8                      ; 0x34180DCA
+
.L44:
+  0x34181262:  6902         LDR        R2, [R0, #16]
+  0x34181264:  6823         LDR        R3, [R4]
+  0x34181266:  F003 0307    AND        R3, R3, #7
+  0x3418126A:  429A         CMP        R2, R3
+  0x3418126C:  BF3F         ITTTT      CC
+  0x3418126E:  6823         LDRCC      R3, [R4]
+  0x34181270:  F023 0307    BICCC      R3, R3, #7
+  0x34181274:  431A         ORRCC      R2, R3
+  0x34181276:  6022         STRCC      R2, [R4]
+  0x34181278:  06CA         LSLS       R2, R1, #27
+  0x3418127A:  F57F ADA9    BPL.W      46L9                      ; 0x34180DD0
+
.L45:
+  0x3418127E:  6942         LDR        R2, [R0, #20]
+  0x34181280:  6823         LDR        R3, [R4]
+  0x34181282:  F003 0370    AND        R3, R3, #112
+  0x34181286:  429A         CMP        R2, R3
+  0x34181288:  BF3F         ITTTT      CC
+  0x3418128A:  6823         LDRCC      R3, [R4]
+  0x3418128C:  F023 0370    BICCC      R3, R3, #112
+  0x34181290:  431A         ORRCC      R2, R3
+  0x34181292:  6022         STRCC      R2, [R4]
+  0x34181294:  068A         LSLS       R2, R1, #26
+  0x34181296:  F57F AD9E    BPL.W      46L10                     ; 0x34180DD6
+
.L46:
+  0x3418129A:  6982         LDR        R2, [R0, #24]
+  0x3418129C:  6823         LDR        R3, [R4]
+  0x3418129E:  F403 43E0    AND        R3, R3, #0x7000
+  0x341812A2:  429A         CMP        R2, R3
+  0x341812A4:  BF3F         ITTTT      CC
+  0x341812A6:  6823         LDRCC      R3, [R4]
+  0x341812A8:  F423 43E0    BICCC      R3, R3, #0x7000
+  0x341812AC:  431A         ORRCC      R2, R3
+  0x341812AE:  6022         STRCC      R2, [R4]
+  0x341812B0:  0649         LSLS       R1, R1, #25
+  0x341812B2:  F53F AD92    BMI.W      46L11                     ; 0x34180DDA
+  0x341812B6:  E59B         B          46L12                     ; 0x34180DF0
+
.L47:
+  0x341812B8:  4606         MOV        R6, R0
+  0x341812BA:  6EE0         LDR        R0, [R4, #108]
+  0x341812BC:  F000 40E0    AND        R0, R0, #0x70000000
+  0x341812C0:  F000 F88E    BL         RCCEx_GetPLLSourceFreq   ; 0x341813E0
+  0x341812C4:  0001         MOVS       R1, R0
+  0x341812C6:  F43F AECC    BEQ.W      46L27                     ; 0x34181062
+  0x341812CA:  6EE0         LDR        R0, [R4, #108]
+  0x341812CC:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x341812D0:  4630         MOV        R0, R6
+  0x341812D2:  2A00         CMP        R2, #0
+  0x341812D4:  F43F AF7D    BEQ.W      46L36                     ; 0x341811D2
+  0x341812D8:  EE00 1A10    VMOV       S0, R1
+  0x341812DC:  6EE1         LDR        R1, [R4, #108]
+  0x341812DE:  6F23         LDR        R3, [R4, #112]
+  0x341812E0:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x341812E4:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x341812E8:  EE01 1A10    VMOV       S2, R1
+  0x341812EC:  6F61         LDR        R1, [R4, #116]
+  0x341812EE:  EE02 3A10    VMOV       S4, R3
+  0x341812F2:  6F63         LDR        R3, [R4, #116]
+
.L48:
+  0x341812F4:  EEB8 2A42    VCVT.F32.U32 S4, S4
+  0x341812F8:  ED9F 3A13    VLDR       S6, =0x33800000          ; [PC, #76] [0x34181348]
+  0x341812FC:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34181300:  EE22 2A03    VMUL.F32   S4, S4, S6
+  0x34181304:  EEB8 0A40    VCVT.F32.U32 S0, S0
+  0x34181308:  EE32 1A01    VADD.F32   S2, S4, S2
+  0x3418130C:  F3C1 61C2    UBFX       R1, R1, #27, #3
+  0x34181310:  EE21 0A00    VMUL.F32   S0, S2, S0
+  0x34181314:  EE01 2A10    VMOV       S2, R2
+  0x34181318:  F3C3 6302    UBFX       R3, R3, #24, #3
+  0x3418131C:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34181320:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34181324:  EE01 1A10    VMOV       S2, R1
+  0x34181328:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x3418132C:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34181330:  EE01 3A10    VMOV       S2, R3
+  0x34181334:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34181338:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x3418133C:  EEBC 0AC0    VCVT.U32.F32 S0, S0
+  0x34181340:  EE10 1A10    VMOV       R1, S0
+  0x34181344:  E746         B          46L37                     ; 0x341811D4
+  0x34181346:  BF00         NOP
+  0x34181348:  33800000     DC.W       0x33800000
+
+

Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=148, align=4

+ +
+
RCC_IC_CheckPLLSources:
+  0x3418134C:  F248 0204    MOVW       R2, #0x8004
+  0x34181350:  EA4F 7030    ROR        R0, R0, #28
+  0x34181354:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181358:  2803         CMP        R0, #3
+  0x3418135A:  D81F         BHI        46L3                      ; 0x3418139C
+  0x3418135C:  E8DF F000    TBB        91PC, R0]
+  0x34181360:  02           DC.B       0x02                     ; '\x02'
+  0x34181361:  18           DC.B       0x18                     ; '\x18'
+  0x34181362:  08           DC.B       0x08                     ; '\b'
+  0x34181363:  11           DC.B       0x11                     ; '\x11'
+  0x34181364:  4610         MOV        R0, R2
+  0x34181366:  F850 3B7C    LDR        R3, [R0], #124
+  0x3418136A:  05DB         LSLS       R3, R3, #23
+  0x3418136C:  D505         BPL        46L1                      ; 0x3418137A
+  0x3418136E:  E00D         B          46L2                      ; 0x3418138C
+  0x34181370:  4610         MOV        R0, R2
+  0x34181372:  F850 3B9C    LDR        R3, [R0], #156
+  0x34181376:  055B         LSLS       R3, R3, #21
+  0x34181378:  D408         BMI        46L2                      ; 0x3418138C
+
.L1:
+  0x3418137A:  6800         LDR        R0, [R0]
+  0x3418137C:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x34181380:  E00D         B          46L4                      ; 0x3418139E
+  0x34181382:  4610         MOV        R0, R2
+  0x34181384:  F850 3BAC    LDR        R3, [R0], #172
+  0x34181388:  051B         LSLS       R3, R3, #20
+  0x3418138A:  D5F6         BPL        46L1                      ; 0x3418137A
+
.L2:
+  0x3418138C:  2001         MOVS       R0, #1
+  0x3418138E:  E006         B          46L4                      ; 0x3418139E
+  0x34181390:  4610         MOV        R0, R2
+  0x34181392:  F850 3B8C    LDR        R3, [R0], #140
+  0x34181396:  059B         LSLS       R3, R3, #22
+  0x34181398:  D4F8         BMI        46L2                      ; 0x3418138C
+  0x3418139A:  E7EE         B          46L1                      ; 0x3418137A
+
.L3:
+  0x3418139C:  2000         MOVS       R0, #0
+
.L4:
+  0x3418139E:  EA4F 7131    ROR        R1, R1, #28
+  0x341813A2:  2903         CMP        R1, #3
+  0x341813A4:  D81A         BHI        46L7                      ; 0x341813DC
+  0x341813A6:  E8DF F001    TBB        91PC, R1]
+  0x341813AA:  02           DC.B       0x02                     ; '\x02'
+  0x341813AB:  14           DC.B       0x14                     ; '\x14'
+  0x341813AC:  07           DC.B       0x07                     ; '\x07'
+  0x341813AD:  0F           DC.B       0x0F                     ; '\x0F'
+  0x341813AE:  F852 1B7C    LDR        R1, [R2], #124
+  0x341813B2:  05C9         LSLS       R1, R1, #23
+  0x341813B4:  D504         BPL        46L5                      ; 0x341813C0
+  0x341813B6:  4770         BX         LR
+  0x341813B8:  F852 1B9C    LDR        R1, [R2], #156
+  0x341813BC:  0549         LSLS       R1, R1, #21
+  0x341813BE:  D402         BMI        46L6                      ; 0x341813C6
+
.L5:
+  0x341813C0:  6811         LDR        R1, [R2]
+  0x341813C2:  EA00 60D1    AND.W      R0, R0, R1, LSR #27
+
.L6:
+  0x341813C6:  4770         BX         LR
+  0x341813C8:  F852 1BAC    LDR        R1, [R2], #172
+  0x341813CC:  0509         LSLS       R1, R1, #20
+  0x341813CE:  D5F7         BPL        46L5                      ; 0x341813C0
+  0x341813D0:  4770         BX         LR
+  0x341813D2:  F852 1B8C    LDR        R1, [R2], #140
+  0x341813D6:  0589         LSLS       R1, R1, #22
+  0x341813D8:  D5F2         BPL        46L5                      ; 0x341813C0
+  0x341813DA:  4770         BX         LR
+
.L7:
+  0x341813DC:  2000         MOVS       R0, #0
+  0x341813DE:  4770         BX         LR
+
+

Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=128, align=4

+ +
+
RCCEx_GetPLLSourceFreq:
+  0x341813E0:  EA4F 7030    ROR        R0, R0, #28
+  0x341813E4:  2803         CMP        R0, #3
+  0x341813E6:  D82D         BHI        46L1                      ; 0x34181444
+  0x341813E8:  E8DF F000    TBB        91PC, R0]
+  0x341813EC:  02           DC.B       0x02                     ; '\x02'
+  0x341813ED:  25           DC.B       0x25                     ; '%'
+  0x341813EE:  13           DC.B       0x13                     ; '\x13'
+  0x341813EF:  20           DC.B       0x20                     ; ' '
+  0x341813F0:  F248 0004    MOVW       R0, #0x8004
+  0x341813F4:  F2C5 6002    MOVT       R0, #0x5602
+  0x341813F8:  6801         LDR        R1, [R0]
+  0x341813FA:  0709         LSLS       R1, R1, #28
+  0x341813FC:  D522         BPL        46L1                      ; 0x34181444
+  0x341813FE:  6C40         LDR        R0, [R0, #68]
+  0x34181400:  F249 0100    MOVW       R1, #0x9000
+  0x34181404:  F2C0 31D0    MOVT       R1, #0x03D0
+  0x34181408:  F3C0 10C1    UBFX       R0, R0, #7, #2
+  0x3418140C:  FA21 F000    LSR.W      R0, R1, R0
+  0x34181410:  4770         BX         LR
+  0x34181412:  F248 0004    MOVW       R0, #0x8004
+  0x34181416:  F646 4100    MOVW       R1, #0x6C00
+  0x3418141A:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418141E:  6800         LDR        R0, [R0]
+  0x34181420:  F2C0 21DC    MOVT       R1, #0x02DC
+  0x34181424:  06C0         LSLS       R0, R0, #27
+  0x34181426:  EA01 70E0    AND.W      R0, R1, R0, ASR #31
+  0x3418142A:  4770         BX         LR
+  0x3418142C:  F248 0000    MOVW       R0, #0x8000
+  0x34181430:  F2C0 00BB    MOVT       R0, #187
+  0x34181434:  4770         BX         LR
+  0x34181436:  F248 0004    MOVW       R0, #0x8004
+  0x3418143A:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418143E:  6801         LDR        R1, [R0]
+  0x34181440:  0749         LSLS       R1, R1, #29
+  0x34181442:  D401         BMI        46L2                      ; 0x34181448
+
.L1:
+  0x34181444:  2000         MOVS       R0, #0
+  0x34181446:  4770         BX         LR
+
.L2:
+  0x34181448:  6C00         LDR        R0, [R0, #64]
+  0x3418144A:  0580         LSLS       R0, R0, #22
+  0x3418144C:  F242 4000    MOVW       R0, #0x2400
+  0x34181450:  F2C0 00F4    MOVT       R0, #244
+  0x34181454:  BF5C         ITT        PL
+  0x34181456:  F640 1000    MOVWPL     R0, #0x0900
+  0x3418145A:  F2C0 003D    MOVTPL     R0, #61
+  0x3418145E:  4770         BX         LR
+
+

Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto2_FSBL_lto.o, size=64, align=4

+ +
+  0x34181460:  00           DC.B       0x00                     ; '\0'
+  0x34181461:  00           DC.B       0x00                     ; '\0'
+  0x34181462:  00           DC.B       0x00                     ; '\0'
+  0x34181463:  00           DC.B       0x00                     ; '\0'
+  0x34181464:  01           DC.B       0x01                     ; '\x01'
+  0x34181465:  00           DC.B       0x00                     ; '\0'
+  0x34181466:  00           DC.B       0x00                     ; '\0'
+  0x34181467:  00           DC.B       0x00                     ; '\0'
+  0x34181468:  02           DC.B       0x02                     ; '\x02'
+  0x34181469:  00           DC.B       0x00                     ; '\0'
+  0x3418146A:  00           DC.B       0x00                     ; '\0'
+  0x3418146B:  00           DC.B       0x00                     ; '\0'
+  0x3418146C:  03           DC.B       0x03                     ; '\x03'
+  0x3418146D:  00           DC.B       0x00                     ; '\0'
+  0x3418146E:  00           DC.B       0x00                     ; '\0'
+  0x3418146F:  00           DC.B       0x00                     ; '\0'
+  0x34181470:  04           DC.B       0x04                     ; '\x04'
+  0x34181471:  00           DC.B       0x00                     ; '\0'
+  0x34181472:  00           DC.B       0x00                     ; '\0'
+  0x34181473:  00           DC.B       0x00                     ; '\0'
+  0x34181474:  05           DC.B       0x05                     ; '\x05'
+  0x34181475:  00           DC.B       0x00                     ; '\0'
+  0x34181476:  00           DC.B       0x00                     ; '\0'
+  0x34181477:  00           DC.B       0x00                     ; '\0'
+  0x34181478:  06           DC.B       0x06                     ; '\x06'
+  0x34181479:  00           DC.B       0x00                     ; '\0'
+  0x3418147A:  00           DC.B       0x00                     ; '\0'
+  0x3418147B:  00           DC.B       0x00                     ; '\0'
+  0x3418147C:  07           DC.B       0x07                     ; '\x07'
+  0x3418147D:  00           DC.B       0x00                     ; '\0'
+  0x3418147E:  00           DC.B       0x00                     ; '\0'
+  0x3418147F:  00           DC.B       0x00                     ; '\0'
+  0x34181480:  00           DC.B       0x00                     ; '\0'
+  0x34181481:  00           DC.B       0x00                     ; '\0'
+  0x34181482:  00           DC.B       0x00                     ; '\0'
+  0x34181483:  00           DC.B       0x00                     ; '\0'
+  0x34181484:  00           DC.B       0x00                     ; '\0'
+  0x34181485:  00           DC.B       0x00                     ; '\0'
+  0x34181486:  00           DC.B       0x00                     ; '\0'
+  0x34181487:  00           DC.B       0x00                     ; '\0'
+  0x34181488:  00           DC.B       0x00                     ; '\0'
+  0x34181489:  00           DC.B       0x00                     ; '\0'
+  0x3418148A:  00           DC.B       0x00                     ; '\0'
+  0x3418148B:  00           DC.B       0x00                     ; '\0'
+  0x3418148C:  00           DC.B       0x00                     ; '\0'
+  0x3418148D:  00           DC.B       0x00                     ; '\0'
+  0x3418148E:  00           DC.B       0x00                     ; '\0'
+  0x3418148F:  00           DC.B       0x00                     ; '\0'
+  0x34181490:  00           DC.B       0x00                     ; '\0'
+  0x34181491:  00           DC.B       0x00                     ; '\0'
+  0x34181492:  00           DC.B       0x00                     ; '\0'
+  0x34181493:  00           DC.B       0x00                     ; '\0'
+  0x34181494:  08           DC.B       0x08                     ; '\b'
+  0x34181495:  00           DC.B       0x00                     ; '\0'
+  0x34181496:  00           DC.B       0x00                     ; '\0'
+  0x34181497:  00           DC.B       0x00                     ; '\0'
+  0x34181498:  09           DC.B       0x09                     ; '\t'
+  0x34181499:  00           DC.B       0x00                     ; '\0'
+  0x3418149A:  00           DC.B       0x00                     ; '\0'
+  0x3418149B:  00           DC.B       0x00                     ; '\0'
+  0x3418149C:  0A           DC.B       0x0A                     ; '\n'
+  0x3418149D:  00           DC.B       0x00                     ; '\0'
+  0x3418149E:  00           DC.B       0x00                     ; '\0'
+  0x3418149F:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lswitch.table.RCC_PLL_Config from blto2_FSBL_lto.o, size=12, align=4

+ +
+  0x341814A0:  03           DC.B       0x03                     ; '\x03'
+  0x341814A1:  00           DC.B       0x00                     ; '\0'
+  0x341814A2:  00           DC.B       0x00                     ; '\0'
+  0x341814A3:  00           DC.B       0x00                     ; '\0'
+  0x341814A4:  02           DC.B       0x02                     ; '\x02'
+  0x341814A5:  00           DC.B       0x00                     ; '\0'
+  0x341814A6:  00           DC.B       0x00                     ; '\0'
+  0x341814A7:  00           DC.B       0x00                     ; '\0'
+  0x341814A8:  04           DC.B       0x04                     ; '\x04'
+  0x341814A9:  00           DC.B       0x00                     ; '\0'
+  0x341814AA:  00           DC.B       0x00                     ; '\0'
+  0x341814AB:  00           DC.B       0x00                     ; '\0'
+
+

Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

+ +
+
_start:
+  0x341814AC:  4C03         LDR        R4, =0x341822D4          ; [PC, #12] [0x341814BC] 
+
.L1:
+  0x341814AE:  6820         LDR        R0, [R4]
+  0x341814B0:  3404         ADDS       R4, #4
+  0x341814B2:  4780         BLX        R0
+  0x341814B4:  E7FB         B          46L1                      ; 0x341814AE
+
__SEGGER_init_done:
+__startup_complete:
+  0x341814B6:  F7FF F949    BL         main                     ; 0x3418074C
+
exit:
+  0x341814BA:  E7FE         B          exit                     ; 0x341814BA
+  0x341814BC:  341822D4     DC.W       341822D4               ; R_ARM_ABS32
+
+

Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4

+ +
+
reset_handler:
+Reset_Handler:
+  0x341814C0:  4909         LDR        R1, =0x341FE000          ; [PC, #36] [0x341814E8] 
+  0x341814C2:  F381 880A    MSR        MSPLIM, R1
+  0x341814C6:  F04F 0100    MOV.W      R1, #0
+  0x341814CA:  F381 880B    MSR        PSPLIM, R1
+  0x341814CE:  F000 F851    BL         SystemInit               ; 0x34181574
+  0x341814D2:  F64E 5088    MOVW       R0, #0xED88
+  0x341814D6:  F2CE 0000    MOVT       R0, #0xE000
+  0x341814DA:  6801         LDR        R1, [R0]
+  0x341814DC:  F451 0170    ORRS       R1, R1, #0xF00000
+  0x341814E0:  6001         STR        R1, [R0]
+  0x341814E2:  F7FF FFE3    BL         _start                   ; 0x341814AC
+  0x341814E6:  00           DC.B       0x00                     ; '\0'
+  0x341814E7:  00           DC.B       0x00                     ; '\0'
+  0x341814E8:  341FE000     DC.W       341FE000               ; R_ARM_ABS32
+
+

Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4

+ +
+
__aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x341814EC:  2200         MOVS       R2, #0
+
__aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x341814EE:  000B         MOVS       R3, R1
+  0x341814F0:  0011         MOVS       R1, R2
+  0x341814F2:  001A         MOVS       R2, R3
+
memset:
+  0x341814F4:  4684         MOV        R12, R0
+  0x341814F6:  B35A         CBZ        R2, .L7                  ; 0x34181550
+
.L1:
+  0x341814F8:  0783         LSLS       R3, R0, #30
+  0x341814FA:  D004         BEQ        46L2                      ; 0x34181506
+  0x341814FC:  F800 1B01    STRB       R1, [R0], #1
+  0x34181500:  1E52         SUBS       R2, R2, #1
+  0x34181502:  D1F9         BNE        46L1                      ; 0x341814F8
+  0x34181504:  E024         B          46L7                      ; 0x34181550
+
.L2:
+  0x34181506:  B2C9         UXTB       R1, R1
+  0x34181508:  EA41 2101    ORR.W      R1, R1, R1, LSL #8
+  0x3418150C:  EA41 4101    ORR.W      R1, R1, R1, LSL #16
+  0x34181510:  2A20         CMP        R2, #32
+  0x34181512:  D311         BCC        46L4                      ; 0x34181538
+  0x34181514:  3A20         SUBS       R2, #32
+  0x34181516:  E92D 03F0    PUSH.W     123R4-R9}
+  0x3418151A:  460B         MOV        R3, R1
+  0x3418151C:  460C         MOV        R4, R1
+  0x3418151E:  460D         MOV        R5, R1
+  0x34181520:  460E         MOV        R6, R1
+  0x34181522:  460F         MOV        R7, R1
+  0x34181524:  4688         MOV        R8, R1
+  0x34181526:  4689         MOV        R9, R1
+
.L3:
+  0x34181528:  E8A0 03FA    STM.W      R0!, {R1, R3-R9}
+  0x3418152C:  3A20         SUBS       R2, #32
+  0x3418152E:  D2FB         BCS        46L3                      ; 0x34181528
+  0x34181530:  E8BD 03F0    POP.W      123R4-R9}
+  0x34181534:  3220         ADDS       R2, #32
+  0x34181536:  D00B         BEQ        46L7                      ; 0x34181550
+
.L4:
+  0x34181538:  2A04         CMP        R2, #4
+  0x3418153A:  D305         BCC        46L6                      ; 0x34181548
+
.L5:
+  0x3418153C:  F840 1B04    STR        R1, [R0], #4
+  0x34181540:  1F12         SUBS       R2, R2, #4
+  0x34181542:  D005         BEQ        46L7                      ; 0x34181550
+  0x34181544:  2A04         CMP        R2, #4
+  0x34181546:  D2F9         BCS        46L5                      ; 0x3418153C
+
.L6:
+  0x34181548:  F800 1B01    STRB       R1, [R0], #1
+  0x3418154C:  1E52         SUBS       R2, R2, #1
+  0x3418154E:  D1FB         BNE        46L6                      ; 0x34181548
+
.L7:
+  0x34181550:  4660         MOV        R0, R12
+  0x34181552:  4770         BX         LR
+
+

Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
NMI_Handler:
+  0x34181554:  E7FE         B          NMI_Handler              ; 0x34181554
+
+

Section .init.PVD_PVM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
PVD_PVM_IRQHandler:
+  0x34181556:  E7FE         B          PVD_PVM_IRQHandler       ; 0x34181556
+
+

Section .text.HardFault_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
HardFault_Handler:
+  0x34181558:  E7FE         B          HardFault_Handler        ; 0x34181558
+
+

Section .init.DTS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DTS_IRQHandler:
+  0x3418155A:  E7FE         B          DTS_IRQHandler           ; 0x3418155A
+
+

Section .text.MemManage_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
MemManage_Handler:
+  0x3418155C:  E7FE         B          MemManage_Handler        ; 0x3418155C
+
+

Section .init.RCC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RCC_IRQHandler:
+  0x3418155E:  E7FE         B          RCC_IRQHandler           ; 0x3418155E
+
+

Section .text.BusFault_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
BusFault_Handler:
+  0x34181560:  E7FE         B          BusFault_Handler         ; 0x34181560
+
+

Section .init.LOCKUP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LOCKUP_IRQHandler:
+  0x34181562:  E7FE         B          LOCKUP_IRQHandler        ; 0x34181562
+
+

Section .text.UsageFault_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
UsageFault_Handler:
+  0x34181564:  E7FE         B          UsageFault_Handler       ; 0x34181564
+
+

Section .init.CACHE_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CACHE_ECC_IRQHandler:
+  0x34181566:  E7FE         B          CACHE_ECC_IRQHandler     ; 0x34181566
+
+

Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
SVC_Handler:
+  0x34181568:  4770         BX         LR
+
+

Section .init.TCM_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TCM_ECC_IRQHandler:
+  0x3418156A:  E7FE         B          TCM_ECC_IRQHandler       ; 0x3418156A
+
+

Section .text.DebugMon_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
DebugMon_Handler:
+  0x3418156C:  4770         BX         LR
+
+

Section .init.BCK_ECC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
BCK_ECC_IRQHandler:
+  0x3418156E:  E7FE         B          BCK_ECC_IRQHandler       ; 0x3418156E
+
+

Section .text.PendSV_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
PendSV_Handler:
+  0x34181570:  4770         BX         LR
+
+

Section .init.FPU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FPU_IRQHandler:
+  0x34181572:  E7FE         B          FPU_IRQHandler           ; 0x34181572
+
+

Section .text.SystemInit from blto2_FSBL_lto.o, size=302, align=4

+ +
+
SystemInit:
+  0x34181574:  B530         PUSH       123R4-R5, LR}
+  0x34181576:  F240 4100    MOVW       R1, #0x0400              ; 0x34180400 = g_pfnVectors
+  0x3418157A:  F64E 50D8    MOVW       R0, #0xEDD8
+  0x3418157E:  F648 2C18    MOVW       R12, #0x8A18
+  0x34181582:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34180400 = g_pfnVectors
+  0x34181586:  F2CE 0000    MOVT       R0, #0xE000
+  0x3418158A:  2200         MOVS       R2, #0
+  0x3418158C:  F2C5 6C02    MOVT       R12, #0x5602
+  0x34181590:  2302         MOVS       R3, #2
+  0x34181592:  F840 1CD0    STR        R1, [R0, #-208]
+  0x34181596:  2101         MOVS       R1, #1
+  0x34181598:  F60C 0E08    ADDW       LR, R12, #0x0808
+  0x3418159C:  F8CC 1000    STR.W      R1, [R12]
+  0x341815A0:  F8CC 1800    STR.W      R1, [R12, #0x0800]
+  0x341815A4:  F8CE 1038    STR.W      R1, [LR, #56]
+  0x341815A8:  6002         STR        R2, [R0]
+  0x341815AA:  6042         STR        R2, [R0, #4]
+  0x341815AC:  6082         STR        R2, [R0, #8]
+  0x341815AE:  6001         STR        R1, [R0]
+  0x341815B0:  6042         STR        R2, [R0, #4]
+  0x341815B2:  6082         STR        R2, [R0, #8]
+  0x341815B4:  6003         STR        R3, [R0]
+  0x341815B6:  2303         MOVS       R3, #3
+  0x341815B8:  6042         STR        R2, [R0, #4]
+  0x341815BA:  6082         STR        R2, [R0, #8]
+  0x341815BC:  6003         STR        R3, [R0]
+  0x341815BE:  2304         MOVS       R3, #4
+  0x341815C0:  6042         STR        R2, [R0, #4]
+  0x341815C2:  6082         STR        R2, [R0, #8]
+  0x341815C4:  6003         STR        R3, [R0]
+  0x341815C6:  2305         MOVS       R3, #5
+  0x341815C8:  6042         STR        R2, [R0, #4]
+  0x341815CA:  6082         STR        R2, [R0, #8]
+  0x341815CC:  6003         STR        R3, [R0]
+  0x341815CE:  2306         MOVS       R3, #6
+  0x341815D0:  6042         STR        R2, [R0, #4]
+  0x341815D2:  6082         STR        R2, [R0, #8]
+  0x341815D4:  6003         STR        R3, [R0]
+  0x341815D6:  2307         MOVS       R3, #7
+  0x341815D8:  6042         STR        R2, [R0, #4]
+  0x341815DA:  6082         STR        R2, [R0, #8]
+  0x341815DC:  6003         STR        R3, [R0]
+  0x341815DE:  6042         STR        R2, [R0, #4]
+  0x341815E0:  6082         STR        R2, [R0, #8]
+  0x341815E2:  F5AC 62F4    SUB.W      R2, R12, #0x07A0
+  0x341815E6:  F8CC 1060    STR.W      R1, [R12, #96]
+  0x341815EA:  6813         LDR        R3, [R2]
+  0x341815EC:  F850 4CD0    LDR        R4, [R0, #-208]
+  0x341815F0:  F248 0310    MOVW       R3, #0x8010
+  0x341815F4:  F2C5 6300    MOVT       R3, #0x5600
+  0x341815F8:  601C         STR        R4, [R3]
+  0x341815FA:  F644 043C    MOVW       R4, #0x483C
+  0x341815FE:  F2C5 6402    MOVT       R4, #0x5602
+  0x34181602:  F854 5C08    LDR        R5, [R4, #-8]
+  0x34181606:  F445 7580    ORR        R5, R5, #0x0100
+  0x3418160A:  F844 5C08    STR        R5, [R4, #-8]
+  0x3418160E:  F854 5C04    LDR        R5, [R4, #-4]
+  0x34181612:  F445 7580    ORR        R5, R5, #0x0100
+  0x34181616:  F844 5C04    STR        R5, [R4, #-4]
+  0x3418161A:  6825         LDR        R5, [R4]
+  0x3418161C:  F445 7540    ORR        R5, R5, #0x0300
+  0x34181620:  6025         STR        R5, [R4]
+  0x34181622:  F240 2587    MOVW       R5, #0x0287
+  0x34181626:  645D         STR        R5, [R3, #68]
+  0x34181628:  64DD         STR        R5, [R3, #76]
+  0x3418162A:  635D         STR        R5, [R3, #52]
+  0x3418162C:  63DD         STR        R5, [R3, #60]
+  0x3418162E:  655D         STR        R5, [R3, #84]
+  0x34181630:  6825         LDR        R5, [R4]
+  0x34181632:  F445 5580    ORR        R5, R5, #0x1000
+  0x34181636:  6025         STR        R5, [R4]
+  0x34181638:  6825         LDR        R5, [R4]
+  0x3418163A:  F045 0510    ORR        R5, R5, #16
+  0x3418163E:  6025         STR        R5, [R4]
+  0x34181640:  6824         LDR        R4, [R4]
+  0x34181642:  F852 4C04    LDR        R4, [R2, #-4]
+  0x34181646:  F444 4400    ORR        R4, R4, #0x8000
+  0x3418164A:  F842 4C04    STR        R4, [R2, #-4]
+  0x3418164E:  6814         LDR        R4, [R2]
+  0x34181650:  F044 0410    ORR        R4, R4, #16
+  0x34181654:  6014         STR        R4, [R2]
+  0x34181656:  6814         LDR        R4, [R2]
+  0x34181658:  6814         LDR        R4, [R2]
+  0x3418165A:  F024 0410    BIC        R4, R4, #16
+  0x3418165E:  6014         STR        R4, [R2]
+  0x34181660:  F44F 5240    MOV.W      R2, #0x3000
+  0x34181664:  F8CC 2008    STR.W      R2, [R12, #8]
+  0x34181668:  F8CE 2000    STR.W      R2, [LR]
+  0x3418166C:  2240         MOVS       R2, #64
+  0x3418166E:  F8CC 100C    STR.W      R1, [R12, #12]
+  0x34181672:  F8CE 1004    STR.W      R1, [LR, #4]
+  0x34181676:  F8CE 1044    STR.W      R1, [LR, #68]
+  0x3418167A:  F8CE 203C    STR.W      R2, [LR, #60]
+  0x3418167E:  681A         LDR        R2, [R3]
+  0x34181680:  F8CE 1058    STR.W      R1, [LR, #88]
+  0x34181684:  F850 1C50    LDR        R1, [R0, #-80]
+  0x34181688:  F441 0170    ORR        R1, R1, #0xF00000
+  0x3418168C:  F840 1C50    STR        R1, [R0, #-80]
+  0x34181690:  F64E 5088    MOVW       R0, #0xED88
+  0x34181694:  F2CE 0002    MOVT       R0, #0xE002
+  0x34181698:  6801         LDR        R1, [R0]
+  0x3418169A:  F441 0170    ORR        R1, R1, #0xF00000
+  0x3418169E:  6001         STR        R1, [R0]
+  0x341816A0:  BD30         POP        123R4-R5, PC}
+
+

Section .init.RTC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RTC_S_IRQHandler:
+  0x341816A2:  E7FE         B          RTC_S_IRQHandler         ; 0x341816A2
+
+

Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=418, align=4

+ +
+
HAL_GPIO_Init:
+  0x341816A4:  E92D 4FF0    PUSH.W     123R4-R11, LR}
+  0x341816A8:  B083         SUB        SP, SP, #12
+  0x341816AA:  680C         LDR        R4, [R1]
+  0x341816AC:  2C00         CMP        R4, #0
+  0x341816AE:  F000 80C7    BEQ.W      46L6                      ; 0x34181840
+  0x341816B2:  F245 0E00    MOVW       LR, #0x5000
+  0x341816B6:  F100 4328    ADD.W      R3, R0, #0xA8000000
+  0x341816BA:  F2C5 6E02    MOVT       LR, #0x5602
+  0x341816BE:  F103 73FF    ADD.W      R3, R3, #0x01FE0000
+  0x341816C2:  EA4F 22B3    ROR        R2, R3, #10
+  0x341816C6:  F5AE 5380    SUB.W      R3, LR, #0x1000
+  0x341816CA:  4298         CMP        R0, R3
+  0x341816CC:  BF14         ITE        NE
+  0x341816CE:  2310         MOVNE      R3, #16
+  0x341816D0:  230B         MOVEQ      R3, #11
+  0x341816D2:  B297         UXTH       R7, R2
+  0x341816D4:  F24E 06FF    MOVW       R6, #0xE0FF
+  0x341816D8:  9302         STR        R3, [SP, #8]
+  0x341816DA:  2500         MOVS       R5, #0
+  0x341816DC:  2A10         CMP        R2, #16
+  0x341816DE:  EA5F 932F    CSET       R3, CC
+  0x341816E2:  FA26 F707    LSR.W      R7, R6, R7
+  0x341816E6:  9200         STR        R2, [SP, #0]
+  0x341816E8:  EA03 0207    AND.W      R2, R3, R7
+  0x341816EC:  9201         STR        R2, [SP, #4]
+  0x341816EE:  E084         B          46L5                      ; 0x341817FA
+
.L1:
+  0x341816F0:  F1BB 0F03    CMP.W      R11, #3
+  0x341816F4:  BF08         IT         EQ
+  0x341816F6:  F1BC 0F01    CMPEQ.W    R12, #1
+  0x341816FA:  D024         BEQ        46L3                      ; 0x34181746
+  0x341816FC:  006B         LSLS       R3, R5, #1
+  0x341816FE:  2203         MOVS       R2, #3
+  0x34181700:  FA02 F303    LSL.W      R3, R2, R3
+  0x34181704:  43DC         MVNS       R4, R3
+
.L2:
+  0x34181706:  68C3         LDR        R3, [R0, #12]
+  0x34181708:  4023         ANDS       R3, R4
+  0x3418170A:  006C         LSLS       R4, R5, #1
+  0x3418170C:  FA0C F604    LSL.W      R6, R12, R4
+  0x34181710:  4333         ORRS       R3, R6
+  0x34181712:  F1BB 0F02    CMP.W      R11, #2
+  0x34181716:  60C3         STR        R3, [R0, #12]
+  0x34181718:  D115         BNE        46L3                      ; 0x34181746
+  0x3418171A:  F06F 0203    MVN        R2, #3
+  0x3418171E:  EA02 0655    AND.W      R6, R2, R5, LSR #1
+  0x34181722:  221C         MOVS       R2, #28
+  0x34181724:  690B         LDR        R3, [R1, #16]
+  0x34181726:  EA02 0485    AND.W      R4, R2, R5, LSL #2
+  0x3418172A:  220F         MOVS       R2, #15
+  0x3418172C:  40A3         LSLS       R3, R4
+  0x3418172E:  FA02 F404    LSL.W      R4, R2, R4
+  0x34181732:  F100 0220    ADD.W      R2, R0, #32
+  0x34181736:  5997         LDR        R7, [R2, R6]
+  0x34181738:  43A7         BICS       R7, R4
+  0x3418173A:  433B         ORRS       R3, R7
+  0x3418173C:  5193         STR        R3, [R2, R6]
+  0x3418173E:  F8D1 9004    LDR.W      R9, [R1, #4]
+  0x34181742:  F009 0B03    AND        R11, R9, #3
+
.L3:
+  0x34181746:  006B         LSLS       R3, R5, #1
+  0x34181748:  2203         MOVS       R2, #3
+  0x3418174A:  6806         LDR        R6, [R0]
+  0x3418174C:  FA0B F703    LSL.W      R7, R11, R3
+  0x34181750:  FA02 F303    LSL.W      R3, R2, R3
+  0x34181754:  EA26 0303    BIC.W      R3, R6, R3
+  0x34181758:  433B         ORRS       R3, R7
+  0x3418175A:  F419 3F40    TST        R9, #0x030000
+  0x3418175E:  6003         STR        R3, [R0]
+  0x34181760:  D046         BEQ        46L4                      ; 0x341817F0
+  0x34181762:  F10E 0460    ADD.W      R4, LR, #96
+  0x34181766:  F025 0303    BIC        R3, R5, #3
+  0x3418176A:  58E6         LDR        R6, [R4, R3]
+  0x3418176C:  E9DD 2301    LDRD       R2, R3, [SP, #4]
+  0x34181770:  2A00         CMP        R2, #0
+  0x34181772:  BF1F         ITTTT      NE
+  0x34181774:  9A00         LDRNE      R2, [SP, #0]
+  0x34181776:  F241 4360    MOVWNE     R3, #0x1460              ; 0x34181460 = .rodata..Lswitch.table.HAL_GPIO_DeInit
+  0x3418177A:  F2C3 4318    MOVTNE     R3, #0x3418              ; 0x34181460 = .rodata..Lswitch.table.HAL_GPIO_DeInit
+  0x3418177E:  F853 3022    LDRNE.W    R3, [R3, R2, LSL #2]
+  0x34181782:  2218         MOVS       R2, #24
+  0x34181784:  EA02 07C5    AND.W      R7, R2, R5, LSL #3
+  0x34181788:  220F         MOVS       R2, #15
+  0x3418178A:  40BB         LSLS       R3, R7
+  0x3418178C:  FA02 F707    LSL.W      R7, R2, R7
+  0x34181790:  EA26 0707    BIC.W      R7, R6, R7
+  0x34181794:  433B         ORRS       R3, R7
+  0x34181796:  08AF         LSRS       R7, R5, #2
+  0x34181798:  F844 3027    STR.W      R3, [R4, R7, LSL #2]
+  0x3418179C:  F8DE 3080    LDR.W      R3, [LR, #128]
+  0x341817A0:  684F         LDR        R7, [R1, #4]
+  0x341817A2:  03FE         LSLS       R6, R7, #15
+  0x341817A4:  BF4C         ITE        MI
+  0x341817A6:  EA43 0608    ORRMI.W    R6, R3, R8
+  0x341817AA:  EA23 0608    BICPL.W    R6, R3, R8
+  0x341817AE:  F8CE 6080    STR.W      R6, [LR, #128]
+  0x341817B2:  F8DE 3084    LDR.W      R3, [LR, #132]
+  0x341817B6:  03BE         LSLS       R6, R7, #14
+  0x341817B8:  BF4C         ITE        MI
+  0x341817BA:  EA43 0608    ORRMI.W    R6, R3, R8
+  0x341817BE:  EA23 0608    BICPL.W    R6, R3, R8
+  0x341817C2:  F8CE 6084    STR.W      R6, [LR, #132]
+  0x341817C6:  F8DE 3000    LDR.W      R3, [LR]
+  0x341817CA:  02FE         LSLS       R6, R7, #11
+  0x341817CC:  BF4C         ITE        MI
+  0x341817CE:  EA43 0608    ORRMI.W    R6, R3, R8
+  0x341817D2:  EA23 0608    BICPL.W    R6, R3, R8
+  0x341817D6:  F8CE 6000    STR.W      R6, [LR]
+  0x341817DA:  02BB         LSLS       R3, R7, #10
+  0x341817DC:  F8DE 3004    LDR.W      R3, [LR, #4]
+  0x341817E0:  EA43 0708    ORR.W      R7, R3, R8
+  0x341817E4:  BF58         IT         PL
+  0x341817E6:  EA23 0708    BICPL.W    R7, R3, R8
+  0x341817EA:  F8CE 7004    STR.W      R7, [LR, #4]
+  0x341817EE:  BF00         NOP
+
.L4:
+  0x341817F0:  680C         LDR        R4, [R1]
+  0x341817F2:  3501         ADDS       R5, #1
+  0x341817F4:  FA34 F305    LSRS.W     R3, R4, R5
+  0x341817F8:  D022         BEQ        46L6                      ; 0x34181840
+
.L5:
+  0x341817FA:  2201         MOVS       R2, #1
+  0x341817FC:  FA02 FA05    LSL.W      R10, R2, R5
+  0x34181800:  EA1A 0804    ANDS.W     R8, R10, R4
+  0x34181804:  D0F4         BEQ        46L4                      ; 0x341817F0
+  0x34181806:  E9D1 9C01    LDRD       R9, R12, [R1, #4]
+  0x3418180A:  F009 0B03    AND        R11, R9, #3
+  0x3418180E:  F1AB 0301    SUB.W      R3, R11, #1
+  0x34181812:  2B01         CMP        R3, #1
+  0x34181814:  F63F AF6C    BHI.W      46L1                      ; 0x341816F0
+  0x34181818:  68CB         LDR        R3, [R1, #12]
+  0x3418181A:  2203         MOVS       R2, #3
+  0x3418181C:  006C         LSLS       R4, R5, #1
+  0x3418181E:  6886         LDR        R6, [R0, #8]
+  0x34181820:  40A3         LSLS       R3, R4
+  0x34181822:  FA02 F404    LSL.W      R4, R2, R4
+  0x34181826:  43A6         BICS       R6, R4
+  0x34181828:  4333         ORRS       R3, R6
+  0x3418182A:  6083         STR        R3, [R0, #8]
+  0x3418182C:  6843         LDR        R3, [R0, #4]
+  0x3418182E:  F3C9 1600    UBFX       R6, R9, #4, #1
+  0x34181832:  EA23 030A    BIC.W      R3, R3, R10
+  0x34181836:  40AE         LSLS       R6, R5
+  0x34181838:  4333         ORRS       R3, R6
+  0x3418183A:  43E4         MVNS       R4, R4
+  0x3418183C:  6043         STR        R3, [R0, #4]
+  0x3418183E:  E762         B          46L2                      ; 0x34181706
+
.L6:
+  0x34181840:  B003         ADD        SP, SP, #12
+  0x34181842:  E8BD 8FF0    POP.W      123R4-R11, PC}
+
+

Section .init.TAMP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TAMP_IRQHandler:
+  0x34181846:  E7FE         B          TAMP_IRQHandler          ; 0x34181846
+
+

Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=1714, align=4

+ +
+
HAL_RCC_OscConfig:
+  0x34181848:  E92D 4FF8    PUSH.W     123R3-R11, LR}
+  0x3418184C:  6801         LDR        R1, [R0]
+  0x3418184E:  F248 0604    MOVW       R6, #0x8004
+  0x34181852:  4604         MOV        R4, R0
+  0x34181854:  F2C5 6602    MOVT       R6, #0x5602
+  0x34181858:  07C8         LSLS       R0, R1, #31
+  0x3418185A:  69F0         LDR        R0, [R6, #28]
+  0x3418185C:  F400 1A40    AND        R10, R0, #0x300000
+  0x34181860:  69F0         LDR        R0, [R6, #28]
+  0x34181862:  F000 5840    AND        R8, R0, #0x30000000
+  0x34181866:  6FF0         LDR        R0, [R6, #124]
+  0x34181868:  F000 49E0    AND        R9, R0, #0x70000000
+  0x3418186C:  F8D6 008C    LDR.W      R0, [R6, #140]
+  0x34181870:  F000 4BE0    AND        R11, R0, #0x70000000
+  0x34181874:  F8D6 009C    LDR.W      R0, [R6, #156]
+  0x34181878:  F000 4EE0    AND        LR, R0, #0x70000000
+  0x3418187C:  F8D6 00AC    LDR.W      R0, [R6, #172]
+  0x34181880:  6832         LDR        R2, [R6]
+  0x34181882:  F000 4CE0    AND        R12, R0, #0x70000000
+  0x34181886:  D01D         BEQ        46L4                      ; 0x341818C4
+  0x34181888:  F5BA 1F00    CMP.W      R10, #0x200000
+  0x3418188C:  BF18         IT         NE
+  0x3418188E:  F1B8 5F00    CMPNE.W    R8, #0x20000000
+  0x34181892:  F040 82D1    BNE.W      46L65                     ; 0x34181E38
+
.L1:
+  0x34181896:  6860         LDR        R0, [R4, #4]
+  0x34181898:  2800         CMP        R0, #0
+  0x3418189A:  F000 8246    BEQ.W      46L49                     ; 0x34181D2A
+  0x3418189E:  F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
+  0x341818A2:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
+  0x341818A6:  6807         LDR        R7, [R0]
+
.L2:
+  0x341818A8:  6833         LDR        R3, [R6]
+  0x341818AA:  06DB         LSLS       R3, R3, #27
+  0x341818AC:  6803         LDR        R3, [R0]
+  0x341818AE:  D405         BMI        46L3                      ; 0x341818BC
+  0x341818B0:  1BDB         SUBS       R3, R3, R7
+  0x341818B2:  2B64         CMP        R3, #100
+  0x341818B4:  D9F8         BLS        46L2                      ; 0x341818A8
+  0x341818B6:  2003         MOVS       R0, #3
+  0x341818B8:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L3:
+  0x341818BC:  6807         LDR        R7, [R0]
+  0x341818BE:  1AFF         SUBS       R7, R7, R3
+  0x341818C0:  2F02         CMP        R7, #2
+  0x341818C2:  D3FB         BCC        46L3                      ; 0x341818BC
+
.L4:
+  0x341818C4:  0788         LSLS       R0, R1, #30
+  0x341818C6:  D516         BPL        46L7                      ; 0x341818F6
+  0x341818C8:  F1BA 0F00    CMP.W      R10, #0
+  0x341818CC:  BF18         IT         NE
+  0x341818CE:  F1B8 0F00    CMPNE.W    R8, #0
+  0x341818D2:  D177         BNE        46L16                     ; 0x341819C4
+
.L5:
+  0x341818D4:  68E0         LDR        R0, [R4, #12]
+  0x341818D6:  2800         CMP        R0, #0
+  0x341818D8:  F000 8227    BEQ.W      46L49                     ; 0x34181D2A
+
.L6:
+  0x341818DC:  6C70         LDR        R0, [R6, #68]
+  0x341818DE:  E9D4 3704    LDRD       R3, R7, [R4, #16]
+  0x341818E2:  F420 70C0    BIC        R0, R0, #0x0180
+  0x341818E6:  4318         ORRS       R0, R3
+  0x341818E8:  6470         STR        R0, [R6, #68]
+  0x341818EA:  6C70         LDR        R0, [R6, #68]
+  0x341818EC:  F420 00FE    BIC        R0, R0, #0x7F0000
+  0x341818F0:  EA40 4007    ORR.W      R0, R0, R7, LSL #16
+  0x341818F4:  6470         STR        R0, [R6, #68]
+
.L7:
+  0x341818F6:  06C8         LSLS       R0, R1, #27
+  0x341818F8:  D511         BPL        46L10                     ; 0x3418191E
+  0x341818FA:  F5BA 1F80    CMP.W      R10, #0x100000
+  0x341818FE:  BF18         IT         NE
+  0x34181900:  F1B8 5F80    CMPNE.W    R8, #0x10000000
+  0x34181904:  F040 8096    BNE.W      46L22                     ; 0x34181A34
+
.L8:
+  0x34181908:  69E0         LDR        R0, [R4, #28]
+  0x3418190A:  2800         CMP        R0, #0
+  0x3418190C:  F000 820D    BEQ.W      46L49                     ; 0x34181D2A
+  0x34181910:  6A63         LDR        R3, [R4, #36]
+
.L9:
+  0x34181912:  6C30         LDR        R0, [R6, #64]
+  0x34181914:  F420 10F8    BIC        R0, R0, #0x1F0000
+  0x34181918:  EA40 4003    ORR.W      R0, R0, R3, LSL #16
+  0x3418191C:  6430         STR        R0, [R6, #64]
+
.L10:
+  0x3418191E:  F648 0500    MOVW       R5, #0x8800
+  0x34181922:  0708         LSLS       R0, R1, #28
+  0x34181924:  F2C5 6502    MOVT       R5, #0x5602
+  0x34181928:  D437         BMI        46L14                     ; 0x3418199A
+
.L11:
+  0x3418192A:  0748         LSLS       R0, R1, #29
+  0x3418192C:  F100 816F    BMI.W      46L37                     ; 0x34181C0E
+
.L12:
+  0x34181930:  46A1         MOV        R9, R4
+  0x34181932:  F859 0F28    LDR        R0, [R9, #40]!
+  0x34181936:  2800         CMP        R0, #0
+  0x34181938:  F000 80E7    BEQ.W      46L32                     ; 0x34181B0A
+  0x3418193C:  2000         MOVS       R0, #0
+  0x3418193E:  4649         MOV        R1, R9
+  0x34181940:  F000 FADC    BL         RCC_PLL_IsNewConfig      ; 0x34181EFC
+  0x34181944:  2800         CMP        R0, #0
+  0x34181946:  6830         LDR        R0, [R6]
+  0x34181948:  F000 80D7    BEQ.W      46L31                     ; 0x34181AFA
+  0x3418194C:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181950:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181954:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181958:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x3418195C:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181960:  BF08         IT         EQ
+  0x34181962:  F013 5340    ANDSEQ     R3, R3, #0x30000000
+  0x34181966:  F000 81E0    BEQ.W      46L49                     ; 0x34181D2A
+  0x3418196A:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x3418196E:  D10C         BNE        46L13                     ; 0x3418198A
+  0x34181970:  F010 5F40    TST        R0, #0x30000000
+  0x34181974:  F04F 0001    MOV.W      R0, #1
+  0x34181978:  F000 82BD    BEQ.W      46L78                     ; 0x34181EF6
+  0x3418197C:  F012 5240    ANDS       R2, R2, #0x30000000
+  0x34181980:  BF18         IT         NE
+  0x34181982:  F011 5140    ANDSNE     R1, R1, #0x30000000
+  0x34181986:  F000 82B6    BEQ.W      46L78                     ; 0x34181EF6
+
.L13:
+  0x3418198A:  2000         MOVS       R0, #0
+  0x3418198C:  4649         MOV        R1, R9
+  0x3418198E:  F000 FAF9    BL         RCC_PLL_Config           ; 0x34181F84
+  0x34181992:  2800         CMP        R0, #0
+  0x34181994:  F040 81C9    BNE.W      46L49                     ; 0x34181D2A
+  0x34181998:  E0B7         B          46L32                     ; 0x34181B0A
+
.L14:
+  0x3418199A:  69A0         LDR        R0, [R4, #24]
+  0x3418199C:  2201         MOVS       R2, #1
+  0x3418199E:  2800         CMP        R0, #0
+  0x341819A0:  F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
+  0x341819A4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
+  0x341819A8:  F000 8098    BEQ.W      46L29                     ; 0x34181ADC
+  0x341819AC:  602A         STR        R2, [R5]
+  0x341819AE:  6802         LDR        R2, [R0]
+
.L15:
+  0x341819B0:  6833         LDR        R3, [R6]
+  0x341819B2:  07DB         LSLS       R3, R3, #31
+  0x341819B4:  D1B9         BNE        46L11                     ; 0x3418192A
+  0x341819B6:  6803         LDR        R3, [R0]
+  0x341819B8:  1A9B         SUBS       R3, R3, R2
+  0x341819BA:  2B01         CMP        R3, #1
+  0x341819BC:  D9F8         BLS        46L15                     ; 0x341819B0
+  0x341819BE:  2003         MOVS       R0, #3
+  0x341819C0:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L16:
+  0x341819C4:  F1B9 0F00    CMP.W      R9, #0
+  0x341819C8:  D103         BNE        46L17                     ; 0x341819D2
+  0x341819CA:  F412 7080    ANDS       R0, R2, #0x0100
+  0x341819CE:  F47F AF81    BNE.W      46L5                      ; 0x341818D4
+
.L17:
+  0x341819D2:  F1BB 0F00    CMP.W      R11, #0
+  0x341819D6:  D103         BNE        46L18                     ; 0x341819E0
+  0x341819D8:  F412 7000    ANDS       R0, R2, #0x0200
+  0x341819DC:  F47F AF7A    BNE.W      46L5                      ; 0x341818D4
+
.L18:
+  0x341819E0:  F1BE 0F00    CMP.W      LR, #0
+  0x341819E4:  D103         BNE        46L19                     ; 0x341819EE
+  0x341819E6:  F412 6080    ANDS       R0, R2, #0x0400
+  0x341819EA:  F47F AF73    BNE.W      46L5                      ; 0x341818D4
+
.L19:
+  0x341819EE:  F1BC 0F00    CMP.W      R12, #0
+  0x341819F2:  D103         BNE        46L20                     ; 0x341819FC
+  0x341819F4:  F412 6000    ANDS       R0, R2, #0x0800
+  0x341819F8:  F47F AF6C    BNE.W      46L5                      ; 0x341818D4
+
.L20:
+  0x341819FC:  68E3         LDR        R3, [R4, #12]
+  0x341819FE:  F648 0000    MOVW       R0, #0x8800
+  0x34181A02:  F242 25A4    MOVW       R5, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181A06:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A0A:  2B00         CMP        R3, #0
+  0x34181A0C:  F04F 0308    MOV.W      R3, #8
+  0x34181A10:  F2C3 4518    MOVT       R5, #0x3418              ; 0x341822A4 = uwTick
+  0x34181A14:  F000 81F1    BEQ.W      46L61                     ; 0x34181DFA
+  0x34181A18:  6003         STR        R3, [R0]
+  0x34181A1A:  682B         LDR        R3, [R5]
+
.L21:
+  0x34181A1C:  6830         LDR        R0, [R6]
+  0x34181A1E:  0700         LSLS       R0, R0, #28
+  0x34181A20:  F53F AF5C    BMI.W      46L6                      ; 0x341818DC
+  0x34181A24:  6828         LDR        R0, [R5]
+  0x34181A26:  1AC0         SUBS       R0, R0, R3
+  0x34181A28:  2801         CMP        R0, #1
+  0x34181A2A:  F04F 0003    MOV.W      R0, #3
+  0x34181A2E:  D9F5         BLS        46L21                     ; 0x34181A1C
+  0x34181A30:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L22:
+  0x34181A34:  F1B9 5F80    CMP.W      R9, #0x10000000
+  0x34181A38:  D103         BNE        46L23                     ; 0x34181A42
+  0x34181A3A:  F412 7080    ANDS       R0, R2, #0x0100
+  0x34181A3E:  F47F AF63    BNE.W      46L8                      ; 0x34181908
+
.L23:
+  0x34181A42:  F1BB 5F80    CMP.W      R11, #0x10000000
+  0x34181A46:  D103         BNE        46L24                     ; 0x34181A50
+  0x34181A48:  F412 7000    ANDS       R0, R2, #0x0200
+  0x34181A4C:  F47F AF5C    BNE.W      46L8                      ; 0x34181908
+
.L24:
+  0x34181A50:  F1BE 5F80    CMP.W      LR, #0x10000000
+  0x34181A54:  D103         BNE        46L25                     ; 0x34181A5E
+  0x34181A56:  F412 6080    ANDS       R0, R2, #0x0400
+  0x34181A5A:  F47F AF55    BNE.W      46L8                      ; 0x34181908
+
.L25:
+  0x34181A5E:  F1BC 5F80    CMP.W      R12, #0x10000000
+  0x34181A62:  D103         BNE        46L26                     ; 0x34181A6C
+  0x34181A64:  F412 6000    ANDS       R0, R2, #0x0800
+  0x34181A68:  F47F AF4E    BNE.W      46L8                      ; 0x34181908
+
.L26:
+  0x34181A6C:  69E2         LDR        R2, [R4, #28]
+  0x34181A6E:  F648 0000    MOVW       R0, #0x8800
+  0x34181A72:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181A76:  2A00         CMP        R2, #0
+  0x34181A78:  F242 22A4    MOVW       R2, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181A7C:  F2C3 4218    MOVT       R2, #0x3418              ; 0x341822A4 = uwTick
+  0x34181A80:  F000 81CA    BEQ.W      46L63                     ; 0x34181E18
+  0x34181A84:  E9D4 7308    LDRD       R7, R3, [R4, #32]
+  0x34181A88:  F8D6 9040    LDR.W      R9, [R6, #64]
+  0x34181A8C:  F429 7900    BIC        R9, R9, #0x0200
+  0x34181A90:  EA47 0709    ORR.W      R7, R7, R9
+  0x34181A94:  6437         STR        R7, [R6, #64]
+  0x34181A96:  2704         MOVS       R7, #4
+  0x34181A98:  6007         STR        R7, [R0]
+  0x34181A9A:  F8D2 9000    LDR.W      R9, [R2]
+
.L27:
+  0x34181A9E:  6830         LDR        R0, [R6]
+  0x34181AA0:  0740         LSLS       R0, R0, #29
+  0x34181AA2:  F53F AF36    BMI.W      46L9                      ; 0x34181912
+  0x34181AA6:  6810         LDR        R0, [R2]
+  0x34181AA8:  EBA0 0009    SUB.W      R0, R0, R9
+  0x34181AAC:  2801         CMP        R0, #1
+  0x34181AAE:  F04F 0003    MOV.W      R0, #3
+  0x34181AB2:  D9F4         BLS        46L27                     ; 0x34181A9E
+  0x34181AB4:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L28:
+  0x34181AB8:  F248 0102    MOVW       R1, #0x8002
+  0x34181ABC:  4288         CMP        R0, R1
+  0x34181ABE:  F000 80D9    BEQ.W      46L41                     ; 0x34181C74
+  0x34181AC2:  F501 3180    ADD.W      R1, R1, #0x010000
+  0x34181AC6:  4288         CMP        R0, R1
+  0x34181AC8:  F040 80AA    BNE.W      46L38                     ; 0x34181C20
+  0x34181ACC:  6BF0         LDR        R0, [R6, #60]
+  0x34181ACE:  F440 4000    ORR        R0, R0, #0x8000
+  0x34181AD2:  63F0         STR        R0, [R6, #60]
+  0x34181AD4:  6BF0         LDR        R0, [R6, #60]
+  0x34181AD6:  F440 3080    ORR        R0, R0, #0x010000
+  0x34181ADA:  E0D2         B          46L42                     ; 0x34181C82
+
.L29:
+  0x34181ADC:  F8C5 2800    STR.W      R2, [R5, #0x0800]
+  0x34181AE0:  6802         LDR        R2, [R0]
+  0x34181AE2:  BF00         NOP
+
.L30:
+  0x34181AE4:  6833         LDR        R3, [R6]
+  0x34181AE6:  07DB         LSLS       R3, R3, #31
+  0x34181AE8:  F43F AF1F    BEQ.W      46L11                     ; 0x3418192A
+  0x34181AEC:  6803         LDR        R3, [R0]
+  0x34181AEE:  1A9B         SUBS       R3, R3, R2
+  0x34181AF0:  2B01         CMP        R3, #1
+  0x34181AF2:  D9F7         BLS        46L30                     ; 0x34181AE4
+  0x34181AF4:  2003         MOVS       R0, #3
+  0x34181AF6:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L31:
+  0x34181AFA:  F8D9 1000    LDR.W      R1, [R9]
+  0x34181AFE:  2902         CMP        R1, #2
+  0x34181B00:  BF08         IT         EQ
+  0x34181B02:  F410 7080    ANDSEQ     R0, R0, #0x0100
+  0x34181B06:  F000 8113    BEQ.W      46L50                     ; 0x34181D30
+
.L32:
+  0x34181B0A:  46A1         MOV        R9, R4
+  0x34181B0C:  F859 0F44    LDR        R0, [R9, #68]!
+  0x34181B10:  2800         CMP        R0, #0
+  0x34181B12:  D03F         BEQ        46L35                     ; 0x34181B94
+  0x34181B14:  2001         MOVS       R0, #1
+  0x34181B16:  4649         MOV        R1, R9
+  0x34181B18:  F000 F9F0    BL         RCC_PLL_IsNewConfig      ; 0x34181EFC
+  0x34181B1C:  2800         CMP        R0, #0
+  0x34181B1E:  6830         LDR        R0, [R6]
+  0x34181B20:  D030         BEQ        46L34                     ; 0x34181B84
+  0x34181B22:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181B26:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181B2A:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181B2E:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x34181B32:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181B36:  BF04         ITT        EQ
+  0x34181B38:  F003 5340    ANDEQ      R3, R3, #0x30000000
+  0x34181B3C:  F1B3 5F80    CMPEQ.W    R3, #0x10000000
+  0x34181B40:  F000 80F3    BEQ.W      46L49                     ; 0x34181D2A
+  0x34181B44:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x34181B48:  D112         BNE        46L33                     ; 0x34181B70
+  0x34181B4A:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181B4E:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34181B52:  F04F 0001    MOV.W      R0, #1
+  0x34181B56:  BF1C         ITT        NE
+  0x34181B58:  F002 5240    ANDNE      R2, R2, #0x30000000
+  0x34181B5C:  F1B2 5F80    CMPNE.W    R2, #0x10000000
+  0x34181B60:  F000 81C9    BEQ.W      46L78                     ; 0x34181EF6
+  0x34181B64:  F001 5140    AND        R1, R1, #0x30000000
+  0x34181B68:  F1B1 5F80    CMP.W      R1, #0x10000000
+  0x34181B6C:  F000 81C3    BEQ.W      46L78                     ; 0x34181EF6
+
.L33:
+  0x34181B70:  2001         MOVS       R0, #1
+  0x34181B72:  4649         MOV        R1, R9
+  0x34181B74:  F000 FA06    BL         RCC_PLL_Config           ; 0x34181F84
+  0x34181B78:  0001         MOVS       R1, R0
+  0x34181B7A:  F04F 0001    MOV.W      R0, #1
+  0x34181B7E:  F040 81BA    BNE.W      46L78                     ; 0x34181EF6
+  0x34181B82:  E007         B          46L35                     ; 0x34181B94
+
.L34:
+  0x34181B84:  F8D9 1000    LDR.W      R1, [R9]
+  0x34181B88:  2902         CMP        R1, #2
+  0x34181B8A:  BF08         IT         EQ
+  0x34181B8C:  F410 7000    ANDSEQ     R0, R0, #0x0200
+  0x34181B90:  F000 80EB    BEQ.W      46L54                     ; 0x34181D6A
+
.L35:
+  0x34181B94:  46A1         MOV        R9, R4
+  0x34181B96:  F859 0F60    LDR        R0, [R9, #96]!
+  0x34181B9A:  2800         CMP        R0, #0
+  0x34181B9C:  F000 808E    BEQ.W      46L47                     ; 0x34181CBC
+  0x34181BA0:  2002         MOVS       R0, #2
+  0x34181BA2:  4649         MOV        R1, R9
+  0x34181BA4:  F000 F9AA    BL         RCC_PLL_IsNewConfig      ; 0x34181EFC
+  0x34181BA8:  2800         CMP        R0, #0
+  0x34181BAA:  6830         LDR        R0, [R6]
+  0x34181BAC:  F000 807F    BEQ.W      46L46                     ; 0x34181CAE
+  0x34181BB0:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181BB4:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181BB8:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181BBC:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x34181BC0:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181BC4:  BF04         ITT        EQ
+  0x34181BC6:  F003 5340    ANDEQ      R3, R3, #0x30000000
+  0x34181BCA:  F1B3 5F00    CMPEQ.W    R3, #0x20000000
+  0x34181BCE:  F000 80AC    BEQ.W      46L49                     ; 0x34181D2A
+  0x34181BD2:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x34181BD6:  D112         BNE        46L36                     ; 0x34181BFE
+  0x34181BD8:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181BDC:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34181BE0:  F04F 0001    MOV.W      R0, #1
+  0x34181BE4:  BF1C         ITT        NE
+  0x34181BE6:  F002 5240    ANDNE      R2, R2, #0x30000000
+  0x34181BEA:  F1B2 5F00    CMPNE.W    R2, #0x20000000
+  0x34181BEE:  F000 8182    BEQ.W      46L78                     ; 0x34181EF6
+  0x34181BF2:  F001 5140    AND        R1, R1, #0x30000000
+  0x34181BF6:  F1B1 5F00    CMP.W      R1, #0x20000000
+  0x34181BFA:  F000 817C    BEQ.W      46L78                     ; 0x34181EF6
+
.L36:
+  0x34181BFE:  2002         MOVS       R0, #2
+  0x34181C00:  4649         MOV        R1, R9
+  0x34181C02:  F000 F9BF    BL         RCC_PLL_Config           ; 0x34181F84
+  0x34181C06:  2800         CMP        R0, #0
+  0x34181C08:  F040 808F    BNE.W      46L49                     ; 0x34181D2A
+  0x34181C0C:  E056         B          46L47                     ; 0x34181CBC
+
.L37:
+  0x34181C0E:  68A0         LDR        R0, [R4, #8]
+  0x34181C10:  F248 0101    MOVW       R1, #0x8001
+  0x34181C14:  4288         CMP        R0, R1
+  0x34181C16:  F73F AF4F    BGT.W      46L28                     ; 0x34181AB8
+  0x34181C1A:  B168         CBZ        R0, .L39                 ; 0x34181C38
+  0x34181C1C:  2802         CMP        R0, #2
+  0x34181C1E:  D032         BEQ        46L43                     ; 0x34181C86
+
.L38:
+  0x34181C20:  2002         MOVS       R0, #2
+  0x34181C22:  F8C5 0800    STR.W      R0, [R5, #0x0800]
+  0x34181C26:  6BF0         LDR        R0, [R6, #60]
+  0x34181C28:  F420 4000    BIC        R0, R0, #0x8000
+  0x34181C2C:  63F0         STR        R0, [R6, #60]
+  0x34181C2E:  6BF0         LDR        R0, [R6, #60]
+  0x34181C30:  F420 3080    BIC        R0, R0, #0x010000
+  0x34181C34:  63F0         STR        R0, [R6, #60]
+  0x34181C36:  E027         B          46L44                     ; 0x34181C88
+
.L39:
+  0x34181C38:  2002         MOVS       R0, #2
+  0x34181C3A:  F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181C3E:  F8C5 0800    STR.W      R0, [R5, #0x0800]
+  0x34181C42:  F241 3388    MOVW       R3, #0x1388
+  0x34181C46:  6BF0         LDR        R0, [R6, #60]
+  0x34181C48:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
+  0x34181C4C:  F420 3080    BIC        R0, R0, #0x010000
+  0x34181C50:  63F0         STR        R0, [R6, #60]
+  0x34181C52:  6BF0         LDR        R0, [R6, #60]
+  0x34181C54:  F420 4000    BIC        R0, R0, #0x8000
+  0x34181C58:  63F0         STR        R0, [R6, #60]
+  0x34181C5A:  680A         LDR        R2, [R1]
+
.L40:
+  0x34181C5C:  6830         LDR        R0, [R6]
+  0x34181C5E:  0780         LSLS       R0, R0, #30
+  0x34181C60:  F57F AE66    BPL.W      46L12                     ; 0x34181930
+  0x34181C64:  6808         LDR        R0, [R1]
+  0x34181C66:  1A80         SUBS       R0, R0, R2
+  0x34181C68:  4298         CMP        R0, R3
+  0x34181C6A:  F04F 0003    MOV.W      R0, #3
+  0x34181C6E:  D9F5         BLS        46L40                     ; 0x34181C5C
+  0x34181C70:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L41:
+  0x34181C74:  6BF0         LDR        R0, [R6, #60]
+  0x34181C76:  F440 4000    ORR        R0, R0, #0x8000
+  0x34181C7A:  63F0         STR        R0, [R6, #60]
+  0x34181C7C:  6BF0         LDR        R0, [R6, #60]
+  0x34181C7E:  F420 3080    BIC        R0, R0, #0x010000
+
.L42:
+  0x34181C82:  63F0         STR        R0, [R6, #60]
+  0x34181C84:  2002         MOVS       R0, #2
+
.L43:
+  0x34181C86:  6028         STR        R0, [R5]
+
.L44:
+  0x34181C88:  F242 20A4    MOVW       R0, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181C8C:  F241 3288    MOVW       R2, #0x1388
+  0x34181C90:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341822A4 = uwTick
+  0x34181C94:  6801         LDR        R1, [R0]
+  0x34181C96:  BF00         NOP
+
.L45:
+  0x34181C98:  6833         LDR        R3, [R6]
+  0x34181C9A:  079B         LSLS       R3, R3, #30
+  0x34181C9C:  F53F AE48    BMI.W      46L12                     ; 0x34181930
+  0x34181CA0:  6803         LDR        R3, [R0]
+  0x34181CA2:  1A5B         SUBS       R3, R3, R1
+  0x34181CA4:  4293         CMP        R3, R2
+  0x34181CA6:  D9F7         BLS        46L45                     ; 0x34181C98
+  0x34181CA8:  2003         MOVS       R0, #3
+  0x34181CAA:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L46:
+  0x34181CAE:  F8D9 1000    LDR.W      R1, [R9]
+  0x34181CB2:  2902         CMP        R1, #2
+  0x34181CB4:  BF08         IT         EQ
+  0x34181CB6:  F410 6080    ANDSEQ     R0, R0, #0x0400
+  0x34181CBA:  D06A         BEQ        46L56                     ; 0x34181D92
+
.L47:
+  0x34181CBC:  F854 0F7C    LDR        R0, [R4, #124]!
+  0x34181CC0:  2800         CMP        R0, #0
+  0x34181CC2:  F000 8118    BEQ.W      46L78                     ; 0x34181EF6
+  0x34181CC6:  2003         MOVS       R0, #3
+  0x34181CC8:  4621         MOV        R1, R4
+  0x34181CCA:  F000 F917    BL         RCC_PLL_IsNewConfig      ; 0x34181EFC
+  0x34181CCE:  2800         CMP        R0, #0
+  0x34181CD0:  6830         LDR        R0, [R6]
+  0x34181CD2:  D041         BEQ        46L52                     ; 0x34181D58
+  0x34181CD4:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181CD8:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181CDC:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181CE0:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x34181CE4:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181CE8:  BF04         ITT        EQ
+  0x34181CEA:  F003 5340    ANDEQ      R3, R3, #0x30000000
+  0x34181CEE:  F1B3 5F40    CMPEQ.W    R3, #0x30000000
+  0x34181CF2:  D01A         BEQ        46L49                     ; 0x34181D2A
+  0x34181CF4:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x34181CF8:  D112         BNE        46L48                     ; 0x34181D20
+  0x34181CFA:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181CFE:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34181D02:  F04F 0001    MOV.W      R0, #1
+  0x34181D06:  BF1C         ITT        NE
+  0x34181D08:  F002 5240    ANDNE      R2, R2, #0x30000000
+  0x34181D0C:  F1B2 5F40    CMPNE.W    R2, #0x30000000
+  0x34181D10:  F000 80F1    BEQ.W      46L78                     ; 0x34181EF6
+  0x34181D14:  F001 5140    AND        R1, R1, #0x30000000
+  0x34181D18:  F1B1 5F40    CMP.W      R1, #0x30000000
+  0x34181D1C:  F000 80EB    BEQ.W      46L78                     ; 0x34181EF6
+
.L48:
+  0x34181D20:  2003         MOVS       R0, #3
+  0x34181D22:  4621         MOV        R1, R4
+  0x34181D24:  F000 F92E    BL         RCC_PLL_Config           ; 0x34181F84
+  0x34181D28:  B1E0         CBZ        R0, .L53                 ; 0x34181D64
+
.L49:
+  0x34181D2A:  2001         MOVS       R0, #1
+  0x34181D2C:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L50:
+  0x34181D30:  F44F 7080    MOV.W      R0, #0x0100
+  0x34181D34:  F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181D38:  6028         STR        R0, [R5]
+  0x34181D3A:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
+  0x34181D3E:  680A         LDR        R2, [R1]
+
.L51:
+  0x34181D40:  6830         LDR        R0, [R6]
+  0x34181D42:  05C0         LSLS       R0, R0, #23
+  0x34181D44:  F53F AEE1    BMI.W      46L32                     ; 0x34181B0A
+  0x34181D48:  6808         LDR        R0, [R1]
+  0x34181D4A:  1A80         SUBS       R0, R0, R2
+  0x34181D4C:  2801         CMP        R0, #1
+  0x34181D4E:  F04F 0001    MOV.W      R0, #1
+  0x34181D52:  D9F5         BLS        46L51                     ; 0x34181D40
+  0x34181D54:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L52:
+  0x34181D58:  6821         LDR        R1, [R4]
+  0x34181D5A:  2902         CMP        R1, #2
+  0x34181D5C:  BF08         IT         EQ
+  0x34181D5E:  F410 6000    ANDSEQ     R0, R0, #0x0800
+  0x34181D62:  D037         BEQ        46L59                     ; 0x34181DD4
+
.L53:
+  0x34181D64:  2000         MOVS       R0, #0
+  0x34181D66:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L54:
+  0x34181D6A:  F44F 7000    MOV.W      R0, #0x0200
+  0x34181D6E:  F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181D72:  6028         STR        R0, [R5]
+  0x34181D74:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
+  0x34181D78:  680A         LDR        R2, [R1]
+
.L55:
+  0x34181D7A:  6830         LDR        R0, [R6]
+  0x34181D7C:  0580         LSLS       R0, R0, #22
+  0x34181D7E:  F53F AF09    BMI.W      46L35                     ; 0x34181B94
+  0x34181D82:  6808         LDR        R0, [R1]
+  0x34181D84:  1A80         SUBS       R0, R0, R2
+  0x34181D86:  2801         CMP        R0, #1
+  0x34181D88:  F04F 0001    MOV.W      R0, #1
+  0x34181D8C:  D9F5         BLS        46L55                     ; 0x34181D7A
+  0x34181D8E:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L56:
+  0x34181D92:  F44F 6080    MOV.W      R0, #0x0400
+  0x34181D96:  F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181D9A:  6028         STR        R0, [R5]
+  0x34181D9C:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
+  0x34181DA0:  680A         LDR        R2, [R1]
+
.L57:
+  0x34181DA2:  6830         LDR        R0, [R6]
+  0x34181DA4:  0540         LSLS       R0, R0, #21
+  0x34181DA6:  F53F AF89    BMI.W      46L47                     ; 0x34181CBC
+  0x34181DAA:  6808         LDR        R0, [R1]
+  0x34181DAC:  1A80         SUBS       R0, R0, R2
+  0x34181DAE:  2801         CMP        R0, #1
+  0x34181DB0:  F04F 0001    MOV.W      R0, #1
+  0x34181DB4:  D9F5         BLS        46L57                     ; 0x34181DA2
+  0x34181DB6:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L58:
+  0x34181DBA:  F248 0310    MOVW       R3, #0x8010
+  0x34181DBE:  4298         CMP        R0, R3
+  0x34181DC0:  F000 8082    BEQ.W      46L73                     ; 0x34181EC8
+  0x34181DC4:  F503 3380    ADD.W      R3, R3, #0x010000
+  0x34181DC8:  4298         CMP        R0, R3
+  0x34181DCA:  D15D         BNE        46L70                     ; 0x34181E88
+  0x34181DCC:  6D30         LDR        R0, [R6, #80]
+  0x34181DCE:  F440 30C0    ORR        R0, R0, #0x018000
+  0x34181DD2:  E080         B          46L74                     ; 0x34181ED6
+
.L59:
+  0x34181DD4:  F44F 6000    MOV.W      R0, #0x0800
+  0x34181DD8:  F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181DDC:  6028         STR        R0, [R5]
+  0x34181DDE:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
+  0x34181DE2:  680A         LDR        R2, [R1]
+
.L60:
+  0x34181DE4:  6830         LDR        R0, [R6]
+  0x34181DE6:  0500         LSLS       R0, R0, #20
+  0x34181DE8:  D4BC         BMI        46L53                     ; 0x34181D64
+  0x34181DEA:  6808         LDR        R0, [R1]
+  0x34181DEC:  1A80         SUBS       R0, R0, R2
+  0x34181DEE:  2801         CMP        R0, #1
+  0x34181DF0:  F04F 0001    MOV.W      R0, #1
+  0x34181DF4:  D9F6         BLS        46L60                     ; 0x34181DE4
+  0x34181DF6:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L61:
+  0x34181DFA:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181DFE:  682B         LDR        R3, [R5]
+
.L62:
+  0x34181E00:  6830         LDR        R0, [R6]
+  0x34181E02:  0700         LSLS       R0, R0, #28
+  0x34181E04:  F57F AD77    BPL.W      46L7                      ; 0x341818F6
+  0x34181E08:  6828         LDR        R0, [R5]
+  0x34181E0A:  1AC0         SUBS       R0, R0, R3
+  0x34181E0C:  2801         CMP        R0, #1
+  0x34181E0E:  F04F 0003    MOV.W      R0, #3
+  0x34181E12:  D9F5         BLS        46L62                     ; 0x34181E00
+  0x34181E14:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L63:
+  0x34181E18:  2304         MOVS       R3, #4
+  0x34181E1A:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181E1E:  6813         LDR        R3, [R2]
+
.L64:
+  0x34181E20:  6830         LDR        R0, [R6]
+  0x34181E22:  0740         LSLS       R0, R0, #29
+  0x34181E24:  F57F AD7B    BPL.W      46L10                     ; 0x3418191E
+  0x34181E28:  6810         LDR        R0, [R2]
+  0x34181E2A:  1AC0         SUBS       R0, R0, R3
+  0x34181E2C:  2801         CMP        R0, #1
+  0x34181E2E:  F04F 0003    MOV.W      R0, #3
+  0x34181E32:  D9F5         BLS        46L64                     ; 0x34181E20
+  0x34181E34:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L65:
+  0x34181E38:  F1B9 5F00    CMP.W      R9, #0x20000000
+  0x34181E3C:  D103         BNE        46L66                     ; 0x34181E46
+  0x34181E3E:  F412 7080    ANDS       R0, R2, #0x0100
+  0x34181E42:  F47F AD28    BNE.W      46L1                      ; 0x34181896
+
.L66:
+  0x34181E46:  F1BB 5F00    CMP.W      R11, #0x20000000
+  0x34181E4A:  D103         BNE        46L67                     ; 0x34181E54
+  0x34181E4C:  F412 7000    ANDS       R0, R2, #0x0200
+  0x34181E50:  F47F AD21    BNE.W      46L1                      ; 0x34181896
+
.L67:
+  0x34181E54:  F1BE 5F00    CMP.W      LR, #0x20000000
+  0x34181E58:  D103         BNE        46L68                     ; 0x34181E62
+  0x34181E5A:  F412 6080    ANDS       R0, R2, #0x0400
+  0x34181E5E:  F47F AD1A    BNE.W      46L1                      ; 0x34181896
+
.L68:
+  0x34181E62:  F1BC 5F00    CMP.W      R12, #0x20000000
+  0x34181E66:  D103         BNE        46L69                     ; 0x34181E70
+  0x34181E68:  F412 6000    ANDS       R0, R2, #0x0800
+  0x34181E6C:  F47F AD13    BNE.W      46L1                      ; 0x34181896
+
.L69:
+  0x34181E70:  6860         LDR        R0, [R4, #4]
+  0x34181E72:  F248 030F    MOVW       R3, #0x800F
+  0x34181E76:  F242 25A4    MOVW       R5, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181E7A:  4298         CMP        R0, R3
+  0x34181E7C:  F2C3 4518    MOVT       R5, #0x3418              ; 0x341822A4 = uwTick
+  0x34181E80:  DC9B         BGT        46L58                     ; 0x34181DBA
+  0x34181E82:  B158         CBZ        R0, .L71                 ; 0x34181E9C
+  0x34181E84:  2810         CMP        R0, #16
+  0x34181E86:  D027         BEQ        46L75                     ; 0x34181ED8
+
.L70:
+  0x34181E88:  F206 70FC    ADDW       R0, R6, #0x07FC
+  0x34181E8C:  2310         MOVS       R3, #16
+  0x34181E8E:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181E92:  6D30         LDR        R0, [R6, #80]
+  0x34181E94:  F420 30C0    BIC        R0, R0, #0x018000
+  0x34181E98:  6530         STR        R0, [R6, #80]
+  0x34181E9A:  E021         B          46L76                     ; 0x34181EE0
+
.L71:
+  0x34181E9C:  F206 70FC    ADDW       R0, R6, #0x07FC
+  0x34181EA0:  2310         MOVS       R3, #16
+  0x34181EA2:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181EA6:  6D30         LDR        R0, [R6, #80]
+  0x34181EA8:  F420 30C0    BIC        R0, R0, #0x018000
+  0x34181EAC:  6530         STR        R0, [R6, #80]
+  0x34181EAE:  682B         LDR        R3, [R5]
+
.L72:
+  0x34181EB0:  6830         LDR        R0, [R6]
+  0x34181EB2:  06C0         LSLS       R0, R0, #27
+  0x34181EB4:  F57F AD06    BPL.W      46L4                      ; 0x341818C4
+  0x34181EB8:  6828         LDR        R0, [R5]
+  0x34181EBA:  1AC0         SUBS       R0, R0, R3
+  0x34181EBC:  2864         CMP        R0, #100
+  0x34181EBE:  F04F 0003    MOV.W      R0, #3
+  0x34181EC2:  D9F5         BLS        46L72                     ; 0x34181EB0
+  0x34181EC4:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L73:
+  0x34181EC8:  6D30         LDR        R0, [R6, #80]
+  0x34181ECA:  F440 4000    ORR        R0, R0, #0x8000
+  0x34181ECE:  6530         STR        R0, [R6, #80]
+  0x34181ED0:  6D30         LDR        R0, [R6, #80]
+  0x34181ED2:  F420 3080    BIC        R0, R0, #0x010000
+
.L74:
+  0x34181ED6:  6530         STR        R0, [R6, #80]
+
.L75:
+  0x34181ED8:  F206 70FC    ADDW       R0, R6, #0x07FC
+  0x34181EDC:  2310         MOVS       R3, #16
+  0x34181EDE:  6003         STR        R3, [R0]
+
.L76:
+  0x34181EE0:  682B         LDR        R3, [R5]
+
.L77:
+  0x34181EE2:  6830         LDR        R0, [R6]
+  0x34181EE4:  06C0         LSLS       R0, R0, #27
+  0x34181EE6:  F53F ACED    BMI.W      46L4                      ; 0x341818C4
+  0x34181EEA:  6828         LDR        R0, [R5]
+  0x34181EEC:  1AC0         SUBS       R0, R0, R3
+  0x34181EEE:  2864         CMP        R0, #100
+  0x34181EF0:  F04F 0003    MOV.W      R0, #3
+  0x34181EF4:  D9F5         BLS        46L77                     ; 0x34181EE2
+
.L78:
+  0x34181EF6:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
+

Section .init.RIFSC_TAMPER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RIFSC_TAMPER_IRQHandler:
+  0x34181EFA:  E7FE         B          RIFSC_TAMPER_IRQHandler  ; 0x34181EFA
+
+

Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=134, align=4

+ +
+
RCC_PLL_IsNewConfig:
+  0x34181EFC:  B530         PUSH       123R4-R5, LR}
+  0x34181EFE:  F248 0E04    MOVW       LR, #0x8004
+  0x34181F02:  0102         LSLS       R2, R0, #4
+  0x34181F04:  F2C5 6E02    MOVT       LR, #0x5602
+  0x34181F08:  F10E 0C7C    ADD.W      R12, LR, #124
+  0x34181F0C:  F85C 2002    LDR.W      R2, [R12, R2]
+  0x34181F10:  E9D1 3401    LDRD       R3, R4, [R1, #4]
+  0x34181F14:  F022 420C    BIC        R2, R2, #0x8C000000
+  0x34181F18:  F022 02FF    BIC        R2, R2, #255
+  0x34181F1C:  EA43 5304    ORR.W      R3, R3, R4, LSL #20
+  0x34181F20:  690C         LDR        R4, [R1, #16]
+  0x34181F22:  EA43 2304    ORR.W      R3, R3, R4, LSL #8
+  0x34181F26:  429A         CMP        R2, R3
+  0x34181F28:  D11E         BNE        46L1                      ; 0x34181F68
+  0x34181F2A:  0082         LSLS       R2, R0, #2
+  0x34181F2C:  EB0E 0382    ADD.W      R3, LR, R2, LSL #2
+  0x34181F30:  F8D3 3080    LDR.W      R3, [R3, #128]
+  0x34181F34:  68CC         LDR        R4, [R1, #12]
+  0x34181F36:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x34181F3A:  42A3         CMP        R3, R4
+  0x34181F3C:  D114         BNE        46L1                      ; 0x34181F68
+  0x34181F3E:  F10E 0384    ADD.W      R3, LR, #132
+  0x34181F42:  F853 3022    LDR.W      R3, [R3, R2, LSL #2]
+  0x34181F46:  E9D1 4505    LDRD       R4, R5, [R1, #20]
+  0x34181F4A:  F003 537C    AND        R3, R3, #0x3F000000
+  0x34181F4E:  062D         LSLS       R5, R5, #24
+  0x34181F50:  EA45 64C4    ORR.W      R4, R5, R4, LSL #27
+  0x34181F54:  42A3         CMP        R3, R4
+  0x34181F56:  D107         BNE        46L1                      ; 0x34181F68
+  0x34181F58:  F8DE 3000    LDR.W      R3, [LR]
+  0x34181F5C:  FA23 F000    LSR.W      R0, R3, R0
+  0x34181F60:  05C0         LSLS       R0, R0, #23
+  0x34181F62:  D503         BPL        46L2                      ; 0x34181F6C
+  0x34181F64:  2002         MOVS       R0, #2
+  0x34181F66:  E007         B          46L3                      ; 0x34181F78
+
.L1:
+  0x34181F68:  2001         MOVS       R0, #1
+  0x34181F6A:  BD30         POP        123R4-R5, PC}
+
.L2:
+  0x34181F6C:  F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
+  0x34181F70:  0100         LSLS       R0, R0, #4
+  0x34181F72:  BF4C         ITE        MI
+  0x34181F74:  2003         MOVMI      R0, #3
+  0x34181F76:  2001         MOVPL      R0, #1
+
.L3:
+  0x34181F78:  6809         LDR        R1, [R1]
+  0x34181F7A:  4288         CMP        R0, R1
+  0x34181F7C:  EA5F 900F    CSET       R0, NE
+  0x34181F80:  BD30         POP        123R4-R5, PC}
+
+

Section .init.IAC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
IAC_IRQHandler:
+  0x34181F82:  E7FE         B          IAC_IRQHandler           ; 0x34181F82
+
+

Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=446, align=4

+ +
+
RCC_PLL_Config:
+  0x34181F84:  E92D 41F0    PUSH.W     123R4-R8, LR}
+  0x34181F88:  F248 0304    MOVW       R3, #0x8004
+  0x34181F8C:  680C         LDR        R4, [R1]
+  0x34181F8E:  F2C5 6302    MOVT       R3, #0x5602
+  0x34181F92:  0082         LSLS       R2, R0, #2
+  0x34181F94:  F103 0C7C    ADD.W      R12, R3, #124
+  0x34181F98:  F103 0E84    ADD.W      LR, R3, #132
+  0x34181F9C:  2C01         CMP        R4, #1
+  0x34181F9E:  D046         BEQ        46L5                      ; 0x3418202E
+  0x34181FA0:  2C03         CMP        R4, #3
+  0x34181FA2:  D01B         BEQ        46L2                      ; 0x34181FDC
+  0x34181FA4:  2C02         CMP        R4, #2
+  0x34181FA6:  F040 80C6    BNE.W      46L12                     ; 0x34182136
+  0x34181FAA:  F44F 7480    MOV.W      R4, #0x0100
+  0x34181FAE:  F603 78FC    ADDW       R8, R3, #0x0FFC
+  0x34181FB2:  FA04 F000    LSL.W      R0, R4, R0
+  0x34181FB6:  F242 24A4    MOVW       R4, #0x22A4              ; 0x341822A4 = uwTick
+  0x34181FBA:  F8C8 0000    STR.W      R0, [R8]
+  0x34181FBE:  F103 0680    ADD.W      R6, R3, #128
+  0x34181FC2:  F2C3 4418    MOVT       R4, #0x3418              ; 0x341822A4 = uwTick
+  0x34181FC6:  6827         LDR        R7, [R4]
+
.L1:
+  0x34181FC8:  681D         LDR        R5, [R3]
+  0x34181FCA:  4205         TST        R5, R0
+  0x34181FCC:  D051         BEQ        46L8                      ; 0x34182072
+  0x34181FCE:  6825         LDR        R5, [R4]
+  0x34181FD0:  1BED         SUBS       R5, R5, R7
+  0x34181FD2:  2D01         CMP        R5, #1
+  0x34181FD4:  D9F8         BLS        46L1                      ; 0x34181FC8
+  0x34181FD6:  2003         MOVS       R0, #3
+  0x34181FD8:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L2:
+  0x34181FDC:  6849         LDR        R1, [R1, #4]
+  0x34181FDE:  EA4F 7731    ROR        R7, R1, #28
+  0x34181FE2:  2F02         CMP        R7, #2
+  0x34181FE4:  D80B         BHI        46L3                      ; 0x34181FFE
+  0x34181FE6:  F241 46A0    MOVW       R6, #0x14A0              ; 0x341814A0 = .rodata..Lswitch.table.RCC_PLL_Config
+  0x34181FEA:  F2C3 4618    MOVT       R6, #0x3418              ; 0x341814A0 = .rodata..Lswitch.table.RCC_PLL_Config
+  0x34181FEE:  F856 7027    LDR.W      R7, [R6, R7, LSL #2]
+  0x34181FF2:  681E         LDR        R6, [R3]
+  0x34181FF4:  FA26 F707    LSR.W      R7, R6, R7
+  0x34181FF8:  07FF         LSLS       R7, R7, #31
+  0x34181FFA:  F000 809F    BEQ.W      46L13                     ; 0x3418213C
+
.L3:
+  0x34181FFE:  F44F 7780    MOV.W      R7, #0x0100
+  0x34182002:  F242 26A4    MOVW       R6, #0x22A4              ; 0x341822A4 = uwTick
+  0x34182006:  FA07 F000    LSL.W      R0, R7, R0
+  0x3418200A:  F603 77FC    ADDW       R7, R3, #0x0FFC
+  0x3418200E:  6038         STR        R0, [R7]
+  0x34182010:  F2C3 4618    MOVT       R6, #0x3418              ; 0x341822A4 = uwTick
+  0x34182014:  6837         LDR        R7, [R6]
+  0x34182016:  BF00         NOP
+
.L4:
+  0x34182018:  681D         LDR        R5, [R3]
+  0x3418201A:  4205         TST        R5, R0
+  0x3418201C:  F000 8082    BEQ.W      46L10                     ; 0x34182124
+  0x34182020:  6835         LDR        R5, [R6]
+  0x34182022:  1BED         SUBS       R5, R5, R7
+  0x34182024:  2D01         CMP        R5, #1
+  0x34182026:  D9F7         BLS        46L4                      ; 0x34182018
+  0x34182028:  2003         MOVS       R0, #3
+  0x3418202A:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L5:
+  0x3418202E:  F85E 1022    LDR.W      R1, [LR, R2, LSL #2]
+  0x34182032:  F021 4180    BIC        R1, R1, #0x40000000
+  0x34182036:  F84E 1022    STR.W      R1, [LR, R2, LSL #2]
+  0x3418203A:  F44F 7180    MOV.W      R1, #0x0100
+  0x3418203E:  FA01 F000    LSL.W      R0, R1, R0
+  0x34182042:  F603 71FC    ADDW       R1, R3, #0x0FFC
+  0x34182046:  6008         STR        R0, [R1]
+  0x34182048:  F242 21A4    MOVW       R1, #0x22A4              ; 0x341822A4 = uwTick
+  0x3418204C:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341822A4 = uwTick
+  0x34182050:  680F         LDR        R7, [R1]
+  0x34182052:  BF00         NOP
+
.L6:
+  0x34182054:  681E         LDR        R6, [R3]
+  0x34182056:  4206         TST        R6, R0
+  0x34182058:  D006         BEQ        46L7                      ; 0x34182068
+  0x3418205A:  680E         LDR        R6, [R1]
+  0x3418205C:  1BF6         SUBS       R6, R6, R7
+  0x3418205E:  2E01         CMP        R6, #1
+  0x34182060:  D9F8         BLS        46L6                      ; 0x34182054
+  0x34182062:  2003         MOVS       R0, #3
+  0x34182064:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L7:
+  0x34182068:  F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
+  0x3418206C:  F020 6000    BIC        R0, R0, #0x08000000
+  0x34182070:  E05F         B          46L11                     ; 0x34182132
+
.L8:
+  0x34182072:  F85E 5022    LDR.W      R5, [LR, R2, LSL #2]
+  0x34182076:  27FF         MOVS       R7, #255
+  0x34182078:  F6C8 4700    MOVT       R7, #0x8C00
+  0x3418207C:  F045 0504    ORR        R5, R5, #4
+  0x34182080:  F84E 5022    STR.W      R5, [LR, R2, LSL #2]
+  0x34182084:  F85C 5022    LDR.W      R5, [R12, R2, LSL #2]
+  0x34182088:  F025 6500    BIC        R5, R5, #0x08000000
+  0x3418208C:  F84C 5022    STR.W      R5, [R12, R2, LSL #2]
+  0x34182090:  F85C 5022    LDR.W      R5, [R12, R2, LSL #2]
+  0x34182094:  403D         ANDS       R5, R7
+  0x34182096:  684F         LDR        R7, [R1, #4]
+  0x34182098:  433D         ORRS       R5, R7
+  0x3418209A:  688F         LDR        R7, [R1, #8]
+  0x3418209C:  EA45 5507    ORR.W      R5, R5, R7, LSL #20
+  0x341820A0:  690F         LDR        R7, [R1, #16]
+  0x341820A2:  EA45 2507    ORR.W      R5, R5, R7, LSL #8
+  0x341820A6:  F84C 5022    STR.W      R5, [R12, R2, LSL #2]
+  0x341820AA:  F85E 7022    LDR.W      R7, [LR, R2, LSL #2]
+  0x341820AE:  694D         LDR        R5, [R1, #20]
+  0x341820B0:  F027 577C    BIC        R7, R7, #0x3F000000
+  0x341820B4:  EA47 67C5    ORR.W      R7, R7, R5, LSL #27
+  0x341820B8:  698D         LDR        R5, [R1, #24]
+  0x341820BA:  EA47 6705    ORR.W      R7, R7, R5, LSL #24
+  0x341820BE:  F84E 7022    STR.W      R7, [LR, R2, LSL #2]
+  0x341820C2:  F856 7022    LDR.W      R7, [R6, R2, LSL #2]
+  0x341820C6:  68CD         LDR        R5, [R1, #12]
+  0x341820C8:  F007 477F    AND        R7, R7, #0xFF000000
+  0x341820CC:  432F         ORRS       R7, R5
+  0x341820CE:  F846 7022    STR.W      R7, [R6, R2, LSL #2]
+  0x341820D2:  F85E 7022    LDR.W      R7, [LR, R2, LSL #2]
+  0x341820D6:  F027 0708    BIC        R7, R7, #8
+  0x341820DA:  F84E 7022    STR.W      R7, [LR, R2, LSL #2]
+  0x341820DE:  68C9         LDR        R1, [R1, #12]
+  0x341820E0:  2900         CMP        R1, #0
+  0x341820E2:  BF1E         ITTT       NE
+  0x341820E4:  F85E 1022    LDRNE.W    R1, [LR, R2, LSL #2]
+  0x341820E8:  F041 010A    ORRNE      R1, R1, #10
+  0x341820EC:  F84E 1022    STRNE.W    R1, [LR, R2, LSL #2]
+  0x341820F0:  F85E 1022    LDR.W      R1, [LR, R2, LSL #2]
+  0x341820F4:  F041 4180    ORR        R1, R1, #0x40000000
+  0x341820F8:  F041 0101    ORR        R1, R1, #1
+  0x341820FC:  F84E 1022    STR.W      R1, [LR, R2, LSL #2]
+  0x34182100:  F64F 0100    MOVW       R1, #0xF800
+  0x34182104:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x34182108:  F848 0001    STR.W      R0, [R8, R1]
+  0x3418210C:  6821         LDR        R1, [R4]
+  0x3418210E:  BF00         NOP
+
.L9:
+  0x34182110:  681A         LDR        R2, [R3]
+  0x34182112:  4202         TST        R2, R0
+  0x34182114:  D10F         BNE        46L12                     ; 0x34182136
+  0x34182116:  6822         LDR        R2, [R4]
+  0x34182118:  1A52         SUBS       R2, R2, R1
+  0x3418211A:  2A01         CMP        R2, #1
+  0x3418211C:  D9F8         BLS        46L9                      ; 0x34182110
+  0x3418211E:  2003         MOVS       R0, #3
+  0x34182120:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L10:
+  0x34182124:  F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
+  0x34182128:  F020 40F0    BIC        R0, R0, #0x78000000
+  0x3418212C:  4308         ORRS       R0, R1
+  0x3418212E:  F040 6000    ORR        R0, R0, #0x08000000
+
.L11:
+  0x34182132:  F84C 0022    STR.W      R0, [R12, R2, LSL #2]
+
.L12:
+  0x34182136:  2000         MOVS       R0, #0
+  0x34182138:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L13:
+  0x3418213C:  2001         MOVS       R0, #1
+  0x3418213E:  E8BD 81F0    POP.W      123R4-R8, PC}
+
+

Section .init.RCC_S_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RCC_S_IRQHandler:
+  0x34182142:  E7FE         B          RCC_S_IRQHandler         ; 0x34182142
+
+

Section .init.RTC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RTC_IRQHandler:
+  0x34182144:  E7FE         B          RTC_IRQHandler           ; 0x34182144
+
+

Section .init.IWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
IWDG_IRQHandler:
+  0x34182146:  E7FE         B          IWDG_IRQHandler          ; 0x34182146
+
+

Section .init.WWDG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
WWDG_IRQHandler:
+  0x34182148:  E7FE         B          WWDG_IRQHandler          ; 0x34182148
+
+

Section .init.EXTI0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI0_IRQHandler:
+  0x3418214A:  E7FE         B          EXTI0_IRQHandler         ; 0x3418214A
+
+

Section .init.EXTI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI1_IRQHandler:
+  0x3418214C:  E7FE         B          EXTI1_IRQHandler         ; 0x3418214C
+
+

Section .init.EXTI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI2_IRQHandler:
+  0x3418214E:  E7FE         B          EXTI2_IRQHandler         ; 0x3418214E
+
+

Section .init.EXTI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI3_IRQHandler:
+  0x34182150:  E7FE         B          EXTI3_IRQHandler         ; 0x34182150
+
+

Section .init.EXTI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI4_IRQHandler:
+  0x34182152:  E7FE         B          EXTI4_IRQHandler         ; 0x34182152
+
+

Section .init.EXTI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI5_IRQHandler:
+  0x34182154:  E7FE         B          EXTI5_IRQHandler         ; 0x34182154
+
+

Section .init.EXTI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI6_IRQHandler:
+  0x34182156:  E7FE         B          EXTI6_IRQHandler         ; 0x34182156
+
+

Section .init.EXTI7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI7_IRQHandler:
+  0x34182158:  E7FE         B          EXTI7_IRQHandler         ; 0x34182158
+
+

Section .init.EXTI8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI8_IRQHandler:
+  0x3418215A:  E7FE         B          EXTI8_IRQHandler         ; 0x3418215A
+
+

Section .init.EXTI9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI9_IRQHandler:
+  0x3418215C:  E7FE         B          EXTI9_IRQHandler         ; 0x3418215C
+
+

Section .init.EXTI10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI10_IRQHandler:
+  0x3418215E:  E7FE         B          EXTI10_IRQHandler        ; 0x3418215E
+
+

Section .init.EXTI11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI11_IRQHandler:
+  0x34182160:  E7FE         B          EXTI11_IRQHandler        ; 0x34182160
+
+

Section .init.EXTI12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI12_IRQHandler:
+  0x34182162:  E7FE         B          EXTI12_IRQHandler        ; 0x34182162
+
+

Section .init.EXTI13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI13_IRQHandler:
+  0x34182164:  E7FE         B          EXTI13_IRQHandler        ; 0x34182164
+
+

Section .init.EXTI14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI14_IRQHandler:
+  0x34182166:  E7FE         B          EXTI14_IRQHandler        ; 0x34182166
+
+

Section .init.EXTI15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
EXTI15_IRQHandler:
+  0x34182168:  E7FE         B          EXTI15_IRQHandler        ; 0x34182168
+
+

Section .init.SAES_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAES_IRQHandler:
+  0x3418216A:  E7FE         B          SAES_IRQHandler          ; 0x3418216A
+
+

Section .init.CRYP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CRYP_IRQHandler:
+  0x3418216C:  E7FE         B          CRYP_IRQHandler          ; 0x3418216C
+
+

Section .init.PKA_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
PKA_IRQHandler:
+  0x3418216E:  E7FE         B          PKA_IRQHandler           ; 0x3418216E
+
+

Section .init.HASH_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HASH_IRQHandler:
+  0x34182170:  E7FE         B          HASH_IRQHandler          ; 0x34182170
+
+

Section .init.RNG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
RNG_IRQHandler:
+  0x34182172:  E7FE         B          RNG_IRQHandler           ; 0x34182172
+
+

Section .init.MCE1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE1_IRQHandler:
+  0x34182174:  E7FE         B          MCE1_IRQHandler          ; 0x34182174
+
+

Section .init.MCE2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE2_IRQHandler:
+  0x34182176:  E7FE         B          MCE2_IRQHandler          ; 0x34182176
+
+

Section .init.MCE3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE3_IRQHandler:
+  0x34182178:  E7FE         B          MCE3_IRQHandler          ; 0x34182178
+
+

Section .init.MCE4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MCE4_IRQHandler:
+  0x3418217A:  E7FE         B          MCE4_IRQHandler          ; 0x3418217A
+
+

Section .init.ADC1_2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ADC1_2_IRQHandler:
+  0x3418217C:  E7FE         B          ADC1_2_IRQHandler        ; 0x3418217C
+
+

Section .init.CSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CSI_IRQHandler:
+  0x3418217E:  E7FE         B          CSI_IRQHandler           ; 0x3418217E
+
+

Section .init.DCMIPP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DCMIPP_IRQHandler:
+  0x34182180:  E7FE         B          DCMIPP_IRQHandler        ; 0x34182180
+
+

Section .init.PAHB_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
PAHB_ERR_IRQHandler:
+  0x34182182:  E7FE         B          PAHB_ERR_IRQHandler      ; 0x34182182
+
+

Section .init.NPU0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU0_IRQHandler:
+  0x34182184:  E7FE         B          NPU0_IRQHandler          ; 0x34182184
+
+

Section .init.NPU1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU1_IRQHandler:
+  0x34182186:  E7FE         B          NPU1_IRQHandler          ; 0x34182186
+
+

Section .init.NPU2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU2_IRQHandler:
+  0x34182188:  E7FE         B          NPU2_IRQHandler          ; 0x34182188
+
+

Section .init.NPU3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
NPU3_IRQHandler:
+  0x3418218A:  E7FE         B          NPU3_IRQHandler          ; 0x3418218A
+
+

Section .init.CACHEAXI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CACHEAXI_IRQHandler:
+  0x3418218C:  E7FE         B          CACHEAXI_IRQHandler      ; 0x3418218C
+
+

Section .init.LTDC_LO_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_LO_IRQHandler:
+  0x3418218E:  E7FE         B          LTDC_LO_IRQHandler       ; 0x3418218E
+
+

Section .init.LTDC_LO_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_LO_ERR_IRQHandler:
+  0x34182190:  E7FE         B          LTDC_LO_ERR_IRQHandler   ; 0x34182190
+
+

Section .init.DMA2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DMA2D_IRQHandler:
+  0x34182192:  E7FE         B          DMA2D_IRQHandler         ; 0x34182192
+
+

Section .init.JPEG_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
JPEG_IRQHandler:
+  0x34182194:  E7FE         B          JPEG_IRQHandler          ; 0x34182194
+
+

Section .init.VENC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
VENC_IRQHandler:
+  0x34182196:  E7FE         B          VENC_IRQHandler          ; 0x34182196
+
+

Section .init.GFXMMU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GFXMMU_IRQHandler:
+  0x34182198:  E7FE         B          GFXMMU_IRQHandler        ; 0x34182198
+
+

Section .init.GFXTIM_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GFXTIM_IRQHandler:
+  0x3418219A:  E7FE         B          GFXTIM_IRQHandler        ; 0x3418219A
+
+

Section .init.GPU2D_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPU2D_IRQHandler:
+  0x3418219C:  E7FE         B          GPU2D_IRQHandler         ; 0x3418219C
+
+

Section .init.GPU2D_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPU2D_ER_IRQHandler:
+  0x3418219E:  E7FE         B          GPU2D_ER_IRQHandler      ; 0x3418219E
+
+

Section .init.ICACHE_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ICACHE_IRQHandler:
+  0x341821A0:  E7FE         B          ICACHE_IRQHandler        ; 0x341821A0
+
+

Section .init.HPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel0_IRQHandler:
+  0x341821A2:  E7FE         B          HPDMA1_Channel0_IRQHandler ; 0x341821A2
+
+

Section .init.HPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel1_IRQHandler:
+  0x341821A4:  E7FE         B          HPDMA1_Channel1_IRQHandler ; 0x341821A4
+
+

Section .init.HPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel2_IRQHandler:
+  0x341821A6:  E7FE         B          HPDMA1_Channel2_IRQHandler ; 0x341821A6
+
+

Section .init.HPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel3_IRQHandler:
+  0x341821A8:  E7FE         B          HPDMA1_Channel3_IRQHandler ; 0x341821A8
+
+

Section .init.HPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel4_IRQHandler:
+  0x341821AA:  E7FE         B          HPDMA1_Channel4_IRQHandler ; 0x341821AA
+
+

Section .init.HPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel5_IRQHandler:
+  0x341821AC:  E7FE         B          HPDMA1_Channel5_IRQHandler ; 0x341821AC
+
+

Section .init.HPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel6_IRQHandler:
+  0x341821AE:  E7FE         B          HPDMA1_Channel6_IRQHandler ; 0x341821AE
+
+

Section .init.HPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel7_IRQHandler:
+  0x341821B0:  E7FE         B          HPDMA1_Channel7_IRQHandler ; 0x341821B0
+
+

Section .init.HPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel8_IRQHandler:
+  0x341821B2:  E7FE         B          HPDMA1_Channel8_IRQHandler ; 0x341821B2
+
+

Section .init.HPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel9_IRQHandler:
+  0x341821B4:  E7FE         B          HPDMA1_Channel9_IRQHandler ; 0x341821B4
+
+

Section .init.HPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel10_IRQHandler:
+  0x341821B6:  E7FE         B          HPDMA1_Channel10_IRQHandler ; 0x341821B6
+
+

Section .init.HPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel11_IRQHandler:
+  0x341821B8:  E7FE         B          HPDMA1_Channel11_IRQHandler ; 0x341821B8
+
+

Section .init.HPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel12_IRQHandler:
+  0x341821BA:  E7FE         B          HPDMA1_Channel12_IRQHandler ; 0x341821BA
+
+

Section .init.HPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel13_IRQHandler:
+  0x341821BC:  E7FE         B          HPDMA1_Channel13_IRQHandler ; 0x341821BC
+
+

Section .init.HPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel14_IRQHandler:
+  0x341821BE:  E7FE         B          HPDMA1_Channel14_IRQHandler ; 0x341821BE
+
+

Section .init.HPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
HPDMA1_Channel15_IRQHandler:
+  0x341821C0:  E7FE         B          HPDMA1_Channel15_IRQHandler ; 0x341821C0
+
+

Section .init.GPDMA1_Channel0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel0_IRQHandler:
+  0x341821C2:  E7FE         B          GPDMA1_Channel0_IRQHandler ; 0x341821C2
+
+

Section .init.GPDMA1_Channel1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel1_IRQHandler:
+  0x341821C4:  E7FE         B          GPDMA1_Channel1_IRQHandler ; 0x341821C4
+
+

Section .init.GPDMA1_Channel2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel2_IRQHandler:
+  0x341821C6:  E7FE         B          GPDMA1_Channel2_IRQHandler ; 0x341821C6
+
+

Section .init.GPDMA1_Channel3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel3_IRQHandler:
+  0x341821C8:  E7FE         B          GPDMA1_Channel3_IRQHandler ; 0x341821C8
+
+

Section .init.GPDMA1_Channel4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel4_IRQHandler:
+  0x341821CA:  E7FE         B          GPDMA1_Channel4_IRQHandler ; 0x341821CA
+
+

Section .init.GPDMA1_Channel5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel5_IRQHandler:
+  0x341821CC:  E7FE         B          GPDMA1_Channel5_IRQHandler ; 0x341821CC
+
+

Section .init.GPDMA1_Channel6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel6_IRQHandler:
+  0x341821CE:  E7FE         B          GPDMA1_Channel6_IRQHandler ; 0x341821CE
+
+

Section .init.GPDMA1_Channel7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel7_IRQHandler:
+  0x341821D0:  E7FE         B          GPDMA1_Channel7_IRQHandler ; 0x341821D0
+
+

Section .init.GPDMA1_Channel8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel8_IRQHandler:
+  0x341821D2:  E7FE         B          GPDMA1_Channel8_IRQHandler ; 0x341821D2
+
+

Section .init.GPDMA1_Channel9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel9_IRQHandler:
+  0x341821D4:  E7FE         B          GPDMA1_Channel9_IRQHandler ; 0x341821D4
+
+

Section .init.GPDMA1_Channel10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel10_IRQHandler:
+  0x341821D6:  E7FE         B          GPDMA1_Channel10_IRQHandler ; 0x341821D6
+
+

Section .init.GPDMA1_Channel11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel11_IRQHandler:
+  0x341821D8:  E7FE         B          GPDMA1_Channel11_IRQHandler ; 0x341821D8
+
+

Section .init.GPDMA1_Channel12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel12_IRQHandler:
+  0x341821DA:  E7FE         B          GPDMA1_Channel12_IRQHandler ; 0x341821DA
+
+

Section .init.GPDMA1_Channel13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel13_IRQHandler:
+  0x341821DC:  E7FE         B          GPDMA1_Channel13_IRQHandler ; 0x341821DC
+
+

Section .init.GPDMA1_Channel14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel14_IRQHandler:
+  0x341821DE:  E7FE         B          GPDMA1_Channel14_IRQHandler ; 0x341821DE
+
+

Section .init.GPDMA1_Channel15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
GPDMA1_Channel15_IRQHandler:
+  0x341821E0:  E7FE         B          GPDMA1_Channel15_IRQHandler ; 0x341821E0
+
+

Section .init.I2C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C1_EV_IRQHandler:
+  0x341821E2:  E7FE         B          I2C1_EV_IRQHandler       ; 0x341821E2
+
+

Section .init.I2C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C1_ER_IRQHandler:
+  0x341821E4:  E7FE         B          I2C1_ER_IRQHandler       ; 0x341821E4
+
+

Section .init.I2C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C2_EV_IRQHandler:
+  0x341821E6:  E7FE         B          I2C2_EV_IRQHandler       ; 0x341821E6
+
+

Section .init.I2C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C2_ER_IRQHandler:
+  0x341821E8:  E7FE         B          I2C2_ER_IRQHandler       ; 0x341821E8
+
+

Section .init.I2C3_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C3_EV_IRQHandler:
+  0x341821EA:  E7FE         B          I2C3_EV_IRQHandler       ; 0x341821EA
+
+

Section .init.I2C3_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C3_ER_IRQHandler:
+  0x341821EC:  E7FE         B          I2C3_ER_IRQHandler       ; 0x341821EC
+
+

Section .init.I2C4_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C4_EV_IRQHandler:
+  0x341821EE:  E7FE         B          I2C4_EV_IRQHandler       ; 0x341821EE
+
+

Section .init.I2C4_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I2C4_ER_IRQHandler:
+  0x341821F0:  E7FE         B          I2C4_ER_IRQHandler       ; 0x341821F0
+
+

Section .init.I3C1_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C1_EV_IRQHandler:
+  0x341821F2:  E7FE         B          I3C1_EV_IRQHandler       ; 0x341821F2
+
+

Section .init.I3C1_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C1_ER_IRQHandler:
+  0x341821F4:  E7FE         B          I3C1_ER_IRQHandler       ; 0x341821F4
+
+

Section .init.I3C2_EV_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C2_EV_IRQHandler:
+  0x341821F6:  E7FE         B          I3C2_EV_IRQHandler       ; 0x341821F6
+
+

Section .init.I3C2_ER_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
I3C2_ER_IRQHandler:
+  0x341821F8:  E7FE         B          I3C2_ER_IRQHandler       ; 0x341821F8
+
+

Section .init.TIM1_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_BRK_IRQHandler:
+  0x341821FA:  E7FE         B          TIM1_BRK_IRQHandler      ; 0x341821FA
+
+

Section .init.TIM1_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_UP_IRQHandler:
+  0x341821FC:  E7FE         B          TIM1_UP_IRQHandler       ; 0x341821FC
+
+

Section .init.TIM1_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_TRG_CCU_IRQHandler:
+  0x341821FE:  E7FE         B          TIM1_TRG_CCU_IRQHandler  ; 0x341821FE
+
+

Section .init.TIM1_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM1_CC_IRQHandler:
+  0x34182200:  E7FE         B          TIM1_CC_IRQHandler       ; 0x34182200
+
+

Section .init.TIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM2_IRQHandler:
+  0x34182202:  E7FE         B          TIM2_IRQHandler          ; 0x34182202
+
+

Section .init.TIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM3_IRQHandler:
+  0x34182204:  E7FE         B          TIM3_IRQHandler          ; 0x34182204
+
+

Section .init.TIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM4_IRQHandler:
+  0x34182206:  E7FE         B          TIM4_IRQHandler          ; 0x34182206
+
+

Section .init.TIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM5_IRQHandler:
+  0x34182208:  E7FE         B          TIM5_IRQHandler          ; 0x34182208
+
+

Section .init.TIM6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM6_IRQHandler:
+  0x3418220A:  E7FE         B          TIM6_IRQHandler          ; 0x3418220A
+
+

Section .init.TIM7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM7_IRQHandler:
+  0x3418220C:  E7FE         B          TIM7_IRQHandler          ; 0x3418220C
+
+

Section .init.TIM8_BRK_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_BRK_IRQHandler:
+  0x3418220E:  E7FE         B          TIM8_BRK_IRQHandler      ; 0x3418220E
+
+

Section .init.TIM8_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_UP_IRQHandler:
+  0x34182210:  E7FE         B          TIM8_UP_IRQHandler       ; 0x34182210
+
+

Section .init.TIM8_TRG_CCU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_TRG_CCU_IRQHandler:
+  0x34182212:  E7FE         B          TIM8_TRG_CCU_IRQHandler  ; 0x34182212
+
+

Section .init.TIM8_CC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM8_CC_IRQHandler:
+  0x34182214:  E7FE         B          TIM8_CC_IRQHandler       ; 0x34182214
+
+

Section .init.TIM9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM9_IRQHandler:
+  0x34182216:  E7FE         B          TIM9_IRQHandler          ; 0x34182216
+
+

Section .init.TIM10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM10_IRQHandler:
+  0x34182218:  E7FE         B          TIM10_IRQHandler         ; 0x34182218
+
+

Section .init.TIM11_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM11_IRQHandler:
+  0x3418221A:  E7FE         B          TIM11_IRQHandler         ; 0x3418221A
+
+

Section .init.TIM12_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM12_IRQHandler:
+  0x3418221C:  E7FE         B          TIM12_IRQHandler         ; 0x3418221C
+
+

Section .init.TIM13_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM13_IRQHandler:
+  0x3418221E:  E7FE         B          TIM13_IRQHandler         ; 0x3418221E
+
+

Section .init.TIM14_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM14_IRQHandler:
+  0x34182220:  E7FE         B          TIM14_IRQHandler         ; 0x34182220
+
+

Section .init.TIM15_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM15_IRQHandler:
+  0x34182222:  E7FE         B          TIM15_IRQHandler         ; 0x34182222
+
+

Section .init.TIM16_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM16_IRQHandler:
+  0x34182224:  E7FE         B          TIM16_IRQHandler         ; 0x34182224
+
+

Section .init.TIM17_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM17_IRQHandler:
+  0x34182226:  E7FE         B          TIM17_IRQHandler         ; 0x34182226
+
+

Section .init.TIM18_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
TIM18_IRQHandler:
+  0x34182228:  E7FE         B          TIM18_IRQHandler         ; 0x34182228
+
+

Section .init.LPTIM1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM1_IRQHandler:
+  0x3418222A:  E7FE         B          LPTIM1_IRQHandler        ; 0x3418222A
+
+

Section .init.LPTIM2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM2_IRQHandler:
+  0x3418222C:  E7FE         B          LPTIM2_IRQHandler        ; 0x3418222C
+
+

Section .init.LPTIM3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM3_IRQHandler:
+  0x3418222E:  E7FE         B          LPTIM3_IRQHandler        ; 0x3418222E
+
+

Section .init.LPTIM4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM4_IRQHandler:
+  0x34182230:  E7FE         B          LPTIM4_IRQHandler        ; 0x34182230
+
+

Section .init.LPTIM5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPTIM5_IRQHandler:
+  0x34182232:  E7FE         B          LPTIM5_IRQHandler        ; 0x34182232
+
+

Section .init.ADF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ADF1_FLT0_IRQHandler:
+  0x34182234:  E7FE         B          ADF1_FLT0_IRQHandler     ; 0x34182234
+
+

Section .init.MDF1_FLT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT0_IRQHandler:
+  0x34182236:  E7FE         B          MDF1_FLT0_IRQHandler     ; 0x34182236
+
+

Section .init.MDF1_FLT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT1_IRQHandler:
+  0x34182238:  E7FE         B          MDF1_FLT1_IRQHandler     ; 0x34182238
+
+

Section .init.MDF1_FLT2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT2_IRQHandler:
+  0x3418223A:  E7FE         B          MDF1_FLT2_IRQHandler     ; 0x3418223A
+
+

Section .init.MDF1_FLT3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT3_IRQHandler:
+  0x3418223C:  E7FE         B          MDF1_FLT3_IRQHandler     ; 0x3418223C
+
+

Section .init.MDF1_FLT4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT4_IRQHandler:
+  0x3418223E:  E7FE         B          MDF1_FLT4_IRQHandler     ; 0x3418223E
+
+

Section .init.MDF1_FLT5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDF1_FLT5_IRQHandler:
+  0x34182240:  E7FE         B          MDF1_FLT5_IRQHandler     ; 0x34182240
+
+

Section .init.SAI1_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI1_A_IRQHandler:
+  0x34182242:  E7FE         B          SAI1_A_IRQHandler        ; 0x34182242
+
+

Section .init.SAI1_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI1_B_IRQHandler:
+  0x34182244:  E7FE         B          SAI1_B_IRQHandler        ; 0x34182244
+
+

Section .init.SAI2_A_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI2_A_IRQHandler:
+  0x34182246:  E7FE         B          SAI2_A_IRQHandler        ; 0x34182246
+
+

Section .init.SAI2_B_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SAI2_B_IRQHandler:
+  0x34182248:  E7FE         B          SAI2_B_IRQHandler        ; 0x34182248
+
+

Section .init.SPDIFRX_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPDIFRX_IRQHandler:
+  0x3418224A:  E7FE         B          SPDIFRX_IRQHandler       ; 0x3418224A
+
+

Section .init.SPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI1_IRQHandler:
+  0x3418224C:  E7FE         B          SPI1_IRQHandler          ; 0x3418224C
+
+

Section .init.SPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI2_IRQHandler:
+  0x3418224E:  E7FE         B          SPI2_IRQHandler          ; 0x3418224E
+
+

Section .init.SPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI3_IRQHandler:
+  0x34182250:  E7FE         B          SPI3_IRQHandler          ; 0x34182250
+
+

Section .init.SPI4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI4_IRQHandler:
+  0x34182252:  E7FE         B          SPI4_IRQHandler          ; 0x34182252
+
+

Section .init.SPI5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI5_IRQHandler:
+  0x34182254:  E7FE         B          SPI5_IRQHandler          ; 0x34182254
+
+

Section .init.SPI6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SPI6_IRQHandler:
+  0x34182256:  E7FE         B          SPI6_IRQHandler          ; 0x34182256
+
+

Section .init.USART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART1_IRQHandler:
+  0x34182258:  E7FE         B          USART1_IRQHandler        ; 0x34182258
+
+

Section .init.USART2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART2_IRQHandler:
+  0x3418225A:  E7FE         B          USART2_IRQHandler        ; 0x3418225A
+
+

Section .init.USART3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART3_IRQHandler:
+  0x3418225C:  E7FE         B          USART3_IRQHandler        ; 0x3418225C
+
+

Section .init.UART4_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART4_IRQHandler:
+  0x3418225E:  E7FE         B          UART4_IRQHandler         ; 0x3418225E
+
+

Section .init.UART5_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART5_IRQHandler:
+  0x34182260:  E7FE         B          UART5_IRQHandler         ; 0x34182260
+
+

Section .init.USART6_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART6_IRQHandler:
+  0x34182262:  E7FE         B          USART6_IRQHandler        ; 0x34182262
+
+

Section .init.UART7_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART7_IRQHandler:
+  0x34182264:  E7FE         B          UART7_IRQHandler         ; 0x34182264
+
+

Section .init.UART8_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART8_IRQHandler:
+  0x34182266:  E7FE         B          UART8_IRQHandler         ; 0x34182266
+
+

Section .init.UART9_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UART9_IRQHandler:
+  0x34182268:  E7FE         B          UART9_IRQHandler         ; 0x34182268
+
+

Section .init.USART10_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USART10_IRQHandler:
+  0x3418226A:  E7FE         B          USART10_IRQHandler       ; 0x3418226A
+
+

Section .init.LPUART1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LPUART1_IRQHandler:
+  0x3418226C:  E7FE         B          LPUART1_IRQHandler       ; 0x3418226C
+
+

Section .init.XSPI1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
XSPI1_IRQHandler:
+  0x3418226E:  E7FE         B          XSPI1_IRQHandler         ; 0x3418226E
+
+

Section .init.XSPI2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
XSPI2_IRQHandler:
+  0x34182270:  E7FE         B          XSPI2_IRQHandler         ; 0x34182270
+
+

Section .init.XSPI3_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
XSPI3_IRQHandler:
+  0x34182272:  E7FE         B          XSPI3_IRQHandler         ; 0x34182272
+
+

Section .init.FMC_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FMC_IRQHandler:
+  0x34182274:  E7FE         B          FMC_IRQHandler           ; 0x34182274
+
+

Section .init.SDMMC1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SDMMC1_IRQHandler:
+  0x34182276:  E7FE         B          SDMMC1_IRQHandler        ; 0x34182276
+
+

Section .init.SDMMC2_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
SDMMC2_IRQHandler:
+  0x34182278:  E7FE         B          SDMMC2_IRQHandler        ; 0x34182278
+
+

Section .init.UCPD1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
UCPD1_IRQHandler:
+  0x3418227A:  E7FE         B          UCPD1_IRQHandler         ; 0x3418227A
+
+

Section .init.USB1_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USB1_OTG_HS_IRQHandler:
+  0x3418227C:  E7FE         B          USB1_OTG_HS_IRQHandler   ; 0x3418227C
+
+

Section .init.USB2_OTG_HS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
USB2_OTG_HS_IRQHandler:
+  0x3418227E:  E7FE         B          USB2_OTG_HS_IRQHandler   ; 0x3418227E
+
+

Section .init.ETH1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
ETH1_IRQHandler:
+  0x34182280:  E7FE         B          ETH1_IRQHandler          ; 0x34182280
+
+

Section .init.FDCAN1_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN1_IT0_IRQHandler:
+  0x34182282:  E7FE         B          FDCAN1_IT0_IRQHandler    ; 0x34182282
+
+

Section .init.FDCAN1_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN1_IT1_IRQHandler:
+  0x34182284:  E7FE         B          FDCAN1_IT1_IRQHandler    ; 0x34182284
+
+

Section .init.FDCAN2_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN2_IT0_IRQHandler:
+  0x34182286:  E7FE         B          FDCAN2_IT0_IRQHandler    ; 0x34182286
+
+

Section .init.FDCAN2_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN2_IT1_IRQHandler:
+  0x34182288:  E7FE         B          FDCAN2_IT1_IRQHandler    ; 0x34182288
+
+

Section .init.FDCAN3_IT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN3_IT0_IRQHandler:
+  0x3418228A:  E7FE         B          FDCAN3_IT0_IRQHandler    ; 0x3418228A
+
+

Section .init.FDCAN3_IT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN3_IT1_IRQHandler:
+  0x3418228C:  E7FE         B          FDCAN3_IT1_IRQHandler    ; 0x3418228C
+
+

Section .init.FDCAN_CU_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
FDCAN_CU_IRQHandler:
+  0x3418228E:  E7FE         B          FDCAN_CU_IRQHandler      ; 0x3418228E
+
+

Section .init.MDIOS_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
MDIOS_IRQHandler:
+  0x34182290:  E7FE         B          MDIOS_IRQHandler         ; 0x34182290
+
+

Section .init.DCMI_PSSI_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
DCMI_PSSI_IRQHandler:
+  0x34182292:  E7FE         B          DCMI_PSSI_IRQHandler     ; 0x34182292
+
+

Section .init.WAKEUP_PIN_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
WAKEUP_PIN_IRQHandler:
+  0x34182294:  E7FE         B          WAKEUP_PIN_IRQHandler    ; 0x34182294
+
+

Section .init.CTI_INT0_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CTI_INT0_IRQHandler:
+  0x34182296:  E7FE         B          CTI_INT0_IRQHandler      ; 0x34182296
+
+

Section .init.CTI_INT1_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
CTI_INT1_IRQHandler:
+  0x34182298:  E7FE         B          CTI_INT1_IRQHandler      ; 0x34182298
+
+

Section .init.LTDC_UP_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_UP_IRQHandler:
+  0x3418229A:  E7FE         B          LTDC_UP_IRQHandler       ; 0x3418229A
+
+

Section .init.LTDC_UP_ERR_IRQHandler from stm32n657xx_Vectors.o, size=2, align=2

+ +
+
LTDC_UP_ERR_IRQHandler:
+  0x3418229C:  E7FE         B          LTDC_UP_ERR_IRQHandler   ; 0x3418229C
+
+

Section .init_array from STM32N6xx_Startup.o, size=4, align=4

+ +
+  0x341822A0:  34180BFD     DC.W       SystemCoreClockUpdate
+
+

Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4

+ +
+
uwTick:
+  0x341822A4:  00           DC.B       0x00                     ; '\0'
+  0x341822A5:  00           DC.B       0x00                     ; '\0'
+  0x341822A6:  00           DC.B       0x00                     ; '\0'
+  0x341822A7:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.uwTickPrio from blto2_FSBL_lto.o, size=1, align=4

+ +
+
uwTickPrio:
+  0x341822A8:  03           DC.B       0x03                     ; '\x03'
+
+

Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4

+ +
+
SystemCoreClock:
+  0x341822AC:  00           DC.B       0x00                     ; '\0'
+  0x341822AD:  90           DC.B       0x90                     ; '\x90'
+  0x341822AE:  D0           DC.B       0xD0                     ; '\xD0'
+  0x341822AF:  03           DC.B       0x03                     ; '\x03'
+
+

Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4

+ +
+
__SEGGER_init_ctors:
+  0x341822B0:  B500         PUSH       123LR}
+  0x341822B2:  4806         LDR        R0, =0x341822A0          ; [PC, #24] [0x341822CC] 
+  0x341822B4:  4906         LDR        R1, =uwTick              ; [PC, #24] [0x341822D0] =0x341822A4 
+
.L1:
+  0x341822B6:  4288         CMP        R0, R1
+  0x341822B8:  D005         BEQ        46L2                      ; 0x341822C6
+  0x341822BA:  6802         LDR        R2, [R0]
+  0x341822BC:  3004         ADDS       R0, #4
+  0x341822BE:  B403         PUSH       123R0-R1}
+  0x341822C0:  4790         BLX        R2
+  0x341822C2:  BC03         POP        123R0-R1}
+  0x341822C4:  E7F7         B          46L1                      ; 0x341822B6
+
.L2:
+  0x341822C6:  BC08         POP        123R3}
+  0x341822C8:  4718         BX         R3
+  0x341822CA:  0000         NOP
+  0x341822CC:  341822A0     DC.W       341822A0               ; R_ARM_ABS32
+  0x341822D0:  341822A4     DC.W       uwTick
+
+

Section .segger.init.table from [ Linker created ], size=36, align=4

+ +
+  0x341822D4:  341822FD     DC.W       __SEGGER_init_zero
+  0x341822D8:  A4           DC.B       0xA4                     ; '\xA4'
+  0x341822D9:  22           DC.B       0x22                     ; '\"'
+  0x341822DA:  18           DC.B       0x18                     ; '\x18'
+  0x341822DB:  34           DC.B       0x34                     ; '4'
+  0x341822DC:  05           DC.B       0x05                     ; '\x05'
+  0x341822DD:  00           DC.B       0x00                     ; '\0'
+  0x341822DE:  00           DC.B       0x00                     ; '\0'
+  0x341822DF:  00           DC.B       0x00                     ; '\0'
+  0x341822E0:  3418230F     DC.W       __SEGGER_init_copy
+  0x341822E4:  AC           DC.B       0xAC                     ; '\xAC'
+  0x341822E5:  22           DC.B       0x22                     ; '\"'
+  0x341822E6:  18           DC.B       0x18                     ; '\x18'
+  0x341822E7:  34           DC.B       0x34                     ; '4'
+  0x341822E8:  341822F8     DC.W       341822F8               ; R_ARM_ABS32
+  0x341822EC:  04           DC.B       0x04                     ; '\x04'
+  0x341822ED:  00           DC.B       0x00                     ; '\0'
+  0x341822EE:  00           DC.B       0x00                     ; '\0'
+  0x341822EF:  00           DC.B       0x00                     ; '\0'
+  0x341822F0:  341822B1     DC.W       __SEGGER_init_ctors
+  0x341822F4:  341814B7     DC.W       __SEGGER_init_done
+
+

Section .segger.init.data from [ Linker created ], size=4, align=4

+ +
+  0x341822F8:  00           DC.B       0x00                     ; '\0'
+  0x341822F9:  90           DC.B       0x90                     ; '\x90'
+  0x341822FA:  D0           DC.B       0xD0                     ; '\xD0'
+  0x341822FB:  03           DC.B       0x03                     ; '\x03'
+
+

Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2

+ +
+
__SEGGER_init_zero:
+  0x341822FC:  6820         LDR        R0, [R4]
+  0x341822FE:  6861         LDR        R1, [R4, #4]
+  0x34182300:  3408         ADDS       R4, #8
+  0x34182302:  2200         MOVS       R2, #0
+  0x34182304:  E000         B          46L2                      ; 0x34182308
+
.L1:
+  0x34182306:  5442         STRB       R2, [R0, R1]
+
.L2:
+  0x34182308:  1E49         SUBS       R1, R1, #1
+  0x3418230A:  D5FC         BPL        46L1                      ; 0x34182306
+  0x3418230C:  4770         BX         LR
+
+

Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2

+ +
+
__SEGGER_init_copy:
+  0x3418230E:  6820         LDR        R0, [R4]
+  0x34182310:  6861         LDR        R1, [R4, #4]
+  0x34182312:  68A2         LDR        R2, [R4, #8]
+  0x34182314:  340C         ADDS       R4, #12
+  0x34182316:  E001         B          46L2                      ; 0x3418231C
+
.L1:
+  0x34182318:  5C8B         LDRB       R3, [R1, R2]
+  0x3418231A:  5483         STRB       R3, [R0, R2]
+
.L2:
+  0x3418231C:  1E52         SUBS       R2, R2, #1
+  0x3418231E:  D5FB         BPL        46L1                      ; 0x34182318
+  0x34182320:  4770         BX         LR
+
+

Section .bss.block.stack from [ Linker created ], size=8192, align=8

+ +
+(341FE000-341FFFFF excluded)
+
+

LINK SUMMARY

+ + +
+  7 836 bytes read-only  code    + 
+    116 bytes read-only  data    =   7 952 bytes read-only (total)
+  8 201 bytes read-write data
+
+ + + + + + + + + + + + + + + + + + + +
NameRangeSizeUsedUnusedAlignment Loss
AXI_RAM234180400-341FFFFF523 26416 157 3.09507 104 96.913 0.00
+ + +
+Link complete: 0 errors.
+
+ Index: trunk/firmware/FSBL/SES/Output/Release/Exe/blto2_FSBL.htm =================================================================== --- trunk/firmware/FSBL/SES/Output/Release/Exe/blto2_FSBL.htm (revision 16) +++ trunk/firmware/FSBL/SES/Output/Release/Exe/blto2_FSBL.htm (revision 16) @@ -0,0 +1,13170 @@ + + + + +

CONTENTS

+ +

LINK INFORMATION

+ + +
+SEGGER ARM Linker 4.44.5 compiled Aug  7 2026 18:47:09
+Copyright (c) 2017-2026 SEGGER Microcontroller GmbH    www.segger.com
+
+ + +
+--add-region:ITCM_RAM=0x00010000@0x10000000
+--add-region:DTCM_RAM=0x00020000@0x30000000
+--add-region:FLEX_RAM=0x00064000@0x34000000
+--add-region:AXI_RAM1=0x0009c000@0x34064000
+--add-region:AXI_RAM2=0x0007fc00@0x34180400
+--add-region:AXI_RAM3=0x00070000@0x34200000
+--add-region:AXI_RAM4=0x00070000@0x34270000
+--add-region:AXI_RAM5=0x00070000@0x342e0000
+--add-region:AXI_RAM6=0x00070000@0x34350000
+--add-region:AXI_RAM7=0x00040000@0x343c0000
+--add-region:AXI_RAM8=0x00020000@0x34400000
+--add-region:AHB_RAM1=0x00004000@0x38000000
+--add-region:AHB_RAM2=0x00004000@0x38004000
+--add-region:BKP_RAM=0x00002000@0x3c000000
+--full-section-headers
+--dedupe-code
+--merge-sections
+--merge-strings
+--map-html
+--map-file=Output/Release/Exe/blto2_FSBL.htm
+--map-full
+--list-all-undefineds
+-eReset_Handler
+-EL
+-mcpu=8.1-M.main
+--silent
+-TD:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf
+--defsym=__STACKSIZE__=8192
+--defsym=__STACKSIZE_PROCESS__=0
+--defsym=__HEAPSIZE__=256
+--defsym=__SEGGER_RTL_vfprintf=__SEGGER_RTL_vfprintf_short_float_long_long
+--defsym=__SEGGER_RTL_vfscanf=__SEGGER_RTL_vfscanf_int
+-u_vectors
+-o
+D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Release/Exe/blto2_FSBL.elf
+D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/Output/Release/Obj/blto2_FSBL_lto.o
+Output/Release/Obj/SEGGER_THUMB_Startup.o
+Output/Release/Obj/stm32n657xx_Vectors.o
+Output/Release/Obj/STM32N6xx_Startup.o
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/libc_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/prinops_rtt_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/heapops_disable_interrupts_locking_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+C:/Program Files/SEGGER/SEGGER Embedded Studio 8.30a/lib/mbops_timeops_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a
+
+

LINKER SCRIPT

+

Linker script 'D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf'

+ +
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2026 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : STM32N6xx_RAM.icf
+Purpose : STM32N6xx linker script for application placement in RAM
+          (to be copied to RAM by bootloader or debugger)
+          for use with the SEGGER Linker.
+Maps    : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ,
+          STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ,
+          STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ,
+          STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ,
+          STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ,
+          STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region RAM   = AXI_RAM2;
+
+//
+// Block definitions
+//
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { section .vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+//
+// Explicit placement in RAMn
+//
+place in AHB_RAM1                           { section .AHB_RAM1, section .AHB_RAM1.* };
+place in AHB_RAM2                           { section .AHB_RAM2, section .AHB_RAM2.* };
+place in AXI_RAM1                           { section .AXI_RAM1, section .AXI_RAM1.* };  // This region may be deactivated and not accessible
+place in AXI_RAM2                           { section .AXI_RAM2, section .AXI_RAM2.* };  // This region may be deactivated and not accessible
+place in AXI_RAM3                           { section .AXI_RAM3, section .AXI_RAM3.* };  // This region may be deactivated and not accessible
+place in AXI_RAM4                           { section .AXI_RAM4, section .AXI_RAM4.* };  // This region may be deactivated and not accessible
+place in BKP_RAM                            { section .BKP_RAM,  section .BKP_RAM.*  };  // This region may be deactivated and not accessible
+place in DTCM_RAM                           { section .DTCM_RAM, section .DTCM_RAM.* };  // This region may be deactivated and not accessible
+place in FLEX_RAM                           { section .FLEX_RAM, section .FLEX_RAM.* };
+place in ITCM_RAM                           { section .ITCM_RAM, section .ITCM_RAM.* };  // This region may be deactivated and not accessible
+
+//
+// RAM Placement
+//
+place at start of RAM                       { section .vectors };                                   // Vector table section
+place in RAM with minimum size order        { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+place in RAM                                { section .fast, section .fast.* };                     // "ramfunc" section
+place in RAM with auto order                { block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM                         { block stack };                                        // Stack reserved block at the end
+
+
+

PLACEMENT SUMMARY

+

place at 0x34180400

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
_vectorsCode0x341804008441024stm32n657xx_Vectors.o
+

place at 0x34200000

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.stack]None0x341FE0008 1928[ Linker created ]
+

"<#14> at line 120, col 45": place in [0x34180400 to 0x341FFFFF] with maximum packing

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
mainCode0x3418074C1 0364blto2_FSBL_lto.o
SysTick_HandlerCode0x34180B58164blto2_FSBL_lto.o
SystemCoreClockUpdateCode0x34180B684004blto2_FSBL_lto.o
HAL_RCC_ClockConfigCode0x34180CF81 4724blto2_FSBL_lto.o
RCC_IC_CheckPLLSourcesCode0x341812B81484blto2_FSBL_lto.o
RCCEx_GetPLLSourceFreqCode0x3418134C1284blto2_FSBL_lto.o
[.rodata..Lswitch.table.HAL_GPIO_DeInit]Cnst0x341813CC644blto2_FSBL_lto.o
[.rodata..Lswitch.table.RCC_PLL_Config]Cnst0x3418140C124blto2_FSBL_lto.o
_startCode0x34181418204SEGGER_THUMB_Startup.o
reset_handlerCode0x3418142C444STM32N6xx_Startup.o
__aeabi_memclrCode0x341814581044strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
NMI_HandlerCode0x341814C024blto2_FSBL_lto.o
[.rodata.block.tdata.copy]Cnst0x341814C21[ Linker created ]
SVC_HandlerCode0x341814C424blto2_FSBL_lto.o
SystemInitCode0x341814C83024blto2_FSBL_lto.o
HAL_GPIO_InitCode0x341815F84184blto2_FSBL_lto.o
HAL_RCC_OscConfigCode0x3418179C1 7144blto2_FSBL_lto.o
RCC_PLL_IsNewConfigCode0x34181E501344blto2_FSBL_lto.o
RCC_PLL_ConfigCode0x34181ED84464blto2_FSBL_lto.o
[.init_array]----0x3418209844STM32N6xx_Startup.o
__SEGGER_init_ctorsCode0x341820A8364SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_table__Cnst0x341820CC364[ Linker created ]
__SEGGER_init_data__Cnst0x341820F044[ Linker created ]
__SEGGER_init_zeroCode0x341820F4182SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_copyCode0x34182106202SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
+

"<#16> at line 128, col 45": place in [0x34180400 to 0x341FFFFF] with auto order

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x341814C88[ Linker created ]
uwTickZero0x3418209C44blto2_FSBL_lto.o
uwTickPrioZero0x341820A014blto2_FSBL_lto.o
SystemCoreClockInit0x341820A444blto2_FSBL_lto.o
[.bss.block.stack]None0x341FE0008 1928[ Linker created ]
+

"<#17> at line 132, col 45": place in [0x34180400 to 0x341FFFFF] with auto order

+ + + + + + + + + + + + + + + + + + +
Symbol or [section] nameTypeAddressSizeAlignObject File
[.bss.block.heap]None0x341814C88[ Linker created ]
+

MODULE SUMMARY

+

Memory use by input file

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Object FileRX CodeRO DataRW DataZI Data
blto2_FSBL_lto.o6 2187645
SEGGER_THUMB_Startup.o20
stm32n657xx_Vectors.o844
STM32N6xx_Startup.o44
Subtotal (4 objects)7 1267645
SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a74
strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a104
Subtotal (2archives)178
Linker created (shared data, fills, blocks):408 192
Total:7 30411648 197
+

Memory use by archive member

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Archive memberRX CodeRO DataRW DataZI Data
SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)74
strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)104
Subtotal (2 members from 2 archives)178
Objects (4 files)7 1267645
Linker created (shared data, fills, blocks):408 192
Total:7 30411648 197
+

Memory use by linker

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DescriptionRX CodeRO DataRW DataZI Data
Initialization table40
Memory for block 'stack'8 192
Subtotal (linker created):408 192
Objects (4 files)7 1267645
Archives (2 files)178
Total:7 30411648 197
+

MODULE DETAIL

+

Module blto2_FSBL_lto.o

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
HAL_RCC_OscConfig1 714
HAL_RCC_ClockConfig1 472
main1 036
RCC_PLL_Config446
HAL_GPIO_Init418
SystemCoreClockUpdate400
SystemInit302
RCC_IC_CheckPLLSources148
RCC_PLL_IsNewConfig134
RCCEx_GetPLLSourceFreq128
SysTick_Handler16
NMI_Handler2
SVC_Handler2
[.rodata..Lswitch.table.HAL_GPIO_DeInit]64
[.rodata..Lswitch.table.RCC_PLL_Config]12
SystemCoreClock4
uwTick4
uwTickPrio1
Total:6 2187645
+

Module SEGGER_THUMB_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_start20
Total:20
+

Module stm32n657xx_Vectors.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
_vectors844
Total:844
+

Module STM32N6xx_Startup.o

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
reset_handler44
Total:44
+

Module SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__SEGGER_init_ctors36
__SEGGER_init_copy20
__SEGGER_init_zero18
Total:74
+

Module strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)

+ + + + + + + + + + + + + + + + + + + + + + + +
Symbol or [section] nameCodeRO DataRW DataZI Data
__aeabi_memclr104
Total:104
+

All modules

+ + + + + + + + + + + + + + + + +
CodeRO DataRW DataZI Data
Grand total:7 3047645
+

SECTION DETAIL

+

Sections by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSymbol or [section] NameSizeAlInitAcObject File
34180400-3418074B_vectors8441024CodeRXstm32n657xx_Vectors.o
3418074C-34180B57main1 0364CodeRXblto2_FSBL_lto.o
34180B58-34180B67SysTick_Handler164CodeRXblto2_FSBL_lto.o
34180B68-34180CF7SystemCoreClockUpdate4004CodeRXblto2_FSBL_lto.o
34180CF8-341812B7HAL_RCC_ClockConfig1 4724CodeRXblto2_FSBL_lto.o
341812B8-3418134BRCC_IC_CheckPLLSources1484CodeRXblto2_FSBL_lto.o
3418134C-341813CBRCCEx_GetPLLSourceFreq1284CodeRXblto2_FSBL_lto.o
341813CC-3418140B[.rodata..Lswitch.table.HAL_GPIO_DeInit]644CnstROblto2_FSBL_lto.o
3418140C-34181417[.rodata..Lswitch.table.RCC_PLL_Config]124CnstROblto2_FSBL_lto.o
34181418-3418142B_start204CodeRXSEGGER_THUMB_Startup.o
3418142C-34181457reset_handler444CodeRXSTM32N6xx_Startup.o
34181458-341814BF__aeabi_memclr1044CodeRXstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
341814C0-341814C1NMI_Handler24CodeRXblto2_FSBL_lto.o
341814C2-341814C3( ALIGN .=.+2 )2-------
341814C4-341814C5SVC_Handler24CodeRXblto2_FSBL_lto.o
341814C6-341814C7( ALIGN .=.+2 )2-------
341814C8-341815F5SystemInit3024CodeRXblto2_FSBL_lto.o
341815F6-341815F7( ALIGN .=.+2 )2-------
341815F8-34181799HAL_GPIO_Init4184CodeRXblto2_FSBL_lto.o
3418179A-3418179B( ALIGN .=.+2 )2-------
3418179C-34181E4DHAL_RCC_OscConfig1 7144CodeRXblto2_FSBL_lto.o
34181E4E-34181E4F( ALIGN .=.+2 )2-------
34181E50-34181ED5RCC_PLL_IsNewConfig1344CodeRXblto2_FSBL_lto.o
34181ED6-34181ED7( ALIGN .=.+2 )2-------
34181ED8-34182095RCC_PLL_Config4464CodeRXblto2_FSBL_lto.o
34182096-34182097( ALIGN .=.+2 )2-------
34182098-3418209B[.init_array]44------STM32N6xx_Startup.o
3418209C-3418209FuwTick44ZeroZIblto2_FSBL_lto.o
341820A0-341820A0uwTickPrio14ZeroZIblto2_FSBL_lto.o
341820A1-341820A3( ALIGN .=.+3 )3-------
341820A4-341820A7SystemCoreClock44InitRWblto2_FSBL_lto.o
341820A8-341820CB__SEGGER_init_ctors364CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
341820CC-341820EF__SEGGER_init_table__364CnstRO[ Linker created ]
341820F0-341820F3__SEGGER_init_data__44CnstRO[ Linker created ]
341820F4-34182105__SEGGER_init_zero182CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
34182106-34182119__SEGGER_init_copy202CodeRXSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
3418211A-341FDFFF( UNUSED .=.+507622 )507 622-------
341FE000-341FFFFF[.bss.block.stack]8 1928NoneZI[ Linker created ]
+

UNUSED MEMORY SUMMARY

+

Detail

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeSizeReason
341814C2-341814C32Filler between sections '.text.NMI_Handler' and '.text.SVC_Handler' as align=4
NOTE: section '.text.NMI_Handler' has size 2 that is not a multiple of its alignment 4
341814C6-341814C72Filler between sections '.text.SVC_Handler' and '.text.SystemInit' as align=4
NOTE: section '.text.SVC_Handler' has size 2 that is not a multiple of its alignment 4
341815F6-341815F72Filler between sections '.text.SystemInit' and '.text.HAL_GPIO_Init' as align=4
NOTE: section '.text.SystemInit' has size 302 that is not a multiple of its alignment 4
3418179A-3418179B2Filler between sections '.text.HAL_GPIO_Init' and '.text.HAL_RCC_OscConfig' as align=4
NOTE: section '.text.HAL_GPIO_Init' has size 418 that is not a multiple of its alignment 4
34181E4E-34181E4F2Filler between sections '.text.HAL_RCC_OscConfig' and '.text.RCC_PLL_IsNewConfig' as align=4
NOTE: section '.text.HAL_RCC_OscConfig' has size 1714 that is not a multiple of its alignment 4
34181ED6-34181ED72Filler between sections '.text.RCC_PLL_IsNewConfig' and '.text.RCC_PLL_Config' as align=4
NOTE: section '.text.RCC_PLL_IsNewConfig' has size 134 that is not a multiple of its alignment 4
34182096-341820972Filler between sections '.text.RCC_PLL_Config' and '.init_array' as align=4
NOTE: section '.text.RCC_PLL_Config' has size 446 that is not a multiple of its alignment 4
341820A1-341820A33Filler between sections '.bss.uwTickPrio' and '.data.SystemCoreClock' as align=4
NOTE: section '.bss.uwTickPrio' has size 1 that is not a multiple of its alignment 4
3418211A-341FDFFF507 622Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.block.stack'
+

INITIALIZATION TABLE

+

Constructor list

+ + + + + + + + + + + + +
Table
Address		Called
Address		Called
Symbol or [section] name
0x341820980x34180B69SystemCoreClockUpdate
+

Initialize by zero

+ + + + + + + + + + + + + + + + + + + + + + +

Initialize by copy with packing=none

+ +
RangeSizeSymbol or [section] name
3418209C-3418209F4uwTick
341820A0-341820A01uwTickPrio
3418209C-341820A05Total (2 sections)
+ + + + + + + + + + + + + + + + +

Summary

+ +
RangeSizeSymbol or [section] name
341820A4-341820A74SystemCoreClock
341820A4-341820A74Total (1 sections)
+ + + + + + + + + + + + + + + + + + + + +
DescriptionSize
Initialization table36 bytes
Source image4 bytes
Destination image9 bytes
Saving-31 bytes
+

LINKER-CREATED VENEERS

+

Arm-Arm range extension veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Thumb range extension veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Arm-Thumb mode switch veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Thumb-Arm mode switch veneers

+ + + + + + + + + + + + +
Veneer SizeTargetSource
0Total
+

Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
Veneer TypeSize
Thumb-Arm mode switch0
Arm-Thumb mode switch0
Thumb-Thumb range extension0
Arm-Arm range extension0
Total:0
+

SYMBOL LIST

+

Function symbols by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameAddressSizeAlignTypeBdObject File
ADC1_2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
ADF1_FLT0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
BCK_ECC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
BusFault_Handler0x341814C124CodeGbblto2_FSBL_lto.o
CACHEAXI_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
CACHE_ECC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
CRYP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
CSI_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
CTI_INT0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
CTI_INT1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
DCMIPP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
DCMI_PSSI_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
DMA2D_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
DTS_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
DebugMon_Handler0x341814C524CodeGbblto2_FSBL_lto.o
ETH1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI10_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI11_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI12_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI13_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI14_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI15_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI6_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI7_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI8_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
EXTI9_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FDCAN_CU_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FMC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
FPU_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GFXMMU_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GFXTIM_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPU2D_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
GPU2D_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HAL_GPIO_Init0x341815F94184CodeLcblto2_FSBL_lto.o
HAL_RCC_ClockConfig0x34180CF91 4724CodeLcblto2_FSBL_lto.o
HAL_RCC_OscConfig0x3418179D1 7144CodeLcblto2_FSBL_lto.o
HASH_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
HardFault_Handler0x341814C124CodeGbblto2_FSBL_lto.o
I2C1_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C1_EV_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C2_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C2_EV_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C3_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C3_EV_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C4_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I2C4_EV_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I3C1_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I3C1_EV_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I3C2_ER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
I3C2_EV_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
IAC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
ICACHE_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
IWDG_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
JPEG_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LOCKUP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LPTIM1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LPTIM2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LPTIM3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LPTIM4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LPTIM5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LPUART1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LTDC_LO_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
LTDC_UP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MCE1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MCE2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MCE3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MCE4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDF1_FLT0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDF1_FLT1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDF1_FLT2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDF1_FLT3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDF1_FLT4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDF1_FLT5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MDIOS_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
MemManage_Handler0x341814C124CodeGbblto2_FSBL_lto.o
NMI_Handler0x341814C124CodeGbblto2_FSBL_lto.o
NPU0_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
NPU1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
NPU2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
NPU3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
PAHB_ERR_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
PKA_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
PVD_PVM_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
PendSV_Handler0x341814C524CodeGbblto2_FSBL_lto.o
RCCEx_GetPLLSourceFreq0x3418134D1284CodeLcblto2_FSBL_lto.o
RCC_IC_CheckPLLSources0x341812B91484CodeLcblto2_FSBL_lto.o
RCC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
RCC_PLL_Config0x34181ED94464CodeLcblto2_FSBL_lto.o
RCC_PLL_IsNewConfig0x34181E511344CodeLcblto2_FSBL_lto.o
RCC_S_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
RIFSC_TAMPER_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
RNG_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
RTC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
RTC_S_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
Reset_Handler0x3418142D4CodeGbSTM32N6xx_Startup.o
SAES_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SAI1_A_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SAI1_B_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SAI2_A_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SAI2_B_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SDMMC1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SDMMC2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPDIFRX_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPI1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPI2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPI3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPI4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPI5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SPI6_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
SVC_Handler0x341814C524CodeGbblto2_FSBL_lto.o
SysTick_Handler0x34180B59164CodeGbblto2_FSBL_lto.o
SystemCoreClockUpdate0x34180B694004CodeGbblto2_FSBL_lto.o
SystemInit0x341814C93024CodeGbblto2_FSBL_lto.o
TAMP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TCM_ECC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM10_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM11_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM12_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM13_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM14_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM15_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM16_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM17_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM18_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM1_BRK_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM1_CC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM1_UP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM6_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM7_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM8_BRK_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM8_CC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM8_UP_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
TIM9_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UART4_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UART5_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UART7_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UART8_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UART9_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UCPD1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USART10_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USART1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USART2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USART3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USART6_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
UsageFault_Handler0x341814C124CodeGbblto2_FSBL_lto.o
VENC_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
WWDG_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
XSPI1_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
XSPI2_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
XSPI3_IRQHandler0x341814C14CodeWkstm32n657xx_Vectors.o
__SEGGER_init_copy0x34182107202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_ctors0x341820A9264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_done0x341814234CodeGbSEGGER_THUMB_Startup.o
__SEGGER_init_zero0x341820F5182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr0x341814591044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr40x341814594CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memclr80x341814594CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset0x3418145B4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset40x3418145B4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__aeabi_memset80x3418145B4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__startup_complete0x341814234CodeGbSEGGER_THUMB_Startup.o
_start0x34181419144CodeGbSEGGER_THUMB_Startup.o
exit0x3418142724CodeGbSEGGER_THUMB_Startup.o
main0x3418074D1 0364CodeGbblto2_FSBL_lto.o
memset0x341814614CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
reset_handler0x3418142D4CodeGbSTM32N6xx_Startup.o
+

Function symbols by address

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AddressSymbol nameSizeAlignTypeBdObject File
0x3418074Dmain1 0364CodeGbblto2_FSBL_lto.o
0x34180B59SysTick_Handler164CodeGbblto2_FSBL_lto.o
0x34180B69SystemCoreClockUpdate4004CodeGbblto2_FSBL_lto.o
0x34180CF9HAL_RCC_ClockConfig1 4724CodeLcblto2_FSBL_lto.o
0x341812B9RCC_IC_CheckPLLSources1484CodeLcblto2_FSBL_lto.o
0x3418134DRCCEx_GetPLLSourceFreq1284CodeLcblto2_FSBL_lto.o
0x34181419_start144CodeGbSEGGER_THUMB_Startup.o
0x34181423__startup_complete4CodeGbSEGGER_THUMB_Startup.o
0x34181423__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
0x34181427exit24CodeGbSEGGER_THUMB_Startup.o
0x3418142Dreset_handler4CodeGbSTM32N6xx_Startup.o
0x3418142DReset_Handler4CodeGbSTM32N6xx_Startup.o
0x34181459__aeabi_memclr84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181459__aeabi_memclr44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181459__aeabi_memclr1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x3418145B__aeabi_memset84CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x3418145B__aeabi_memset44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x3418145B__aeabi_memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34181461memset4CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341814C1XSPI3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1XSPI2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1XSPI1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1WWDG_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1WAKEUP_PIN_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1VENC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UsageFault_Handler24CodeGbblto2_FSBL_lto.o
0x341814C1USB2_OTG_HS_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1USB1_OTG_HS_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1USART6_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1USART3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1USART2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1USART1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1USART10_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UCPD1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UART9_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UART8_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UART7_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UART5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1UART4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM9_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM8_UP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM8_TRG_CCU_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM8_CC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM8_BRK_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM7_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM6_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM1_UP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM1_TRG_CCU_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM1_CC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM1_BRK_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM18_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM17_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM16_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM15_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM14_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM13_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM12_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM11_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TIM10_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TCM_ECC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1TAMP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPI6_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPI5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPI4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPI3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPI2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPI1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SPDIFRX_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SDMMC2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SDMMC1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SAI2_B_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SAI2_A_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SAI1_B_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SAI1_A_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1SAES_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1RTC_S_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1RTC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1RNG_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1RIFSC_TAMPER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1RCC_S_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1RCC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1PVD_PVM_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1PKA_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1PAHB_ERR_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1NPU3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1NPU2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1NPU1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1NPU0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1NMI_Handler24CodeGbblto2_FSBL_lto.o
0x341814C1MemManage_Handler24CodeGbblto2_FSBL_lto.o
0x341814C1MDIOS_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MDF1_FLT5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MDF1_FLT4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MDF1_FLT3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MDF1_FLT2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MDF1_FLT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MDF1_FLT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MCE4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MCE3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MCE2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1MCE1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LTDC_UP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LTDC_UP_ERR_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LTDC_LO_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LTDC_LO_ERR_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LPUART1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LPTIM5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LPTIM4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LPTIM3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LPTIM2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LPTIM1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1LOCKUP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1JPEG_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1IWDG_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1ICACHE_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1IAC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I3C2_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I3C2_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I3C1_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I3C1_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C4_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C4_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C3_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C3_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C2_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C2_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C1_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1I2C1_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HardFault_Handler24CodeGbblto2_FSBL_lto.o
0x341814C1HPDMA1_Channel9_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel8_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel7_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel6_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel15_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel14_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel13_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel12_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel11_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel10_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HPDMA1_Channel0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1HASH_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPU2D_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPU2D_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel9_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel8_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel7_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel6_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel15_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel14_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel13_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel12_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel11_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel10_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GPDMA1_Channel0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GFXTIM_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1GFXMMU_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FPU_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FMC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN_CU_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN3_IT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN3_IT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN2_IT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN2_IT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN1_IT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1FDCAN1_IT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI9_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI8_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI7_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI6_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI5_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI4_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI3_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI15_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI14_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI13_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI12_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI11_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI10_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1EXTI0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1ETH1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1DTS_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1DMA2D_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1DCMI_PSSI_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1DCMIPP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1CTI_INT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1CTI_INT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1CSI_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1CRYP_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1CACHE_ECC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1CACHEAXI_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1BusFault_Handler24CodeGbblto2_FSBL_lto.o
0x341814C1BCK_ECC_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1ADF1_FLT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C1ADC1_2_IRQHandler4CodeWkstm32n657xx_Vectors.o
0x341814C5SVC_Handler24CodeGbblto2_FSBL_lto.o
0x341814C5PendSV_Handler24CodeGbblto2_FSBL_lto.o
0x341814C5DebugMon_Handler24CodeGbblto2_FSBL_lto.o
0x341814C9SystemInit3024CodeGbblto2_FSBL_lto.o
0x341815F9HAL_GPIO_Init4184CodeLcblto2_FSBL_lto.o
0x3418179DHAL_RCC_OscConfig1 7144CodeLcblto2_FSBL_lto.o
0x34181E51RCC_PLL_IsNewConfig1344CodeLcblto2_FSBL_lto.o
0x34181ED9RCC_PLL_Config4464CodeLcblto2_FSBL_lto.o
0x341820A9__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x341820F5__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
0x34182107__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
+

Function symbols by descending size

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Symbol nameSizeAlignTypeBdObject File
HAL_RCC_OscConfig1 7144CodeLcblto2_FSBL_lto.o
HAL_RCC_ClockConfig1 4724CodeLcblto2_FSBL_lto.o
main1 0364CodeGbblto2_FSBL_lto.o
RCC_PLL_Config4464CodeLcblto2_FSBL_lto.o
HAL_GPIO_Init4184CodeLcblto2_FSBL_lto.o
SystemCoreClockUpdate4004CodeGbblto2_FSBL_lto.o
SystemInit3024CodeGbblto2_FSBL_lto.o
RCC_IC_CheckPLLSources1484CodeLcblto2_FSBL_lto.o
RCC_PLL_IsNewConfig1344CodeLcblto2_FSBL_lto.o
RCCEx_GetPLLSourceFreq1284CodeLcblto2_FSBL_lto.o
__aeabi_memclr1044CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_ctors264CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_copy202CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
__SEGGER_init_zero182CodeWkSEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
SysTick_Handler164CodeGbblto2_FSBL_lto.o
_start144CodeGbSEGGER_THUMB_Startup.o
BusFault_Handler24CodeGbblto2_FSBL_lto.o
DebugMon_Handler24CodeGbblto2_FSBL_lto.o
HardFault_Handler24CodeGbblto2_FSBL_lto.o
MemManage_Handler24CodeGbblto2_FSBL_lto.o
NMI_Handler24CodeGbblto2_FSBL_lto.o
PendSV_Handler24CodeGbblto2_FSBL_lto.o
SVC_Handler24CodeGbblto2_FSBL_lto.o
UsageFault_Handler24CodeGbblto2_FSBL_lto.o
exit24CodeGbSEGGER_THUMB_Startup.o
ADC1_2_IRQHandler4CodeWkstm32n657xx_Vectors.o
ADF1_FLT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
BCK_ECC_IRQHandler4CodeWkstm32n657xx_Vectors.o
CACHEAXI_IRQHandler4CodeWkstm32n657xx_Vectors.o
CACHE_ECC_IRQHandler4CodeWkstm32n657xx_Vectors.o
CRYP_IRQHandler4CodeWkstm32n657xx_Vectors.o
CSI_IRQHandler4CodeWkstm32n657xx_Vectors.o
CTI_INT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
CTI_INT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
DCMIPP_IRQHandler4CodeWkstm32n657xx_Vectors.o
DCMI_PSSI_IRQHandler4CodeWkstm32n657xx_Vectors.o
DMA2D_IRQHandler4CodeWkstm32n657xx_Vectors.o
DTS_IRQHandler4CodeWkstm32n657xx_Vectors.o
ETH1_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI0_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI10_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI11_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI12_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI13_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI14_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI15_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI1_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI2_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI3_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI4_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI5_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI6_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI7_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI8_IRQHandler4CodeWkstm32n657xx_Vectors.o
EXTI9_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN1_IT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN1_IT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN2_IT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN2_IT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN3_IT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN3_IT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
FDCAN_CU_IRQHandler4CodeWkstm32n657xx_Vectors.o
FMC_IRQHandler4CodeWkstm32n657xx_Vectors.o
FPU_IRQHandler4CodeWkstm32n657xx_Vectors.o
GFXMMU_IRQHandler4CodeWkstm32n657xx_Vectors.o
GFXTIM_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel0_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel10_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel11_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel12_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel13_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel14_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel15_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel1_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel2_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel3_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel4_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel5_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel6_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel7_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel8_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPDMA1_Channel9_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPU2D_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
GPU2D_IRQHandler4CodeWkstm32n657xx_Vectors.o
HASH_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel0_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel10_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel11_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel12_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel13_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel14_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel15_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel1_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel2_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel3_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel4_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel5_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel6_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel7_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel8_IRQHandler4CodeWkstm32n657xx_Vectors.o
HPDMA1_Channel9_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C1_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C1_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C2_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C2_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C3_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C3_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C4_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
I2C4_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
I3C1_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
I3C1_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
I3C2_ER_IRQHandler4CodeWkstm32n657xx_Vectors.o
I3C2_EV_IRQHandler4CodeWkstm32n657xx_Vectors.o
IAC_IRQHandler4CodeWkstm32n657xx_Vectors.o
ICACHE_IRQHandler4CodeWkstm32n657xx_Vectors.o
IWDG_IRQHandler4CodeWkstm32n657xx_Vectors.o
JPEG_IRQHandler4CodeWkstm32n657xx_Vectors.o
LOCKUP_IRQHandler4CodeWkstm32n657xx_Vectors.o
LPTIM1_IRQHandler4CodeWkstm32n657xx_Vectors.o
LPTIM2_IRQHandler4CodeWkstm32n657xx_Vectors.o
LPTIM3_IRQHandler4CodeWkstm32n657xx_Vectors.o
LPTIM4_IRQHandler4CodeWkstm32n657xx_Vectors.o
LPTIM5_IRQHandler4CodeWkstm32n657xx_Vectors.o
LPUART1_IRQHandler4CodeWkstm32n657xx_Vectors.o
LTDC_LO_ERR_IRQHandler4CodeWkstm32n657xx_Vectors.o
LTDC_LO_IRQHandler4CodeWkstm32n657xx_Vectors.o
LTDC_UP_ERR_IRQHandler4CodeWkstm32n657xx_Vectors.o
LTDC_UP_IRQHandler4CodeWkstm32n657xx_Vectors.o
MCE1_IRQHandler4CodeWkstm32n657xx_Vectors.o
MCE2_IRQHandler4CodeWkstm32n657xx_Vectors.o
MCE3_IRQHandler4CodeWkstm32n657xx_Vectors.o
MCE4_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDF1_FLT0_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDF1_FLT1_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDF1_FLT2_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDF1_FLT3_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDF1_FLT4_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDF1_FLT5_IRQHandler4CodeWkstm32n657xx_Vectors.o
MDIOS_IRQHandler4CodeWkstm32n657xx_Vectors.o
NPU0_IRQHandler4CodeWkstm32n657xx_Vectors.o
NPU1_IRQHandler4CodeWkstm32n657xx_Vectors.o
NPU2_IRQHandler4CodeWkstm32n657xx_Vectors.o
NPU3_IRQHandler4CodeWkstm32n657xx_Vectors.o
PAHB_ERR_IRQHandler4CodeWkstm32n657xx_Vectors.o
PKA_IRQHandler4CodeWkstm32n657xx_Vectors.o
PVD_PVM_IRQHandler4CodeWkstm32n657xx_Vectors.o
RCC_IRQHandler4CodeWkstm32n657xx_Vectors.o
RCC_S_IRQHandler4CodeWkstm32n657xx_Vectors.o
RIFSC_TAMPER_IRQHandler4CodeWkstm32n657xx_Vectors.o
RNG_IRQHandler4CodeWkstm32n657xx_Vectors.o
RTC_IRQHandler4CodeWkstm32n657xx_Vectors.o
RTC_S_IRQHandler4CodeWkstm32n657xx_Vectors.o
Reset_Handler4CodeGbSTM32N6xx_Startup.o
SAES_IRQHandler4CodeWkstm32n657xx_Vectors.o
SAI1_A_IRQHandler4CodeWkstm32n657xx_Vectors.o
SAI1_B_IRQHandler4CodeWkstm32n657xx_Vectors.o
SAI2_A_IRQHandler4CodeWkstm32n657xx_Vectors.o
SAI2_B_IRQHandler4CodeWkstm32n657xx_Vectors.o
SDMMC1_IRQHandler4CodeWkstm32n657xx_Vectors.o
SDMMC2_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPDIFRX_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPI1_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPI2_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPI3_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPI4_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPI5_IRQHandler4CodeWkstm32n657xx_Vectors.o
SPI6_IRQHandler4CodeWkstm32n657xx_Vectors.o
TAMP_IRQHandler4CodeWkstm32n657xx_Vectors.o
TCM_ECC_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM10_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM11_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM12_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM13_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM14_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM15_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM16_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM17_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM18_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM1_BRK_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM1_CC_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM1_TRG_CCU_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM1_UP_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM2_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM3_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM4_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM5_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM6_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM7_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM8_BRK_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM8_CC_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM8_TRG_CCU_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM8_UP_IRQHandler4CodeWkstm32n657xx_Vectors.o
TIM9_IRQHandler4CodeWkstm32n657xx_Vectors.o
UART4_IRQHandler4CodeWkstm32n657xx_Vectors.o
UART5_IRQHandler4CodeWkstm32n657xx_Vectors.o
UART7_IRQHandler4CodeWkstm32n657xx_Vectors.o
UART8_IRQHandler4CodeWkstm32n657xx_Vectors.o
UART9_IRQHandler4CodeWkstm32n657xx_Vectors.o
UCPD1_IRQHandler4CodeWkstm32n657xx_Vectors.o
USART10_IRQHandler4CodeWkstm32n657xx_Vectors.o
USART1_IRQHandler4CodeWkstm32n657xx_Vectors.o
USART2_IRQHandler4CodeWkstm32n657xx_Vectors.o
USART3_IRQHandler4CodeWkstm32n657xx_Vectors.o
USART6_IRQHandler4CodeWkstm32n657xx_Vectors.o
USB1_OTG_HS_IRQHandler4CodeWkstm32n657xx_Vectors.o
USB2_OTG_HS_IRQHandler4CodeWkstm32n657xx_Vectors.o
VENC_IRQHandler4CodeWkstm32n657xx_Vectors.o
WAKEUP_PIN_IRQHandler4CodeWkstm32n657xx_Vectors.o
WWDG_IRQHandler4CodeWkstm32n657xx_Vectors.o
XSPI1_IRQHandler4CodeWkstm32n657xx_Vectors.o
XSPI2_IRQHandler4CodeWkstm32n657xx_Vectors.o
XSPI3_IRQHandler4CodeWkstm32n657xx_Vectors.o
__SEGGER_init_done4CodeGbSEGGER_THUMB_Startup.o
__aeabi_memclr44CodeWkstrasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a)
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Regions by name

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameRangeSize
AHB_RAM138000000-38003FFF16 384
AHB_RAM238004000-38007FFF16 384
AXI_RAM134064000-340FFFFF638 976
AXI_RAM234180400-341FFFFF523 264
AXI_RAM334200000-3426FFFF458 752
AXI_RAM434270000-342DFFFF458 752
AXI_RAM5342E0000-3434FFFF458 752
AXI_RAM634350000-343BFFFF458 752
AXI_RAM7343C0000-343FFFFF262 144
AXI_RAM834400000-3441FFFF131 072
BKP_RAM3C000000-3C001FFF8 192
DTCM_RAM30000000-3001FFFF131 072
FLEX_RAM34000000-34063FFF409 600
ITCM_RAM10000000-1000FFFF65 536
RAM34180400-341FFFFF523 264
+

Analysis

+ +AXI_RAM2: + Identical to region RAM + +RAM: + Identical to region AXI_RAM2 +

BLOCK LIST

+

Blocks by name

+ + + + + + + + + + + + + + + + + + + + +
NameRangeSizeOrdering
ctors34182098-3418209B4Auto
stack341FE000-341FFFFF8 192Auto
+

Blocks by address

+ + + + + + + + + + + + + + + + + + + + +
RangeSizeNameOrdering
34182098-3418209B4ctorsAuto
341FE000-341FFFFF8 192stackAuto
+

STACK SIZES

+

Functions by stack size

+ + + + + + + +
Function nameStackObject File
+

Functions without stack size information

+ + HAL_RCC_OscConfig + HAL_RCC_ClockConfig + HAL_GPIO_Init + RCC_PLL_IsNewConfig + RCC_PLL_Config + RCC_IC_CheckPLLSources + RCCEx_GetPLLSourceFreq + main + SystemCoreClockUpdate + NMI_Handler + HardFault_Handler + MemManage_Handler + BusFault_Handler + UsageFault_Handler + SVC_Handler + DebugMon_Handler + PendSV_Handler + SysTick_Handler + SystemInit + _start + __SEGGER_init_done + __startup_complete + exit + PVD_PVM_IRQHandler + DTS_IRQHandler + RCC_IRQHandler + LOCKUP_IRQHandler + CACHE_ECC_IRQHandler + TCM_ECC_IRQHandler + BCK_ECC_IRQHandler + FPU_IRQHandler + RTC_S_IRQHandler + TAMP_IRQHandler + RIFSC_TAMPER_IRQHandler + IAC_IRQHandler + RCC_S_IRQHandler + RTC_IRQHandler + IWDG_IRQHandler + WWDG_IRQHandler + EXTI0_IRQHandler + EXTI1_IRQHandler + EXTI2_IRQHandler + EXTI3_IRQHandler + EXTI4_IRQHandler + EXTI5_IRQHandler + EXTI6_IRQHandler + EXTI7_IRQHandler + EXTI8_IRQHandler + EXTI9_IRQHandler + EXTI10_IRQHandler + EXTI11_IRQHandler + EXTI12_IRQHandler + EXTI13_IRQHandler + EXTI14_IRQHandler + EXTI15_IRQHandler + SAES_IRQHandler + CRYP_IRQHandler + PKA_IRQHandler + HASH_IRQHandler + RNG_IRQHandler + MCE1_IRQHandler + MCE2_IRQHandler + MCE3_IRQHandler + MCE4_IRQHandler + ADC1_2_IRQHandler + CSI_IRQHandler + DCMIPP_IRQHandler + PAHB_ERR_IRQHandler + NPU0_IRQHandler + NPU1_IRQHandler + NPU2_IRQHandler + NPU3_IRQHandler + CACHEAXI_IRQHandler + LTDC_LO_IRQHandler + LTDC_LO_ERR_IRQHandler + DMA2D_IRQHandler + JPEG_IRQHandler + VENC_IRQHandler + GFXMMU_IRQHandler + GFXTIM_IRQHandler + GPU2D_IRQHandler + GPU2D_ER_IRQHandler + ICACHE_IRQHandler + HPDMA1_Channel0_IRQHandler + HPDMA1_Channel1_IRQHandler + HPDMA1_Channel2_IRQHandler + HPDMA1_Channel3_IRQHandler + HPDMA1_Channel4_IRQHandler + HPDMA1_Channel5_IRQHandler + HPDMA1_Channel6_IRQHandler + HPDMA1_Channel7_IRQHandler + HPDMA1_Channel8_IRQHandler + HPDMA1_Channel9_IRQHandler + HPDMA1_Channel10_IRQHandler + HPDMA1_Channel11_IRQHandler + HPDMA1_Channel12_IRQHandler + HPDMA1_Channel13_IRQHandler + HPDMA1_Channel14_IRQHandler + HPDMA1_Channel15_IRQHandler + GPDMA1_Channel0_IRQHandler + GPDMA1_Channel1_IRQHandler + GPDMA1_Channel2_IRQHandler + GPDMA1_Channel3_IRQHandler + GPDMA1_Channel4_IRQHandler + GPDMA1_Channel5_IRQHandler + GPDMA1_Channel6_IRQHandler + GPDMA1_Channel7_IRQHandler + GPDMA1_Channel8_IRQHandler + GPDMA1_Channel9_IRQHandler + GPDMA1_Channel10_IRQHandler + GPDMA1_Channel11_IRQHandler + GPDMA1_Channel12_IRQHandler + GPDMA1_Channel13_IRQHandler + GPDMA1_Channel14_IRQHandler + GPDMA1_Channel15_IRQHandler + I2C1_EV_IRQHandler + I2C1_ER_IRQHandler + I2C2_EV_IRQHandler + I2C2_ER_IRQHandler + I2C3_EV_IRQHandler + I2C3_ER_IRQHandler + I2C4_EV_IRQHandler + I2C4_ER_IRQHandler + I3C1_EV_IRQHandler + I3C1_ER_IRQHandler + I3C2_EV_IRQHandler + I3C2_ER_IRQHandler + TIM1_BRK_IRQHandler + TIM1_UP_IRQHandler + TIM1_TRG_CCU_IRQHandler + TIM1_CC_IRQHandler + TIM2_IRQHandler + TIM3_IRQHandler + TIM4_IRQHandler + TIM5_IRQHandler + TIM6_IRQHandler + TIM7_IRQHandler + TIM8_BRK_IRQHandler + TIM8_UP_IRQHandler + TIM8_TRG_CCU_IRQHandler + TIM8_CC_IRQHandler + TIM9_IRQHandler + TIM10_IRQHandler + TIM11_IRQHandler + TIM12_IRQHandler + TIM13_IRQHandler + TIM14_IRQHandler + TIM15_IRQHandler + TIM16_IRQHandler + TIM17_IRQHandler + TIM18_IRQHandler + LPTIM1_IRQHandler + LPTIM2_IRQHandler + LPTIM3_IRQHandler + LPTIM4_IRQHandler + LPTIM5_IRQHandler + ADF1_FLT0_IRQHandler + MDF1_FLT0_IRQHandler + MDF1_FLT1_IRQHandler + MDF1_FLT2_IRQHandler + MDF1_FLT3_IRQHandler + MDF1_FLT4_IRQHandler + MDF1_FLT5_IRQHandler + SAI1_A_IRQHandler + SAI1_B_IRQHandler + SAI2_A_IRQHandler + SAI2_B_IRQHandler + SPDIFRX_IRQHandler + SPI1_IRQHandler + SPI2_IRQHandler + SPI3_IRQHandler + SPI4_IRQHandler + SPI5_IRQHandler + SPI6_IRQHandler + USART1_IRQHandler + USART2_IRQHandler + USART3_IRQHandler + UART4_IRQHandler + UART5_IRQHandler + USART6_IRQHandler + UART7_IRQHandler + UART8_IRQHandler + UART9_IRQHandler + USART10_IRQHandler + LPUART1_IRQHandler + XSPI1_IRQHandler + XSPI2_IRQHandler + XSPI3_IRQHandler + FMC_IRQHandler + SDMMC1_IRQHandler + SDMMC2_IRQHandler + UCPD1_IRQHandler + USB1_OTG_HS_IRQHandler + USB2_OTG_HS_IRQHandler + ETH1_IRQHandler + FDCAN1_IT0_IRQHandler + FDCAN1_IT1_IRQHandler + FDCAN2_IT0_IRQHandler + FDCAN2_IT1_IRQHandler + FDCAN3_IT0_IRQHandler + FDCAN3_IT1_IRQHandler + FDCAN_CU_IRQHandler + MDIOS_IRQHandler + DCMI_PSSI_IRQHandler + WAKEUP_PIN_IRQHandler + CTI_INT0_IRQHandler + CTI_INT1_IRQHandler + LTDC_UP_IRQHandler + LTDC_UP_ERR_IRQHandler + reset_handler + Reset_Handler + __SEGGER_init_zero + __SEGGER_init_copy + __SEGGER_init_ctors + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset +

UNUSED INPUTS

+

Unused object files

+ +No unused object files +

ABSOLUTE LISTING

+

Section .vectors from stm32n657xx_Vectors.o, size=844, align=1024

+ +
+
_vectors:
+g_pfnVectors:
+  0x34180400:  34200000     DC.W       34200000               ; R_ARM_ABS32
+  0x34180404:  3418142D     DC.W       reset_handler
+  0x34180408:  341814C1     DC.W       NMI_Handler
+  0x3418040C:  341814C1     DC.W       NMI_Handler
+  0x34180410:  341814C1     DC.W       NMI_Handler
+  0x34180414:  341814C1     DC.W       NMI_Handler
+  0x34180418:  341814C1     DC.W       NMI_Handler
+  0x3418041C:  00           DC.B       0x00                     ; '\0'
+  0x3418041D:  00           DC.B       0x00                     ; '\0'
+  0x3418041E:  00           DC.B       0x00                     ; '\0'
+  0x3418041F:  00           DC.B       0x00                     ; '\0'
+  0x34180420:  00           DC.B       0x00                     ; '\0'
+  0x34180421:  00           DC.B       0x00                     ; '\0'
+  0x34180422:  00           DC.B       0x00                     ; '\0'
+  0x34180423:  00           DC.B       0x00                     ; '\0'
+  0x34180424:  00           DC.B       0x00                     ; '\0'
+  0x34180425:  00           DC.B       0x00                     ; '\0'
+  0x34180426:  00           DC.B       0x00                     ; '\0'
+  0x34180427:  00           DC.B       0x00                     ; '\0'
+  0x34180428:  00           DC.B       0x00                     ; '\0'
+  0x34180429:  00           DC.B       0x00                     ; '\0'
+  0x3418042A:  00           DC.B       0x00                     ; '\0'
+  0x3418042B:  00           DC.B       0x00                     ; '\0'
+  0x3418042C:  341814C5     DC.W       SVC_Handler
+  0x34180430:  341814C5     DC.W       SVC_Handler
+  0x34180434:  00           DC.B       0x00                     ; '\0'
+  0x34180435:  00           DC.B       0x00                     ; '\0'
+  0x34180436:  00           DC.B       0x00                     ; '\0'
+  0x34180437:  00           DC.B       0x00                     ; '\0'
+  0x34180438:  341814C5     DC.W       SVC_Handler
+  0x3418043C:  34180B59     DC.W       SysTick_Handler
+  0x34180440:  341814C1     DC.W       NMI_Handler
+  0x34180444:  00           DC.B       0x00                     ; '\0'
+  0x34180445:  00           DC.B       0x00                     ; '\0'
+  0x34180446:  00           DC.B       0x00                     ; '\0'
+  0x34180447:  00           DC.B       0x00                     ; '\0'
+  0x34180448:  341814C1     DC.W       NMI_Handler
+  0x3418044C:  341814C1     DC.W       NMI_Handler
+  0x34180450:  341814C1     DC.W       NMI_Handler
+  0x34180454:  341814C1     DC.W       NMI_Handler
+  0x34180458:  341814C1     DC.W       NMI_Handler
+  0x3418045C:  341814C1     DC.W       NMI_Handler
+  0x34180460:  341814C1     DC.W       NMI_Handler
+  0x34180464:  00           DC.B       0x00                     ; '\0'
+  0x34180465:  00           DC.B       0x00                     ; '\0'
+  0x34180466:  00           DC.B       0x00                     ; '\0'
+  0x34180467:  00           DC.B       0x00                     ; '\0'
+  0x34180468:  341814C1     DC.W       NMI_Handler
+  0x3418046C:  341814C1     DC.W       NMI_Handler
+  0x34180470:  341814C1     DC.W       NMI_Handler
+  0x34180474:  341814C1     DC.W       NMI_Handler
+  0x34180478:  341814C1     DC.W       NMI_Handler
+  0x3418047C:  00           DC.B       0x00                     ; '\0'
+  0x3418047D:  00           DC.B       0x00                     ; '\0'
+  0x3418047E:  00           DC.B       0x00                     ; '\0'
+  0x3418047F:  00           DC.B       0x00                     ; '\0'
+  0x34180480:  341814C1     DC.W       NMI_Handler
+  0x34180484:  00           DC.B       0x00                     ; '\0'
+  0x34180485:  00           DC.B       0x00                     ; '\0'
+  0x34180486:  00           DC.B       0x00                     ; '\0'
+  0x34180487:  00           DC.B       0x00                     ; '\0'
+  0x34180488:  341814C1     DC.W       NMI_Handler
+  0x3418048C:  341814C1     DC.W       NMI_Handler
+  0x34180490:  341814C1     DC.W       NMI_Handler
+  0x34180494:  341814C1     DC.W       NMI_Handler
+  0x34180498:  341814C1     DC.W       NMI_Handler
+  0x3418049C:  341814C1     DC.W       NMI_Handler
+  0x341804A0:  341814C1     DC.W       NMI_Handler
+  0x341804A4:  341814C1     DC.W       NMI_Handler
+  0x341804A8:  341814C1     DC.W       NMI_Handler
+  0x341804AC:  341814C1     DC.W       NMI_Handler
+  0x341804B0:  341814C1     DC.W       NMI_Handler
+  0x341804B4:  341814C1     DC.W       NMI_Handler
+  0x341804B8:  341814C1     DC.W       NMI_Handler
+  0x341804BC:  341814C1     DC.W       NMI_Handler
+  0x341804C0:  341814C1     DC.W       NMI_Handler
+  0x341804C4:  341814C1     DC.W       NMI_Handler
+  0x341804C8:  341814C1     DC.W       NMI_Handler
+  0x341804CC:  341814C1     DC.W       NMI_Handler
+  0x341804D0:  341814C1     DC.W       NMI_Handler
+  0x341804D4:  341814C1     DC.W       NMI_Handler
+  0x341804D8:  341814C1     DC.W       NMI_Handler
+  0x341804DC:  341814C1     DC.W       NMI_Handler
+  0x341804E0:  341814C1     DC.W       NMI_Handler
+  0x341804E4:  00           DC.B       0x00                     ; '\0'
+  0x341804E5:  00           DC.B       0x00                     ; '\0'
+  0x341804E6:  00           DC.B       0x00                     ; '\0'
+  0x341804E7:  00           DC.B       0x00                     ; '\0'
+  0x341804E8:  341814C1     DC.W       NMI_Handler
+  0x341804EC:  341814C1     DC.W       NMI_Handler
+  0x341804F0:  341814C1     DC.W       NMI_Handler
+  0x341804F4:  341814C1     DC.W       NMI_Handler
+  0x341804F8:  341814C1     DC.W       NMI_Handler
+  0x341804FC:  341814C1     DC.W       NMI_Handler
+  0x34180500:  341814C1     DC.W       NMI_Handler
+  0x34180504:  00           DC.B       0x00                     ; '\0'
+  0x34180505:  00           DC.B       0x00                     ; '\0'
+  0x34180506:  00           DC.B       0x00                     ; '\0'
+  0x34180507:  00           DC.B       0x00                     ; '\0'
+  0x34180508:  00           DC.B       0x00                     ; '\0'
+  0x34180509:  00           DC.B       0x00                     ; '\0'
+  0x3418050A:  00           DC.B       0x00                     ; '\0'
+  0x3418050B:  00           DC.B       0x00                     ; '\0'
+  0x3418050C:  00           DC.B       0x00                     ; '\0'
+  0x3418050D:  00           DC.B       0x00                     ; '\0'
+  0x3418050E:  00           DC.B       0x00                     ; '\0'
+  0x3418050F:  00           DC.B       0x00                     ; '\0'
+  0x34180510:  341814C1     DC.W       NMI_Handler
+  0x34180514:  341814C1     DC.W       NMI_Handler
+  0x34180518:  341814C1     DC.W       NMI_Handler
+  0x3418051C:  341814C1     DC.W       NMI_Handler
+  0x34180520:  341814C1     DC.W       NMI_Handler
+  0x34180524:  341814C1     DC.W       NMI_Handler
+  0x34180528:  341814C1     DC.W       NMI_Handler
+  0x3418052C:  341814C1     DC.W       NMI_Handler
+  0x34180530:  341814C1     DC.W       NMI_Handler
+  0x34180534:  341814C1     DC.W       NMI_Handler
+  0x34180538:  341814C1     DC.W       NMI_Handler
+  0x3418053C:  341814C1     DC.W       NMI_Handler
+  0x34180540:  341814C1     DC.W       NMI_Handler
+  0x34180544:  341814C1     DC.W       NMI_Handler
+  0x34180548:  341814C1     DC.W       NMI_Handler
+  0x3418054C:  341814C1     DC.W       NMI_Handler
+  0x34180550:  341814C1     DC.W       NMI_Handler
+  0x34180554:  341814C1     DC.W       NMI_Handler
+  0x34180558:  341814C1     DC.W       NMI_Handler
+  0x3418055C:  341814C1     DC.W       NMI_Handler
+  0x34180560:  341814C1     DC.W       NMI_Handler
+  0x34180564:  341814C1     DC.W       NMI_Handler
+  0x34180568:  341814C1     DC.W       NMI_Handler
+  0x3418056C:  341814C1     DC.W       NMI_Handler
+  0x34180570:  341814C1     DC.W       NMI_Handler
+  0x34180574:  341814C1     DC.W       NMI_Handler
+  0x34180578:  341814C1     DC.W       NMI_Handler
+  0x3418057C:  341814C1     DC.W       NMI_Handler
+  0x34180580:  341814C1     DC.W       NMI_Handler
+  0x34180584:  341814C1     DC.W       NMI_Handler
+  0x34180588:  341814C1     DC.W       NMI_Handler
+  0x3418058C:  341814C1     DC.W       NMI_Handler
+  0x34180590:  341814C1     DC.W       NMI_Handler
+  0x34180594:  341814C1     DC.W       NMI_Handler
+  0x34180598:  341814C1     DC.W       NMI_Handler
+  0x3418059C:  341814C1     DC.W       NMI_Handler
+  0x341805A0:  341814C1     DC.W       NMI_Handler
+  0x341805A4:  341814C1     DC.W       NMI_Handler
+  0x341805A8:  341814C1     DC.W       NMI_Handler
+  0x341805AC:  341814C1     DC.W       NMI_Handler
+  0x341805B0:  341814C1     DC.W       NMI_Handler
+  0x341805B4:  341814C1     DC.W       NMI_Handler
+  0x341805B8:  341814C1     DC.W       NMI_Handler
+  0x341805BC:  341814C1     DC.W       NMI_Handler
+  0x341805C0:  341814C1     DC.W       NMI_Handler
+  0x341805C4:  341814C1     DC.W       NMI_Handler
+  0x341805C8:  341814C1     DC.W       NMI_Handler
+  0x341805CC:  341814C1     DC.W       NMI_Handler
+  0x341805D0:  341814C1     DC.W       NMI_Handler
+  0x341805D4:  341814C1     DC.W       NMI_Handler
+  0x341805D8:  341814C1     DC.W       NMI_Handler
+  0x341805DC:  341814C1     DC.W       NMI_Handler
+  0x341805E0:  341814C1     DC.W       NMI_Handler
+  0x341805E4:  341814C1     DC.W       NMI_Handler
+  0x341805E8:  341814C1     DC.W       NMI_Handler
+  0x341805EC:  341814C1     DC.W       NMI_Handler
+  0x341805F0:  341814C1     DC.W       NMI_Handler
+  0x341805F4:  341814C1     DC.W       NMI_Handler
+  0x341805F8:  341814C1     DC.W       NMI_Handler
+  0x341805FC:  341814C1     DC.W       NMI_Handler
+  0x34180600:  341814C1     DC.W       NMI_Handler
+  0x34180604:  341814C1     DC.W       NMI_Handler
+  0x34180608:  341814C1     DC.W       NMI_Handler
+  0x3418060C:  341814C1     DC.W       NMI_Handler
+  0x34180610:  341814C1     DC.W       NMI_Handler
+  0x34180614:  341814C1     DC.W       NMI_Handler
+  0x34180618:  341814C1     DC.W       NMI_Handler
+  0x3418061C:  341814C1     DC.W       NMI_Handler
+  0x34180620:  341814C1     DC.W       NMI_Handler
+  0x34180624:  341814C1     DC.W       NMI_Handler
+  0x34180628:  341814C1     DC.W       NMI_Handler
+  0x3418062C:  341814C1     DC.W       NMI_Handler
+  0x34180630:  341814C1     DC.W       NMI_Handler
+  0x34180634:  341814C1     DC.W       NMI_Handler
+  0x34180638:  341814C1     DC.W       NMI_Handler
+  0x3418063C:  341814C1     DC.W       NMI_Handler
+  0x34180640:  341814C1     DC.W       NMI_Handler
+  0x34180644:  341814C1     DC.W       NMI_Handler
+  0x34180648:  341814C1     DC.W       NMI_Handler
+  0x3418064C:  341814C1     DC.W       NMI_Handler
+  0x34180650:  341814C1     DC.W       NMI_Handler
+  0x34180654:  341814C1     DC.W       NMI_Handler
+  0x34180658:  341814C1     DC.W       NMI_Handler
+  0x3418065C:  341814C1     DC.W       NMI_Handler
+  0x34180660:  341814C1     DC.W       NMI_Handler
+  0x34180664:  341814C1     DC.W       NMI_Handler
+  0x34180668:  341814C1     DC.W       NMI_Handler
+  0x3418066C:  341814C1     DC.W       NMI_Handler
+  0x34180670:  341814C1     DC.W       NMI_Handler
+  0x34180674:  341814C1     DC.W       NMI_Handler
+  0x34180678:  341814C1     DC.W       NMI_Handler
+  0x3418067C:  341814C1     DC.W       NMI_Handler
+  0x34180680:  341814C1     DC.W       NMI_Handler
+  0x34180684:  341814C1     DC.W       NMI_Handler
+  0x34180688:  341814C1     DC.W       NMI_Handler
+  0x3418068C:  341814C1     DC.W       NMI_Handler
+  0x34180690:  341814C1     DC.W       NMI_Handler
+  0x34180694:  341814C1     DC.W       NMI_Handler
+  0x34180698:  341814C1     DC.W       NMI_Handler
+  0x3418069C:  341814C1     DC.W       NMI_Handler
+  0x341806A0:  341814C1     DC.W       NMI_Handler
+  0x341806A4:  341814C1     DC.W       NMI_Handler
+  0x341806A8:  341814C1     DC.W       NMI_Handler
+  0x341806AC:  341814C1     DC.W       NMI_Handler
+  0x341806B0:  341814C1     DC.W       NMI_Handler
+  0x341806B4:  341814C1     DC.W       NMI_Handler
+  0x341806B8:  341814C1     DC.W       NMI_Handler
+  0x341806BC:  341814C1     DC.W       NMI_Handler
+  0x341806C0:  341814C1     DC.W       NMI_Handler
+  0x341806C4:  341814C1     DC.W       NMI_Handler
+  0x341806C8:  341814C1     DC.W       NMI_Handler
+  0x341806CC:  341814C1     DC.W       NMI_Handler
+  0x341806D0:  341814C1     DC.W       NMI_Handler
+  0x341806D4:  341814C1     DC.W       NMI_Handler
+  0x341806D8:  341814C1     DC.W       NMI_Handler
+  0x341806DC:  341814C1     DC.W       NMI_Handler
+  0x341806E0:  341814C1     DC.W       NMI_Handler
+  0x341806E4:  341814C1     DC.W       NMI_Handler
+  0x341806E8:  341814C1     DC.W       NMI_Handler
+  0x341806EC:  341814C1     DC.W       NMI_Handler
+  0x341806F0:  341814C1     DC.W       NMI_Handler
+  0x341806F4:  341814C1     DC.W       NMI_Handler
+  0x341806F8:  341814C1     DC.W       NMI_Handler
+  0x341806FC:  341814C1     DC.W       NMI_Handler
+  0x34180700:  341814C1     DC.W       NMI_Handler
+  0x34180704:  341814C1     DC.W       NMI_Handler
+  0x34180708:  341814C1     DC.W       NMI_Handler
+  0x3418070C:  341814C1     DC.W       NMI_Handler
+  0x34180710:  341814C1     DC.W       NMI_Handler
+  0x34180714:  341814C1     DC.W       NMI_Handler
+  0x34180718:  341814C1     DC.W       NMI_Handler
+  0x3418071C:  341814C1     DC.W       NMI_Handler
+  0x34180720:  341814C1     DC.W       NMI_Handler
+  0x34180724:  341814C1     DC.W       NMI_Handler
+  0x34180728:  341814C1     DC.W       NMI_Handler
+  0x3418072C:  341814C1     DC.W       NMI_Handler
+  0x34180730:  341814C1     DC.W       NMI_Handler
+  0x34180734:  341814C1     DC.W       NMI_Handler
+  0x34180738:  341814C1     DC.W       NMI_Handler
+  0x3418073C:  341814C1     DC.W       NMI_Handler
+  0x34180740:  00           DC.B       0x00                     ; '\0'
+  0x34180741:  00           DC.B       0x00                     ; '\0'
+  0x34180742:  00           DC.B       0x00                     ; '\0'
+  0x34180743:  00           DC.B       0x00                     ; '\0'
+  0x34180744:  341814C1     DC.W       NMI_Handler
+  0x34180748:  341814C1     DC.W       NMI_Handler
+
+

Section .text.main from blto2_FSBL_lto.o, size=1036, align=4

+ +
+
main:
+_vectors_end:
+  0x3418074C:  B0B6         SUB        SP, SP, #216
+  0x3418074E:  F64E 5A0C    MOVW       R10, #0xED0C
+  0x34180752:  F64F 01FF    MOVW       R1, #0xF8FF
+  0x34180756:  F2CE 0A00    MOVT       R10, #0xE000
+  0x3418075A:  F644 0520    MOVW       R5, #0x4820
+  0x3418075E:  F8DA 0000    LDR.W      R0, [R10]
+  0x34180762:  F2C5 6502    MOVT       R5, #0x5602
+  0x34180766:  4008         ANDS       R0, R1
+  0x34180768:  F240 3100    MOVW       R1, #0x0300
+  0x3418076C:  F2C0 51FA    MOVT       R1, #0x05FA
+  0x34180770:  4308         ORRS       R0, R1
+  0x34180772:  F8CA 0000    STR.W      R0, [R10]
+  0x34180776:  F000 F9F7    BL         SystemCoreClockUpdate    ; 0x34180B68
+  0x3418077A:  F242 00A4    MOVW       R0, #0x20A4              ; 0x341820A4 = SystemCoreClock
+  0x3418077E:  F644 51D3    MOVW       R1, #0x4DD3
+  0x34180782:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341820A4 = SystemCoreClock
+  0x34180786:  6800         LDR        R0, [R0]
+  0x34180788:  F2C1 0162    MOVT       R1, #0x1062
+  0x3418078C:  FBA0 0101    UMULL      R0, R1, R0, R1
+  0x34180790:  F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+  0x34180794:  EB00 1191    ADD.W      R1, R0, R1, LSR #6
+  0x34180798:  0E0A         LSRS       R2, R1, #24
+  0x3418079A:  D124         BNE        46L1                      ; 0x341807E6
+  0x3418079C:  F6AA 42FC    SUBW       R2, R10, #0x0CFC
+  0x341807A0:  6051         STR        R1, [R2, #4]
+  0x341807A2:  21F0         MOVS       R1, #240
+  0x341807A4:  F88A 1017    STRB.W     R1, [R10, #23]
+  0x341807A8:  2100         MOVS       R1, #0
+  0x341807AA:  6091         STR        R1, [R2, #8]
+  0x341807AC:  2107         MOVS       R1, #7
+  0x341807AE:  6011         STR        R1, [R2]
+  0x341807B0:  F8DA 1000    LDR.W      R1, [R10]
+  0x341807B4:  F3C1 2102    UBFX       R1, R1, #8, #3
+  0x341807B8:  F081 0207    EOR        R2, R1, #7
+  0x341807BC:  2A04         CMP        R2, #4
+  0x341807BE:  BF28         IT         CS
+  0x341807C0:  2204         MOVCS      R2, #4
+  0x341807C2:  4090         LSLS       R0, R2
+  0x341807C4:  43C0         MVNS       R0, R0
+  0x341807C6:  3903         SUBS       R1, #3
+  0x341807C8:  BF28         IT         CS
+  0x341807CA:  4088         LSLCS      R0, R1
+  0x341807CC:  2101         MOVS       R1, #1
+  0x341807CE:  0100         LSLS       R0, R0, #4
+  0x341807D0:  F88A 0017    STRB.W     R0, [R10, #23]
+  0x341807D4:  F242 00A0    MOVW       R0, #0x20A0              ; 0x341820A0 = uwTickPrio
+  0x341807D8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341820A0 = uwTickPrio
+  0x341807DC:  7001         STRB       R1, [R0]
+  0x341807DE:  69E8         LDR        R0, [R5, #28]
+  0x341807E0:  F440 7000    ORR        R0, R0, #0x0200
+  0x341807E4:  61E8         STR        R0, [R5, #28]
+
.L1:
+  0x341807E6:  A811         ADD        R0, SP, #68
+  0x341807E8:  2194         MOVS       R1, #148
+  0x341807EA:  F000 FE35    BL         __aeabi_memclr           ; 0x34181458
+  0x341807EE:  4668         MOV        R0, SP
+  0x341807F0:  2140         MOVS       R1, #64
+  0x341807F2:  F000 FE31    BL         __aeabi_memclr           ; 0x34181458
+  0x341807F6:  F855 0C20    LDR        R0, [R5, #-32]
+  0x341807FA:  F242 0B9C    MOVW       R11, #0x209C             ; 0x3418209C = uwTick
+  0x341807FE:  F2C3 4B18    MOVT       R11, #0x3418             ; 0x3418209C = uwTick
+  0x34180802:  F020 0004    BIC        R0, R0, #4
+  0x34180806:  F845 0C20    STR        R0, [R5, #-32]
+  0x3418080A:  F8DB 0000    LDR.W      R0, [R11]
+  0x3418080E:  BF00         NOP
+
.L2:
+  0x34180810:  6829         LDR        R1, [R5]
+  0x34180812:  0389         LSLS       R1, R1, #14
+  0x34180814:  D407         BMI        46L4                      ; 0x34180826
+  0x34180816:  F8DB 1000    LDR.W      R1, [R11]
+  0x3418081A:  1A09         SUBS       R1, R1, R0
+  0x3418081C:  F5B1 7F7A    CMP.W      R1, #0x03E8
+  0x34180820:  D9F6         BLS        46L2                      ; 0x34180810
+  0x34180822:  B672         CPSID      i
+
.L3:
+  0x34180824:  E7FE         B          46L3                      ; 0x34180824
+
.L4:
+  0x34180826:  6828         LDR        R0, [R5]
+  0x34180828:  F040 0001    ORR        R0, R0, #1
+  0x3418082C:  6028         STR        R0, [R5]
+  0x3418082E:  F8DB 0000    LDR.W      R0, [R11]
+  0x34180832:  BF00         NOP
+
.L5:
+  0x34180834:  6829         LDR        R1, [R5]
+  0x34180836:  0789         LSLS       R1, R1, #30
+  0x34180838:  D407         BMI        46L7                      ; 0x3418084A
+  0x3418083A:  F8DB 1000    LDR.W      R1, [R11]
+  0x3418083E:  1A09         SUBS       R1, R1, R0
+  0x34180840:  F5B1 7F7A    CMP.W      R1, #0x03E8
+  0x34180844:  D9F6         BLS        46L5                      ; 0x34180834
+  0x34180846:  B672         CPSID      i
+
.L6:
+  0x34180848:  E7FE         B          46L6                      ; 0x34180848
+
.L7:
+  0x3418084A:  2002         MOVS       R0, #2
+  0x3418084C:  9010         STR        R0, [SP, #64]
+  0x3418084E:  2008         MOVS       R0, #8
+  0x34180850:  9013         STR        R0, [SP, #76]
+  0x34180852:  2000         MOVS       R0, #0
+  0x34180854:  E9CD 0014    STRD       R0, R0, [SP, #80]
+  0x34180858:  901A         STR        R0, [SP, #104]
+  0x3418085A:  9021         STR        R0, [SP, #132]
+  0x3418085C:  9028         STR        R0, [SP, #160]
+  0x3418085E:  902F         STR        R0, [SP, #188]
+  0x34180860:  A810         ADD        R0, SP, #64
+  0x34180862:  F000 FF9B    BL         HAL_RCC_OscConfig        ; 0x3418179C
+  0x34180866:  B110         CBZ        R0, .L9                  ; 0x3418086E
+  0x34180868:  B672         CPSID      i
+  0x3418086A:  BF00         NOP
+
.L8:
+  0x3418086C:  E7FE         B          46L8                      ; 0x3418086C
+
.L9:
+  0x3418086E:  207F         MOVS       R0, #127
+  0x34180870:  F248 265C    MOVW       R6, #0x825C
+  0x34180874:  9000         STR        R0, [SP, #0]
+  0x34180876:  F64F 50C4    MOVW       R0, #0xFDC4
+  0x3418087A:  F2C5 6602    MOVT       R6, #0x5602
+  0x3418087E:  F44F 3140    MOV.W      R1, #0x030000
+  0x34180882:  F6CF 70FF    MOVT       R0, #0xFFFF
+  0x34180886:  5830         LDR        R0, [R6, R0]
+  0x34180888:  EA01 1110    AND.W      R1, R1, R0, LSR #4
+  0x3418088C:  9101         STR        R1, [SP, #4]
+  0x3418088E:  F5B1 3F40    CMP.W      R1, #0x030000
+  0x34180892:  F04F 7140    MOV.W      R1, #0x03000000
+  0x34180896:  EA01 1010    AND.W      R0, R1, R0, LSR #4
+  0x3418089A:  F64F 51C8    MOVW       R1, #0xFDC8
+  0x3418089E:  9002         STR        R0, [SP, #8]
+  0x341808A0:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x341808A4:  5871         LDR        R1, [R6, R1]
+  0x341808A6:  F401 02E0    AND        R2, R1, #0x700000
+  0x341808AA:  9203         STR        R2, [SP, #12]
+  0x341808AC:  F001 0207    AND        R2, R1, #7
+  0x341808B0:  9204         STR        R2, [SP, #16]
+  0x341808B2:  F001 0270    AND        R2, R1, #112
+  0x341808B6:  9205         STR        R2, [SP, #20]
+  0x341808B8:  F401 42E0    AND        R2, R1, #0x7000
+  0x341808BC:  F401 21E0    AND        R1, R1, #0x070000
+  0x341808C0:  E9CD 2106    STRD       R2, R1, [SP, #24]
+  0x341808C4:  F64F 6168    MOVW       R1, #0xFE68
+  0x341808C8:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x341808CC:  5871         LDR        R1, [R6, R1]
+  0x341808CE:  F001 5240    AND        R2, R1, #0x30000000
+  0x341808D2:  9208         STR        R2, [SP, #32]
+  0x341808D4:  F04F 0201    MOV.W      R2, #1
+  0x341808D8:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x341808DC:  9109         STR        R1, [SP, #36]
+  0x341808DE:  F64F 616C    MOVW       R1, #0xFE6C
+  0x341808E2:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x341808E6:  5871         LDR        R1, [R6, R1]
+  0x341808E8:  F001 5340    AND        R3, R1, #0x30000000
+  0x341808EC:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x341808F0:  E9CD 310A    STRD       R3, R1, [SP, #40]
+  0x341808F4:  F64F 617C    MOVW       R1, #0xFE7C
+  0x341808F8:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x341808FC:  5871         LDR        R1, [R6, R1]
+  0x341808FE:  F001 5340    AND        R3, R1, #0x30000000
+  0x34180902:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x34180906:  E9CD 310C    STRD       R3, R1, [SP, #48]
+  0x3418090A:  F64F 6190    MOVW       R1, #0xFE90
+  0x3418090E:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x34180912:  5871         LDR        R1, [R6, R1]
+  0x34180914:  FA52 F2A1    UXTAB      R2, R2, R1, ROR #16
+  0x34180918:  F001 5140    AND        R1, R1, #0x30000000
+  0x3418091C:  E9CD 120E    STRD       R1, R2, [SP, #56]
+  0x34180920:  BF18         IT         NE
+  0x34180922:  F1B0 7F40    CMPNE.W    R0, #0x03000000
+  0x34180926:  D10A         BNE        46L11                     ; 0x3418093E
+  0x34180928:  2003         MOVS       R0, #3
+  0x3418092A:  9000         STR        R0, [SP, #0]
+  0x3418092C:  2000         MOVS       R0, #0
+  0x3418092E:  E9CD 0001    STRD       R0, R0, [SP, #4]
+  0x34180932:  4668         MOV        R0, SP
+  0x34180934:  F000 F9E0    BL         HAL_RCC_ClockConfig      ; 0x34180CF8
+  0x34180938:  B108         CBZ        R0, .L11                 ; 0x3418093E
+  0x3418093A:  B672         CPSID      i
+
.L10:
+  0x3418093C:  E7FE         B          46L10                     ; 0x3418093C
+
.L11:
+  0x3418093E:  2500         MOVS       R5, #0
+  0x34180940:  204B         MOVS       R0, #75
+  0x34180942:  E9CD 501D    STRD       R5, R0, [SP, #116]
+  0x34180946:  2001         MOVS       R0, #1
+  0x34180948:  F04F 0902    MOV.W      R9, #2
+  0x3418094C:  F04F 0804    MOV.W      R8, #4
+  0x34180950:  9510         STR        R5, [SP, #64]
+  0x34180952:  E9CD 001F    STRD       R0, R0, [SP, #124]
+  0x34180956:  A810         ADD        R0, SP, #64
+  0x34180958:  F8CD 8070    STR.W      R8, [SP, #112]
+  0x3418095C:  E9CD 951A    STRD       R9, R5, [SP, #104]
+  0x34180960:  9521         STR        R5, [SP, #132]
+  0x34180962:  9528         STR        R5, [SP, #160]
+  0x34180964:  952F         STR        R5, [SP, #188]
+  0x34180966:  F000 FF19    BL         HAL_RCC_OscConfig        ; 0x3418179C
+  0x3418096A:  B110         CBZ        R0, .L13                 ; 0x34180972
+  0x3418096C:  B672         CPSID      i
+  0x3418096E:  BF00         NOP
+
.L12:
+  0x34180970:  E7FE         B          46L12                     ; 0x34180970
+
.L13:
+  0x34180972:  207F         MOVS       R0, #127
+  0x34180974:  2403         MOVS       R4, #3
+  0x34180976:  9000         STR        R0, [SP, #0]
+  0x34180978:  F44F 3040    MOV.W      R0, #0x030000
+  0x3418097C:  9001         STR        R0, [SP, #4]
+  0x3418097E:  F04F 7040    MOV.W      R0, #0x03000000
+  0x34180982:  9002         STR        R0, [SP, #8]
+  0x34180984:  F44F 1080    MOV.W      R0, #0x100000
+  0x34180988:  E9CD 0503    STRD       R0, R5, [SP, #12]
+  0x3418098C:  A80B         ADD        R0, SP, #44
+  0x3418098E:  E880 0130    STM.W      R0, {R4-R5, R8}
+  0x34180992:  4668         MOV        R0, SP
+  0x34180994:  E9CD 5505    STRD       R5, R5, [SP, #20]
+  0x34180998:  E9CD 5507    STRD       R5, R5, [SP, #28]
+  0x3418099C:  E9CD 9509    STRD       R9, R5, [SP, #36]
+  0x341809A0:  E9CD 540E    STRD       R5, R4, [SP, #56]
+  0x341809A4:  F000 F9A8    BL         HAL_RCC_ClockConfig      ; 0x34180CF8
+  0x341809A8:  B108         CBZ        R0, .L15                 ; 0x341809AE
+  0x341809AA:  B672         CPSID      i
+
.L14:
+  0x341809AC:  E7FE         B          46L14                     ; 0x341809AC
+
.L15:
+  0x341809AE:  2700         MOVS       R7, #0
+  0x341809B0:  F506 6000    ADD.W      R0, R6, #0x0800
+  0x341809B4:  F44F 3180    MOV.W      R1, #0x010000
+  0x341809B8:  F641 0528    MOVW       R5, #0x1828
+  0x341809BC:  E9CD 7713    STRD       R7, R7, [SP, #76]
+  0x341809C0:  6001         STR        R1, [R0]
+  0x341809C2:  6831         LDR        R1, [R6]
+  0x341809C4:  F2C5 6502    MOVT       R5, #0x5602
+  0x341809C8:  9100         STR        R1, [SP, #0]
+  0x341809CA:  9900         LDR        R1, [SP, #0]
+  0x341809CC:  F8C0 8000    STR.W      R8, [R0]
+  0x341809D0:  F04F 0801    MOV.W      R8, #1
+  0x341809D4:  6831         LDR        R1, [R6]
+  0x341809D6:  9100         STR        R1, [SP, #0]
+  0x341809D8:  9900         LDR        R1, [SP, #0]
+  0x341809DA:  2110         MOVS       R1, #16
+  0x341809DC:  6001         STR        R1, [R0]
+  0x341809DE:  6831         LDR        R1, [R6]
+  0x341809E0:  9100         STR        R1, [SP, #0]
+  0x341809E2:  9900         LDR        R1, [SP, #0]
+  0x341809E4:  2108         MOVS       R1, #8
+  0x341809E6:  6001         STR        R1, [R0]
+  0x341809E8:  6831         LDR        R1, [R6]
+  0x341809EA:  9100         STR        R1, [SP, #0]
+  0x341809EC:  9900         LDR        R1, [SP, #0]
+  0x341809EE:  2180         MOVS       R1, #128
+  0x341809F0:  6001         STR        R1, [R0]
+  0x341809F2:  6831         LDR        R1, [R6]
+  0x341809F4:  9100         STR        R1, [SP, #0]
+  0x341809F6:  9900         LDR        R1, [SP, #0]
+  0x341809F8:  F8C0 9000    STR.W      R9, [R0]
+  0x341809FC:  6831         LDR        R1, [R6]
+  0x341809FE:  9100         STR        R1, [SP, #0]
+  0x34180A00:  9900         LDR        R1, [SP, #0]
+  0x34180A02:  F44F 4100    MOV.W      R1, #0x8000
+  0x34180A06:  6001         STR        R1, [R0]
+  0x34180A08:  6831         LDR        R1, [R6]
+  0x34180A0A:  9100         STR        R1, [SP, #0]
+  0x34180A0C:  9900         LDR        R1, [SP, #0]
+  0x34180A0E:  F44F 4180    MOV.W      R1, #0x4000
+  0x34180A12:  6001         STR        R1, [R0]
+  0x34180A14:  6831         LDR        R1, [R6]
+  0x34180A16:  9100         STR        R1, [SP, #0]
+  0x34180A18:  9900         LDR        R1, [SP, #0]
+  0x34180A1A:  2140         MOVS       R1, #64
+  0x34180A1C:  6001         STR        R1, [R0]
+  0x34180A1E:  6831         LDR        R1, [R6]
+  0x34180A20:  9100         STR        R1, [SP, #0]
+  0x34180A22:  9900         LDR        R1, [SP, #0]
+  0x34180A24:  2120         MOVS       R1, #32
+  0x34180A26:  6001         STR        R1, [R0]
+  0x34180A28:  6831         LDR        R1, [R6]
+  0x34180A2A:  9100         STR        R1, [SP, #0]
+  0x34180A2C:  9900         LDR        R1, [SP, #0]
+  0x34180A2E:  F44F 5100    MOV.W      R1, #0x2000
+  0x34180A32:  6001         STR        R1, [R0]
+  0x34180A34:  6831         LDR        R1, [R6]
+  0x34180A36:  9100         STR        R1, [SP, #0]
+  0x34180A38:  9900         LDR        R1, [SP, #0]
+  0x34180A3A:  F8C0 8000    STR.W      R8, [R0]
+  0x34180A3E:  A910         ADD        R1, SP, #64
+  0x34180A40:  6830         LDR        R0, [R6]
+  0x34180A42:  9000         STR        R0, [SP, #0]
+  0x34180A44:  9800         LDR        R0, [SP, #0]
+  0x34180A46:  20FF         MOVS       R0, #255
+  0x34180A48:  F8C5 8000    STR.W      R8, [R5]
+  0x34180A4C:  C191         STM        R1!, {R0, R4, R7}
+  0x34180A4E:  A910         ADD        R1, SP, #64
+  0x34180A50:  F244 0000    MOVW       R0, #0x4000
+  0x34180A54:  F2C5 6002    MOVT       R0, #0x5602
+  0x34180A58:  F000 FDCE    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180A5C:  F643 70FF    MOVW       R0, #0x3FFF
+  0x34180A60:  A910         ADD        R1, SP, #64
+  0x34180A62:  F1A5 0928    SUB.W      R9, R5, #40
+  0x34180A66:  C191         STM        R1!, {R0, R4, R7}
+  0x34180A68:  F5A9 5080    SUB.W      R0, R9, #0x1000
+  0x34180A6C:  A910         ADD        R1, SP, #64
+  0x34180A6E:  F000 FDC3    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180A72:  F64F 76FF    MOVW       R6, #0xFFFF
+  0x34180A76:  F5A9 6000    SUB.W      R0, R9, #0x0800
+  0x34180A7A:  A910         ADD        R1, SP, #64
+  0x34180A7C:  9712         STR        R7, [SP, #72]
+  0x34180A7E:  E9CD 6410    STRD       R6, R4, [SP, #64]
+  0x34180A82:  F000 FDB9    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180A86:  F5A9 6040    SUB.W      R0, R9, #0x0C00
+  0x34180A8A:  A910         ADD        R1, SP, #64
+  0x34180A8C:  E9CD 6410    STRD       R6, R4, [SP, #64]
+  0x34180A90:  9712         STR        R7, [SP, #72]
+  0x34180A92:  F000 FDB1    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180A96:  F44F 707F    MOV.W      R0, #0x03FC
+  0x34180A9A:  A910         ADD        R1, SP, #64
+  0x34180A9C:  C191         STM        R1!, {R0, R4, R7}
+  0x34180A9E:  F505 7076    ADD.W      R0, R5, #0x03D8
+  0x34180AA2:  A910         ADD        R1, SP, #64
+  0x34180AA4:  F000 FDA8    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180AA8:  F5A9 50A0    SUB.W      R0, R9, #0x1400
+  0x34180AAC:  A910         ADD        R1, SP, #64
+  0x34180AAE:  E9CD 6410    STRD       R6, R4, [SP, #64]
+  0x34180AB2:  9712         STR        R7, [SP, #72]
+  0x34180AB4:  F000 FDA0    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180AB8:  E9CD 6410    STRD       R6, R4, [SP, #64]
+  0x34180ABC:  F509 56E0    ADD.W      R6, R9, #0x1C00
+  0x34180AC0:  A910         ADD        R1, SP, #64
+  0x34180AC2:  F506 6000    ADD.W      R0, R6, #0x0800
+  0x34180AC6:  9712         STR        R7, [SP, #72]
+  0x34180AC8:  F000 FD96    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180ACC:  203F         MOVS       R0, #63
+  0x34180ACE:  A910         ADD        R1, SP, #64
+  0x34180AD0:  C191         STM        R1!, {R0, R4, R7}
+  0x34180AD2:  F506 6080    ADD.W      R0, R6, #0x0400
+  0x34180AD6:  A910         ADD        R1, SP, #64
+  0x34180AD8:  F000 FD8E    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180ADC:  F64F 30FE    MOVW       R0, #0xFBFE
+  0x34180AE0:  A910         ADD        R1, SP, #64
+  0x34180AE2:  C191         STM        R1!, {R0, R4, R7}
+  0x34180AE4:  4648         MOV        R0, R9
+  0x34180AE6:  A910         ADD        R1, SP, #64
+  0x34180AE8:  F000 FD86    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180AEC:  F64F 70FF    MOVW       R0, #0xFFFF
+  0x34180AF0:  A910         ADD        R1, SP, #64
+  0x34180AF2:  C191         STM        R1!, {R0, R4, R7}
+  0x34180AF4:  F5A9 6080    SUB.W      R0, R9, #0x0400
+  0x34180AF8:  A910         ADD        R1, SP, #64
+  0x34180AFA:  F000 FD7D    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180AFE:  F649 70FF    MOVW       R0, #0x9FFF
+  0x34180B02:  A910         ADD        R1, SP, #64
+  0x34180B04:  C191         STM        R1!, {R0, R4, R7}
+  0x34180B06:  F5A9 50C0    SUB.W      R0, R9, #0x1800
+  0x34180B0A:  A910         ADD        R1, SP, #64
+  0x34180B0C:  F000 FD74    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180B10:  F44F 5084    MOV.W      R0, #0x1080
+  0x34180B14:  A910         ADD        R1, SP, #64
+  0x34180B16:  C191         STM        R1!, {R0, R4, R7}
+  0x34180B18:  4630         MOV        R0, R6
+  0x34180B1A:  A910         ADD        R1, SP, #64
+  0x34180B1C:  F000 FD6C    BL         HAL_GPIO_Init            ; 0x341815F8
+  0x34180B20:  4648         MOV        R0, R9
+  0x34180B22:  A910         ADD        R1, SP, #64
+  0x34180B24:  E9CD 8810    STRD       R8, R8, [SP, #64]
+  0x34180B28:  E9CD 7712    STRD       R7, R7, [SP, #72]
+  0x34180B2C:  F000 FD64    BL         HAL_GPIO_Init            ; 0x341815F8
+
.L16:
+  0x34180B30:  F845 8C10    STR        R8, [R5, #-16]
+  0x34180B34:  F8DB 0000    LDR.W      R0, [R11]
+
.L17:
+  0x34180B38:  F8DB 1000    LDR.W      R1, [R11]
+  0x34180B3C:  1A09         SUBS       R1, R1, R0
+  0x34180B3E:  29FB         CMP        R1, #251
+  0x34180B40:  D3FA         BCC        46L17                     ; 0x34180B38
+  0x34180B42:  F8C5 8000    STR.W      R8, [R5]
+  0x34180B46:  F8DB 0000    LDR.W      R0, [R11]
+  0x34180B4A:  BF00         NOP
+
.L18:
+  0x34180B4C:  F8DB 1000    LDR.W      R1, [R11]
+  0x34180B50:  1A09         SUBS       R1, R1, R0
+  0x34180B52:  29FB         CMP        R1, #251
+  0x34180B54:  D3FA         BCC        46L18                     ; 0x34180B4C
+  0x34180B56:  E7EB         B          46L16                     ; 0x34180B30
+
+

Section .text.SysTick_Handler from blto2_FSBL_lto.o, size=16, align=4

+ +
+
SysTick_Handler:
+  0x34180B58:  F242 009C    MOVW       R0, #0x209C              ; 0x3418209C = uwTick
+  0x34180B5C:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418209C = uwTick
+  0x34180B60:  6801         LDR        R1, [R0]
+  0x34180B62:  3101         ADDS       R1, #1
+  0x34180B64:  6001         STR        R1, [R0]
+  0x34180B66:  4770         BX         LR
+
+

Section .text.SystemCoreClockUpdate from blto2_FSBL_lto.o, size=400, align=4

+ +
+
SystemCoreClockUpdate:
+  0x34180B68:  F248 0144    MOVW       R1, #0x8044
+  0x34180B6C:  F646 4000    MOVW       R0, #0x6C00
+  0x34180B70:  F2C5 6102    MOVT       R1, #0x5602
+  0x34180B74:  F851 2C24    LDR        R2, [R1, #-36]
+  0x34180B78:  F3C2 5201    UBFX       R2, R2, #20, #2
+  0x34180B7C:  F2C0 20DC    MOVT       R0, #0x02DC
+  0x34180B80:  E8DF F002    TBB        91PC, R2]
+  0x34180B84:  02           DC.B       0x02                     ; '\x02'
+  0x34180B85:  0C           DC.B       0x0C                     ; '\x0C'
+  0x34180B86:  AB           DC.B       0xAB                     ; '\xAB'
+  0x34180B87:  19           DC.B       0x19                     ; '\x19'
+  0x34180B88:  6848         LDR        R0, [R1, #4]
+  0x34180B8A:  F249 0100    MOVW       R1, #0x9000
+  0x34180B8E:  F2C0 31D0    MOVT       R1, #0x03D0
+  0x34180B92:  F3C0 10C1    UBFX       R0, R0, #7, #2
+  0x34180B96:  FA21 F000    LSR.W      R0, R1, R0
+  0x34180B9A:  E09E         B          46L6                      ; 0x34180CDA
+  0x34180B9C:  6808         LDR        R0, [R1]
+  0x34180B9E:  0580         LSLS       R0, R0, #22
+  0x34180BA0:  F242 4000    MOVW       R0, #0x2400
+  0x34180BA4:  F2C0 00F4    MOVT       R0, #244
+  0x34180BA8:  F100 8097    BMI.W      46L6                      ; 0x34180CDA
+  0x34180BAC:  F640 1000    MOVW       R0, #0x0900
+  0x34180BB0:  F2C0 003D    MOVT       R0, #61
+  0x34180BB4:  E091         B          46L6                      ; 0x34180CDA
+  0x34180BB6:  F8D1 2080    LDR.W      R2, [R1, #128]
+  0x34180BBA:  F3C2 7201    UBFX       R2, R2, #28, #2
+  0x34180BBE:  B530         PUSH       123R4-R5, LR}
+  0x34180BC0:  E8DF F002    TBB        91PC, R2]
+  0x34180BC4:  02           DC.B       0x02                     ; '\x02'
+  0x34180BC5:  1A           DC.B       0x1A                     ; '\x1A'
+  0x34180BC6:  0A           DC.B       0x0A                     ; '\n'
+  0x34180BC7:  12           DC.B       0x12                     ; '\x12'
+  0x34180BC8:  6BCD         LDR        R5, [R1, #60]
+  0x34180BCA:  012B         LSLS       R3, R5, #4
+  0x34180BCC:  D442         BMI        46L2                      ; 0x34180C54
+  0x34180BCE:  F101 0C40    ADD.W      R12, R1, #64
+  0x34180BD2:  F101 0E44    ADD.W      LR, R1, #68
+  0x34180BD6:  E016         B          46L1                      ; 0x34180C06
+  0x34180BD8:  6DCD         LDR        R5, [R1, #92]
+  0x34180BDA:  012B         LSLS       R3, R5, #4
+  0x34180BDC:  D43A         BMI        46L2                      ; 0x34180C54
+  0x34180BDE:  F101 0C60    ADD.W      R12, R1, #96
+  0x34180BE2:  F101 0E64    ADD.W      LR, R1, #100
+  0x34180BE6:  E00E         B          46L1                      ; 0x34180C06
+  0x34180BE8:  6ECD         LDR        R5, [R1, #108]
+  0x34180BEA:  012B         LSLS       R3, R5, #4
+  0x34180BEC:  D432         BMI        46L2                      ; 0x34180C54
+  0x34180BEE:  F101 0C70    ADD.W      R12, R1, #112
+  0x34180BF2:  F101 0E74    ADD.W      LR, R1, #116
+  0x34180BF6:  E006         B          46L1                      ; 0x34180C06
+  0x34180BF8:  6CCD         LDR        R5, [R1, #76]
+  0x34180BFA:  012B         LSLS       R3, R5, #4
+  0x34180BFC:  D42A         BMI        46L2                      ; 0x34180C54
+  0x34180BFE:  F101 0C50    ADD.W      R12, R1, #80
+  0x34180C02:  F101 0E54    ADD.W      LR, R1, #84
+
.L1:
+  0x34180C06:  F8DC 3000    LDR.W      R3, [R12]
+  0x34180C0A:  F3C5 240B    UBFX       R4, R5, #8, #12
+  0x34180C0E:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x34180C12:  EE01 3A10    VMOV       S2, R3
+  0x34180C16:  F8DE 2000    LDR.W      R2, [LR]
+  0x34180C1A:  EE00 4A10    VMOV       S0, R4
+  0x34180C1E:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180C22:  ED9F 2A34    VLDR       S4, =0x33800000          ; [PC, #208] [0x34180CF4]
+  0x34180C26:  F3C5 5305    UBFX       R3, R5, #20, #6
+  0x34180C2A:  F3C2 64C2    UBFX       R4, R2, #27, #3
+  0x34180C2E:  F3C2 6202    UBFX       R2, R2, #24, #3
+  0x34180C32:  EEB8 0A40    VCVT.F32.U32 S0, S0
+  0x34180C36:  EE21 1A02    VMUL.F32   S2, S2, S4
+  0x34180C3A:  4362         MULS       R2, R4, R2
+  0x34180C3C:  EE31 0A00    VADD.F32   S0, S2, S0
+  0x34180C40:  EE01 3A10    VMOV       S2, R3
+  0x34180C44:  2301         MOVS       R3, #1
+  0x34180C46:  EEB8 2A41    VCVT.F32.U32 S4, S2
+  0x34180C4A:  EE01 2A10    VMOV       S2, R2
+  0x34180C4E:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34180C52:  E006         B          46L3                      ; 0x34180C62
+
.L2:
+  0x34180C54:  ED9F 0A26    VLDR       S0, =0x00000000          ; [PC, #152] [0x34180CF0]
+  0x34180C58:  2300         MOVS       R3, #0
+  0x34180C5A:  EEB0 1A40    VMOV.F32   S2, S0
+  0x34180C5E:  EEB0 2A40    VMOV.F32   S4, S0
+
.L3:
+  0x34180C62:  F3C5 7202    UBFX       R2, R5, #28, #3
+  0x34180C66:  2A03         CMP        R2, #3
+  0x34180C68:  D83D         BHI        46L7                      ; 0x34180CE6
+  0x34180C6A:  E8DF F002    TBB        91PC, R2]
+  0x34180C6E:  02           DC.B       0x02                     ; '\x02'
+  0x34180C6F:  0D           DC.B       0x0D                     ; '\r'
+  0x34180C70:  1E           DC.B       0x1E                     ; '\x1E'
+  0x34180C71:  1A           DC.B       0x1A                     ; '\x1A'
+  0x34180C72:  6848         LDR        R0, [R1, #4]
+  0x34180C74:  F249 0200    MOVW       R2, #0x9000
+  0x34180C78:  F2C0 32D0    MOVT       R2, #0x03D0
+  0x34180C7C:  F3C0 10C1    UBFX       R0, R0, #7, #2
+  0x34180C80:  FA22 F000    LSR.W      R0, R2, R0
+  0x34180C84:  B993         CBNZ       R3, .L4                  ; 0x34180CAC
+  0x34180C86:  E01F         B          46L5                      ; 0x34180CC8
+  0x34180C88:  6808         LDR        R0, [R1]
+  0x34180C8A:  0580         LSLS       R0, R0, #22
+  0x34180C8C:  F242 4000    MOVW       R0, #0x2400
+  0x34180C90:  F2C0 00F4    MOVT       R0, #244
+  0x34180C94:  BF5C         ITT        PL
+  0x34180C96:  F640 1000    MOVWPL     R0, #0x0900
+  0x34180C9A:  F2C0 003D    MOVTPL     R0, #61
+  0x34180C9E:  B92B         CBNZ       R3, .L4                  ; 0x34180CAC
+  0x34180CA0:  E012         B          46L5                      ; 0x34180CC8
+  0x34180CA2:  F248 0000    MOVW       R0, #0x8000
+  0x34180CA6:  F2C0 00BB    MOVT       R0, #187
+  0x34180CAA:  B16B         CBZ        R3, .L5                  ; 0x34180CC8
+
.L4:
+  0x34180CAC:  EE03 0A10    VMOV       S6, R0
+  0x34180CB0:  EEB8 3A43    VCVT.F32.U32 S6, S6
+  0x34180CB4:  EE20 0A03    VMUL.F32   S0, S0, S6
+  0x34180CB8:  EE80 0A02    VDIV.F32   S0, S0, S4
+  0x34180CBC:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34180CC0:  EEBC 0AC0    VCVT.U32.F32 S0, S0
+  0x34180CC4:  EE10 0A10    VMOV       R0, S0
+
.L5:
+  0x34180CC8:  F8D1 1080    LDR.W      R1, [R1, #128]
+  0x34180CCC:  2201         MOVS       R2, #1
+  0x34180CCE:  FA52 F1A1    UXTAB      R1, R2, R1, ROR #16
+  0x34180CD2:  FBB0 F0F1    UDIV       R0, R0, R1
+  0x34180CD6:  E8BD 4030    POP.W      123R4-R5, LR}
+
.L6:
+  0x34180CDA:  F242 01A4    MOVW       R1, #0x20A4              ; 0x341820A4 = SystemCoreClock
+  0x34180CDE:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341820A4 = SystemCoreClock
+  0x34180CE2:  6008         STR        R0, [R1]
+  0x34180CE4:  4770         BX         LR
+
.L7:
+  0x34180CE6:  2000         MOVS       R0, #0
+  0x34180CE8:  2B00         CMP        R3, #0
+  0x34180CEA:  D1DF         BNE        46L4                      ; 0x34180CAC
+  0x34180CEC:  E7EC         B          46L5                      ; 0x34180CC8
+  0x34180CEE:  BF00         NOP
+  0x34180CF0:  00000000     DC.W       0x00000000
+  0x34180CF4:  33800000     DC.W       0x33800000
+
+

Section .text.HAL_RCC_ClockConfig from blto2_FSBL_lto.o, size=1472, align=4

+ +
+
HAL_RCC_ClockConfig:
+  0x34180CF8:  B570         PUSH       123R4-R6, LR}
+  0x34180CFA:  6801         LDR        R1, [R0]
+  0x34180CFC:  F248 0424    MOVW       R4, #0x8024
+  0x34180D00:  F2C5 6402    MOVT       R4, #0x5602
+  0x34180D04:  070A         LSLS       R2, R1, #28
+  0x34180D06:  D46A         BMI        46L13                     ; 0x34180DDE
+  0x34180D08:  06CA         LSLS       R2, R1, #27
+  0x34180D0A:  D475         BMI        46L14                     ; 0x34180DF8
+
.L1:
+  0x34180D0C:  068A         LSLS       R2, R1, #26
+  0x34180D0E:  F100 8081    BMI.W      46L15                     ; 0x34180E14
+
.L2:
+  0x34180D12:  064A         LSLS       R2, R1, #25
+  0x34180D14:  F100 808C    BMI.W      46L16                     ; 0x34180E30
+
.L3:
+  0x34180D18:  074A         LSLS       R2, R1, #29
+  0x34180D1A:  F100 8097    BMI.W      46L17                     ; 0x34180E4C
+
.L4:
+  0x34180D1E:  07CA         LSLS       R2, R1, #31
+  0x34180D20:  F040 80A2    BNE.W      46L18                     ; 0x34180E68
+
.L5:
+  0x34180D24:  078A         LSLS       R2, R1, #30
+  0x34180D26:  F100 8216    BMI.W      46L39                     ; 0x34181156
+
.L6:
+  0x34180D2A:  074A         LSLS       R2, R1, #29
+  0x34180D2C:  F100 8241    BMI.W      46L43                     ; 0x341811B2
+
.L7:
+  0x34180D30:  070A         LSLS       R2, R1, #28
+  0x34180D32:  F100 824C    BMI.W      46L44                     ; 0x341811CE
+
.L8:
+  0x34180D36:  06CA         LSLS       R2, R1, #27
+  0x34180D38:  F100 8257    BMI.W      46L45                     ; 0x341811EA
+
.L9:
+  0x34180D3C:  068A         LSLS       R2, R1, #26
+  0x34180D3E:  F100 8262    BMI.W      46L46                     ; 0x34181206
+
.L10:
+  0x34180D42:  0649         LSLS       R1, R1, #25
+  0x34180D44:  D50A         BPL        46L12                     ; 0x34180D5C
+
.L11:
+  0x34180D46:  69C0         LDR        R0, [R0, #28]
+  0x34180D48:  6821         LDR        R1, [R4]
+  0x34180D4A:  F401 21E0    AND        R1, R1, #0x070000
+  0x34180D4E:  4288         CMP        R0, R1
+  0x34180D50:  BF3F         ITTTT      CC
+  0x34180D52:  6821         LDRCC      R1, [R4]
+  0x34180D54:  F421 21E0    BICCC      R1, R1, #0x070000
+  0x34180D58:  4308         ORRCC      R0, R1
+  0x34180D5A:  6020         STRCC      R0, [R4]
+
.L12:
+  0x34180D5C:  F242 00A4    MOVW       R0, #0x20A4              ; 0x341820A4 = SystemCoreClock
+  0x34180D60:  F644 51D3    MOVW       R1, #0x4DD3
+  0x34180D64:  F2C3 4018    MOVT       R0, #0x3418              ; 0x341820A4 = SystemCoreClock
+  0x34180D68:  6800         LDR        R0, [R0]
+  0x34180D6A:  F2C1 0162    MOVT       R1, #0x1062
+  0x34180D6E:  FBA0 0101    UMULL      R0, R1, R0, R1
+  0x34180D72:  F04F 30FF    MOV.W      R0, #0xFFFFFFFF
+  0x34180D76:  EB00 1091    ADD.W      R0, R0, R1, LSR #6
+  0x34180D7A:  0E01         LSRS       R1, R0, #24
+  0x34180D7C:  F040 81DA    BNE.W      46L34                     ; 0x34181134
+  0x34180D80:  F242 01A0    MOVW       R1, #0x20A0              ; 0x341820A0 = uwTickPrio
+  0x34180D84:  F24E 0310    MOVW       R3, #0xE010
+  0x34180D88:  F2C3 4118    MOVT       R1, #0x3418              ; 0x341820A0 = uwTickPrio
+  0x34180D8C:  780A         LDRB       R2, [R1]
+  0x34180D8E:  F2CE 0300    MOVT       R3, #0xE000
+  0x34180D92:  6058         STR        R0, [R3, #4]
+  0x34180D94:  20F0         MOVS       R0, #240
+  0x34180D96:  2A01         CMP        R2, #1
+  0x34180D98:  F603 5213    ADDW       R2, R3, #0x0D13
+  0x34180D9C:  7010         STRB       R0, [R2]
+  0x34180D9E:  F04F 0000    MOV.W      R0, #0
+  0x34180DA2:  6098         STR        R0, [R3, #8]
+  0x34180DA4:  F04F 0007    MOV.W      R0, #7
+  0x34180DA8:  6018         STR        R0, [R3]
+  0x34180DAA:  F04F 0001    MOV.W      R0, #1
+  0x34180DAE:  F040 808A    BNE.W      46L20                     ; 0x34180EC6
+  0x34180DB2:  F852 3C17    LDR        R3, [R2, #-23]
+  0x34180DB6:  F04F 35FF    MOV.W      R5, #0xFFFFFFFF
+  0x34180DBA:  F3C3 2302    UBFX       R3, R3, #8, #3
+  0x34180DBE:  F083 0607    EOR        R6, R3, #7
+  0x34180DC2:  2E04         CMP        R6, #4
+  0x34180DC4:  BF28         IT         CS
+  0x34180DC6:  2604         MOVCS      R6, #4
+  0x34180DC8:  FA05 F606    LSL.W      R6, R5, R6
+  0x34180DCC:  43F6         MVNS       R6, R6
+  0x34180DCE:  3B03         SUBS       R3, #3
+  0x34180DD0:  BF28         IT         CS
+  0x34180DD2:  409E         LSLCS      R6, R3
+  0x34180DD4:  0133         LSLS       R3, R6, #4
+  0x34180DD6:  7013         STRB       R3, [R2]
+  0x34180DD8:  7008         STRB       R0, [R1]
+  0x34180DDA:  2000         MOVS       R0, #0
+  0x34180DDC:  BD70         POP        123R4-R6, PC}
+
.L13:
+  0x34180DDE:  6902         LDR        R2, [R0, #16]
+  0x34180DE0:  6823         LDR        R3, [R4]
+  0x34180DE2:  F003 0307    AND        R3, R3, #7
+  0x34180DE6:  429A         CMP        R2, R3
+  0x34180DE8:  BF81         ITTTT      HI
+  0x34180DEA:  6823         LDRHI      R3, [R4]
+  0x34180DEC:  F023 0307    BICHI      R3, R3, #7
+  0x34180DF0:  431A         ORRHI      R2, R3
+  0x34180DF2:  6022         STRHI      R2, [R4]
+  0x34180DF4:  06CA         LSLS       R2, R1, #27
+  0x34180DF6:  D589         BPL        46L1                      ; 0x34180D0C
+
.L14:
+  0x34180DF8:  6942         LDR        R2, [R0, #20]
+  0x34180DFA:  6823         LDR        R3, [R4]
+  0x34180DFC:  F003 0370    AND        R3, R3, #112
+  0x34180E00:  429A         CMP        R2, R3
+  0x34180E02:  BF81         ITTTT      HI
+  0x34180E04:  6823         LDRHI      R3, [R4]
+  0x34180E06:  F023 0370    BICHI      R3, R3, #112
+  0x34180E0A:  431A         ORRHI      R2, R3
+  0x34180E0C:  6022         STRHI      R2, [R4]
+  0x34180E0E:  068A         LSLS       R2, R1, #26
+  0x34180E10:  F57F AF7F    BPL.W      46L2                      ; 0x34180D12
+
.L15:
+  0x34180E14:  6982         LDR        R2, [R0, #24]
+  0x34180E16:  6823         LDR        R3, [R4]
+  0x34180E18:  F403 43E0    AND        R3, R3, #0x7000
+  0x34180E1C:  429A         CMP        R2, R3
+  0x34180E1E:  BF81         ITTTT      HI
+  0x34180E20:  6823         LDRHI      R3, [R4]
+  0x34180E22:  F423 43E0    BICHI      R3, R3, #0x7000
+  0x34180E26:  431A         ORRHI      R2, R3
+  0x34180E28:  6022         STRHI      R2, [R4]
+  0x34180E2A:  064A         LSLS       R2, R1, #25
+  0x34180E2C:  F57F AF74    BPL.W      46L3                      ; 0x34180D18
+
.L16:
+  0x34180E30:  69C2         LDR        R2, [R0, #28]
+  0x34180E32:  6823         LDR        R3, [R4]
+  0x34180E34:  F403 23E0    AND        R3, R3, #0x070000
+  0x34180E38:  429A         CMP        R2, R3
+  0x34180E3A:  BF81         ITTTT      HI
+  0x34180E3C:  6823         LDRHI      R3, [R4]
+  0x34180E3E:  F423 23E0    BICHI      R3, R3, #0x070000
+  0x34180E42:  431A         ORRHI      R2, R3
+  0x34180E44:  6022         STRHI      R2, [R4]
+  0x34180E46:  074A         LSLS       R2, R1, #29
+  0x34180E48:  F57F AF69    BPL.W      46L4                      ; 0x34180D1E
+
.L17:
+  0x34180E4C:  68C2         LDR        R2, [R0, #12]
+  0x34180E4E:  6823         LDR        R3, [R4]
+  0x34180E50:  F403 03E0    AND        R3, R3, #0x700000
+  0x34180E54:  429A         CMP        R2, R3
+  0x34180E56:  BF81         ITTTT      HI
+  0x34180E58:  6823         LDRHI      R3, [R4]
+  0x34180E5A:  F423 03E0    BICHI      R3, R3, #0x700000
+  0x34180E5E:  431A         ORRHI      R2, R3
+  0x34180E60:  6022         STRHI      R2, [R4]
+  0x34180E62:  07CA         LSLS       R2, R1, #31
+  0x34180E64:  F43F AF5E    BEQ.W      46L5                      ; 0x34180D24
+
.L18:
+  0x34180E68:  6841         LDR        R1, [R0, #4]
+  0x34180E6A:  F5B1 3F80    CMP.W      R1, #0x010000
+  0x34180E6E:  D02B         BEQ        46L21                     ; 0x34180EC8
+  0x34180E70:  F5B1 3F40    CMP.W      R1, #0x030000
+  0x34180E74:  D00A         BEQ        46L19                     ; 0x34180E8C
+  0x34180E76:  F854 2C20    LDR        R2, [R4, #-32]
+  0x34180E7A:  F5B1 3F00    CMP.W      R1, #0x020000
+  0x34180E7E:  D12B         BNE        46L22                     ; 0x34180ED8
+  0x34180E80:  06D1         LSLS       R1, R2, #27
+  0x34180E82:  F140 8157    BPL.W      46L34                     ; 0x34181134
+  0x34180E86:  F44F 3100    MOV.W      R1, #0x020000
+  0x34180E8A:  E028         B          46L23                     ; 0x34180EDE
+
.L19:
+  0x34180E8C:  4605         MOV        R5, R0
+  0x34180E8E:  6A01         LDR        R1, [R0, #32]
+  0x34180E90:  F8D4 00A0    LDR.W      R0, [R4, #160]
+  0x34180E94:  F000 5040    AND        R0, R0, #0x30000000
+  0x34180E98:  F000 FA0E    BL         RCC_IC_CheckPLLSources   ; 0x341812B8
+  0x34180E9C:  2800         CMP        R0, #0
+  0x34180E9E:  F04F 0001    MOV.W      R0, #1
+  0x34180EA2:  D010         BEQ        46L20                     ; 0x34180EC6
+  0x34180EA4:  E9D5 1308    LDRD       R1, R3, [R5, #32]
+  0x34180EA8:  2600         MOVS       R6, #0
+  0x34180EAA:  F6CF 76FF    MOVT       R6, #0xFFFF
+  0x34180EAE:  2201         MOVS       R2, #1
+  0x34180EB0:  4628         MOV        R0, R5
+  0x34180EB2:  EB06 4303    ADD.W      R3, R6, R3, LSL #16
+  0x34180EB6:  430B         ORRS       R3, R1
+  0x34180EB8:  6869         LDR        R1, [R5, #4]
+  0x34180EBA:  F8C4 30A0    STR.W      R3, [R4, #160]
+  0x34180EBE:  F604 231C    ADDW       R3, R4, #0x0A1C
+  0x34180EC2:  601A         STR        R2, [R3]
+  0x34180EC4:  E00B         B          46L23                     ; 0x34180EDE
+
.L20:
+  0x34180EC6:  BD70         POP        123R4-R6, PC}
+
.L21:
+  0x34180EC8:  F854 1C20    LDR        R1, [R4, #-32]
+  0x34180ECC:  0749         LSLS       R1, R1, #29
+  0x34180ECE:  F140 8131    BPL.W      46L34                     ; 0x34181134
+  0x34180ED2:  F44F 3180    MOV.W      R1, #0x010000
+  0x34180ED6:  E002         B          46L23                     ; 0x34180EDE
+
.L22:
+  0x34180ED8:  0712         LSLS       R2, R2, #28
+  0x34180EDA:  F140 812B    BPL.W      46L34                     ; 0x34181134
+
.L23:
+  0x34180EDE:  F854 2C04    LDR        R2, [R4, #-4]
+  0x34180EE2:  F241 3688    MOVW       R6, #0x1388
+  0x34180EE6:  F422 3240    BIC        R2, R2, #0x030000
+  0x34180EEA:  430A         ORRS       R2, R1
+  0x34180EEC:  F844 2C04    STR        R2, [R4, #-4]
+  0x34180EF0:  F242 029C    MOVW       R2, #0x209C              ; 0x3418209C = uwTick
+  0x34180EF4:  F2C3 4218    MOVT       R2, #0x3418              ; 0x3418209C = uwTick
+  0x34180EF8:  6813         LDR        R3, [R2]
+  0x34180EFA:  BF00         NOP
+
.L24:
+  0x34180EFC:  F854 5C04    LDR        R5, [R4, #-4]
+  0x34180F00:  F405 1540    AND        R5, R5, #0x300000
+  0x34180F04:  EBB5 1F01    CMP.W      R5, R1, LSL #4
+  0x34180F08:  D005         BEQ        46L25                     ; 0x34180F16
+  0x34180F0A:  6815         LDR        R5, [R2]
+  0x34180F0C:  1AED         SUBS       R5, R5, R3
+  0x34180F0E:  42B5         CMP        R5, R6
+  0x34180F10:  D9F4         BLS        46L24                     ; 0x34180EFC
+  0x34180F12:  2003         MOVS       R0, #3
+  0x34180F14:  BD70         POP        123R4-R6, PC}
+
.L25:
+  0x34180F16:  F854 1C04    LDR        R1, [R4, #-4]
+  0x34180F1A:  F3C1 5201    UBFX       R2, R1, #20, #2
+  0x34180F1E:  F646 4100    MOVW       R1, #0x6C00
+  0x34180F22:  F2C0 21DC    MOVT       R1, #0x02DC
+  0x34180F26:  E8DF F012    TBH        91PC, R2, LSL #1]
+  0x34180F2A:  04           DC.B       0x04                     ; '\x04'
+  0x34180F2B:  00           DC.B       0x00                     ; '\0'
+  0x34180F2C:  0E           DC.B       0x0E                     ; '\x0E'
+  0x34180F2D:  00           DC.B       0x00                     ; '\0'
+  0x34180F2E:  0D           DC.B       0x0D                     ; '\r'
+  0x34180F2F:  01           DC.B       0x01                     ; '\x01'
+  0x34180F30:  1B           DC.B       0x1B                     ; '\x1B'
+  0x34180F31:  00           DC.B       0x00                     ; '\0'
+  0x34180F32:  6A61         LDR        R1, [R4, #36]
+  0x34180F34:  F249 0200    MOVW       R2, #0x9000
+  0x34180F38:  F2C0 32D0    MOVT       R2, #0x03D0
+  0x34180F3C:  F3C1 11C1    UBFX       R1, R1, #7, #2
+  0x34180F40:  FA22 F101    LSR.W      R1, R2, R1
+  0x34180F44:  E0FE         B          46L38                     ; 0x34181144
+  0x34180F46:  6A21         LDR        R1, [R4, #32]
+  0x34180F48:  0589         LSLS       R1, R1, #22
+  0x34180F4A:  F242 4100    MOVW       R1, #0x2400
+  0x34180F4E:  F2C0 01F4    MOVT       R1, #244
+  0x34180F52:  F100 80F7    BMI.W      46L38                     ; 0x34181144
+  0x34180F56:  F640 1100    MOVW       R1, #0x0900
+  0x34180F5A:  F2C0 013D    MOVT       R1, #61
+  0x34180F5E:  E0F1         B          46L38                     ; 0x34181144
+  0x34180F60:  F8D4 10A0    LDR.W      R1, [R4, #160]
+  0x34180F64:  2201         MOVS       R2, #1
+  0x34180F66:  FA52 F5A1    UXTAB      R5, R2, R1, ROR #16
+  0x34180F6A:  F8D4 10A0    LDR.W      R1, [R4, #160]
+  0x34180F6E:  F3C1 7201    UBFX       R2, R1, #28, #2
+  0x34180F72:  F854 1C20    LDR        R1, [R4, #-32]
+  0x34180F76:  E8DF F002    TBB        91PC, R2]
+  0x34180F7A:  02           DC.B       0x02                     ; '\x02'
+  0x34180F7B:  1C           DC.B       0x1C                     ; '\x1C'
+  0x34180F7C:  0A           DC.B       0x0A                     ; '\n'
+  0x34180F7D:  12           DC.B       0x12                     ; '\x12'
+  0x34180F7E:  05C9         LSLS       R1, R1, #23
+  0x34180F80:  D475         BMI        46L30                     ; 0x3418106E
+  0x34180F82:  6DE1         LDR        R1, [R4, #92]
+  0x34180F84:  0109         LSLS       R1, R1, #4
+  0x34180F86:  F140 80DA    BPL.W      46L36                     ; 0x3418113E
+  0x34180F8A:  6DE1         LDR        R1, [R4, #92]
+  0x34180F8C:  E019         B          46L26                     ; 0x34180FC2
+  0x34180F8E:  0549         LSLS       R1, R1, #21
+  0x34180F90:  D41F         BMI        46L28                     ; 0x34180FD2
+  0x34180F92:  6FE1         LDR        R1, [R4, #124]
+  0x34180F94:  0109         LSLS       R1, R1, #4
+  0x34180F96:  F140 80D2    BPL.W      46L36                     ; 0x3418113E
+  0x34180F9A:  6FE1         LDR        R1, [R4, #124]
+  0x34180F9C:  E011         B          46L26                     ; 0x34180FC2
+  0x34180F9E:  0509         LSLS       R1, R1, #20
+  0x34180FA0:  D43D         BMI        46L29                     ; 0x3418101E
+  0x34180FA2:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x34180FA6:  0109         LSLS       R1, R1, #4
+  0x34180FA8:  F140 80C9    BPL.W      46L36                     ; 0x3418113E
+  0x34180FAC:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x34180FB0:  E007         B          46L26                     ; 0x34180FC2
+  0x34180FB2:  0589         LSLS       R1, R1, #22
+  0x34180FB4:  F100 80C0    BMI.W      46L35                     ; 0x34181138
+  0x34180FB8:  6EE1         LDR        R1, [R4, #108]
+  0x34180FBA:  0109         LSLS       R1, R1, #4
+  0x34180FBC:  F140 80BF    BPL.W      46L36                     ; 0x3418113E
+  0x34180FC0:  6EE1         LDR        R1, [R4, #108]
+
.L26:
+  0x34180FC2:  4606         MOV        R6, R0
+  0x34180FC4:  F001 40E0    AND        R0, R1, #0x70000000
+  0x34180FC8:  F000 F9C0    BL         RCCEx_GetPLLSourceFreq   ; 0x3418134C
+  0x34180FCC:  4601         MOV        R1, R0
+
.L27:
+  0x34180FCE:  4630         MOV        R0, R6
+  0x34180FD0:  E0B6         B          46L37                     ; 0x34181140
+
.L28:
+  0x34180FD2:  F8D4 1084    LDR.W      R1, [R4, #132]
+  0x34180FD6:  0049         LSLS       R1, R1, #1
+  0x34180FD8:  F140 80B1    BPL.W      46L36                     ; 0x3418113E
+  0x34180FDC:  4606         MOV        R6, R0
+  0x34180FDE:  6FE0         LDR        R0, [R4, #124]
+  0x34180FE0:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34180FE4:  F000 F9B2    BL         RCCEx_GetPLLSourceFreq   ; 0x3418134C
+  0x34180FE8:  0001         MOVS       R1, R0
+  0x34180FEA:  D0F0         BEQ        46L27                     ; 0x34180FCE
+  0x34180FEC:  6FE0         LDR        R0, [R4, #124]
+  0x34180FEE:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x34180FF2:  4630         MOV        R0, R6
+  0x34180FF4:  2A00         CMP        R2, #0
+  0x34180FF6:  F000 80A2    BEQ.W      46L36                     ; 0x3418113E
+  0x34180FFA:  EE00 1A10    VMOV       S0, R1
+  0x34180FFE:  6FE1         LDR        R1, [R4, #124]
+  0x34181000:  F8D4 3080    LDR.W      R3, [R4, #128]
+  0x34181004:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x34181008:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x3418100C:  EE01 1A10    VMOV       S2, R1
+  0x34181010:  F8D4 1084    LDR.W      R1, [R4, #132]
+  0x34181014:  EE02 3A10    VMOV       S4, R3
+  0x34181018:  F8D4 3084    LDR.W      R3, [R4, #132]
+  0x3418101C:  E120         B          46L48                     ; 0x34181260
+
.L29:
+  0x3418101E:  F8D4 1094    LDR.W      R1, [R4, #148]
+  0x34181022:  0049         LSLS       R1, R1, #1
+  0x34181024:  F140 808B    BPL.W      46L36                     ; 0x3418113E
+  0x34181028:  4606         MOV        R6, R0
+  0x3418102A:  F8D4 008C    LDR.W      R0, [R4, #140]
+  0x3418102E:  F000 40E0    AND        R0, R0, #0x70000000
+  0x34181032:  F000 F98B    BL         RCCEx_GetPLLSourceFreq   ; 0x3418134C
+  0x34181036:  0001         MOVS       R1, R0
+  0x34181038:  D0C9         BEQ        46L27                     ; 0x34180FCE
+  0x3418103A:  F8D4 008C    LDR.W      R0, [R4, #140]
+  0x3418103E:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x34181042:  4630         MOV        R0, R6
+  0x34181044:  2A00         CMP        R2, #0
+  0x34181046:  D07A         BEQ        46L36                     ; 0x3418113E
+  0x34181048:  EE00 1A10    VMOV       S0, R1
+  0x3418104C:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x34181050:  F8D4 3090    LDR.W      R3, [R4, #144]
+  0x34181054:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x34181058:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x3418105C:  EE01 1A10    VMOV       S2, R1
+  0x34181060:  F8D4 1094    LDR.W      R1, [R4, #148]
+  0x34181064:  EE02 3A10    VMOV       S4, R3
+  0x34181068:  F8D4 3094    LDR.W      R3, [R4, #148]
+  0x3418106C:  E0F8         B          46L48                     ; 0x34181260
+
.L30:
+  0x3418106E:  6E61         LDR        R1, [R4, #100]
+  0x34181070:  0049         LSLS       R1, R1, #1
+  0x34181072:  D564         BPL        46L36                     ; 0x3418113E
+  0x34181074:  4606         MOV        R6, R0
+  0x34181076:  6DE0         LDR        R0, [R4, #92]
+  0x34181078:  F000 40E0    AND        R0, R0, #0x70000000
+  0x3418107C:  F000 F966    BL         RCCEx_GetPLLSourceFreq   ; 0x3418134C
+  0x34181080:  0001         MOVS       R1, R0
+  0x34181082:  D0A4         BEQ        46L27                     ; 0x34180FCE
+  0x34181084:  6DE0         LDR        R0, [R4, #92]
+  0x34181086:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x3418108A:  4630         MOV        R0, R6
+  0x3418108C:  2A00         CMP        R2, #0
+  0x3418108E:  D056         BEQ        46L36                     ; 0x3418113E
+  0x34181090:  EE00 1A10    VMOV       S0, R1
+  0x34181094:  6DE1         LDR        R1, [R4, #92]
+  0x34181096:  6E23         LDR        R3, [R4, #96]
+  0x34181098:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x3418109C:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x341810A0:  EE01 1A10    VMOV       S2, R1
+  0x341810A4:  6E61         LDR        R1, [R4, #100]
+  0x341810A6:  EE02 3A10    VMOV       S4, R3
+  0x341810AA:  6E63         LDR        R3, [R4, #100]
+  0x341810AC:  E0D8         B          46L48                     ; 0x34181260
+
.L31:
+  0x341810AE:  4605         MOV        R5, R0
+  0x341810B0:  6A81         LDR        R1, [R0, #40]
+  0x341810B2:  F8D4 00A4    LDR.W      R0, [R4, #164]
+  0x341810B6:  F000 5040    AND        R0, R0, #0x30000000
+  0x341810BA:  F000 F8FD    BL         RCC_IC_CheckPLLSources   ; 0x341812B8
+  0x341810BE:  B3C8         CBZ        R0, .L34                 ; 0x34181134
+  0x341810C0:  F8D4 00B4    LDR.W      R0, [R4, #180]
+  0x341810C4:  6B29         LDR        R1, [R5, #48]
+  0x341810C6:  F000 5040    AND        R0, R0, #0x30000000
+  0x341810CA:  F000 F8F5    BL         RCC_IC_CheckPLLSources   ; 0x341812B8
+  0x341810CE:  B388         CBZ        R0, .L34                 ; 0x34181134
+  0x341810D0:  F8D4 00C8    LDR.W      R0, [R4, #200]
+  0x341810D4:  6BA9         LDR        R1, [R5, #56]
+  0x341810D6:  F000 5040    AND        R0, R0, #0x30000000
+  0x341810DA:  F000 F8ED    BL         RCC_IC_CheckPLLSources   ; 0x341812B8
+  0x341810DE:  B348         CBZ        R0, .L34                 ; 0x34181134
+  0x341810E0:  E9D5 210A    LDRD       R2, R1, [R5, #40]
+  0x341810E4:  2300         MOVS       R3, #0
+  0x341810E6:  F6CF 73FF    MOVT       R3, #0xFFFF
+  0x341810EA:  4628         MOV        R0, R5
+  0x341810EC:  6B2E         LDR        R6, [R5, #48]
+  0x341810EE:  EB03 4101    ADD.W      R1, R3, R1, LSL #16
+  0x341810F2:  430A         ORRS       R2, R1
+  0x341810F4:  68A9         LDR        R1, [R5, #8]
+  0x341810F6:  F8C4 20A4    STR.W      R2, [R4, #164]
+  0x341810FA:  6B6A         LDR        R2, [R5, #52]
+  0x341810FC:  EB03 4202    ADD.W      R2, R3, R2, LSL #16
+  0x34181100:  4332         ORRS       R2, R6
+  0x34181102:  F8C4 20B4    STR.W      R2, [R4, #180]
+  0x34181106:  6BEA         LDR        R2, [R5, #60]
+  0x34181108:  EB03 4202    ADD.W      R2, R3, R2, LSL #16
+  0x3418110C:  6BAB         LDR        R3, [R5, #56]
+  0x3418110E:  431A         ORRS       R2, R3
+  0x34181110:  F240 4322    MOVW       R3, #0x0422
+  0x34181114:  F8C4 20C8    STR.W      R2, [R4, #200]
+  0x34181118:  F648 2240    MOVW       R2, #0x8A40
+  0x3418111C:  F2C5 6202    MOVT       R2, #0x5602
+  0x34181120:  6013         STR        R3, [R2]
+  0x34181122:  E027         B          46L40                     ; 0x34181174
+
.L32:
+  0x34181124:  F854 1C20    LDR        R1, [R4, #-32]
+  0x34181128:  0709         LSLS       R1, R1, #28
+  0x3418112A:  D503         BPL        46L34                     ; 0x34181134
+  0x3418112C:  2100         MOVS       R1, #0
+  0x3418112E:  E021         B          46L40                     ; 0x34181174
+
.L33:
+  0x34181130:  0752         LSLS       R2, R2, #29
+  0x34181132:  D41F         BMI        46L40                     ; 0x34181174
+
.L34:
+  0x34181134:  2001         MOVS       R0, #1
+  0x34181136:  BD70         POP        123R4-R6, PC}
+
.L35:
+  0x34181138:  6F61         LDR        R1, [R4, #116]
+  0x3418113A:  0049         LSLS       R1, R1, #1
+  0x3418113C:  D472         BMI        46L47                     ; 0x34181224
+
.L36:
+  0x3418113E:  2100         MOVS       R1, #0
+
.L37:
+  0x34181140:  FBB1 F1F5    UDIV       R1, R1, R5
+
.L38:
+  0x34181144:  F242 02A4    MOVW       R2, #0x20A4              ; 0x341820A4 = SystemCoreClock
+  0x34181148:  F2C3 4218    MOVT       R2, #0x3418              ; 0x341820A4 = SystemCoreClock
+  0x3418114C:  6011         STR        R1, [R2]
+  0x3418114E:  6801         LDR        R1, [R0]
+  0x34181150:  078A         LSLS       R2, R1, #30
+  0x34181152:  F57F ADEA    BPL.W      46L6                      ; 0x34180D2A
+
.L39:
+  0x34181156:  6881         LDR        R1, [R0, #8]
+  0x34181158:  2900         CMP        R1, #0
+  0x3418115A:  D0E3         BEQ        46L32                     ; 0x34181124
+  0x3418115C:  F1B1 7F40    CMP.W      R1, #0x03000000
+  0x34181160:  D0A5         BEQ        46L31                     ; 0x341810AE
+  0x34181162:  F854 2C20    LDR        R2, [R4, #-32]
+  0x34181166:  F1B1 7F00    CMP.W      R1, #0x02000000
+  0x3418116A:  D1E1         BNE        46L33                     ; 0x34181130
+  0x3418116C:  06D1         LSLS       R1, R2, #27
+  0x3418116E:  D5E1         BPL        46L34                     ; 0x34181134
+  0x34181170:  F04F 7100    MOV.W      R1, #0x02000000
+
.L40:
+  0x34181174:  F854 2C04    LDR        R2, [R4, #-4]
+  0x34181178:  F241 3688    MOVW       R6, #0x1388
+  0x3418117C:  F022 7240    BIC        R2, R2, #0x03000000
+  0x34181180:  430A         ORRS       R2, R1
+  0x34181182:  F844 2C04    STR        R2, [R4, #-4]
+  0x34181186:  F242 029C    MOVW       R2, #0x209C              ; 0x3418209C = uwTick
+  0x3418118A:  F2C3 4218    MOVT       R2, #0x3418              ; 0x3418209C = uwTick
+  0x3418118E:  6813         LDR        R3, [R2]
+
.L41:
+  0x34181190:  F854 5C04    LDR        R5, [R4, #-4]
+  0x34181194:  F005 5540    AND        R5, R5, #0x30000000
+  0x34181198:  EBB5 1F01    CMP.W      R5, R1, LSL #4
+  0x3418119C:  D005         BEQ        46L42                     ; 0x341811AA
+  0x3418119E:  6815         LDR        R5, [R2]
+  0x341811A0:  1AED         SUBS       R5, R5, R3
+  0x341811A2:  42B5         CMP        R5, R6
+  0x341811A4:  D9F4         BLS        46L41                     ; 0x34181190
+  0x341811A6:  2003         MOVS       R0, #3
+  0x341811A8:  BD70         POP        123R4-R6, PC}
+
.L42:
+  0x341811AA:  6801         LDR        R1, [R0]
+  0x341811AC:  074A         LSLS       R2, R1, #29
+  0x341811AE:  F57F ADBF    BPL.W      46L7                      ; 0x34180D30
+
.L43:
+  0x341811B2:  68C2         LDR        R2, [R0, #12]
+  0x341811B4:  6823         LDR        R3, [R4]
+  0x341811B6:  F403 03E0    AND        R3, R3, #0x700000
+  0x341811BA:  429A         CMP        R2, R3
+  0x341811BC:  BF3F         ITTTT      CC
+  0x341811BE:  6823         LDRCC      R3, [R4]
+  0x341811C0:  F423 03E0    BICCC      R3, R3, #0x700000
+  0x341811C4:  431A         ORRCC      R2, R3
+  0x341811C6:  6022         STRCC      R2, [R4]
+  0x341811C8:  070A         LSLS       R2, R1, #28
+  0x341811CA:  F57F ADB4    BPL.W      46L8                      ; 0x34180D36
+
.L44:
+  0x341811CE:  6902         LDR        R2, [R0, #16]
+  0x341811D0:  6823         LDR        R3, [R4]
+  0x341811D2:  F003 0307    AND        R3, R3, #7
+  0x341811D6:  429A         CMP        R2, R3
+  0x341811D8:  BF3F         ITTTT      CC
+  0x341811DA:  6823         LDRCC      R3, [R4]
+  0x341811DC:  F023 0307    BICCC      R3, R3, #7
+  0x341811E0:  431A         ORRCC      R2, R3
+  0x341811E2:  6022         STRCC      R2, [R4]
+  0x341811E4:  06CA         LSLS       R2, R1, #27
+  0x341811E6:  F57F ADA9    BPL.W      46L9                      ; 0x34180D3C
+
.L45:
+  0x341811EA:  6942         LDR        R2, [R0, #20]
+  0x341811EC:  6823         LDR        R3, [R4]
+  0x341811EE:  F003 0370    AND        R3, R3, #112
+  0x341811F2:  429A         CMP        R2, R3
+  0x341811F4:  BF3F         ITTTT      CC
+  0x341811F6:  6823         LDRCC      R3, [R4]
+  0x341811F8:  F023 0370    BICCC      R3, R3, #112
+  0x341811FC:  431A         ORRCC      R2, R3
+  0x341811FE:  6022         STRCC      R2, [R4]
+  0x34181200:  068A         LSLS       R2, R1, #26
+  0x34181202:  F57F AD9E    BPL.W      46L10                     ; 0x34180D42
+
.L46:
+  0x34181206:  6982         LDR        R2, [R0, #24]
+  0x34181208:  6823         LDR        R3, [R4]
+  0x3418120A:  F403 43E0    AND        R3, R3, #0x7000
+  0x3418120E:  429A         CMP        R2, R3
+  0x34181210:  BF3F         ITTTT      CC
+  0x34181212:  6823         LDRCC      R3, [R4]
+  0x34181214:  F423 43E0    BICCC      R3, R3, #0x7000
+  0x34181218:  431A         ORRCC      R2, R3
+  0x3418121A:  6022         STRCC      R2, [R4]
+  0x3418121C:  0649         LSLS       R1, R1, #25
+  0x3418121E:  F53F AD92    BMI.W      46L11                     ; 0x34180D46
+  0x34181222:  E59B         B          46L12                     ; 0x34180D5C
+
.L47:
+  0x34181224:  4606         MOV        R6, R0
+  0x34181226:  6EE0         LDR        R0, [R4, #108]
+  0x34181228:  F000 40E0    AND        R0, R0, #0x70000000
+  0x3418122C:  F000 F88E    BL         RCCEx_GetPLLSourceFreq   ; 0x3418134C
+  0x34181230:  0001         MOVS       R1, R0
+  0x34181232:  F43F AECC    BEQ.W      46L27                     ; 0x34180FCE
+  0x34181236:  6EE0         LDR        R0, [R4, #108]
+  0x34181238:  F3C0 5205    UBFX       R2, R0, #20, #6
+  0x3418123C:  4630         MOV        R0, R6
+  0x3418123E:  2A00         CMP        R2, #0
+  0x34181240:  F43F AF7D    BEQ.W      46L36                     ; 0x3418113E
+  0x34181244:  EE00 1A10    VMOV       S0, R1
+  0x34181248:  6EE1         LDR        R1, [R4, #108]
+  0x3418124A:  6F23         LDR        R3, [R4, #112]
+  0x3418124C:  F3C1 210B    UBFX       R1, R1, #8, #12
+  0x34181250:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x34181254:  EE01 1A10    VMOV       S2, R1
+  0x34181258:  6F61         LDR        R1, [R4, #116]
+  0x3418125A:  EE02 3A10    VMOV       S4, R3
+  0x3418125E:  6F63         LDR        R3, [R4, #116]
+
.L48:
+  0x34181260:  EEB8 2A42    VCVT.F32.U32 S4, S4
+  0x34181264:  ED9F 3A13    VLDR       S6, =0x33800000          ; [PC, #76] [0x341812B4]
+  0x34181268:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x3418126C:  EE22 2A03    VMUL.F32   S4, S4, S6
+  0x34181270:  EEB8 0A40    VCVT.F32.U32 S0, S0
+  0x34181274:  EE32 1A01    VADD.F32   S2, S4, S2
+  0x34181278:  F3C1 61C2    UBFX       R1, R1, #27, #3
+  0x3418127C:  EE21 0A00    VMUL.F32   S0, S2, S0
+  0x34181280:  EE01 2A10    VMOV       S2, R2
+  0x34181284:  F3C3 6302    UBFX       R3, R3, #24, #3
+  0x34181288:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x3418128C:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x34181290:  EE01 1A10    VMOV       S2, R1
+  0x34181294:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x34181298:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x3418129C:  EE01 3A10    VMOV       S2, R3
+  0x341812A0:  EEB8 1A41    VCVT.F32.U32 S2, S2
+  0x341812A4:  EE80 0A01    VDIV.F32   S0, S0, S2
+  0x341812A8:  EEBC 0AC0    VCVT.U32.F32 S0, S0
+  0x341812AC:  EE10 1A10    VMOV       R1, S0
+  0x341812B0:  E746         B          46L37                     ; 0x34181140
+  0x341812B2:  BF00         NOP
+  0x341812B4:  33800000     DC.W       0x33800000
+
+

Section .text.RCC_IC_CheckPLLSources from blto2_FSBL_lto.o, size=148, align=4

+ +
+
RCC_IC_CheckPLLSources:
+  0x341812B8:  F248 0204    MOVW       R2, #0x8004
+  0x341812BC:  EA4F 7030    ROR        R0, R0, #28
+  0x341812C0:  F2C5 6202    MOVT       R2, #0x5602
+  0x341812C4:  2803         CMP        R0, #3
+  0x341812C6:  D81F         BHI        46L3                      ; 0x34181308
+  0x341812C8:  E8DF F000    TBB        91PC, R0]
+  0x341812CC:  02           DC.B       0x02                     ; '\x02'
+  0x341812CD:  18           DC.B       0x18                     ; '\x18'
+  0x341812CE:  08           DC.B       0x08                     ; '\b'
+  0x341812CF:  11           DC.B       0x11                     ; '\x11'
+  0x341812D0:  4610         MOV        R0, R2
+  0x341812D2:  F850 3B7C    LDR        R3, [R0], #124
+  0x341812D6:  05DB         LSLS       R3, R3, #23
+  0x341812D8:  D505         BPL        46L1                      ; 0x341812E6
+  0x341812DA:  E00D         B          46L2                      ; 0x341812F8
+  0x341812DC:  4610         MOV        R0, R2
+  0x341812DE:  F850 3B9C    LDR        R3, [R0], #156
+  0x341812E2:  055B         LSLS       R3, R3, #21
+  0x341812E4:  D408         BMI        46L2                      ; 0x341812F8
+
.L1:
+  0x341812E6:  6800         LDR        R0, [R0]
+  0x341812E8:  F3C0 60C0    UBFX       R0, R0, #27, #1
+  0x341812EC:  E00D         B          46L4                      ; 0x3418130A
+  0x341812EE:  4610         MOV        R0, R2
+  0x341812F0:  F850 3BAC    LDR        R3, [R0], #172
+  0x341812F4:  051B         LSLS       R3, R3, #20
+  0x341812F6:  D5F6         BPL        46L1                      ; 0x341812E6
+
.L2:
+  0x341812F8:  2001         MOVS       R0, #1
+  0x341812FA:  E006         B          46L4                      ; 0x3418130A
+  0x341812FC:  4610         MOV        R0, R2
+  0x341812FE:  F850 3B8C    LDR        R3, [R0], #140
+  0x34181302:  059B         LSLS       R3, R3, #22
+  0x34181304:  D4F8         BMI        46L2                      ; 0x341812F8
+  0x34181306:  E7EE         B          46L1                      ; 0x341812E6
+
.L3:
+  0x34181308:  2000         MOVS       R0, #0
+
.L4:
+  0x3418130A:  EA4F 7131    ROR        R1, R1, #28
+  0x3418130E:  2903         CMP        R1, #3
+  0x34181310:  D81A         BHI        46L7                      ; 0x34181348
+  0x34181312:  E8DF F001    TBB        91PC, R1]
+  0x34181316:  02           DC.B       0x02                     ; '\x02'
+  0x34181317:  14           DC.B       0x14                     ; '\x14'
+  0x34181318:  07           DC.B       0x07                     ; '\x07'
+  0x34181319:  0F           DC.B       0x0F                     ; '\x0F'
+  0x3418131A:  F852 1B7C    LDR        R1, [R2], #124
+  0x3418131E:  05C9         LSLS       R1, R1, #23
+  0x34181320:  D504         BPL        46L5                      ; 0x3418132C
+  0x34181322:  4770         BX         LR
+  0x34181324:  F852 1B9C    LDR        R1, [R2], #156
+  0x34181328:  0549         LSLS       R1, R1, #21
+  0x3418132A:  D402         BMI        46L6                      ; 0x34181332
+
.L5:
+  0x3418132C:  6811         LDR        R1, [R2]
+  0x3418132E:  EA00 60D1    AND.W      R0, R0, R1, LSR #27
+
.L6:
+  0x34181332:  4770         BX         LR
+  0x34181334:  F852 1BAC    LDR        R1, [R2], #172
+  0x34181338:  0509         LSLS       R1, R1, #20
+  0x3418133A:  D5F7         BPL        46L5                      ; 0x3418132C
+  0x3418133C:  4770         BX         LR
+  0x3418133E:  F852 1B8C    LDR        R1, [R2], #140
+  0x34181342:  0589         LSLS       R1, R1, #22
+  0x34181344:  D5F2         BPL        46L5                      ; 0x3418132C
+  0x34181346:  4770         BX         LR
+
.L7:
+  0x34181348:  2000         MOVS       R0, #0
+  0x3418134A:  4770         BX         LR
+
+

Section .text.RCCEx_GetPLLSourceFreq from blto2_FSBL_lto.o, size=128, align=4

+ +
+
RCCEx_GetPLLSourceFreq:
+  0x3418134C:  EA4F 7030    ROR        R0, R0, #28
+  0x34181350:  2803         CMP        R0, #3
+  0x34181352:  D82D         BHI        46L1                      ; 0x341813B0
+  0x34181354:  E8DF F000    TBB        91PC, R0]
+  0x34181358:  02           DC.B       0x02                     ; '\x02'
+  0x34181359:  25           DC.B       0x25                     ; '%'
+  0x3418135A:  13           DC.B       0x13                     ; '\x13'
+  0x3418135B:  20           DC.B       0x20                     ; ' '
+  0x3418135C:  F248 0004    MOVW       R0, #0x8004
+  0x34181360:  F2C5 6002    MOVT       R0, #0x5602
+  0x34181364:  6801         LDR        R1, [R0]
+  0x34181366:  0709         LSLS       R1, R1, #28
+  0x34181368:  D522         BPL        46L1                      ; 0x341813B0
+  0x3418136A:  6C40         LDR        R0, [R0, #68]
+  0x3418136C:  F249 0100    MOVW       R1, #0x9000
+  0x34181370:  F2C0 31D0    MOVT       R1, #0x03D0
+  0x34181374:  F3C0 10C1    UBFX       R0, R0, #7, #2
+  0x34181378:  FA21 F000    LSR.W      R0, R1, R0
+  0x3418137C:  4770         BX         LR
+  0x3418137E:  F248 0004    MOVW       R0, #0x8004
+  0x34181382:  F646 4100    MOVW       R1, #0x6C00
+  0x34181386:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418138A:  6800         LDR        R0, [R0]
+  0x3418138C:  F2C0 21DC    MOVT       R1, #0x02DC
+  0x34181390:  06C0         LSLS       R0, R0, #27
+  0x34181392:  EA01 70E0    AND.W      R0, R1, R0, ASR #31
+  0x34181396:  4770         BX         LR
+  0x34181398:  F248 0000    MOVW       R0, #0x8000
+  0x3418139C:  F2C0 00BB    MOVT       R0, #187
+  0x341813A0:  4770         BX         LR
+  0x341813A2:  F248 0004    MOVW       R0, #0x8004
+  0x341813A6:  F2C5 6002    MOVT       R0, #0x5602
+  0x341813AA:  6801         LDR        R1, [R0]
+  0x341813AC:  0749         LSLS       R1, R1, #29
+  0x341813AE:  D401         BMI        46L2                      ; 0x341813B4
+
.L1:
+  0x341813B0:  2000         MOVS       R0, #0
+  0x341813B2:  4770         BX         LR
+
.L2:
+  0x341813B4:  6C00         LDR        R0, [R0, #64]
+  0x341813B6:  0580         LSLS       R0, R0, #22
+  0x341813B8:  F242 4000    MOVW       R0, #0x2400
+  0x341813BC:  F2C0 00F4    MOVT       R0, #244
+  0x341813C0:  BF5C         ITT        PL
+  0x341813C2:  F640 1000    MOVWPL     R0, #0x0900
+  0x341813C6:  F2C0 003D    MOVTPL     R0, #61
+  0x341813CA:  4770         BX         LR
+
+

Section .rodata..Lswitch.table.HAL_GPIO_DeInit from blto2_FSBL_lto.o, size=64, align=4

+ +
+  0x341813CC:  00           DC.B       0x00                     ; '\0'
+  0x341813CD:  00           DC.B       0x00                     ; '\0'
+  0x341813CE:  00           DC.B       0x00                     ; '\0'
+  0x341813CF:  00           DC.B       0x00                     ; '\0'
+  0x341813D0:  01           DC.B       0x01                     ; '\x01'
+  0x341813D1:  00           DC.B       0x00                     ; '\0'
+  0x341813D2:  00           DC.B       0x00                     ; '\0'
+  0x341813D3:  00           DC.B       0x00                     ; '\0'
+  0x341813D4:  02           DC.B       0x02                     ; '\x02'
+  0x341813D5:  00           DC.B       0x00                     ; '\0'
+  0x341813D6:  00           DC.B       0x00                     ; '\0'
+  0x341813D7:  00           DC.B       0x00                     ; '\0'
+  0x341813D8:  03           DC.B       0x03                     ; '\x03'
+  0x341813D9:  00           DC.B       0x00                     ; '\0'
+  0x341813DA:  00           DC.B       0x00                     ; '\0'
+  0x341813DB:  00           DC.B       0x00                     ; '\0'
+  0x341813DC:  04           DC.B       0x04                     ; '\x04'
+  0x341813DD:  00           DC.B       0x00                     ; '\0'
+  0x341813DE:  00           DC.B       0x00                     ; '\0'
+  0x341813DF:  00           DC.B       0x00                     ; '\0'
+  0x341813E0:  05           DC.B       0x05                     ; '\x05'
+  0x341813E1:  00           DC.B       0x00                     ; '\0'
+  0x341813E2:  00           DC.B       0x00                     ; '\0'
+  0x341813E3:  00           DC.B       0x00                     ; '\0'
+  0x341813E4:  06           DC.B       0x06                     ; '\x06'
+  0x341813E5:  00           DC.B       0x00                     ; '\0'
+  0x341813E6:  00           DC.B       0x00                     ; '\0'
+  0x341813E7:  00           DC.B       0x00                     ; '\0'
+  0x341813E8:  07           DC.B       0x07                     ; '\x07'
+  0x341813E9:  00           DC.B       0x00                     ; '\0'
+  0x341813EA:  00           DC.B       0x00                     ; '\0'
+  0x341813EB:  00           DC.B       0x00                     ; '\0'
+  0x341813EC:  00           DC.B       0x00                     ; '\0'
+  0x341813ED:  00           DC.B       0x00                     ; '\0'
+  0x341813EE:  00           DC.B       0x00                     ; '\0'
+  0x341813EF:  00           DC.B       0x00                     ; '\0'
+  0x341813F0:  00           DC.B       0x00                     ; '\0'
+  0x341813F1:  00           DC.B       0x00                     ; '\0'
+  0x341813F2:  00           DC.B       0x00                     ; '\0'
+  0x341813F3:  00           DC.B       0x00                     ; '\0'
+  0x341813F4:  00           DC.B       0x00                     ; '\0'
+  0x341813F5:  00           DC.B       0x00                     ; '\0'
+  0x341813F6:  00           DC.B       0x00                     ; '\0'
+  0x341813F7:  00           DC.B       0x00                     ; '\0'
+  0x341813F8:  00           DC.B       0x00                     ; '\0'
+  0x341813F9:  00           DC.B       0x00                     ; '\0'
+  0x341813FA:  00           DC.B       0x00                     ; '\0'
+  0x341813FB:  00           DC.B       0x00                     ; '\0'
+  0x341813FC:  00           DC.B       0x00                     ; '\0'
+  0x341813FD:  00           DC.B       0x00                     ; '\0'
+  0x341813FE:  00           DC.B       0x00                     ; '\0'
+  0x341813FF:  00           DC.B       0x00                     ; '\0'
+  0x34181400:  08           DC.B       0x08                     ; '\b'
+  0x34181401:  00           DC.B       0x00                     ; '\0'
+  0x34181402:  00           DC.B       0x00                     ; '\0'
+  0x34181403:  00           DC.B       0x00                     ; '\0'
+  0x34181404:  09           DC.B       0x09                     ; '\t'
+  0x34181405:  00           DC.B       0x00                     ; '\0'
+  0x34181406:  00           DC.B       0x00                     ; '\0'
+  0x34181407:  00           DC.B       0x00                     ; '\0'
+  0x34181408:  0A           DC.B       0x0A                     ; '\n'
+  0x34181409:  00           DC.B       0x00                     ; '\0'
+  0x3418140A:  00           DC.B       0x00                     ; '\0'
+  0x3418140B:  00           DC.B       0x00                     ; '\0'
+
+

Section .rodata..Lswitch.table.RCC_PLL_Config from blto2_FSBL_lto.o, size=12, align=4

+ +
+  0x3418140C:  03           DC.B       0x03                     ; '\x03'
+  0x3418140D:  00           DC.B       0x00                     ; '\0'
+  0x3418140E:  00           DC.B       0x00                     ; '\0'
+  0x3418140F:  00           DC.B       0x00                     ; '\0'
+  0x34181410:  02           DC.B       0x02                     ; '\x02'
+  0x34181411:  00           DC.B       0x00                     ; '\0'
+  0x34181412:  00           DC.B       0x00                     ; '\0'
+  0x34181413:  00           DC.B       0x00                     ; '\0'
+  0x34181414:  04           DC.B       0x04                     ; '\x04'
+  0x34181415:  00           DC.B       0x00                     ; '\0'
+  0x34181416:  00           DC.B       0x00                     ; '\0'
+  0x34181417:  00           DC.B       0x00                     ; '\0'
+
+

Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

+ +
+
_start:
+  0x34181418:  4C03         LDR        R4, =0x341820CC          ; [PC, #12] [0x34181428] 
+
.L1:
+  0x3418141A:  6820         LDR        R0, [R4]
+  0x3418141C:  3404         ADDS       R4, #4
+  0x3418141E:  4780         BLX        R0
+  0x34181420:  E7FB         B          46L1                      ; 0x3418141A
+
__SEGGER_init_done:
+__startup_complete:
+  0x34181422:  F7FF F993    BL         main                     ; 0x3418074C
+
exit:
+  0x34181426:  E7FE         B          exit                     ; 0x34181426
+  0x34181428:  341820CC     DC.W       341820CC               ; R_ARM_ABS32
+
+

Section .init.Reset_Handler from STM32N6xx_Startup.o, size=44, align=4

+ +
+
reset_handler:
+Reset_Handler:
+  0x3418142C:  4909         LDR        R1, =0x341FE000          ; [PC, #36] [0x34181454] 
+  0x3418142E:  F381 880A    MSR        MSPLIM, R1
+  0x34181432:  F04F 0100    MOV.W      R1, #0
+  0x34181436:  F381 880B    MSR        PSPLIM, R1
+  0x3418143A:  F000 F845    BL         SystemInit               ; 0x341814C8
+  0x3418143E:  F64E 5088    MOVW       R0, #0xED88
+  0x34181442:  F2CE 0000    MOVT       R0, #0xE000
+  0x34181446:  6801         LDR        R1, [R0]
+  0x34181448:  F451 0170    ORRS       R1, R1, #0xF00000
+  0x3418144C:  6001         STR        R1, [R0]
+  0x3418144E:  F7FF FFE3    BL         _start                   ; 0x34181418
+  0x34181452:  00           DC.B       0x00                     ; '\0'
+  0x34181453:  00           DC.B       0x00                     ; '\0'
+  0x34181454:  341FE000     DC.W       341FE000               ; R_ARM_ABS32
+
+

Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4

+ +
+
__aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x34181458:  2200         MOVS       R2, #0
+
__aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x3418145A:  000B         MOVS       R3, R1
+  0x3418145C:  0011         MOVS       R1, R2
+  0x3418145E:  001A         MOVS       R2, R3
+
memset:
+  0x34181460:  4684         MOV        R12, R0
+  0x34181462:  B35A         CBZ        R2, .L7                  ; 0x341814BC
+
.L1:
+  0x34181464:  0783         LSLS       R3, R0, #30
+  0x34181466:  D004         BEQ        46L2                      ; 0x34181472
+  0x34181468:  F800 1B01    STRB       R1, [R0], #1
+  0x3418146C:  1E52         SUBS       R2, R2, #1
+  0x3418146E:  D1F9         BNE        46L1                      ; 0x34181464
+  0x34181470:  E024         B          46L7                      ; 0x341814BC
+
.L2:
+  0x34181472:  B2C9         UXTB       R1, R1
+  0x34181474:  EA41 2101    ORR.W      R1, R1, R1, LSL #8
+  0x34181478:  EA41 4101    ORR.W      R1, R1, R1, LSL #16
+  0x3418147C:  2A20         CMP        R2, #32
+  0x3418147E:  D311         BCC        46L4                      ; 0x341814A4
+  0x34181480:  3A20         SUBS       R2, #32
+  0x34181482:  E92D 03F0    PUSH.W     123R4-R9}
+  0x34181486:  460B         MOV        R3, R1
+  0x34181488:  460C         MOV        R4, R1
+  0x3418148A:  460D         MOV        R5, R1
+  0x3418148C:  460E         MOV        R6, R1
+  0x3418148E:  460F         MOV        R7, R1
+  0x34181490:  4688         MOV        R8, R1
+  0x34181492:  4689         MOV        R9, R1
+
.L3:
+  0x34181494:  E8A0 03FA    STM.W      R0!, {R1, R3-R9}
+  0x34181498:  3A20         SUBS       R2, #32
+  0x3418149A:  D2FB         BCS        46L3                      ; 0x34181494
+  0x3418149C:  E8BD 03F0    POP.W      123R4-R9}
+  0x341814A0:  3220         ADDS       R2, #32
+  0x341814A2:  D00B         BEQ        46L7                      ; 0x341814BC
+
.L4:
+  0x341814A4:  2A04         CMP        R2, #4
+  0x341814A6:  D305         BCC        46L6                      ; 0x341814B4
+
.L5:
+  0x341814A8:  F840 1B04    STR        R1, [R0], #4
+  0x341814AC:  1F12         SUBS       R2, R2, #4
+  0x341814AE:  D005         BEQ        46L7                      ; 0x341814BC
+  0x341814B0:  2A04         CMP        R2, #4
+  0x341814B2:  D2F9         BCS        46L5                      ; 0x341814A8
+
.L6:
+  0x341814B4:  F800 1B01    STRB       R1, [R0], #1
+  0x341814B8:  1E52         SUBS       R2, R2, #1
+  0x341814BA:  D1FB         BNE        46L6                      ; 0x341814B4
+
.L7:
+  0x341814BC:  4660         MOV        R0, R12
+  0x341814BE:  4770         BX         LR
+
+

Section .text.NMI_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
NMI_Handler:
+HardFault_Handler:
+MemManage_Handler:
+BusFault_Handler:
+UsageFault_Handler:
+PVD_PVM_IRQHandler:
+DTS_IRQHandler:
+RCC_IRQHandler:
+LOCKUP_IRQHandler:
+CACHE_ECC_IRQHandler:
+TCM_ECC_IRQHandler:
+BCK_ECC_IRQHandler:
+FPU_IRQHandler:
+RTC_S_IRQHandler:
+TAMP_IRQHandler:
+RIFSC_TAMPER_IRQHandler:
+IAC_IRQHandler:
+RCC_S_IRQHandler:
+RTC_IRQHandler:
+IWDG_IRQHandler:
+WWDG_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+EXTI5_IRQHandler:
+EXTI6_IRQHandler:
+EXTI7_IRQHandler:
+EXTI8_IRQHandler:
+EXTI9_IRQHandler:
+EXTI10_IRQHandler:
+EXTI11_IRQHandler:
+EXTI12_IRQHandler:
+EXTI13_IRQHandler:
+EXTI14_IRQHandler:
+EXTI15_IRQHandler:
+SAES_IRQHandler:
+CRYP_IRQHandler:
+PKA_IRQHandler:
+HASH_IRQHandler:
+RNG_IRQHandler:
+MCE1_IRQHandler:
+MCE2_IRQHandler:
+MCE3_IRQHandler:
+MCE4_IRQHandler:
+ADC1_2_IRQHandler:
+CSI_IRQHandler:
+DCMIPP_IRQHandler:
+PAHB_ERR_IRQHandler:
+NPU0_IRQHandler:
+NPU1_IRQHandler:
+NPU2_IRQHandler:
+NPU3_IRQHandler:
+CACHEAXI_IRQHandler:
+LTDC_LO_IRQHandler:
+LTDC_LO_ERR_IRQHandler:
+DMA2D_IRQHandler:
+JPEG_IRQHandler:
+VENC_IRQHandler:
+GFXMMU_IRQHandler:
+GFXTIM_IRQHandler:
+GPU2D_IRQHandler:
+GPU2D_ER_IRQHandler:
+ICACHE_IRQHandler:
+HPDMA1_Channel0_IRQHandler:
+HPDMA1_Channel1_IRQHandler:
+HPDMA1_Channel2_IRQHandler:
+HPDMA1_Channel3_IRQHandler:
+HPDMA1_Channel4_IRQHandler:
+HPDMA1_Channel5_IRQHandler:
+HPDMA1_Channel6_IRQHandler:
+HPDMA1_Channel7_IRQHandler:
+HPDMA1_Channel8_IRQHandler:
+HPDMA1_Channel9_IRQHandler:
+HPDMA1_Channel10_IRQHandler:
+HPDMA1_Channel11_IRQHandler:
+HPDMA1_Channel12_IRQHandler:
+HPDMA1_Channel13_IRQHandler:
+HPDMA1_Channel14_IRQHandler:
+HPDMA1_Channel15_IRQHandler:
+GPDMA1_Channel0_IRQHandler:
+GPDMA1_Channel1_IRQHandler:
+GPDMA1_Channel2_IRQHandler:
+GPDMA1_Channel3_IRQHandler:
+GPDMA1_Channel4_IRQHandler:
+GPDMA1_Channel5_IRQHandler:
+GPDMA1_Channel6_IRQHandler:
+GPDMA1_Channel7_IRQHandler:
+GPDMA1_Channel8_IRQHandler:
+GPDMA1_Channel9_IRQHandler:
+GPDMA1_Channel10_IRQHandler:
+GPDMA1_Channel11_IRQHandler:
+GPDMA1_Channel12_IRQHandler:
+GPDMA1_Channel13_IRQHandler:
+GPDMA1_Channel14_IRQHandler:
+GPDMA1_Channel15_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+I2C3_EV_IRQHandler:
+I2C3_ER_IRQHandler:
+I2C4_EV_IRQHandler:
+I2C4_ER_IRQHandler:
+I3C1_EV_IRQHandler:
+I3C1_ER_IRQHandler:
+I3C2_EV_IRQHandler:
+I3C2_ER_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_CCU_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+TIM5_IRQHandler:
+TIM6_IRQHandler:
+TIM7_IRQHandler:
+TIM8_BRK_IRQHandler:
+TIM8_UP_IRQHandler:
+TIM8_TRG_CCU_IRQHandler:
+TIM8_CC_IRQHandler:
+TIM9_IRQHandler:
+TIM10_IRQHandler:
+TIM11_IRQHandler:
+TIM12_IRQHandler:
+TIM13_IRQHandler:
+TIM14_IRQHandler:
+TIM15_IRQHandler:
+TIM16_IRQHandler:
+TIM17_IRQHandler:
+TIM18_IRQHandler:
+LPTIM1_IRQHandler:
+LPTIM2_IRQHandler:
+LPTIM3_IRQHandler:
+LPTIM4_IRQHandler:
+LPTIM5_IRQHandler:
+ADF1_FLT0_IRQHandler:
+MDF1_FLT0_IRQHandler:
+MDF1_FLT1_IRQHandler:
+MDF1_FLT2_IRQHandler:
+MDF1_FLT3_IRQHandler:
+MDF1_FLT4_IRQHandler:
+MDF1_FLT5_IRQHandler:
+SAI1_A_IRQHandler:
+SAI1_B_IRQHandler:
+SAI2_A_IRQHandler:
+SAI2_B_IRQHandler:
+SPDIFRX_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+SPI3_IRQHandler:
+SPI4_IRQHandler:
+SPI5_IRQHandler:
+SPI6_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+UART4_IRQHandler:
+UART5_IRQHandler:
+USART6_IRQHandler:
+UART7_IRQHandler:
+UART8_IRQHandler:
+UART9_IRQHandler:
+USART10_IRQHandler:
+LPUART1_IRQHandler:
+XSPI1_IRQHandler:
+XSPI2_IRQHandler:
+XSPI3_IRQHandler:
+FMC_IRQHandler:
+SDMMC1_IRQHandler:
+SDMMC2_IRQHandler:
+UCPD1_IRQHandler:
+USB1_OTG_HS_IRQHandler:
+USB2_OTG_HS_IRQHandler:
+ETH1_IRQHandler:
+FDCAN1_IT0_IRQHandler:
+FDCAN1_IT1_IRQHandler:
+FDCAN2_IT0_IRQHandler:
+FDCAN2_IT1_IRQHandler:
+FDCAN3_IT0_IRQHandler:
+FDCAN3_IT1_IRQHandler:
+FDCAN_CU_IRQHandler:
+MDIOS_IRQHandler:
+DCMI_PSSI_IRQHandler:
+WAKEUP_PIN_IRQHandler:
+CTI_INT0_IRQHandler:
+CTI_INT1_IRQHandler:
+LTDC_UP_IRQHandler:
+LTDC_UP_ERR_IRQHandler:
+  0x341814C0:  E7FE         B          NMI_Handler              ; Dedupe identical section .init.LTDC_UP_ERR_IRQHandler
+
+

Section .text.SVC_Handler from blto2_FSBL_lto.o, size=2, align=4

+ +
+
SVC_Handler:
+DebugMon_Handler:
+PendSV_Handler:
+  0x341814C4:  4770         BX         LR                       ; Dedupe identical section .text.PendSV_Handler
+
+

Section .text.SystemInit from blto2_FSBL_lto.o, size=302, align=4

+ +
+
SystemInit:
+  0x341814C8:  B530         PUSH       123R4-R5, LR}
+  0x341814CA:  F240 4100    MOVW       R1, #0x0400              ; 0x34180400 = g_pfnVectors
+  0x341814CE:  F64E 50D8    MOVW       R0, #0xEDD8
+  0x341814D2:  F648 2C18    MOVW       R12, #0x8A18
+  0x341814D6:  F2C3 4118    MOVT       R1, #0x3418              ; 0x34180400 = g_pfnVectors
+  0x341814DA:  F2CE 0000    MOVT       R0, #0xE000
+  0x341814DE:  2200         MOVS       R2, #0
+  0x341814E0:  F2C5 6C02    MOVT       R12, #0x5602
+  0x341814E4:  2302         MOVS       R3, #2
+  0x341814E6:  F840 1CD0    STR        R1, [R0, #-208]
+  0x341814EA:  2101         MOVS       R1, #1
+  0x341814EC:  F60C 0E08    ADDW       LR, R12, #0x0808
+  0x341814F0:  F8CC 1000    STR.W      R1, [R12]
+  0x341814F4:  F8CC 1800    STR.W      R1, [R12, #0x0800]
+  0x341814F8:  F8CE 1038    STR.W      R1, [LR, #56]
+  0x341814FC:  6002         STR        R2, [R0]
+  0x341814FE:  6042         STR        R2, [R0, #4]
+  0x34181500:  6082         STR        R2, [R0, #8]
+  0x34181502:  6001         STR        R1, [R0]
+  0x34181504:  6042         STR        R2, [R0, #4]
+  0x34181506:  6082         STR        R2, [R0, #8]
+  0x34181508:  6003         STR        R3, [R0]
+  0x3418150A:  2303         MOVS       R3, #3
+  0x3418150C:  6042         STR        R2, [R0, #4]
+  0x3418150E:  6082         STR        R2, [R0, #8]
+  0x34181510:  6003         STR        R3, [R0]
+  0x34181512:  2304         MOVS       R3, #4
+  0x34181514:  6042         STR        R2, [R0, #4]
+  0x34181516:  6082         STR        R2, [R0, #8]
+  0x34181518:  6003         STR        R3, [R0]
+  0x3418151A:  2305         MOVS       R3, #5
+  0x3418151C:  6042         STR        R2, [R0, #4]
+  0x3418151E:  6082         STR        R2, [R0, #8]
+  0x34181520:  6003         STR        R3, [R0]
+  0x34181522:  2306         MOVS       R3, #6
+  0x34181524:  6042         STR        R2, [R0, #4]
+  0x34181526:  6082         STR        R2, [R0, #8]
+  0x34181528:  6003         STR        R3, [R0]
+  0x3418152A:  2307         MOVS       R3, #7
+  0x3418152C:  6042         STR        R2, [R0, #4]
+  0x3418152E:  6082         STR        R2, [R0, #8]
+  0x34181530:  6003         STR        R3, [R0]
+  0x34181532:  6042         STR        R2, [R0, #4]
+  0x34181534:  6082         STR        R2, [R0, #8]
+  0x34181536:  F5AC 62F4    SUB.W      R2, R12, #0x07A0
+  0x3418153A:  F8CC 1060    STR.W      R1, [R12, #96]
+  0x3418153E:  6813         LDR        R3, [R2]
+  0x34181540:  F850 4CD0    LDR        R4, [R0, #-208]
+  0x34181544:  F248 0310    MOVW       R3, #0x8010
+  0x34181548:  F2C5 6300    MOVT       R3, #0x5600
+  0x3418154C:  601C         STR        R4, [R3]
+  0x3418154E:  F644 043C    MOVW       R4, #0x483C
+  0x34181552:  F2C5 6402    MOVT       R4, #0x5602
+  0x34181556:  F854 5C08    LDR        R5, [R4, #-8]
+  0x3418155A:  F445 7580    ORR        R5, R5, #0x0100
+  0x3418155E:  F844 5C08    STR        R5, [R4, #-8]
+  0x34181562:  F854 5C04    LDR        R5, [R4, #-4]
+  0x34181566:  F445 7580    ORR        R5, R5, #0x0100
+  0x3418156A:  F844 5C04    STR        R5, [R4, #-4]
+  0x3418156E:  6825         LDR        R5, [R4]
+  0x34181570:  F445 7540    ORR        R5, R5, #0x0300
+  0x34181574:  6025         STR        R5, [R4]
+  0x34181576:  F240 2587    MOVW       R5, #0x0287
+  0x3418157A:  645D         STR        R5, [R3, #68]
+  0x3418157C:  64DD         STR        R5, [R3, #76]
+  0x3418157E:  635D         STR        R5, [R3, #52]
+  0x34181580:  63DD         STR        R5, [R3, #60]
+  0x34181582:  655D         STR        R5, [R3, #84]
+  0x34181584:  6825         LDR        R5, [R4]
+  0x34181586:  F445 5580    ORR        R5, R5, #0x1000
+  0x3418158A:  6025         STR        R5, [R4]
+  0x3418158C:  6825         LDR        R5, [R4]
+  0x3418158E:  F045 0510    ORR        R5, R5, #16
+  0x34181592:  6025         STR        R5, [R4]
+  0x34181594:  6824         LDR        R4, [R4]
+  0x34181596:  F852 4C04    LDR        R4, [R2, #-4]
+  0x3418159A:  F444 4400    ORR        R4, R4, #0x8000
+  0x3418159E:  F842 4C04    STR        R4, [R2, #-4]
+  0x341815A2:  6814         LDR        R4, [R2]
+  0x341815A4:  F044 0410    ORR        R4, R4, #16
+  0x341815A8:  6014         STR        R4, [R2]
+  0x341815AA:  6814         LDR        R4, [R2]
+  0x341815AC:  6814         LDR        R4, [R2]
+  0x341815AE:  F024 0410    BIC        R4, R4, #16
+  0x341815B2:  6014         STR        R4, [R2]
+  0x341815B4:  F44F 5240    MOV.W      R2, #0x3000
+  0x341815B8:  F8CC 2008    STR.W      R2, [R12, #8]
+  0x341815BC:  F8CE 2000    STR.W      R2, [LR]
+  0x341815C0:  2240         MOVS       R2, #64
+  0x341815C2:  F8CC 100C    STR.W      R1, [R12, #12]
+  0x341815C6:  F8CE 1004    STR.W      R1, [LR, #4]
+  0x341815CA:  F8CE 1044    STR.W      R1, [LR, #68]
+  0x341815CE:  F8CE 203C    STR.W      R2, [LR, #60]
+  0x341815D2:  681A         LDR        R2, [R3]
+  0x341815D4:  F8CE 1058    STR.W      R1, [LR, #88]
+  0x341815D8:  F850 1C50    LDR        R1, [R0, #-80]
+  0x341815DC:  F441 0170    ORR        R1, R1, #0xF00000
+  0x341815E0:  F840 1C50    STR        R1, [R0, #-80]
+  0x341815E4:  F64E 5088    MOVW       R0, #0xED88
+  0x341815E8:  F2CE 0002    MOVT       R0, #0xE002
+  0x341815EC:  6801         LDR        R1, [R0]
+  0x341815EE:  F441 0170    ORR        R1, R1, #0xF00000
+  0x341815F2:  6001         STR        R1, [R0]
+  0x341815F4:  BD30         POP        123R4-R5, PC}
+
+

Section .text.HAL_GPIO_Init from blto2_FSBL_lto.o, size=418, align=4

+ +
+
HAL_GPIO_Init:
+  0x341815F8:  E92D 4FF0    PUSH.W     123R4-R11, LR}
+  0x341815FC:  B083         SUB        SP, SP, #12
+  0x341815FE:  680C         LDR        R4, [R1]
+  0x34181600:  2C00         CMP        R4, #0
+  0x34181602:  F000 80C7    BEQ.W      46L6                      ; 0x34181794
+  0x34181606:  F245 0E00    MOVW       LR, #0x5000
+  0x3418160A:  F100 4328    ADD.W      R3, R0, #0xA8000000
+  0x3418160E:  F2C5 6E02    MOVT       LR, #0x5602
+  0x34181612:  F103 73FF    ADD.W      R3, R3, #0x01FE0000
+  0x34181616:  EA4F 22B3    ROR        R2, R3, #10
+  0x3418161A:  F5AE 5380    SUB.W      R3, LR, #0x1000
+  0x3418161E:  4298         CMP        R0, R3
+  0x34181620:  BF14         ITE        NE
+  0x34181622:  2310         MOVNE      R3, #16
+  0x34181624:  230B         MOVEQ      R3, #11
+  0x34181626:  B297         UXTH       R7, R2
+  0x34181628:  F24E 06FF    MOVW       R6, #0xE0FF
+  0x3418162C:  9302         STR        R3, [SP, #8]
+  0x3418162E:  2500         MOVS       R5, #0
+  0x34181630:  2A10         CMP        R2, #16
+  0x34181632:  EA5F 932F    CSET       R3, CC
+  0x34181636:  FA26 F707    LSR.W      R7, R6, R7
+  0x3418163A:  9200         STR        R2, [SP, #0]
+  0x3418163C:  EA03 0207    AND.W      R2, R3, R7
+  0x34181640:  9201         STR        R2, [SP, #4]
+  0x34181642:  E084         B          46L5                      ; 0x3418174E
+
.L1:
+  0x34181644:  F1BB 0F03    CMP.W      R11, #3
+  0x34181648:  BF08         IT         EQ
+  0x3418164A:  F1BC 0F01    CMPEQ.W    R12, #1
+  0x3418164E:  D024         BEQ        46L3                      ; 0x3418169A
+  0x34181650:  006B         LSLS       R3, R5, #1
+  0x34181652:  2203         MOVS       R2, #3
+  0x34181654:  FA02 F303    LSL.W      R3, R2, R3
+  0x34181658:  43DC         MVNS       R4, R3
+
.L2:
+  0x3418165A:  68C3         LDR        R3, [R0, #12]
+  0x3418165C:  4023         ANDS       R3, R4
+  0x3418165E:  006C         LSLS       R4, R5, #1
+  0x34181660:  FA0C F604    LSL.W      R6, R12, R4
+  0x34181664:  4333         ORRS       R3, R6
+  0x34181666:  F1BB 0F02    CMP.W      R11, #2
+  0x3418166A:  60C3         STR        R3, [R0, #12]
+  0x3418166C:  D115         BNE        46L3                      ; 0x3418169A
+  0x3418166E:  F06F 0203    MVN        R2, #3
+  0x34181672:  EA02 0655    AND.W      R6, R2, R5, LSR #1
+  0x34181676:  221C         MOVS       R2, #28
+  0x34181678:  690B         LDR        R3, [R1, #16]
+  0x3418167A:  EA02 0485    AND.W      R4, R2, R5, LSL #2
+  0x3418167E:  220F         MOVS       R2, #15
+  0x34181680:  40A3         LSLS       R3, R4
+  0x34181682:  FA02 F404    LSL.W      R4, R2, R4
+  0x34181686:  F100 0220    ADD.W      R2, R0, #32
+  0x3418168A:  5997         LDR        R7, [R2, R6]
+  0x3418168C:  43A7         BICS       R7, R4
+  0x3418168E:  433B         ORRS       R3, R7
+  0x34181690:  5193         STR        R3, [R2, R6]
+  0x34181692:  F8D1 9004    LDR.W      R9, [R1, #4]
+  0x34181696:  F009 0B03    AND        R11, R9, #3
+
.L3:
+  0x3418169A:  006B         LSLS       R3, R5, #1
+  0x3418169C:  2203         MOVS       R2, #3
+  0x3418169E:  6806         LDR        R6, [R0]
+  0x341816A0:  FA0B F703    LSL.W      R7, R11, R3
+  0x341816A4:  FA02 F303    LSL.W      R3, R2, R3
+  0x341816A8:  EA26 0303    BIC.W      R3, R6, R3
+  0x341816AC:  433B         ORRS       R3, R7
+  0x341816AE:  F419 3F40    TST        R9, #0x030000
+  0x341816B2:  6003         STR        R3, [R0]
+  0x341816B4:  D046         BEQ        46L4                      ; 0x34181744
+  0x341816B6:  F10E 0460    ADD.W      R4, LR, #96
+  0x341816BA:  F025 0303    BIC        R3, R5, #3
+  0x341816BE:  58E6         LDR        R6, [R4, R3]
+  0x341816C0:  E9DD 2301    LDRD       R2, R3, [SP, #4]
+  0x341816C4:  2A00         CMP        R2, #0
+  0x341816C6:  BF1F         ITTTT      NE
+  0x341816C8:  9A00         LDRNE      R2, [SP, #0]
+  0x341816CA:  F241 33CC    MOVWNE     R3, #0x13CC              ; 0x341813CC = .rodata..Lswitch.table.HAL_GPIO_DeInit
+  0x341816CE:  F2C3 4318    MOVTNE     R3, #0x3418              ; 0x341813CC = .rodata..Lswitch.table.HAL_GPIO_DeInit
+  0x341816D2:  F853 3022    LDRNE.W    R3, [R3, R2, LSL #2]
+  0x341816D6:  2218         MOVS       R2, #24
+  0x341816D8:  EA02 07C5    AND.W      R7, R2, R5, LSL #3
+  0x341816DC:  220F         MOVS       R2, #15
+  0x341816DE:  40BB         LSLS       R3, R7
+  0x341816E0:  FA02 F707    LSL.W      R7, R2, R7
+  0x341816E4:  EA26 0707    BIC.W      R7, R6, R7
+  0x341816E8:  433B         ORRS       R3, R7
+  0x341816EA:  08AF         LSRS       R7, R5, #2
+  0x341816EC:  F844 3027    STR.W      R3, [R4, R7, LSL #2]
+  0x341816F0:  F8DE 3080    LDR.W      R3, [LR, #128]
+  0x341816F4:  684F         LDR        R7, [R1, #4]
+  0x341816F6:  03FE         LSLS       R6, R7, #15
+  0x341816F8:  BF4C         ITE        MI
+  0x341816FA:  EA43 0608    ORRMI.W    R6, R3, R8
+  0x341816FE:  EA23 0608    BICPL.W    R6, R3, R8
+  0x34181702:  F8CE 6080    STR.W      R6, [LR, #128]
+  0x34181706:  F8DE 3084    LDR.W      R3, [LR, #132]
+  0x3418170A:  03BE         LSLS       R6, R7, #14
+  0x3418170C:  BF4C         ITE        MI
+  0x3418170E:  EA43 0608    ORRMI.W    R6, R3, R8
+  0x34181712:  EA23 0608    BICPL.W    R6, R3, R8
+  0x34181716:  F8CE 6084    STR.W      R6, [LR, #132]
+  0x3418171A:  F8DE 3000    LDR.W      R3, [LR]
+  0x3418171E:  02FE         LSLS       R6, R7, #11
+  0x34181720:  BF4C         ITE        MI
+  0x34181722:  EA43 0608    ORRMI.W    R6, R3, R8
+  0x34181726:  EA23 0608    BICPL.W    R6, R3, R8
+  0x3418172A:  F8CE 6000    STR.W      R6, [LR]
+  0x3418172E:  02BB         LSLS       R3, R7, #10
+  0x34181730:  F8DE 3004    LDR.W      R3, [LR, #4]
+  0x34181734:  EA43 0708    ORR.W      R7, R3, R8
+  0x34181738:  BF58         IT         PL
+  0x3418173A:  EA23 0708    BICPL.W    R7, R3, R8
+  0x3418173E:  F8CE 7004    STR.W      R7, [LR, #4]
+  0x34181742:  BF00         NOP
+
.L4:
+  0x34181744:  680C         LDR        R4, [R1]
+  0x34181746:  3501         ADDS       R5, #1
+  0x34181748:  FA34 F305    LSRS.W     R3, R4, R5
+  0x3418174C:  D022         BEQ        46L6                      ; 0x34181794
+
.L5:
+  0x3418174E:  2201         MOVS       R2, #1
+  0x34181750:  FA02 FA05    LSL.W      R10, R2, R5
+  0x34181754:  EA1A 0804    ANDS.W     R8, R10, R4
+  0x34181758:  D0F4         BEQ        46L4                      ; 0x34181744
+  0x3418175A:  E9D1 9C01    LDRD       R9, R12, [R1, #4]
+  0x3418175E:  F009 0B03    AND        R11, R9, #3
+  0x34181762:  F1AB 0301    SUB.W      R3, R11, #1
+  0x34181766:  2B01         CMP        R3, #1
+  0x34181768:  F63F AF6C    BHI.W      46L1                      ; 0x34181644
+  0x3418176C:  68CB         LDR        R3, [R1, #12]
+  0x3418176E:  2203         MOVS       R2, #3
+  0x34181770:  006C         LSLS       R4, R5, #1
+  0x34181772:  6886         LDR        R6, [R0, #8]
+  0x34181774:  40A3         LSLS       R3, R4
+  0x34181776:  FA02 F404    LSL.W      R4, R2, R4
+  0x3418177A:  43A6         BICS       R6, R4
+  0x3418177C:  4333         ORRS       R3, R6
+  0x3418177E:  6083         STR        R3, [R0, #8]
+  0x34181780:  6843         LDR        R3, [R0, #4]
+  0x34181782:  F3C9 1600    UBFX       R6, R9, #4, #1
+  0x34181786:  EA23 030A    BIC.W      R3, R3, R10
+  0x3418178A:  40AE         LSLS       R6, R5
+  0x3418178C:  4333         ORRS       R3, R6
+  0x3418178E:  43E4         MVNS       R4, R4
+  0x34181790:  6043         STR        R3, [R0, #4]
+  0x34181792:  E762         B          46L2                      ; 0x3418165A
+
.L6:
+  0x34181794:  B003         ADD        SP, SP, #12
+  0x34181796:  E8BD 8FF0    POP.W      123R4-R11, PC}
+
+

Section .text.HAL_RCC_OscConfig from blto2_FSBL_lto.o, size=1714, align=4

+ +
+
HAL_RCC_OscConfig:
+  0x3418179C:  E92D 4FF8    PUSH.W     123R3-R11, LR}
+  0x341817A0:  6801         LDR        R1, [R0]
+  0x341817A2:  F248 0604    MOVW       R6, #0x8004
+  0x341817A6:  4604         MOV        R4, R0
+  0x341817A8:  F2C5 6602    MOVT       R6, #0x5602
+  0x341817AC:  07C8         LSLS       R0, R1, #31
+  0x341817AE:  69F0         LDR        R0, [R6, #28]
+  0x341817B0:  F400 1A40    AND        R10, R0, #0x300000
+  0x341817B4:  69F0         LDR        R0, [R6, #28]
+  0x341817B6:  F000 5840    AND        R8, R0, #0x30000000
+  0x341817BA:  6FF0         LDR        R0, [R6, #124]
+  0x341817BC:  F000 49E0    AND        R9, R0, #0x70000000
+  0x341817C0:  F8D6 008C    LDR.W      R0, [R6, #140]
+  0x341817C4:  F000 4BE0    AND        R11, R0, #0x70000000
+  0x341817C8:  F8D6 009C    LDR.W      R0, [R6, #156]
+  0x341817CC:  F000 4EE0    AND        LR, R0, #0x70000000
+  0x341817D0:  F8D6 00AC    LDR.W      R0, [R6, #172]
+  0x341817D4:  6832         LDR        R2, [R6]
+  0x341817D6:  F000 4CE0    AND        R12, R0, #0x70000000
+  0x341817DA:  D01D         BEQ        46L4                      ; 0x34181818
+  0x341817DC:  F5BA 1F00    CMP.W      R10, #0x200000
+  0x341817E0:  BF18         IT         NE
+  0x341817E2:  F1B8 5F00    CMPNE.W    R8, #0x20000000
+  0x341817E6:  F040 82D1    BNE.W      46L65                     ; 0x34181D8C
+
.L1:
+  0x341817EA:  6860         LDR        R0, [R4, #4]
+  0x341817EC:  2800         CMP        R0, #0
+  0x341817EE:  F000 8246    BEQ.W      46L49                     ; 0x34181C7E
+  0x341817F2:  F242 009C    MOVW       R0, #0x209C              ; 0x3418209C = uwTick
+  0x341817F6:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418209C = uwTick
+  0x341817FA:  6807         LDR        R7, [R0]
+
.L2:
+  0x341817FC:  6833         LDR        R3, [R6]
+  0x341817FE:  06DB         LSLS       R3, R3, #27
+  0x34181800:  6803         LDR        R3, [R0]
+  0x34181802:  D405         BMI        46L3                      ; 0x34181810
+  0x34181804:  1BDB         SUBS       R3, R3, R7
+  0x34181806:  2B64         CMP        R3, #100
+  0x34181808:  D9F8         BLS        46L2                      ; 0x341817FC
+  0x3418180A:  2003         MOVS       R0, #3
+  0x3418180C:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L3:
+  0x34181810:  6807         LDR        R7, [R0]
+  0x34181812:  1AFF         SUBS       R7, R7, R3
+  0x34181814:  2F02         CMP        R7, #2
+  0x34181816:  D3FB         BCC        46L3                      ; 0x34181810
+
.L4:
+  0x34181818:  0788         LSLS       R0, R1, #30
+  0x3418181A:  D516         BPL        46L7                      ; 0x3418184A
+  0x3418181C:  F1BA 0F00    CMP.W      R10, #0
+  0x34181820:  BF18         IT         NE
+  0x34181822:  F1B8 0F00    CMPNE.W    R8, #0
+  0x34181826:  D177         BNE        46L16                     ; 0x34181918
+
.L5:
+  0x34181828:  68E0         LDR        R0, [R4, #12]
+  0x3418182A:  2800         CMP        R0, #0
+  0x3418182C:  F000 8227    BEQ.W      46L49                     ; 0x34181C7E
+
.L6:
+  0x34181830:  6C70         LDR        R0, [R6, #68]
+  0x34181832:  E9D4 3704    LDRD       R3, R7, [R4, #16]
+  0x34181836:  F420 70C0    BIC        R0, R0, #0x0180
+  0x3418183A:  4318         ORRS       R0, R3
+  0x3418183C:  6470         STR        R0, [R6, #68]
+  0x3418183E:  6C70         LDR        R0, [R6, #68]
+  0x34181840:  F420 00FE    BIC        R0, R0, #0x7F0000
+  0x34181844:  EA40 4007    ORR.W      R0, R0, R7, LSL #16
+  0x34181848:  6470         STR        R0, [R6, #68]
+
.L7:
+  0x3418184A:  06C8         LSLS       R0, R1, #27
+  0x3418184C:  D511         BPL        46L10                     ; 0x34181872
+  0x3418184E:  F5BA 1F80    CMP.W      R10, #0x100000
+  0x34181852:  BF18         IT         NE
+  0x34181854:  F1B8 5F80    CMPNE.W    R8, #0x10000000
+  0x34181858:  F040 8096    BNE.W      46L22                     ; 0x34181988
+
.L8:
+  0x3418185C:  69E0         LDR        R0, [R4, #28]
+  0x3418185E:  2800         CMP        R0, #0
+  0x34181860:  F000 820D    BEQ.W      46L49                     ; 0x34181C7E
+  0x34181864:  6A63         LDR        R3, [R4, #36]
+
.L9:
+  0x34181866:  6C30         LDR        R0, [R6, #64]
+  0x34181868:  F420 10F8    BIC        R0, R0, #0x1F0000
+  0x3418186C:  EA40 4003    ORR.W      R0, R0, R3, LSL #16
+  0x34181870:  6430         STR        R0, [R6, #64]
+
.L10:
+  0x34181872:  F648 0500    MOVW       R5, #0x8800
+  0x34181876:  0708         LSLS       R0, R1, #28
+  0x34181878:  F2C5 6502    MOVT       R5, #0x5602
+  0x3418187C:  D437         BMI        46L14                     ; 0x341818EE
+
.L11:
+  0x3418187E:  0748         LSLS       R0, R1, #29
+  0x34181880:  F100 816F    BMI.W      46L37                     ; 0x34181B62
+
.L12:
+  0x34181884:  46A1         MOV        R9, R4
+  0x34181886:  F859 0F28    LDR        R0, [R9, #40]!
+  0x3418188A:  2800         CMP        R0, #0
+  0x3418188C:  F000 80E7    BEQ.W      46L32                     ; 0x34181A5E
+  0x34181890:  2000         MOVS       R0, #0
+  0x34181892:  4649         MOV        R1, R9
+  0x34181894:  F000 FADC    BL         RCC_PLL_IsNewConfig      ; 0x34181E50
+  0x34181898:  2800         CMP        R0, #0
+  0x3418189A:  6830         LDR        R0, [R6]
+  0x3418189C:  F000 80D7    BEQ.W      46L31                     ; 0x34181A4E
+  0x341818A0:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x341818A4:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x341818A8:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x341818AC:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x341818B0:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x341818B4:  BF08         IT         EQ
+  0x341818B6:  F013 5340    ANDSEQ     R3, R3, #0x30000000
+  0x341818BA:  F000 81E0    BEQ.W      46L49                     ; 0x34181C7E
+  0x341818BE:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x341818C2:  D10C         BNE        46L13                     ; 0x341818DE
+  0x341818C4:  F010 5F40    TST        R0, #0x30000000
+  0x341818C8:  F04F 0001    MOV.W      R0, #1
+  0x341818CC:  F000 82BD    BEQ.W      46L78                     ; 0x34181E4A
+  0x341818D0:  F012 5240    ANDS       R2, R2, #0x30000000
+  0x341818D4:  BF18         IT         NE
+  0x341818D6:  F011 5140    ANDSNE     R1, R1, #0x30000000
+  0x341818DA:  F000 82B6    BEQ.W      46L78                     ; 0x34181E4A
+
.L13:
+  0x341818DE:  2000         MOVS       R0, #0
+  0x341818E0:  4649         MOV        R1, R9
+  0x341818E2:  F000 FAF9    BL         RCC_PLL_Config           ; 0x34181ED8
+  0x341818E6:  2800         CMP        R0, #0
+  0x341818E8:  F040 81C9    BNE.W      46L49                     ; 0x34181C7E
+  0x341818EC:  E0B7         B          46L32                     ; 0x34181A5E
+
.L14:
+  0x341818EE:  69A0         LDR        R0, [R4, #24]
+  0x341818F0:  2201         MOVS       R2, #1
+  0x341818F2:  2800         CMP        R0, #0
+  0x341818F4:  F242 009C    MOVW       R0, #0x209C              ; 0x3418209C = uwTick
+  0x341818F8:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418209C = uwTick
+  0x341818FC:  F000 8098    BEQ.W      46L29                     ; 0x34181A30
+  0x34181900:  602A         STR        R2, [R5]
+  0x34181902:  6802         LDR        R2, [R0]
+
.L15:
+  0x34181904:  6833         LDR        R3, [R6]
+  0x34181906:  07DB         LSLS       R3, R3, #31
+  0x34181908:  D1B9         BNE        46L11                     ; 0x3418187E
+  0x3418190A:  6803         LDR        R3, [R0]
+  0x3418190C:  1A9B         SUBS       R3, R3, R2
+  0x3418190E:  2B01         CMP        R3, #1
+  0x34181910:  D9F8         BLS        46L15                     ; 0x34181904
+  0x34181912:  2003         MOVS       R0, #3
+  0x34181914:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L16:
+  0x34181918:  F1B9 0F00    CMP.W      R9, #0
+  0x3418191C:  D103         BNE        46L17                     ; 0x34181926
+  0x3418191E:  F412 7080    ANDS       R0, R2, #0x0100
+  0x34181922:  F47F AF81    BNE.W      46L5                      ; 0x34181828
+
.L17:
+  0x34181926:  F1BB 0F00    CMP.W      R11, #0
+  0x3418192A:  D103         BNE        46L18                     ; 0x34181934
+  0x3418192C:  F412 7000    ANDS       R0, R2, #0x0200
+  0x34181930:  F47F AF7A    BNE.W      46L5                      ; 0x34181828
+
.L18:
+  0x34181934:  F1BE 0F00    CMP.W      LR, #0
+  0x34181938:  D103         BNE        46L19                     ; 0x34181942
+  0x3418193A:  F412 6080    ANDS       R0, R2, #0x0400
+  0x3418193E:  F47F AF73    BNE.W      46L5                      ; 0x34181828
+
.L19:
+  0x34181942:  F1BC 0F00    CMP.W      R12, #0
+  0x34181946:  D103         BNE        46L20                     ; 0x34181950
+  0x34181948:  F412 6000    ANDS       R0, R2, #0x0800
+  0x3418194C:  F47F AF6C    BNE.W      46L5                      ; 0x34181828
+
.L20:
+  0x34181950:  68E3         LDR        R3, [R4, #12]
+  0x34181952:  F648 0000    MOVW       R0, #0x8800
+  0x34181956:  F242 059C    MOVW       R5, #0x209C              ; 0x3418209C = uwTick
+  0x3418195A:  F2C5 6002    MOVT       R0, #0x5602
+  0x3418195E:  2B00         CMP        R3, #0
+  0x34181960:  F04F 0308    MOV.W      R3, #8
+  0x34181964:  F2C3 4518    MOVT       R5, #0x3418              ; 0x3418209C = uwTick
+  0x34181968:  F000 81F1    BEQ.W      46L61                     ; 0x34181D4E
+  0x3418196C:  6003         STR        R3, [R0]
+  0x3418196E:  682B         LDR        R3, [R5]
+
.L21:
+  0x34181970:  6830         LDR        R0, [R6]
+  0x34181972:  0700         LSLS       R0, R0, #28
+  0x34181974:  F53F AF5C    BMI.W      46L6                      ; 0x34181830
+  0x34181978:  6828         LDR        R0, [R5]
+  0x3418197A:  1AC0         SUBS       R0, R0, R3
+  0x3418197C:  2801         CMP        R0, #1
+  0x3418197E:  F04F 0003    MOV.W      R0, #3
+  0x34181982:  D9F5         BLS        46L21                     ; 0x34181970
+  0x34181984:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L22:
+  0x34181988:  F1B9 5F80    CMP.W      R9, #0x10000000
+  0x3418198C:  D103         BNE        46L23                     ; 0x34181996
+  0x3418198E:  F412 7080    ANDS       R0, R2, #0x0100
+  0x34181992:  F47F AF63    BNE.W      46L8                      ; 0x3418185C
+
.L23:
+  0x34181996:  F1BB 5F80    CMP.W      R11, #0x10000000
+  0x3418199A:  D103         BNE        46L24                     ; 0x341819A4
+  0x3418199C:  F412 7000    ANDS       R0, R2, #0x0200
+  0x341819A0:  F47F AF5C    BNE.W      46L8                      ; 0x3418185C
+
.L24:
+  0x341819A4:  F1BE 5F80    CMP.W      LR, #0x10000000
+  0x341819A8:  D103         BNE        46L25                     ; 0x341819B2
+  0x341819AA:  F412 6080    ANDS       R0, R2, #0x0400
+  0x341819AE:  F47F AF55    BNE.W      46L8                      ; 0x3418185C
+
.L25:
+  0x341819B2:  F1BC 5F80    CMP.W      R12, #0x10000000
+  0x341819B6:  D103         BNE        46L26                     ; 0x341819C0
+  0x341819B8:  F412 6000    ANDS       R0, R2, #0x0800
+  0x341819BC:  F47F AF4E    BNE.W      46L8                      ; 0x3418185C
+
.L26:
+  0x341819C0:  69E2         LDR        R2, [R4, #28]
+  0x341819C2:  F648 0000    MOVW       R0, #0x8800
+  0x341819C6:  F2C5 6002    MOVT       R0, #0x5602
+  0x341819CA:  2A00         CMP        R2, #0
+  0x341819CC:  F242 029C    MOVW       R2, #0x209C              ; 0x3418209C = uwTick
+  0x341819D0:  F2C3 4218    MOVT       R2, #0x3418              ; 0x3418209C = uwTick
+  0x341819D4:  F000 81CA    BEQ.W      46L63                     ; 0x34181D6C
+  0x341819D8:  E9D4 7308    LDRD       R7, R3, [R4, #32]
+  0x341819DC:  F8D6 9040    LDR.W      R9, [R6, #64]
+  0x341819E0:  F429 7900    BIC        R9, R9, #0x0200
+  0x341819E4:  EA47 0709    ORR.W      R7, R7, R9
+  0x341819E8:  6437         STR        R7, [R6, #64]
+  0x341819EA:  2704         MOVS       R7, #4
+  0x341819EC:  6007         STR        R7, [R0]
+  0x341819EE:  F8D2 9000    LDR.W      R9, [R2]
+
.L27:
+  0x341819F2:  6830         LDR        R0, [R6]
+  0x341819F4:  0740         LSLS       R0, R0, #29
+  0x341819F6:  F53F AF36    BMI.W      46L9                      ; 0x34181866
+  0x341819FA:  6810         LDR        R0, [R2]
+  0x341819FC:  EBA0 0009    SUB.W      R0, R0, R9
+  0x34181A00:  2801         CMP        R0, #1
+  0x34181A02:  F04F 0003    MOV.W      R0, #3
+  0x34181A06:  D9F4         BLS        46L27                     ; 0x341819F2
+  0x34181A08:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L28:
+  0x34181A0C:  F248 0102    MOVW       R1, #0x8002
+  0x34181A10:  4288         CMP        R0, R1
+  0x34181A12:  F000 80D9    BEQ.W      46L41                     ; 0x34181BC8
+  0x34181A16:  F501 3180    ADD.W      R1, R1, #0x010000
+  0x34181A1A:  4288         CMP        R0, R1
+  0x34181A1C:  F040 80AA    BNE.W      46L38                     ; 0x34181B74
+  0x34181A20:  6BF0         LDR        R0, [R6, #60]
+  0x34181A22:  F440 4000    ORR        R0, R0, #0x8000
+  0x34181A26:  63F0         STR        R0, [R6, #60]
+  0x34181A28:  6BF0         LDR        R0, [R6, #60]
+  0x34181A2A:  F440 3080    ORR        R0, R0, #0x010000
+  0x34181A2E:  E0D2         B          46L42                     ; 0x34181BD6
+
.L29:
+  0x34181A30:  F8C5 2800    STR.W      R2, [R5, #0x0800]
+  0x34181A34:  6802         LDR        R2, [R0]
+  0x34181A36:  BF00         NOP
+
.L30:
+  0x34181A38:  6833         LDR        R3, [R6]
+  0x34181A3A:  07DB         LSLS       R3, R3, #31
+  0x34181A3C:  F43F AF1F    BEQ.W      46L11                     ; 0x3418187E
+  0x34181A40:  6803         LDR        R3, [R0]
+  0x34181A42:  1A9B         SUBS       R3, R3, R2
+  0x34181A44:  2B01         CMP        R3, #1
+  0x34181A46:  D9F7         BLS        46L30                     ; 0x34181A38
+  0x34181A48:  2003         MOVS       R0, #3
+  0x34181A4A:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L31:
+  0x34181A4E:  F8D9 1000    LDR.W      R1, [R9]
+  0x34181A52:  2902         CMP        R1, #2
+  0x34181A54:  BF08         IT         EQ
+  0x34181A56:  F410 7080    ANDSEQ     R0, R0, #0x0100
+  0x34181A5A:  F000 8113    BEQ.W      46L50                     ; 0x34181C84
+
.L32:
+  0x34181A5E:  46A1         MOV        R9, R4
+  0x34181A60:  F859 0F44    LDR        R0, [R9, #68]!
+  0x34181A64:  2800         CMP        R0, #0
+  0x34181A66:  D03F         BEQ        46L35                     ; 0x34181AE8
+  0x34181A68:  2001         MOVS       R0, #1
+  0x34181A6A:  4649         MOV        R1, R9
+  0x34181A6C:  F000 F9F0    BL         RCC_PLL_IsNewConfig      ; 0x34181E50
+  0x34181A70:  2800         CMP        R0, #0
+  0x34181A72:  6830         LDR        R0, [R6]
+  0x34181A74:  D030         BEQ        46L34                     ; 0x34181AD8
+  0x34181A76:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181A7A:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181A7E:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181A82:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x34181A86:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181A8A:  BF04         ITT        EQ
+  0x34181A8C:  F003 5340    ANDEQ      R3, R3, #0x30000000
+  0x34181A90:  F1B3 5F80    CMPEQ.W    R3, #0x10000000
+  0x34181A94:  F000 80F3    BEQ.W      46L49                     ; 0x34181C7E
+  0x34181A98:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x34181A9C:  D112         BNE        46L33                     ; 0x34181AC4
+  0x34181A9E:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181AA2:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x34181AA6:  F04F 0001    MOV.W      R0, #1
+  0x34181AAA:  BF1C         ITT        NE
+  0x34181AAC:  F002 5240    ANDNE      R2, R2, #0x30000000
+  0x34181AB0:  F1B2 5F80    CMPNE.W    R2, #0x10000000
+  0x34181AB4:  F000 81C9    BEQ.W      46L78                     ; 0x34181E4A
+  0x34181AB8:  F001 5140    AND        R1, R1, #0x30000000
+  0x34181ABC:  F1B1 5F80    CMP.W      R1, #0x10000000
+  0x34181AC0:  F000 81C3    BEQ.W      46L78                     ; 0x34181E4A
+
.L33:
+  0x34181AC4:  2001         MOVS       R0, #1
+  0x34181AC6:  4649         MOV        R1, R9
+  0x34181AC8:  F000 FA06    BL         RCC_PLL_Config           ; 0x34181ED8
+  0x34181ACC:  0001         MOVS       R1, R0
+  0x34181ACE:  F04F 0001    MOV.W      R0, #1
+  0x34181AD2:  F040 81BA    BNE.W      46L78                     ; 0x34181E4A
+  0x34181AD6:  E007         B          46L35                     ; 0x34181AE8
+
.L34:
+  0x34181AD8:  F8D9 1000    LDR.W      R1, [R9]
+  0x34181ADC:  2902         CMP        R1, #2
+  0x34181ADE:  BF08         IT         EQ
+  0x34181AE0:  F410 7000    ANDSEQ     R0, R0, #0x0200
+  0x34181AE4:  F000 80EB    BEQ.W      46L54                     ; 0x34181CBE
+
.L35:
+  0x34181AE8:  46A1         MOV        R9, R4
+  0x34181AEA:  F859 0F60    LDR        R0, [R9, #96]!
+  0x34181AEE:  2800         CMP        R0, #0
+  0x34181AF0:  F000 808E    BEQ.W      46L47                     ; 0x34181C10
+  0x34181AF4:  2002         MOVS       R0, #2
+  0x34181AF6:  4649         MOV        R1, R9
+  0x34181AF8:  F000 F9AA    BL         RCC_PLL_IsNewConfig      ; 0x34181E50
+  0x34181AFC:  2800         CMP        R0, #0
+  0x34181AFE:  6830         LDR        R0, [R6]
+  0x34181B00:  F000 807F    BEQ.W      46L46                     ; 0x34181C02
+  0x34181B04:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181B08:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181B0C:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181B10:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x34181B14:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181B18:  BF04         ITT        EQ
+  0x34181B1A:  F003 5340    ANDEQ      R3, R3, #0x30000000
+  0x34181B1E:  F1B3 5F00    CMPEQ.W    R3, #0x20000000
+  0x34181B22:  F000 80AC    BEQ.W      46L49                     ; 0x34181C7E
+  0x34181B26:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x34181B2A:  D112         BNE        46L36                     ; 0x34181B52
+  0x34181B2C:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181B30:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x34181B34:  F04F 0001    MOV.W      R0, #1
+  0x34181B38:  BF1C         ITT        NE
+  0x34181B3A:  F002 5240    ANDNE      R2, R2, #0x30000000
+  0x34181B3E:  F1B2 5F00    CMPNE.W    R2, #0x20000000
+  0x34181B42:  F000 8182    BEQ.W      46L78                     ; 0x34181E4A
+  0x34181B46:  F001 5140    AND        R1, R1, #0x30000000
+  0x34181B4A:  F1B1 5F00    CMP.W      R1, #0x20000000
+  0x34181B4E:  F000 817C    BEQ.W      46L78                     ; 0x34181E4A
+
.L36:
+  0x34181B52:  2002         MOVS       R0, #2
+  0x34181B54:  4649         MOV        R1, R9
+  0x34181B56:  F000 F9BF    BL         RCC_PLL_Config           ; 0x34181ED8
+  0x34181B5A:  2800         CMP        R0, #0
+  0x34181B5C:  F040 808F    BNE.W      46L49                     ; 0x34181C7E
+  0x34181B60:  E056         B          46L47                     ; 0x34181C10
+
.L37:
+  0x34181B62:  68A0         LDR        R0, [R4, #8]
+  0x34181B64:  F248 0101    MOVW       R1, #0x8001
+  0x34181B68:  4288         CMP        R0, R1
+  0x34181B6A:  F73F AF4F    BGT.W      46L28                     ; 0x34181A0C
+  0x34181B6E:  B168         CBZ        R0, .L39                 ; 0x34181B8C
+  0x34181B70:  2802         CMP        R0, #2
+  0x34181B72:  D032         BEQ        46L43                     ; 0x34181BDA
+
.L38:
+  0x34181B74:  2002         MOVS       R0, #2
+  0x34181B76:  F8C5 0800    STR.W      R0, [R5, #0x0800]
+  0x34181B7A:  6BF0         LDR        R0, [R6, #60]
+  0x34181B7C:  F420 4000    BIC        R0, R0, #0x8000
+  0x34181B80:  63F0         STR        R0, [R6, #60]
+  0x34181B82:  6BF0         LDR        R0, [R6, #60]
+  0x34181B84:  F420 3080    BIC        R0, R0, #0x010000
+  0x34181B88:  63F0         STR        R0, [R6, #60]
+  0x34181B8A:  E027         B          46L44                     ; 0x34181BDC
+
.L39:
+  0x34181B8C:  2002         MOVS       R0, #2
+  0x34181B8E:  F242 019C    MOVW       R1, #0x209C              ; 0x3418209C = uwTick
+  0x34181B92:  F8C5 0800    STR.W      R0, [R5, #0x0800]
+  0x34181B96:  F241 3388    MOVW       R3, #0x1388
+  0x34181B9A:  6BF0         LDR        R0, [R6, #60]
+  0x34181B9C:  F2C3 4118    MOVT       R1, #0x3418              ; 0x3418209C = uwTick
+  0x34181BA0:  F420 3080    BIC        R0, R0, #0x010000
+  0x34181BA4:  63F0         STR        R0, [R6, #60]
+  0x34181BA6:  6BF0         LDR        R0, [R6, #60]
+  0x34181BA8:  F420 4000    BIC        R0, R0, #0x8000
+  0x34181BAC:  63F0         STR        R0, [R6, #60]
+  0x34181BAE:  680A         LDR        R2, [R1]
+
.L40:
+  0x34181BB0:  6830         LDR        R0, [R6]
+  0x34181BB2:  0780         LSLS       R0, R0, #30
+  0x34181BB4:  F57F AE66    BPL.W      46L12                     ; 0x34181884
+  0x34181BB8:  6808         LDR        R0, [R1]
+  0x34181BBA:  1A80         SUBS       R0, R0, R2
+  0x34181BBC:  4298         CMP        R0, R3
+  0x34181BBE:  F04F 0003    MOV.W      R0, #3
+  0x34181BC2:  D9F5         BLS        46L40                     ; 0x34181BB0
+  0x34181BC4:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L41:
+  0x34181BC8:  6BF0         LDR        R0, [R6, #60]
+  0x34181BCA:  F440 4000    ORR        R0, R0, #0x8000
+  0x34181BCE:  63F0         STR        R0, [R6, #60]
+  0x34181BD0:  6BF0         LDR        R0, [R6, #60]
+  0x34181BD2:  F420 3080    BIC        R0, R0, #0x010000
+
.L42:
+  0x34181BD6:  63F0         STR        R0, [R6, #60]
+  0x34181BD8:  2002         MOVS       R0, #2
+
.L43:
+  0x34181BDA:  6028         STR        R0, [R5]
+
.L44:
+  0x34181BDC:  F242 009C    MOVW       R0, #0x209C              ; 0x3418209C = uwTick
+  0x34181BE0:  F241 3288    MOVW       R2, #0x1388
+  0x34181BE4:  F2C3 4018    MOVT       R0, #0x3418              ; 0x3418209C = uwTick
+  0x34181BE8:  6801         LDR        R1, [R0]
+  0x34181BEA:  BF00         NOP
+
.L45:
+  0x34181BEC:  6833         LDR        R3, [R6]
+  0x34181BEE:  079B         LSLS       R3, R3, #30
+  0x34181BF0:  F53F AE48    BMI.W      46L12                     ; 0x34181884
+  0x34181BF4:  6803         LDR        R3, [R0]
+  0x34181BF6:  1A5B         SUBS       R3, R3, R1
+  0x34181BF8:  4293         CMP        R3, R2
+  0x34181BFA:  D9F7         BLS        46L45                     ; 0x34181BEC
+  0x34181BFC:  2003         MOVS       R0, #3
+  0x34181BFE:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L46:
+  0x34181C02:  F8D9 1000    LDR.W      R1, [R9]
+  0x34181C06:  2902         CMP        R1, #2
+  0x34181C08:  BF08         IT         EQ
+  0x34181C0A:  F410 6080    ANDSEQ     R0, R0, #0x0400
+  0x34181C0E:  D06A         BEQ        46L56                     ; 0x34181CE6
+
.L47:
+  0x34181C10:  F854 0F7C    LDR        R0, [R4, #124]!
+  0x34181C14:  2800         CMP        R0, #0
+  0x34181C16:  F000 8118    BEQ.W      46L78                     ; 0x34181E4A
+  0x34181C1A:  2003         MOVS       R0, #3
+  0x34181C1C:  4621         MOV        R1, R4
+  0x34181C1E:  F000 F917    BL         RCC_PLL_IsNewConfig      ; 0x34181E50
+  0x34181C22:  2800         CMP        R0, #0
+  0x34181C24:  6830         LDR        R0, [R6]
+  0x34181C26:  D041         BEQ        46L52                     ; 0x34181CAC
+  0x34181C28:  F8D6 30C0    LDR.W      R3, [R6, #192]
+  0x34181C2C:  F8D6 00C4    LDR.W      R0, [R6, #196]
+  0x34181C30:  F8D6 20D4    LDR.W      R2, [R6, #212]
+  0x34181C34:  F8D6 10E8    LDR.W      R1, [R6, #232]
+  0x34181C38:  F5BA 1F40    CMP.W      R10, #0x300000
+  0x34181C3C:  BF04         ITT        EQ
+  0x34181C3E:  F003 5340    ANDEQ      R3, R3, #0x30000000
+  0x34181C42:  F1B3 5F40    CMPEQ.W    R3, #0x30000000
+  0x34181C46:  D01A         BEQ        46L49                     ; 0x34181C7E
+  0x34181C48:  F1B8 5F40    CMP.W      R8, #0x30000000
+  0x34181C4C:  D112         BNE        46L48                     ; 0x34181C74
+  0x34181C4E:  F000 5040    AND        R0, R0, #0x30000000
+  0x34181C52:  F1B0 5F40    CMP.W      R0, #0x30000000
+  0x34181C56:  F04F 0001    MOV.W      R0, #1
+  0x34181C5A:  BF1C         ITT        NE
+  0x34181C5C:  F002 5240    ANDNE      R2, R2, #0x30000000
+  0x34181C60:  F1B2 5F40    CMPNE.W    R2, #0x30000000
+  0x34181C64:  F000 80F1    BEQ.W      46L78                     ; 0x34181E4A
+  0x34181C68:  F001 5140    AND        R1, R1, #0x30000000
+  0x34181C6C:  F1B1 5F40    CMP.W      R1, #0x30000000
+  0x34181C70:  F000 80EB    BEQ.W      46L78                     ; 0x34181E4A
+
.L48:
+  0x34181C74:  2003         MOVS       R0, #3
+  0x34181C76:  4621         MOV        R1, R4
+  0x34181C78:  F000 F92E    BL         RCC_PLL_Config           ; 0x34181ED8
+  0x34181C7C:  B1E0         CBZ        R0, .L53                 ; 0x34181CB8
+
.L49:
+  0x34181C7E:  2001         MOVS       R0, #1
+  0x34181C80:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L50:
+  0x34181C84:  F44F 7080    MOV.W      R0, #0x0100
+  0x34181C88:  F242 019C    MOVW       R1, #0x209C              ; 0x3418209C = uwTick
+  0x34181C8C:  6028         STR        R0, [R5]
+  0x34181C8E:  F2C3 4118    MOVT       R1, #0x3418              ; 0x3418209C = uwTick
+  0x34181C92:  680A         LDR        R2, [R1]
+
.L51:
+  0x34181C94:  6830         LDR        R0, [R6]
+  0x34181C96:  05C0         LSLS       R0, R0, #23
+  0x34181C98:  F53F AEE1    BMI.W      46L32                     ; 0x34181A5E
+  0x34181C9C:  6808         LDR        R0, [R1]
+  0x34181C9E:  1A80         SUBS       R0, R0, R2
+  0x34181CA0:  2801         CMP        R0, #1
+  0x34181CA2:  F04F 0001    MOV.W      R0, #1
+  0x34181CA6:  D9F5         BLS        46L51                     ; 0x34181C94
+  0x34181CA8:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L52:
+  0x34181CAC:  6821         LDR        R1, [R4]
+  0x34181CAE:  2902         CMP        R1, #2
+  0x34181CB0:  BF08         IT         EQ
+  0x34181CB2:  F410 6000    ANDSEQ     R0, R0, #0x0800
+  0x34181CB6:  D037         BEQ        46L59                     ; 0x34181D28
+
.L53:
+  0x34181CB8:  2000         MOVS       R0, #0
+  0x34181CBA:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L54:
+  0x34181CBE:  F44F 7000    MOV.W      R0, #0x0200
+  0x34181CC2:  F242 019C    MOVW       R1, #0x209C              ; 0x3418209C = uwTick
+  0x34181CC6:  6028         STR        R0, [R5]
+  0x34181CC8:  F2C3 4118    MOVT       R1, #0x3418              ; 0x3418209C = uwTick
+  0x34181CCC:  680A         LDR        R2, [R1]
+
.L55:
+  0x34181CCE:  6830         LDR        R0, [R6]
+  0x34181CD0:  0580         LSLS       R0, R0, #22
+  0x34181CD2:  F53F AF09    BMI.W      46L35                     ; 0x34181AE8
+  0x34181CD6:  6808         LDR        R0, [R1]
+  0x34181CD8:  1A80         SUBS       R0, R0, R2
+  0x34181CDA:  2801         CMP        R0, #1
+  0x34181CDC:  F04F 0001    MOV.W      R0, #1
+  0x34181CE0:  D9F5         BLS        46L55                     ; 0x34181CCE
+  0x34181CE2:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L56:
+  0x34181CE6:  F44F 6080    MOV.W      R0, #0x0400
+  0x34181CEA:  F242 019C    MOVW       R1, #0x209C              ; 0x3418209C = uwTick
+  0x34181CEE:  6028         STR        R0, [R5]
+  0x34181CF0:  F2C3 4118    MOVT       R1, #0x3418              ; 0x3418209C = uwTick
+  0x34181CF4:  680A         LDR        R2, [R1]
+
.L57:
+  0x34181CF6:  6830         LDR        R0, [R6]
+  0x34181CF8:  0540         LSLS       R0, R0, #21
+  0x34181CFA:  F53F AF89    BMI.W      46L47                     ; 0x34181C10
+  0x34181CFE:  6808         LDR        R0, [R1]
+  0x34181D00:  1A80         SUBS       R0, R0, R2
+  0x34181D02:  2801         CMP        R0, #1
+  0x34181D04:  F04F 0001    MOV.W      R0, #1
+  0x34181D08:  D9F5         BLS        46L57                     ; 0x34181CF6
+  0x34181D0A:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L58:
+  0x34181D0E:  F248 0310    MOVW       R3, #0x8010
+  0x34181D12:  4298         CMP        R0, R3
+  0x34181D14:  F000 8082    BEQ.W      46L73                     ; 0x34181E1C
+  0x34181D18:  F503 3380    ADD.W      R3, R3, #0x010000
+  0x34181D1C:  4298         CMP        R0, R3
+  0x34181D1E:  D15D         BNE        46L70                     ; 0x34181DDC
+  0x34181D20:  6D30         LDR        R0, [R6, #80]
+  0x34181D22:  F440 30C0    ORR        R0, R0, #0x018000
+  0x34181D26:  E080         B          46L74                     ; 0x34181E2A
+
.L59:
+  0x34181D28:  F44F 6000    MOV.W      R0, #0x0800
+  0x34181D2C:  F242 019C    MOVW       R1, #0x209C              ; 0x3418209C = uwTick
+  0x34181D30:  6028         STR        R0, [R5]
+  0x34181D32:  F2C3 4118    MOVT       R1, #0x3418              ; 0x3418209C = uwTick
+  0x34181D36:  680A         LDR        R2, [R1]
+
.L60:
+  0x34181D38:  6830         LDR        R0, [R6]
+  0x34181D3A:  0500         LSLS       R0, R0, #20
+  0x34181D3C:  D4BC         BMI        46L53                     ; 0x34181CB8
+  0x34181D3E:  6808         LDR        R0, [R1]
+  0x34181D40:  1A80         SUBS       R0, R0, R2
+  0x34181D42:  2801         CMP        R0, #1
+  0x34181D44:  F04F 0001    MOV.W      R0, #1
+  0x34181D48:  D9F6         BLS        46L60                     ; 0x34181D38
+  0x34181D4A:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L61:
+  0x34181D4E:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181D52:  682B         LDR        R3, [R5]
+
.L62:
+  0x34181D54:  6830         LDR        R0, [R6]
+  0x34181D56:  0700         LSLS       R0, R0, #28
+  0x34181D58:  F57F AD77    BPL.W      46L7                      ; 0x3418184A
+  0x34181D5C:  6828         LDR        R0, [R5]
+  0x34181D5E:  1AC0         SUBS       R0, R0, R3
+  0x34181D60:  2801         CMP        R0, #1
+  0x34181D62:  F04F 0003    MOV.W      R0, #3
+  0x34181D66:  D9F5         BLS        46L62                     ; 0x34181D54
+  0x34181D68:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L63:
+  0x34181D6C:  2304         MOVS       R3, #4
+  0x34181D6E:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181D72:  6813         LDR        R3, [R2]
+
.L64:
+  0x34181D74:  6830         LDR        R0, [R6]
+  0x34181D76:  0740         LSLS       R0, R0, #29
+  0x34181D78:  F57F AD7B    BPL.W      46L10                     ; 0x34181872
+  0x34181D7C:  6810         LDR        R0, [R2]
+  0x34181D7E:  1AC0         SUBS       R0, R0, R3
+  0x34181D80:  2801         CMP        R0, #1
+  0x34181D82:  F04F 0003    MOV.W      R0, #3
+  0x34181D86:  D9F5         BLS        46L64                     ; 0x34181D74
+  0x34181D88:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L65:
+  0x34181D8C:  F1B9 5F00    CMP.W      R9, #0x20000000
+  0x34181D90:  D103         BNE        46L66                     ; 0x34181D9A
+  0x34181D92:  F412 7080    ANDS       R0, R2, #0x0100
+  0x34181D96:  F47F AD28    BNE.W      46L1                      ; 0x341817EA
+
.L66:
+  0x34181D9A:  F1BB 5F00    CMP.W      R11, #0x20000000
+  0x34181D9E:  D103         BNE        46L67                     ; 0x34181DA8
+  0x34181DA0:  F412 7000    ANDS       R0, R2, #0x0200
+  0x34181DA4:  F47F AD21    BNE.W      46L1                      ; 0x341817EA
+
.L67:
+  0x34181DA8:  F1BE 5F00    CMP.W      LR, #0x20000000
+  0x34181DAC:  D103         BNE        46L68                     ; 0x34181DB6
+  0x34181DAE:  F412 6080    ANDS       R0, R2, #0x0400
+  0x34181DB2:  F47F AD1A    BNE.W      46L1                      ; 0x341817EA
+
.L68:
+  0x34181DB6:  F1BC 5F00    CMP.W      R12, #0x20000000
+  0x34181DBA:  D103         BNE        46L69                     ; 0x34181DC4
+  0x34181DBC:  F412 6000    ANDS       R0, R2, #0x0800
+  0x34181DC0:  F47F AD13    BNE.W      46L1                      ; 0x341817EA
+
.L69:
+  0x34181DC4:  6860         LDR        R0, [R4, #4]
+  0x34181DC6:  F248 030F    MOVW       R3, #0x800F
+  0x34181DCA:  F242 059C    MOVW       R5, #0x209C              ; 0x3418209C = uwTick
+  0x34181DCE:  4298         CMP        R0, R3
+  0x34181DD0:  F2C3 4518    MOVT       R5, #0x3418              ; 0x3418209C = uwTick
+  0x34181DD4:  DC9B         BGT        46L58                     ; 0x34181D0E
+  0x34181DD6:  B158         CBZ        R0, .L71                 ; 0x34181DF0
+  0x34181DD8:  2810         CMP        R0, #16
+  0x34181DDA:  D027         BEQ        46L75                     ; 0x34181E2C
+
.L70:
+  0x34181DDC:  F206 70FC    ADDW       R0, R6, #0x07FC
+  0x34181DE0:  2310         MOVS       R3, #16
+  0x34181DE2:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181DE6:  6D30         LDR        R0, [R6, #80]
+  0x34181DE8:  F420 30C0    BIC        R0, R0, #0x018000
+  0x34181DEC:  6530         STR        R0, [R6, #80]
+  0x34181DEE:  E021         B          46L76                     ; 0x34181E34
+
.L71:
+  0x34181DF0:  F206 70FC    ADDW       R0, R6, #0x07FC
+  0x34181DF4:  2310         MOVS       R3, #16
+  0x34181DF6:  F8C0 3800    STR.W      R3, [R0, #0x0800]
+  0x34181DFA:  6D30         LDR        R0, [R6, #80]
+  0x34181DFC:  F420 30C0    BIC        R0, R0, #0x018000
+  0x34181E00:  6530         STR        R0, [R6, #80]
+  0x34181E02:  682B         LDR        R3, [R5]
+
.L72:
+  0x34181E04:  6830         LDR        R0, [R6]
+  0x34181E06:  06C0         LSLS       R0, R0, #27
+  0x34181E08:  F57F AD06    BPL.W      46L4                      ; 0x34181818
+  0x34181E0C:  6828         LDR        R0, [R5]
+  0x34181E0E:  1AC0         SUBS       R0, R0, R3
+  0x34181E10:  2864         CMP        R0, #100
+  0x34181E12:  F04F 0003    MOV.W      R0, #3
+  0x34181E16:  D9F5         BLS        46L72                     ; 0x34181E04
+  0x34181E18:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
.L73:
+  0x34181E1C:  6D30         LDR        R0, [R6, #80]
+  0x34181E1E:  F440 4000    ORR        R0, R0, #0x8000
+  0x34181E22:  6530         STR        R0, [R6, #80]
+  0x34181E24:  6D30         LDR        R0, [R6, #80]
+  0x34181E26:  F420 3080    BIC        R0, R0, #0x010000
+
.L74:
+  0x34181E2A:  6530         STR        R0, [R6, #80]
+
.L75:
+  0x34181E2C:  F206 70FC    ADDW       R0, R6, #0x07FC
+  0x34181E30:  2310         MOVS       R3, #16
+  0x34181E32:  6003         STR        R3, [R0]
+
.L76:
+  0x34181E34:  682B         LDR        R3, [R5]
+
.L77:
+  0x34181E36:  6830         LDR        R0, [R6]
+  0x34181E38:  06C0         LSLS       R0, R0, #27
+  0x34181E3A:  F53F ACED    BMI.W      46L4                      ; 0x34181818
+  0x34181E3E:  6828         LDR        R0, [R5]
+  0x34181E40:  1AC0         SUBS       R0, R0, R3
+  0x34181E42:  2864         CMP        R0, #100
+  0x34181E44:  F04F 0003    MOV.W      R0, #3
+  0x34181E48:  D9F5         BLS        46L77                     ; 0x34181E36
+
.L78:
+  0x34181E4A:  E8BD 8FF8    POP.W      123R3-R11, PC}
+
+

Section .text.RCC_PLL_IsNewConfig from blto2_FSBL_lto.o, size=134, align=4

+ +
+
RCC_PLL_IsNewConfig:
+  0x34181E50:  B530         PUSH       123R4-R5, LR}
+  0x34181E52:  F248 0E04    MOVW       LR, #0x8004
+  0x34181E56:  0102         LSLS       R2, R0, #4
+  0x34181E58:  F2C5 6E02    MOVT       LR, #0x5602
+  0x34181E5C:  F10E 0C7C    ADD.W      R12, LR, #124
+  0x34181E60:  F85C 2002    LDR.W      R2, [R12, R2]
+  0x34181E64:  E9D1 3401    LDRD       R3, R4, [R1, #4]
+  0x34181E68:  F022 420C    BIC        R2, R2, #0x8C000000
+  0x34181E6C:  F022 02FF    BIC        R2, R2, #255
+  0x34181E70:  EA43 5304    ORR.W      R3, R3, R4, LSL #20
+  0x34181E74:  690C         LDR        R4, [R1, #16]
+  0x34181E76:  EA43 2304    ORR.W      R3, R3, R4, LSL #8
+  0x34181E7A:  429A         CMP        R2, R3
+  0x34181E7C:  D11E         BNE        46L1                      ; 0x34181EBC
+  0x34181E7E:  0082         LSLS       R2, R0, #2
+  0x34181E80:  EB0E 0382    ADD.W      R3, LR, R2, LSL #2
+  0x34181E84:  F8D3 3080    LDR.W      R3, [R3, #128]
+  0x34181E88:  68CC         LDR        R4, [R1, #12]
+  0x34181E8A:  F023 437F    BIC        R3, R3, #0xFF000000
+  0x34181E8E:  42A3         CMP        R3, R4
+  0x34181E90:  D114         BNE        46L1                      ; 0x34181EBC
+  0x34181E92:  F10E 0384    ADD.W      R3, LR, #132
+  0x34181E96:  F853 3022    LDR.W      R3, [R3, R2, LSL #2]
+  0x34181E9A:  E9D1 4505    LDRD       R4, R5, [R1, #20]
+  0x34181E9E:  F003 537C    AND        R3, R3, #0x3F000000
+  0x34181EA2:  062D         LSLS       R5, R5, #24
+  0x34181EA4:  EA45 64C4    ORR.W      R4, R5, R4, LSL #27
+  0x34181EA8:  42A3         CMP        R3, R4
+  0x34181EAA:  D107         BNE        46L1                      ; 0x34181EBC
+  0x34181EAC:  F8DE 3000    LDR.W      R3, [LR]
+  0x34181EB0:  FA23 F000    LSR.W      R0, R3, R0
+  0x34181EB4:  05C0         LSLS       R0, R0, #23
+  0x34181EB6:  D503         BPL        46L2                      ; 0x34181EC0
+  0x34181EB8:  2002         MOVS       R0, #2
+  0x34181EBA:  E007         B          46L3                      ; 0x34181ECC
+
.L1:
+  0x34181EBC:  2001         MOVS       R0, #1
+  0x34181EBE:  BD30         POP        123R4-R5, PC}
+
.L2:
+  0x34181EC0:  F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
+  0x34181EC4:  0100         LSLS       R0, R0, #4
+  0x34181EC6:  BF4C         ITE        MI
+  0x34181EC8:  2003         MOVMI      R0, #3
+  0x34181ECA:  2001         MOVPL      R0, #1
+
.L3:
+  0x34181ECC:  6809         LDR        R1, [R1]
+  0x34181ECE:  4288         CMP        R0, R1
+  0x34181ED0:  EA5F 900F    CSET       R0, NE
+  0x34181ED4:  BD30         POP        123R4-R5, PC}
+
+

Section .text.RCC_PLL_Config from blto2_FSBL_lto.o, size=446, align=4

+ +
+
RCC_PLL_Config:
+  0x34181ED8:  E92D 41F0    PUSH.W     123R4-R8, LR}
+  0x34181EDC:  F248 0304    MOVW       R3, #0x8004
+  0x34181EE0:  680C         LDR        R4, [R1]
+  0x34181EE2:  F2C5 6302    MOVT       R3, #0x5602
+  0x34181EE6:  0082         LSLS       R2, R0, #2
+  0x34181EE8:  F103 0C7C    ADD.W      R12, R3, #124
+  0x34181EEC:  F103 0E84    ADD.W      LR, R3, #132
+  0x34181EF0:  2C01         CMP        R4, #1
+  0x34181EF2:  D046         BEQ        46L5                      ; 0x34181F82
+  0x34181EF4:  2C03         CMP        R4, #3
+  0x34181EF6:  D01B         BEQ        46L2                      ; 0x34181F30
+  0x34181EF8:  2C02         CMP        R4, #2
+  0x34181EFA:  F040 80C6    BNE.W      46L12                     ; 0x3418208A
+  0x34181EFE:  F44F 7480    MOV.W      R4, #0x0100
+  0x34181F02:  F603 78FC    ADDW       R8, R3, #0x0FFC
+  0x34181F06:  FA04 F000    LSL.W      R0, R4, R0
+  0x34181F0A:  F242 049C    MOVW       R4, #0x209C              ; 0x3418209C = uwTick
+  0x34181F0E:  F8C8 0000    STR.W      R0, [R8]
+  0x34181F12:  F103 0680    ADD.W      R6, R3, #128
+  0x34181F16:  F2C3 4418    MOVT       R4, #0x3418              ; 0x3418209C = uwTick
+  0x34181F1A:  6827         LDR        R7, [R4]
+
.L1:
+  0x34181F1C:  681D         LDR        R5, [R3]
+  0x34181F1E:  4205         TST        R5, R0
+  0x34181F20:  D051         BEQ        46L8                      ; 0x34181FC6
+  0x34181F22:  6825         LDR        R5, [R4]
+  0x34181F24:  1BED         SUBS       R5, R5, R7
+  0x34181F26:  2D01         CMP        R5, #1
+  0x34181F28:  D9F8         BLS        46L1                      ; 0x34181F1C
+  0x34181F2A:  2003         MOVS       R0, #3
+  0x34181F2C:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L2:
+  0x34181F30:  6849         LDR        R1, [R1, #4]
+  0x34181F32:  EA4F 7731    ROR        R7, R1, #28
+  0x34181F36:  2F02         CMP        R7, #2
+  0x34181F38:  D80B         BHI        46L3                      ; 0x34181F52
+  0x34181F3A:  F241 460C    MOVW       R6, #0x140C              ; 0x3418140C = .rodata..Lswitch.table.RCC_PLL_Config
+  0x34181F3E:  F2C3 4618    MOVT       R6, #0x3418              ; 0x3418140C = .rodata..Lswitch.table.RCC_PLL_Config
+  0x34181F42:  F856 7027    LDR.W      R7, [R6, R7, LSL #2]
+  0x34181F46:  681E         LDR        R6, [R3]
+  0x34181F48:  FA26 F707    LSR.W      R7, R6, R7
+  0x34181F4C:  07FF         LSLS       R7, R7, #31
+  0x34181F4E:  F000 809F    BEQ.W      46L13                     ; 0x34182090
+
.L3:
+  0x34181F52:  F44F 7780    MOV.W      R7, #0x0100
+  0x34181F56:  F242 069C    MOVW       R6, #0x209C              ; 0x3418209C = uwTick
+  0x34181F5A:  FA07 F000    LSL.W      R0, R7, R0
+  0x34181F5E:  F603 77FC    ADDW       R7, R3, #0x0FFC
+  0x34181F62:  6038         STR        R0, [R7]
+  0x34181F64:  F2C3 4618    MOVT       R6, #0x3418              ; 0x3418209C = uwTick
+  0x34181F68:  6837         LDR        R7, [R6]
+  0x34181F6A:  BF00         NOP
+
.L4:
+  0x34181F6C:  681D         LDR        R5, [R3]
+  0x34181F6E:  4205         TST        R5, R0
+  0x34181F70:  F000 8082    BEQ.W      46L10                     ; 0x34182078
+  0x34181F74:  6835         LDR        R5, [R6]
+  0x34181F76:  1BED         SUBS       R5, R5, R7
+  0x34181F78:  2D01         CMP        R5, #1
+  0x34181F7A:  D9F7         BLS        46L4                      ; 0x34181F6C
+  0x34181F7C:  2003         MOVS       R0, #3
+  0x34181F7E:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L5:
+  0x34181F82:  F85E 1022    LDR.W      R1, [LR, R2, LSL #2]
+  0x34181F86:  F021 4180    BIC        R1, R1, #0x40000000
+  0x34181F8A:  F84E 1022    STR.W      R1, [LR, R2, LSL #2]
+  0x34181F8E:  F44F 7180    MOV.W      R1, #0x0100
+  0x34181F92:  FA01 F000    LSL.W      R0, R1, R0
+  0x34181F96:  F603 71FC    ADDW       R1, R3, #0x0FFC
+  0x34181F9A:  6008         STR        R0, [R1]
+  0x34181F9C:  F242 019C    MOVW       R1, #0x209C              ; 0x3418209C = uwTick
+  0x34181FA0:  F2C3 4118    MOVT       R1, #0x3418              ; 0x3418209C = uwTick
+  0x34181FA4:  680F         LDR        R7, [R1]
+  0x34181FA6:  BF00         NOP
+
.L6:
+  0x34181FA8:  681E         LDR        R6, [R3]
+  0x34181FAA:  4206         TST        R6, R0
+  0x34181FAC:  D006         BEQ        46L7                      ; 0x34181FBC
+  0x34181FAE:  680E         LDR        R6, [R1]
+  0x34181FB0:  1BF6         SUBS       R6, R6, R7
+  0x34181FB2:  2E01         CMP        R6, #1
+  0x34181FB4:  D9F8         BLS        46L6                      ; 0x34181FA8
+  0x34181FB6:  2003         MOVS       R0, #3
+  0x34181FB8:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L7:
+  0x34181FBC:  F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
+  0x34181FC0:  F020 6000    BIC        R0, R0, #0x08000000
+  0x34181FC4:  E05F         B          46L11                     ; 0x34182086
+
.L8:
+  0x34181FC6:  F85E 5022    LDR.W      R5, [LR, R2, LSL #2]
+  0x34181FCA:  27FF         MOVS       R7, #255
+  0x34181FCC:  F6C8 4700    MOVT       R7, #0x8C00
+  0x34181FD0:  F045 0504    ORR        R5, R5, #4
+  0x34181FD4:  F84E 5022    STR.W      R5, [LR, R2, LSL #2]
+  0x34181FD8:  F85C 5022    LDR.W      R5, [R12, R2, LSL #2]
+  0x34181FDC:  F025 6500    BIC        R5, R5, #0x08000000
+  0x34181FE0:  F84C 5022    STR.W      R5, [R12, R2, LSL #2]
+  0x34181FE4:  F85C 5022    LDR.W      R5, [R12, R2, LSL #2]
+  0x34181FE8:  403D         ANDS       R5, R7
+  0x34181FEA:  684F         LDR        R7, [R1, #4]
+  0x34181FEC:  433D         ORRS       R5, R7
+  0x34181FEE:  688F         LDR        R7, [R1, #8]
+  0x34181FF0:  EA45 5507    ORR.W      R5, R5, R7, LSL #20
+  0x34181FF4:  690F         LDR        R7, [R1, #16]
+  0x34181FF6:  EA45 2507    ORR.W      R5, R5, R7, LSL #8
+  0x34181FFA:  F84C 5022    STR.W      R5, [R12, R2, LSL #2]
+  0x34181FFE:  F85E 7022    LDR.W      R7, [LR, R2, LSL #2]
+  0x34182002:  694D         LDR        R5, [R1, #20]
+  0x34182004:  F027 577C    BIC        R7, R7, #0x3F000000
+  0x34182008:  EA47 67C5    ORR.W      R7, R7, R5, LSL #27
+  0x3418200C:  698D         LDR        R5, [R1, #24]
+  0x3418200E:  EA47 6705    ORR.W      R7, R7, R5, LSL #24
+  0x34182012:  F84E 7022    STR.W      R7, [LR, R2, LSL #2]
+  0x34182016:  F856 7022    LDR.W      R7, [R6, R2, LSL #2]
+  0x3418201A:  68CD         LDR        R5, [R1, #12]
+  0x3418201C:  F007 477F    AND        R7, R7, #0xFF000000
+  0x34182020:  432F         ORRS       R7, R5
+  0x34182022:  F846 7022    STR.W      R7, [R6, R2, LSL #2]
+  0x34182026:  F85E 7022    LDR.W      R7, [LR, R2, LSL #2]
+  0x3418202A:  F027 0708    BIC        R7, R7, #8
+  0x3418202E:  F84E 7022    STR.W      R7, [LR, R2, LSL #2]
+  0x34182032:  68C9         LDR        R1, [R1, #12]
+  0x34182034:  2900         CMP        R1, #0
+  0x34182036:  BF1E         ITTT       NE
+  0x34182038:  F85E 1022    LDRNE.W    R1, [LR, R2, LSL #2]
+  0x3418203C:  F041 010A    ORRNE      R1, R1, #10
+  0x34182040:  F84E 1022    STRNE.W    R1, [LR, R2, LSL #2]
+  0x34182044:  F85E 1022    LDR.W      R1, [LR, R2, LSL #2]
+  0x34182048:  F041 4180    ORR        R1, R1, #0x40000000
+  0x3418204C:  F041 0101    ORR        R1, R1, #1
+  0x34182050:  F84E 1022    STR.W      R1, [LR, R2, LSL #2]
+  0x34182054:  F64F 0100    MOVW       R1, #0xF800
+  0x34182058:  F6CF 71FF    MOVT       R1, #0xFFFF
+  0x3418205C:  F848 0001    STR.W      R0, [R8, R1]
+  0x34182060:  6821         LDR        R1, [R4]
+  0x34182062:  BF00         NOP
+
.L9:
+  0x34182064:  681A         LDR        R2, [R3]
+  0x34182066:  4202         TST        R2, R0
+  0x34182068:  D10F         BNE        46L12                     ; 0x3418208A
+  0x3418206A:  6822         LDR        R2, [R4]
+  0x3418206C:  1A52         SUBS       R2, R2, R1
+  0x3418206E:  2A01         CMP        R2, #1
+  0x34182070:  D9F8         BLS        46L9                      ; 0x34182064
+  0x34182072:  2003         MOVS       R0, #3
+  0x34182074:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L10:
+  0x34182078:  F85C 0022    LDR.W      R0, [R12, R2, LSL #2]
+  0x3418207C:  F020 40F0    BIC        R0, R0, #0x78000000
+  0x34182080:  4308         ORRS       R0, R1
+  0x34182082:  F040 6000    ORR        R0, R0, #0x08000000
+
.L11:
+  0x34182086:  F84C 0022    STR.W      R0, [R12, R2, LSL #2]
+
.L12:
+  0x3418208A:  2000         MOVS       R0, #0
+  0x3418208C:  E8BD 81F0    POP.W      123R4-R8, PC}
+
.L13:
+  0x34182090:  2001         MOVS       R0, #1
+  0x34182092:  E8BD 81F0    POP.W      123R4-R8, PC}
+
+

Section .init_array from STM32N6xx_Startup.o, size=4, align=4

+ +
+  0x34182098:  34180B69     DC.W       SystemCoreClockUpdate
+
+

Section .bss.uwTick from blto2_FSBL_lto.o, size=4, align=4

+ +
+
uwTick:
+  0x3418209C:  00           DC.B       0x00                     ; '\0'
+  0x3418209D:  00           DC.B       0x00                     ; '\0'
+  0x3418209E:  00           DC.B       0x00                     ; '\0'
+  0x3418209F:  00           DC.B       0x00                     ; '\0'
+
+

Section .bss.uwTickPrio from blto2_FSBL_lto.o, size=1, align=4

+ +
+
uwTickPrio:
+  0x341820A0:  03           DC.B       0x03                     ; '\x03'
+
+

Section .data.SystemCoreClock from blto2_FSBL_lto.o, size=4, align=4

+ +
+
SystemCoreClock:
+  0x341820A4:  00           DC.B       0x00                     ; '\0'
+  0x341820A5:  90           DC.B       0x90                     ; '\x90'
+  0x341820A6:  D0           DC.B       0xD0                     ; '\xD0'
+  0x341820A7:  03           DC.B       0x03                     ; '\x03'
+
+

Section .segger.init.__SEGGER_init_ctors from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=36, align=4

+ +
+
__SEGGER_init_ctors:
+  0x341820A8:  B500         PUSH       123LR}
+  0x341820AA:  4806         LDR        R0, =0x34182098          ; [PC, #24] [0x341820C4] 
+  0x341820AC:  4906         LDR        R1, =uwTick              ; [PC, #24] [0x341820C8] =0x3418209C 
+
.L1:
+  0x341820AE:  4288         CMP        R0, R1
+  0x341820B0:  D005         BEQ        46L2                      ; 0x341820BE
+  0x341820B2:  6802         LDR        R2, [R0]
+  0x341820B4:  3004         ADDS       R0, #4
+  0x341820B6:  B403         PUSH       123R0-R1}
+  0x341820B8:  4790         BLX        R2
+  0x341820BA:  BC03         POP        123R0-R1}
+  0x341820BC:  E7F7         B          46L1                      ; 0x341820AE
+
.L2:
+  0x341820BE:  BC08         POP        123R3}
+  0x341820C0:  4718         BX         R3
+  0x341820C2:  0000         NOP
+  0x341820C4:  34182098     DC.W       34182098               ; R_ARM_ABS32
+  0x341820C8:  3418209C     DC.W       uwTick
+
+

Section .segger.init.table from [ Linker created ], size=36, align=4

+ +
+  0x341820CC:  341820F5     DC.W       __SEGGER_init_zero
+  0x341820D0:  9C           DC.B       0x9C                     ; '\x9C'
+  0x341820D1:  20           DC.B       0x20                     ; ' '
+  0x341820D2:  18           DC.B       0x18                     ; '\x18'
+  0x341820D3:  34           DC.B       0x34                     ; '4'
+  0x341820D4:  05           DC.B       0x05                     ; '\x05'
+  0x341820D5:  00           DC.B       0x00                     ; '\0'
+  0x341820D6:  00           DC.B       0x00                     ; '\0'
+  0x341820D7:  00           DC.B       0x00                     ; '\0'
+  0x341820D8:  34182107     DC.W       __SEGGER_init_copy
+  0x341820DC:  A4           DC.B       0xA4                     ; '\xA4'
+  0x341820DD:  20           DC.B       0x20                     ; ' '
+  0x341820DE:  18           DC.B       0x18                     ; '\x18'
+  0x341820DF:  34           DC.B       0x34                     ; '4'
+  0x341820E0:  341820F0     DC.W       341820F0               ; R_ARM_ABS32
+  0x341820E4:  04           DC.B       0x04                     ; '\x04'
+  0x341820E5:  00           DC.B       0x00                     ; '\0'
+  0x341820E6:  00           DC.B       0x00                     ; '\0'
+  0x341820E7:  00           DC.B       0x00                     ; '\0'
+  0x341820E8:  341820A9     DC.W       __SEGGER_init_ctors
+  0x341820EC:  34181423     DC.W       __SEGGER_init_done
+
+

Section .segger.init.data from [ Linker created ], size=4, align=4

+ +
+  0x341820F0:  00           DC.B       0x00                     ; '\0'
+  0x341820F1:  90           DC.B       0x90                     ; '\x90'
+  0x341820F2:  D0           DC.B       0xD0                     ; '\xD0'
+  0x341820F3:  03           DC.B       0x03                     ; '\x03'
+
+

Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2

+ +
+
__SEGGER_init_zero:
+  0x341820F4:  6820         LDR        R0, [R4]
+  0x341820F6:  6861         LDR        R1, [R4, #4]
+  0x341820F8:  3408         ADDS       R4, #8
+  0x341820FA:  2200         MOVS       R2, #0
+  0x341820FC:  E000         B          46L2                      ; 0x34182100
+
.L1:
+  0x341820FE:  5442         STRB       R2, [R0, R1]
+
.L2:
+  0x34182100:  1E49         SUBS       R1, R1, #1
+  0x34182102:  D5FC         BPL        46L1                      ; 0x341820FE
+  0x34182104:  4770         BX         LR
+
+

Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v81mml_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2

+ +
+
__SEGGER_init_copy:
+  0x34182106:  6820         LDR        R0, [R4]
+  0x34182108:  6861         LDR        R1, [R4, #4]
+  0x3418210A:  68A2         LDR        R2, [R4, #8]
+  0x3418210C:  340C         ADDS       R4, #12
+  0x3418210E:  E001         B          46L2                      ; 0x34182114
+
.L1:
+  0x34182110:  5C8B         LDRB       R3, [R1, R2]
+  0x34182112:  5483         STRB       R3, [R0, R2]
+
.L2:
+  0x34182114:  1E52         SUBS       R2, R2, #1
+  0x34182116:  D5FB         BPL        46L1                      ; 0x34182110
+  0x34182118:  4770         BX         LR
+
+

Section .bss.block.stack from [ Linker created ], size=8192, align=8

+ +
+(341FE000-341FFFFF excluded)
+
+

OPTIMIZATION REPORT

+

Transformations performed

+ + + + + + + + + + + + + + +

LINK SUMMARY

+ + +
+  7 304 bytes read-only  code    + 
+    116 bytes read-only  data    =   7 420 bytes read-only (total)
+  8 201 bytes read-write data
+
+ + +
TransformationBytes saved
Dedupe code384
Total:384
+ + + + + + + + + + + + + + + + +
NameRangeSizeUsedUnusedAlignment Loss
AXI_RAM234180400-341FFFFF523 26415 625 2.99507 622 97.0117 0.00
+ + +
+Link complete: 0 errors.
+
+ Index: trunk/firmware/FSBL/SES/SEGGER_THUMB_Startup.s =================================================================== --- trunk/firmware/FSBL/SES/SEGGER_THUMB_Startup.s (revision 16) +++ trunk/firmware/FSBL/SES/SEGGER_THUMB_Startup.s (revision 16) @@ -0,0 +1,288 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2026 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_THUMB_Startup.s +Purpose : Generic runtime init startup code for ARM CPUs running + in THUMB mode. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + + .syntax unified + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .thumb_func + .code 16 +\Name: +.endm +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .weak \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + ldr R4, =__SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + ldr R0, [R4] // Get next initialization function from table + adds R4, R4, #4 // Increment table pointer to point to function arguments + blx R0 // Call initialization function + b L(RunInit) + // +MARK_FUNC __SEGGER_init_done +MARK_FUNC __startup_complete + // + // Time to call main(), the application entry point. + // +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init R0 and R1. + // + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + b . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load R0 and R1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + movs R0, #ARGSSPACE + ldr R1, =__SEGGER_init_arg_data + bl SEGGER_SEMIHOST_GetArgs + ldr R1, =__SEGGER_init_arg_data + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + bl exit // Call exit function + b . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mov R5, R0 // Save the exit parameter/return result + // + // Call destructors + // + ldr R0, =__dtors_start__ // Pointer to destructor list + ldr R1, =__dtors_end__ +L(Loop): + cmp R0, R1 + beq L(End) // Reached end of destructor list? => Done + ldr R2, [R0] // Load current destructor address into R2 + adds R0, R0, #4 // Increment pointer + push {R0-R1} // Save R0 and R1 + blx R2 // Call destructor + pop {R0-R1} // Restore R0 and R1 + b L(Loop) +L(End): + // + // Call atexit functions + // + bl __SEGGER_RTL_execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mov R0, R5 + // + // Entry points for _exit and _Exit, which terminate immediately. + // Note: Destructors and registered atexit functions are not called. File descriptors are not closed. + // +MARK_FUNC _exit +MARK_FUNC _Exit + bl SEGGER_SEMIHOST_Exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + b L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss + .balign 4 +__SEGGER_init_arg_data: + .space ARGSSPACE + .size __SEGGER_init_arg_data, .-__SEGGER_init_arg_data + .type __SEGGER_init_arg_data, %object +#endif + +/*************************** End of file ****************************/ Index: trunk/firmware/FSBL/SES/STM32N657X0HxQ_MemoryMap.xml =================================================================== --- trunk/firmware/FSBL/SES/STM32N657X0HxQ_MemoryMap.xml (revision 16) +++ trunk/firmware/FSBL/SES/STM32N657X0HxQ_MemoryMap.xml (revision 16) @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + Index: trunk/firmware/FSBL/SES/STM32N657_Registers.xml =================================================================== --- trunk/firmware/FSBL/SES/STM32N657_Registers.xml (revision 16) +++ trunk/firmware/FSBL/SES/STM32N657_Registers.xml (revision 16) @@ -0,0 +1,247787 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/SEGGER_STM32N6xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/SEGGER_STM32N6xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/SEGGER_STM32N6xx.h (revision 16) @@ -0,0 +1,64 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2026 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* - Neither the name of SEGGER Microcontroller GmbH * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. * +* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +#ifndef __SEGGER_STM32N6xx_h +#define __SEGGER_STM32N6xx_h + +#if defined(STM32N657xx) + +#include "stm32n657xx.h" + +#elif defined(STM32N647xx) + +#include "stm32n647xx.h" + +#elif defined(STM32N645xx) + +#include "stm32n645xx.h" + +#elif defined(STM32N655xx) + +#include "stm32n655xx.h" + +#endif + +#endif Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n645xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n645xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n645xx.h (revision 16) @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n645xx.h + * @author MCD Application Team + * @brief CMSIS STM32N645xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N645XX_H +#define PARTITION_STM32N645XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// IAC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// CSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// Reserved <0=> Secure state <1=> Non-Secure state +// LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N645XX_H */ Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n647xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n647xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n647xx.h (revision 16) @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n647xx.h + * @author MCD Application Team + * @brief CMSIS STM32N647xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N647XX_H +#define PARTITION_STM32N647XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// IAC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// CSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// VENC_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// Reserved <0=> Secure state <1=> Non-Secure state +// LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N647XX_H */ Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n655xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n655xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n655xx.h (revision 16) @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n655xx.h + * @author MCD Application Team + * @brief CMSIS STM32N655xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N655XX_H +#define PARTITION_STM32N655XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// IAC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// CSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// Reserved <0=> Secure state <1=> Non-Secure state +// LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N655XX_H */ Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n657xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n657xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n657xx.h (revision 16) @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N657XX_H +#define PARTITION_STM32N657XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// IAC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// CRYP_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// MCE1_IRQn <0=> Secure state <1=> Non-Secure state +// MCE2_IRQn <0=> Secure state <1=> Non-Secure state +// MCE3_IRQn <0=> Secure state <1=> Non-Secure state +// MCE4_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// CSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// VENC_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// Reserved <0=> Secure state <1=> Non-Secure state +// LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N657XX_H */ Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/partition_stm32n6xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/partition_stm32n6xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/partition_stm32n6xx.h (revision 16) @@ -0,0 +1,71 @@ +/** + ****************************************************************************** + * @file partition_stm32n6xx.h + * @author MCD Application Team + * @brief CMSIS STM32N6xx Device Header File for Initial Setup for + * Secure / Non-Secure Zones based on CMSIS CORE V5.3.1 + * + * The file is included in system_stm32L5xx_s.c in secure application. + * It includes the configuration section that allows to select the + * STM32N6xx device partitioning file for system core secure attributes + * and interrupt secure and non-secure assignment. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32N6xx + * @{ + */ + +#ifndef PARTITION_STM32N6XX_H +#define PARTITION_STM32N6XX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Secure_configuration_section + * @{ + */ + +#if defined(STM32N657xx) + #include "partition_stm32n657xx.h" +#elif defined(STM32N655xx) + #include "partition_stm32n655xx.h" +#elif defined(STM32N647xx) + #include "partition_stm32n647xx.h" +#elif defined(STM32N645xx) + #include "partition_stm32n645xx.h" +#else + #error "Please select first the target STM32N6xx device used in your application (in stm32n6xx.h file)" +#endif + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PARTITION_STM32N6XX_H */ + +/** + * @} + */ + +/** + * @} + */ + Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/stm32n645xx.h =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/stm32n645xx.h (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/stm32n645xx.h (revision 16) @@ -0,0 +1,41401 @@ +/** + ****************************************************************************** + * @file stm32n645xx.h + * @author MCD Application Team + * @brief CMSIS STM32N645xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32N645xx_H +#define STM32N645xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32N645xx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ====================================== ARM Cortex-M55 Specific Interrupt Numbers ======================================== */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ +#endif + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* ====================================== STM32N6xx Specific Interrupt Numbers ============================================= */ + PVD_PVM_IRQn = 0, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */ + DTS_IRQn = 2, /*!< Thermal Sensor interruption */ + RCC_IRQn = 3, /*!< RCC non-secure global interrupts through EXTI Line detection */ + LOCKUP_IRQn = 4, /*!< LOCKUP / (no Overstack in CM55) */ + CACHE_ECC_IRQn = 5, /*!< Error ECC cache interrupt */ + TCM_ECC_IRQn = 6, /*!< TCM ECC interrupts */ + BKP_ECC_IRQn = 7, /*!< Backup RAM Interrupts */ + FPU_IRQn = 8, /*!< FPU interrupt */ + RTC_S_IRQn = 10, /*!< RTC secure interrupts through EXTI Line detection */ + TAMP_IRQn = 11, /*!< Tamper secure and non-secure interrupts through EXTI Line detection */ + RIFSC_TAMPER_IRQn = 12, /*!< RIF Tamper interrupts */ + IAC_IRQn = 13, /*!< IAC interrupt */ + RCC_S_IRQn = 14, /*!< RCC secure global interrupts through EXTI Line detection */ + RTC_IRQn = 16, /*!< RTC non-secure interrupts through EXTI Line detection */ + IWDG_IRQn = 18, /*!< Internal Watchdog interrupt */ + WWDG_IRQn = 19, /*!< Window Watchdog interrupt */ + EXTI0_IRQn = 20, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 21, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 22, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 23, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 24, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 25, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 26, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 27, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 28, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 29, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 30, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 31, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 32, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 33, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 34, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 35, /*!< EXTI Line15 interrupt */ + PKA_IRQn = 38, /*!< PKA interrupt */ + HASH_IRQn = 39, /*!< HASH interrupt */ + RNG_IRQn = 40, /*!< RNG global interrupt */ + ADC1_2_IRQn = 46, /*!< ADC1 & ADC2 interrupt */ + CSI_IRQn = 47, /*!< CSI global interrupt */ + DCMIPP_IRQn = 48, /*!< DCMIPP global interrupt */ + PAHB_ERR_IRQn = 52, /*!< PAHB error interrupt */ + LTDC_LO_IRQn = 58, /*!< LTDC low-layer global interrupt */ + LTDC_LO_ERR_IRQn = 59, /*!< LTDC low-layer error interrupt */ + DMA2D_IRQn = 60, /*!< DMA2D global interrupt */ + JPEG_IRQn = 61, /*!< JPEG global interrupt */ + VENC_IRQn = 62, /*!< VENC global interrupt */ + GFXMMU_IRQn = 63, /*!< GFXMMU global interrupt */ + GFXTIM_IRQn = 64, /*!< GFXTIM global interrupt */ + GPU2D_IRQn = 65, /*!< GPU2D interrupt */ + GPU2D_ER_IRQn = 66, /*!< GPU2D error interrupt */ + ICACHE_IRQn = 67, /*!< GPU2D cache interrupt */ + HPDMA1_Channel0_IRQn = 68, /*!< HPDMA1 Channel 0 global interrupt */ + HPDMA1_Channel1_IRQn = 69, /*!< HPDMA1 Channel 1 global interrupt */ + HPDMA1_Channel2_IRQn = 70, /*!< HPDMA1 Channel 2 global interrupt */ + HPDMA1_Channel3_IRQn = 71, /*!< HPDMA1 Channel 3 global interrupt */ + HPDMA1_Channel4_IRQn = 72, /*!< HPDMA1 Channel 4 global interrupt */ + HPDMA1_Channel5_IRQn = 73, /*!< HPDMA1 Channel 5 global interrupt */ + HPDMA1_Channel6_IRQn = 74, /*!< HPDMA1 Channel 6 global interrupt */ + HPDMA1_Channel7_IRQn = 75, /*!< HPDMA1 Channel 7 global interrupt */ + HPDMA1_Channel8_IRQn = 76, /*!< HPDMA1 Channel 8 global interrupt */ + HPDMA1_Channel9_IRQn = 77, /*!< HPDMA1 Channel 9 global interrupt */ + HPDMA1_Channel10_IRQn = 78, /*!< HPDMA1 Channel 10 global interrupt */ + HPDMA1_Channel11_IRQn = 79, /*!< HPDMA1 Channel 11 global interrupt */ + HPDMA1_Channel12_IRQn = 80, /*!< HPDMA1 Channel 12 global interrupt */ + HPDMA1_Channel13_IRQn = 81, /*!< HPDMA1 Channel 13 global interrupt */ + HPDMA1_Channel14_IRQn = 82, /*!< HPDMA1 Channel 14 global interrupt */ + HPDMA1_Channel15_IRQn = 83, /*!< HPDMA1 Channel 15 global interrupt */ + GPDMA1_Channel0_IRQn = 84, /*!< GPDMA1 Channel 0 interrupt */ + GPDMA1_Channel1_IRQn = 85, /*!< GPDMA1 Channel 1 interrupt */ + GPDMA1_Channel2_IRQn = 86, /*!< GPDMA1 Channel 2 interrupt */ + GPDMA1_Channel3_IRQn = 87, /*!< GPDMA1 Channel 3 interrupt */ + GPDMA1_Channel4_IRQn = 88, /*!< GPDMA1 Channel 4 interrupt */ + GPDMA1_Channel5_IRQn = 89, /*!< GPDMA1 Channel 5 interrupt */ + GPDMA1_Channel6_IRQn = 90, /*!< GPDMA1 Channel 6 interrupt */ + GPDMA1_Channel7_IRQn = 91, /*!< GPDMA1 Channel 7 interrupt */ + GPDMA1_Channel8_IRQn = 92, /*!< GPDMA1 Channel 8 interrupt */ + GPDMA1_Channel9_IRQn = 93, /*!< GPDMA1 Channel 9 interrupt */ + GPDMA1_Channel10_IRQn = 94, /*!< GPDMA1 Channel 10 interrupt */ + GPDMA1_Channel11_IRQn = 95, /*!< GPDMA1 Channel 11 interrupt */ + GPDMA1_Channel12_IRQn = 96, /*!< GPDMA1 Channel 12 interrupt */ + GPDMA1_Channel13_IRQn = 97, /*!< GPDMA1 Channel 13 interrupt */ + GPDMA1_Channel14_IRQn = 98, /*!< GPDMA1 Channel 14 interrupt */ + GPDMA1_Channel15_IRQn = 99, /*!< GPDMA1 Channel 15 interrupt */ + I2C1_EV_IRQn = 100, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 101, /*!< I2C1 error interrupt */ + I2C2_EV_IRQn = 102, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 103, /*!< I2C2 error interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + I2C4_EV_IRQn = 106, /*!< I2C4 event interrupt */ + I2C4_ER_IRQn = 107, /*!< I2C4 error interrupt */ + I3C1_EV_IRQn = 108, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 109, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 110, /*!< I3C2 event interrupt */ + I3C2_ER_IRQn = 111, /*!< I3C2 error interrupt */ + TIM1_BRK_IRQn = 112, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 113, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 114, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 115, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 116, /*!< TIM2 global interrupt */ + TIM3_IRQn = 117, /*!< TIM3 global interrupt */ + TIM4_IRQn = 118, /*!< TIM4 global interrupt */ + TIM5_IRQn = 119, /*!< TIM5 global interrupt */ + TIM6_IRQn = 120, /*!< TIM6 global interrupt */ + TIM7_IRQn = 121, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 122, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 123, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 124, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 125, /*!< TIM8 Capture Compare interrupt */ + TIM9_IRQn = 126, /*!< TIM9 global interrupt */ + TIM10_IRQn = 127, /*!< TIM10 global interrupt */ + TIM11_IRQn = 128, /*!< TIM11 global interrupt */ + TIM12_IRQn = 129, /*!< TIM12 global interrupt */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + TIM15_IRQn = 132, /*!< TIM15 global interrupt */ + TIM16_IRQn = 133, /*!< TIM16 global interrupt */ + TIM17_IRQn = 134, /*!< TIM17 global interrupt */ + TIM18_IRQn = 135, /*!< TIM18 global interrupt */ + LPTIM1_IRQn = 136, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 137, /*!< LPTIM2 global interrupt */ + LPTIM3_IRQn = 138, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 139, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 140, /*!< LPTIM5 global interrupt */ + ADF1_FLT0_IRQn = 141, /*!< ADF1 Filter 0 global interrupt */ + MDF1_FLT0_IRQn = 142, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 143, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 144, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 145, /*!< MDF1 Filter 3 global interrupt */ + MDF1_FLT4_IRQn = 146, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 147, /*!< MDF1 Filter 5 global interrupt */ + SAI1_A_IRQn = 148, /*!< Serial Audio Interface 1 block A interrupt */ + SAI1_B_IRQn = 149, /*!< Serial Audio Interface 1 block B interrupt */ + SAI2_A_IRQn = 150, /*!< Serial Audio Interface 2 block A interrupt */ + SAI2_B_IRQn = 151, /*!< Serial Audio Interface 2 block B interrupt */ + SPDIFRX1_IRQn = 152, /*!< SPDIFRX1 interrupt */ + SPI1_IRQn = 153, /*!< SPI1 global interrupt */ + SPI2_IRQn = 154, /*!< SPI2 global interrupt */ + SPI3_IRQn = 155, /*!< SPI3 global interrupt */ + SPI4_IRQn = 156, /*!< SPI4 global interrupt */ + SPI5_IRQn = 157, /*!< SPI5 global interrupt */ + SPI6_IRQn = 158, /*!< SPI6 global interrupt */ + USART1_IRQn = 159, /*!< USART1 global interrupt */ + USART2_IRQn = 160, /*!< USART2 global interrupt */ + USART3_IRQn = 161, /*!< USART3 global interrupt */ + UART4_IRQn = 162, /*!< UART4 global interrupt */ + UART5_IRQn = 163, /*!< UART5 global interrupt */ + USART6_IRQn = 164, /*!< USART3 global interrupt */ + UART7_IRQn = 165, /*!< UART7 global interrupt */ + UART8_IRQn = 166, /*!< UART8 global interrupt */ + UART9_IRQn = 167, /*!< UART9 global interrupt */ + USART10_IRQn = 168, /*!< USART10 global interrupt */ + LPUART1_IRQn = 169, /*!< LPUART1 global interrupt */ + XSPI1_IRQn = 170, /*!< XSPI1 global interrupt */ + XSPI2_IRQn = 171, /*!< XSPI2 global interrupt */ + XSPI3_IRQn = 172, /*!< XSPI3 global interrupt */ + FMC_IRQn = 173, /*!< FMC global interrupt */ + SDMMC1_IRQn = 174, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 175, /*!< SDMMC2 global interrupt */ + UCPD1_IRQn = 176, /*!< UCPD1 global interrupt */ + USB1_OTG_HS_IRQn = 177, /*!< USB1 OTG HS interrupt */ + USB2_OTG_HS_IRQn = 178, /*!< USB2 OTG HS interrupt */ + ETH1_IRQn = 179, /*!< ETH1 global interrupt */ + FDCAN1_IT0_IRQn = 180, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 181, /*!< FDCAN1 interrupt 1 */ + FDCAN2_IT0_IRQn = 182, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 183, /*!< FDCAN2 interrupt 1 */ + FDCAN3_IT0_IRQn = 184, /*!< FDCAN3 interrupt 0 */ + FDCAN3_IT1_IRQn = 185, /*!< FDCAN3 interrupt 1 */ + FDCAN_CU_IRQn = 186, /*!< FDCAN Clock Unit interrupt */ + MDIOS_IRQn = 187, /*!< MDIOS global interrupt */ + DCMI_PSSI_IRQn = 188, /*!< DCMI/PSSI global interrupt */ + WAKEUP_PIN_IRQn = 189, /*!< Wake-up pins interrupt */ + CTI_INT0_IRQn = 190, /*!< CTI INT0 interrupt */ + CTI_INT1_IRQn = 191, /*!< CTI INT1 interrupt */ + LTDC_UP_IRQn = 193, /*!< LTDC up-layer global interrupt */ + LTDC_UP_ERR_IRQn = 194, /*!< LTDC up-layer error interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Configuration of the Cortex-M55 Processor and Core Peripherals + */ +#define __CM55_REV 0x0101U /*!< Cortex-M55 revision r1p1 */ +#define __FPU_PRESENT 1U /*!< CM55 Floating Point Unit present */ +#define __DSP_PRESENT 1U /*!< CM55 Digital Signal Processing Unit present */ +#define __MPU_PRESENT 1U /*!< CM55 Memory Programming Unit present */ +#define __ICACHE_PRESENT 1U /*!< CM55 Instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM55 Data cache present */ +#define __VTOR_PRESENT 1U /*!< CM55 Vector table offset register present */ +#define __PMU_PRESENT 1U /*!< CM55 Performance Monitoring Unit present */ +#define __PMU_NUM_EVENTCNT 8U /*!< CM55 can monitor up to 8 PMU events */ +#define __NVIC_PRIO_BITS 4U /*!< CM55 uses 4 bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __SAUREGION_PRESENT 1U /*!< SAU regions present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CPU_IN_SECURE_STATE +#endif + +#define CPU_AS_TRUSTED_DOMAIN + +#include "core_cm55.h" /*!< ARM Cortex-M55 processor and core peripherals */ +#include "system_stm32n6xx.h" /*!< STM32N6xx System */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32N6xx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020-0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044-0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ + __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ + __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ + __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074-0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090-0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ + __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ + __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ + __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ + __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ + __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x0C8-0x0CC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ +} ADC_Common_TypeDef; + +/** + * @brief Boot and Security + */ + +typedef struct +{ + __IO uint32_t FVRw[384]; /*!< BSEC fuse word (0-383) value register, Address offset: 0x000-0x5FC */ + uint32_t RESERVED0[128]; /*!< Reserved, Address offset: 0x600-0x7FC */ + __IO uint32_t SPLOCKx[12]; /*!< BSEC sticky program lock register (0-11), Address offset: 0x800-0x82C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x830-0x83C */ + __IO uint32_t SWLOCKx[12]; /*!< BSEC sticky write lock register (0-11), Address offset: 0x840-0x86C */ + uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x870-0x87C */ + __IO uint32_t SRLOCKx[12]; /*!< BSEC sticky reload lock register (0-11), Address offset: 0x880-0x8AC */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x8B0-0x8BC */ + __IO uint32_t OTPVLDRx[12]; /*!< BSEC OTP valid register (0-11), Address offset: 0x8C0-0x8EC */ + uint32_t RESERVED4[20]; /*!< Reserved, Address offset: 0x8F0-0x93C */ + __IO uint32_t SFSRx[12]; /*!< BSEC shadowed fuses status register (0-11), Address offset: 0x940-0x96C */ + uint32_t RESERVED5[165]; /*!< Reserved, Address offset: 0x970-0xC00 */ + __IO uint32_t OTPCR; /*!< BSEC OTP control register, Address offset: 0xC04 */ + __IO uint32_t WDR; /*!< BSEC write data register, Address offset: 0xC08 */ + uint32_t RESERVED6[125]; /*!< Reserved, Address offset: 0xC0C-0xDFC */ + __IO uint32_t SCRATCHRx[4]; /*!< BSEC scratch register (0-3), Address offset: 0xE00-0xE0C */ + __IO uint32_t LOCKR; /*!< BSEC lock register, Address offset: 0xE10 */ + __IO uint32_t JTAGINR; /*!< BSEC JTAG input register, Address offset: 0xE14 */ + __IO uint32_t JTAGOUTR; /*!< BSEC JTAG output register, Address offset: 0xE18 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xE1C-0xE20 */ + __IO uint32_t UNMAPR; /*!< BSEC unmap register, Address offset: 0xE24 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0xE28-0xE3C */ + __IO uint32_t SR; /*!< BSEC status register, Address offset: 0xE40 */ + __IO uint32_t OTPSR; /*!< BSEC OTP status register, Address offset: 0xE44 */ + uint32_t RESERVED9[14]; /*!< Reserved, Address offset: 0xE48-0xE7C */ + __IO uint32_t EPOCHRx[2]; /*!< BSEC epoch register (0-1), Address offset: 0xE80-0xE84 */ + __IO uint32_t EPOCHSELR; /*!< BSEC epoch select register, Address offset: 0xE88 */ + __IO uint32_t DBGCR; /*!< BSEC debug control register, Address offset: 0xE8C */ + __IO uint32_t AP_UNLOCK; /*!< BSEC AP unlock, Address offset: 0xE90 */ + __IO uint32_t HDPLSR; /*!< BSEC hide protection level status register, Address offset: 0xE94 */ + __IO uint32_t HDPLCR; /*!< BSEC hide protection level control register, Address offset: 0xE98 */ + __IO uint32_t NEXTLR; /*!< BSEC next hide protection level register, Address offset: 0xE9C */ + uint32_t RESERVED10[40]; /*!< Reserved, Address offset: 0xEA0-0xF3C */ + __IO uint32_t WOSCRx[8]; /*!< BSEC write once scratch register (0-7), Address offset: 0xF40-0xF5C */ + uint32_t RESERVED11[34]; /*!< Reserved, Address offset: 0xF60-0xFE4 */ + __IO uint32_t HRCR; /*!< BSEC hot reset count register, Address offset: 0xFE8 */ + __IO uint32_t WRCR; /*!< BSEC warm reset count register, Address offset: 0xFEC */ +} BSEC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/* + * @brief (CSI) + */ +typedef struct +{ + __IO uint32_t CR; /*!< CSI-2 Host control register Address offset: 0x0000 */ + __IO uint32_t PCR; /*!< CSI-2 Host DPHY_RX control register Address offset: 0x0004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x0008-0x000C */ + __IO uint32_t VC0CFGR1; /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */ + __IO uint32_t VC0CFGR2; /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */ + __IO uint32_t VC0CFGR3; /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */ + __IO uint32_t VC0CFGR4; /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */ + __IO uint32_t VC1CFGR1; /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */ + __IO uint32_t VC1CFGR2; /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */ + __IO uint32_t VC1CFGR3; /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */ + __IO uint32_t VC1CFGR4; /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */ + __IO uint32_t VC2CFGR1; /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */ + __IO uint32_t VC2CFGR2; /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */ + __IO uint32_t VC2CFGR3; /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */ + __IO uint32_t VC2CFGR4; /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */ + __IO uint32_t VC3CFGR1; /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */ + __IO uint32_t VC3CFGR2; /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */ + __IO uint32_t VC3CFGR3; /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */ + __IO uint32_t VC3CFGR4; /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */ + __IO uint32_t LB0CFGR; /*!< CSI-2 Host line byte 0 configuration register Address offset: 0x0050 */ + __IO uint32_t LB1CFGR; /*!< CSI-2 Host line byte 1 configuration register Address offset: 0x0054 */ + __IO uint32_t LB2CFGR; /*!< CSI-2 Host line byte 2 configuration register Address offset: 0x0058 */ + __IO uint32_t LB3CFGR; /*!< CSI-2 Host line byte 3 configuration register Address offset: 0x005C */ + __IO uint32_t TIM0CFGR; /*!< CSI-2 Host timer 0 configuration register Address offset: 0x0060 */ + __IO uint32_t TIM1CFGR; /*!< CSI-2 Host timer 1 configuration register Address offset: 0x0064 */ + __IO uint32_t TIM2CFGR; /*!< CSI-2 Host timer 2 configuration register Address offset: 0x0068 */ + __IO uint32_t TIM3CFGR; /*!< CSI-2 Host timer 3 configuration register Address offset: 0x006C */ + __IO uint32_t LMCFGR; /*!< CSI-2 Host lane merger configuration register Address offset: 0x0070 */ + __IO uint32_t PRGITR; /*!< CSI-2 Host program interrupt register Address offset: 0x0074 */ + __IO uint32_t WDR; /*!< CSI-2 Host watchdog register Address offset: 0x0078 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x007C */ + __IO uint32_t IER0; /*!< CSI-2 Host Interrupt enable register 0 Address offset: 0x0080 */ + __IO uint32_t IER1; /*!< CSI-2 Host Interrupt enable register 1 Address offset: 0x0084 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0088-0x008C */ + __IO uint32_t SR0; /*!< CSI-2 Host status register 0 Address offset: 0x0090 */ + __IO uint32_t SR1; /*!< CSI-2 Host status register 1 Address offset: 0x0094 */ + uint32_t RESERVED3[26]; /*!< Reserved Address offset: 0x0098-0x00FC */ + __IO uint32_t FCR0; /*!< CSI-2 Host Flag clear register 0 Address offset: 0x0100 */ + __IO uint32_t FCR1; /*!< CSI-2 Host Flag clear register 1 Address offset: 0x0104 */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x0108-0x010C */ + __IO uint32_t SPDFR; /*!< CSI-2 Host short packet data field register Address offset: 0x0110 */ + __IO uint32_t ERR1; /*!< CSI-2 Host error register 1 Address offset: 0x0114 */ + __IO uint32_t ERR2; /*!< CSI-2 Host error register 2 Address offset: 0x0118 */ + uint32_t RESERVED5[953]; /*!< Reserved Address offset: 0x011C-0x0FFC */ + __IO uint32_t PRCR; /*!< CSI PHY reset control register Address offset: 0x1000 */ + __IO uint32_t PMCR; /*!< CSI PHY mode control register Address offset: 0x1004 */ + __IO uint32_t PFCR; /*!< CSI PHY frequency control register Address offset: 0x1008 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x100C */ + __IO uint32_t PTCR0; /*!< CSI PHY test control register 0 Address offset: 0x1010 */ + __IO uint32_t PTCR1; /*!< CSI PHY test control register 1 Address offset: 0x1014 */ + __IO uint32_t PTSR; /*!< CSI PHY test status register Address offset: 0x1018 */ + uint32_t RESERVED7[1017]; /*!< Reserved Address offset: 0x101C-0x1FFC */ +} CSI_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x10 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1HFZ1 freeze register, Address offset: 0x14 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x18 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x1C */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register, Address offset: 0x20 */ + __IO uint32_t AHB1FZ1; /*!< Debug MCU AHB1FZ1 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB5FZ1; /*!< Debug MCU AHB5FZ1 freeze register, Address offset: 0x28 */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x2C-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU authentication device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +#define DCMIPP_NUM_OF_PIPES 0x03U + +typedef struct +{ + uint32_t PxRIxCR1; /*! DCMIPP Pipex ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2) */ + uint32_t PxRIxCR2; /*! DCMIPP Pipex ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2) */ +} DCMIPP_Region_TypeDef; + +/* + * @brief Digital camera interface pixel pipeline DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< DCMIPP IPPLUG global register 1 Address offset: 0x000 */ + __IO uint32_t IPGR2; /*!< DCMIPP IPPLUG global register 2 Address offset: 0x004 */ + __IO uint32_t IPGR3; /*!< DCMIPP IPPLUG global register 3 Address offset: 0x008 */ + uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x00C-0x018 */ + __IO uint32_t IPGR8; /*!< DCMIPP IPPLUG identification register Address offset: 0x01C */ + __IO uint32_t IPC1R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */ + __IO uint32_t IPC1R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */ + __IO uint32_t IPC1R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x02C */ + __IO uint32_t IPC2R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x030 */ + __IO uint32_t IPC2R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x034 */ + __IO uint32_t IPC2R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x038 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t IPC3R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x040 */ + __IO uint32_t IPC3R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x044 */ + __IO uint32_t IPC3R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x04C */ + __IO uint32_t IPC4R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x050 */ + __IO uint32_t IPC4R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x054 */ + __IO uint32_t IPC4R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t IPC5R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x060 */ + __IO uint32_t IPC5R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x064 */ + __IO uint32_t IPC5R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x068 */ + uint32_t RESERVED5[38]; /*!< Reserved Address offset: 0x06C-0x100 */ + __IO uint32_t PRCR; /*!< DCMIPP parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< DCMIPP parallel interface embedded synchronization code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */ + uint32_t RESERVED6[57]; /*!< Reserved Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< DCMIPP parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< DCMIPP parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< DCMIPP parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< DCMIPP common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< DCMIPP common frame counter register Address offset: 0x208 */ + uint32_t RESERVED8[121]; /*!< Reserved Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< DCMIPP common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< DCMIPP common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< DCMIPP common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< DCMIPP common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< DCMIPP Pipe0 flow selection configuration register Address offset: 0x404 */ + uint32_t RESERVED10[62]; /*!< Reserved Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< DCMIPP Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< DCMIPP Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< DCMIPP Pipe0 stat/crop size register Address offset: 0x508 */ + uint32_t RESERVED11[41]; /*!< Reserved Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< DCMIPP Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< DCMIPP Pipe0 dump limit register Address offset: 0x5B4 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< DCMIPP Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2 Address offset: 0x5C8 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x5C8-0x5CC */ + __IO uint32_t P0STM0AR; /*!< DCMIPP Pipe0 status Memory0 address register Address offset: 0x5D0 */ + uint32_t RESERVED14[8]; /*!< Reserved Address offset: 0x5D4-0x5F0 */ + __IO uint32_t P0IER; /*!< DCMIPP Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< DCMIPP Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< DCMIPP Pipe0 interrupt clear register Address offset: 0x5FC */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x600 */ + __IO uint32_t P0CFSCR; /*!< DCMIPP Pipe0 current flow selection configuration register Address offset: 0x604 */ + uint32_t RESERVED17[62]; /*!< Reserved Address offset: 0x608-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< DCMIPP Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< DCMIPP Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< DCMIPP Pipe0 current stat/crop size register Address offset: 0x708 */ + uint32_t RESERVED18[45]; /*!< Reserved Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< DCMIPP Pipe0 current pixel packer configuration register Address offset: 0x7C0 */ + __IO uint32_t P0CPPM0AR1; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2 Address offset: */ + uint32_t RESERVED19[14]; /*!< Reserved Address offset: 0x7C8-0x7FC */ + __IO uint32_t P1FSCR; /*!< DCMIPP Pipe1 flow selection configuration register Address offset: 0x804 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0x808-0x81C */ + __IO uint32_t P1SRCR; /*!< DCMIPP Pipe1 stat removal configuration register Address offset: 0x820 */ + __IO uint32_t P1BPRCR; /*!< DCMIPP Pipe1 bad pixel removal control register Address offset: 0x824 */ + __IO uint32_t P1BPRSR; /*!< DCMIPP Pipe1 bad pixel removal status register Address offset: 0x828 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x82C */ + __IO uint32_t P1DECR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x830 */ + uint32_t RESERVED22[3]; /*!< Reserved Address offset: 0x834-0x83C */ + __IO uint32_t P1BLCCR; /*!< DCMIPP Pipe1 black level calibration control register Address offset: 0x840 */ + __IO uint32_t P1EXCR1; /*!< DCMIPP Pipe1 exposure control register 1 Address offset: 0x844 */ + __IO uint32_t P1EXCR2; /*!< DCMIPP Pipe1 exposure control register 2 Address offset: 0x848 */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x84C */ + __IO uint32_t P1ST1CR; /*!< DCMIPP Pipe1 statistics 1 control register Address offset: 0x850 */ + __IO uint32_t P1ST2CR; /*!< DCMIPP Pipe1 statistics 2 control register Address offset: 0x854 */ + __IO uint32_t P1ST3CR; /*!< DCMIPP Pipe1 statistics 3 control register Address offset: 0x858 */ + __IO uint32_t P1STSTR; /*!< DCMIPP Pipe1 statistics window start register Address offset: 0x85C */ + __IO uint32_t P1STSZR; /*!< DCMIPP Pipe1 statistics window size register Address offset: 0x860 */ + __IO uint32_t P1ST1SR; /*!< DCMIPP Pipe1 statistics 1 status register Address offset: 0x864 */ + __IO uint32_t P1ST2SR; /*!< DCMIPP Pipe1 statistics 2 status register Address offset: 0x868 */ + __IO uint32_t P1ST3SR; /*!< DCMIPP Pipe1 statistics 3 status register Address offset: 0x86C */ + __IO uint32_t P1DMCR; /*!< DCMIPP Pipe1 demosaicing configuration register Address offset: 0x870 */ + uint32_t RESERVED24[3]; /*!< Reserved Address offset: 0x874-0x87C */ + __IO uint32_t P1CCCR; /*!< DCMIPP Pipe1 ColorConv configuration register Address offset: 0x880 */ + __IO uint32_t P1CCRR1; /*!< DCMIPP Pipe1 ColorConv red coefficient register 1 Address offset: 0x884 */ + __IO uint32_t P1CCRR2; /*!< DCMIPP Pipe1 ColorConv red coefficient register 2 Address offset: 0x888 */ + __IO uint32_t P1CCGR1; /*!< DCMIPP Pipe1 ColorConv green coefficient register 1 Address offset: 0x88C */ + __IO uint32_t P1CCGR2; /*!< DCMIPP Pipe1 ColorConv green coefficient register 2 Address offset: 0x890 */ + __IO uint32_t P1CCBR1; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1 Address offset: 0x894 */ + __IO uint32_t P1CCBR2; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2 Address offset: 0x898 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x89C */ + __IO uint32_t P1CTCR1; /*!< DCMIPP Pipe1 contrast control register 1 Address offset: 0x8A0 */ + __IO uint32_t P1CTCR2; /*!< DCMIPP Pipe1 contrast control register 2 Address offset: 0x8A4 */ + __IO uint32_t P1CTCR3; /*!< DCMIPP Pipe1 contrast control register 3 Address offset: 0x8A8 */ + uint32_t RESERVED26[21]; /*!< Reserved Address offset: 0x8AC-0x8FC */ + __IO uint32_t P1FCTCR; /*!< DCMIPP Pipe1 flow control configuration register Address offset: 0x900 */ + __IO uint32_t P1CRSTR; /*!< DCMIPP Pipe1 crop window start register Address offset: 0x904 */ + __IO uint32_t P1CRSZR; /*!< DCMIPP Pipe1 crop window size register Address offset: 0x908 */ + __IO uint32_t P1DCCR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x90C */ + __IO uint32_t P1DSCR; /*!< DCMIPP Pipe1 downsize configuration register Address offset: 0x910 */ + __IO uint32_t P1DSRTIOR; /*!< DCMIPP Pipe1 downsize ratio register Address offset: 0x914 */ + __IO uint32_t P1DSSZR; /*!< DCMIPP Pipe1 downsize destination size register Address offset: 0x918 */ + uint32_t RESERVED28; /*!< Reserved Address offset: */ + __IO uint32_t P1CMRICR; /*!< DCMIPP Pipe1 common ROI configuration register Address offset: 0x920 */ + __IO uint32_t P1RIxCR1; /*!< DCMIPP Pipe1 ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */ + __IO uint32_t P1RIxCR2; /*!< DCMIPP Pipe1 ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */ + uint32_t RESERVED29[17]; /*!< Reserved Address offset: */ + __IO uint32_t P1GMCR; /*!< DCMIPP Pipe1 gamma configuration register Address offset: 0x970 */ + uint32_t RESERVED30[3]; /*!< Reserved Address offset: 0x974-0x97C */ + __IO uint32_t P1YUVCR; /*!< DCMIPP Pipe1 YUVConv configuration register Address offset: 0x980 */ + __IO uint32_t P1YUVRR1; /*!< DCMIPP Pipe1 YUVConv red coefficient register 1 Address offset: 0x984 */ + __IO uint32_t P1YUVRR2; /*!< DCMIPP Pipe1 YUVConv red coefficient register 2 Address offset: 0x988 */ + __IO uint32_t P1YUVGR1; /*!< DCMIPP Pipe1 YUVConv green coefficient register 1 Address offset: 0x98C */ + __IO uint32_t P1YUVGR2; /*!< DCMIPP Pipe1 YUVConv green coefficient register 2 Address offset: 0x990 */ + __IO uint32_t P1YUVBR1; /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1 Address offset: 0x994 */ + __IO uint32_t P1YUVBR2; /*!< DCMIPP Pipe1 YUV blue coefficient register 2 Address offset: 0x998 */ + uint32_t RESERVED31[9]; /*!< Reserved Address offset: 0x99C-0x9BC */ + __IO uint32_t P1PPCR; /*!< DCMIPP Pipe1 pixel packer configuration register Address offset: 0x9C0 */ + __IO uint32_t P1PPM0AR1; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1 Address offset: 0x9C4 */ + __IO uint32_t P1PPM0AR2; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2 Address offset: 0x9C8 */ + __IO uint32_t P1PPM0PR; /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register Address offset: 0x9CC */ + __IO uint32_t P1STM0AR; /*!< DCMIPP Pipe1 status Memory0 address register Address offset: 0x9D0 */ + __IO uint32_t P1PPM1AR1; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1 Address offset: 0x9D4 */ + __IO uint32_t P1PPM1AR2; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2 Address offset: 0x9D8 */ + __IO uint32_t P1PPM1PR; /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register Address offset: 0x9DC */ + __IO uint32_t P1STM1AR; /*!< DCMIPP Pipe1 status Memory1 address register Address offset: 0x9E0 */ + __IO uint32_t P1PPM2AR1; /*!< DCMIPP Pipe1 pixel packer memory2 address register 1 Address offset: 0x9E4 */ + __IO uint32_t P1PPM2AR2; /*!< DCMIPP Pipe1 pixel packer memory2 address register 2 Address offset: 0x9E8 */ + __IO uint32_t RESERVED34; /*!< Reserved Address offset: 0x9EC */ + __IO uint32_t P1STM2AR; /*!< DCMIPP Pipe1 status Memory2 address register Address offset: 0x9F0 */ + __IO uint32_t P1IER; /*!< DCMIPP Pipe1 interrupt enable register Address offset: 0x9F4 */ + __IO uint32_t P1SR; /*!< DCMIPP Pipe1 status register Address offset: 0x9F8 */ + __IO uint32_t P1FCR; /*!< DCMIPP Pipe1 interrupt clear register Address offset: 0x9FC */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0xA00 */ + __IO uint32_t P1CFSCR; /*!< DCMIPP Pipe1 current flow selection configuration register Address offset: 0xA04 */ + uint32_t RESERVED36[7]; /*!< Reserved Address offset: 0xA08-0xA20 */ + __IO uint32_t P1CBPRCR; /*!< DCMIPP Pipe1 current bad pixel removal register Address offset: 0xA24 */ + uint32_t RESERVED37[6]; /*!< Reserved Address offset: 0xA28-0xA3C */ + __IO uint32_t P1CBLCCR; /*!< DCMIPP Pipe1 current black level calibration control register Address offset: 0xA40 */ + __IO uint32_t P1CEXCR1; /*!< DCMIPP Pipe1 current exposure control register 1 Address offset: 0xA44 */ + __IO uint32_t P1CEXCR2; /*!< DCMIPP Pipe1 current exposure control register 2 Address offset: 0xA48 */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0xA4C */ + __IO uint32_t P1CST1CR; /*!< DCMIPP Pipe1 current statistics 1 control register Address offset: 0xA50 */ + __IO uint32_t P1CST2CR; /*!< DCMIPP Pipe1 current statistics 2 control register Address offset: 0xA54 */ + __IO uint32_t P1CST3CR; /*!< DCMIPP Pipe1 current statistics 3 control register Address offset: 0xA58 */ + __IO uint32_t P1CSTSTR; /*!< DCMIPP Pipe1 current statistics window start register Address offset: 0xA5C */ + __IO uint32_t P1CSTSZR; /*!< DCMIPP Pipe1 current statistics window size register Address offset: 0xA60 */ + uint32_t RESERVED39[7]; /*!< Reserved Address offset: 0xA64-0xA7C */ + __IO uint32_t P1CCCCR; /*!< DCMIPP Pipe1 current ColorConv configuration register Address offset: 0xA80 */ + __IO uint32_t P1CCCRR1; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1 Address offset: 0xA84 */ + __IO uint32_t P1CCCRR2; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2 Address offset: 0xA88 */ + __IO uint32_t P1CCCGR1; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1 Address offset: 0xA8C */ + __IO uint32_t P1CCCGR2; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2 Address offset: 0xA90 */ + __IO uint32_t P1CCCBR1; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1 Address offset: 0xA94 */ + __IO uint32_t P1CCCBR2; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2 Address offset: 0xA98 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0xA9C */ + __IO uint32_t P1CCTCR1; /*!< DCMIPP Pipe1 current contrast control register 1 Address offset: 0xAA0 */ + __IO uint32_t P1CCTCR2; /*!< DCMIPP Pipe1 current contrast control register 2 Address offset: 0xAA4 */ + __IO uint32_t P1CCTCR3; /*!< DCMIPP Pipe1 current contrast control register 3 Address offset: 0xAA8 */ + uint32_t RESERVED41[21]; /*!< Reserved Address offset: 0xAAC-0xAFC */ + __IO uint32_t P1CFCTCR; /*!< DCMIPP Pipe1 current flow control configuration register Address offset: 0xB00 */ + __IO uint32_t P1CCRSTR; /*!< DCMIPP Pipe1 current crop window start register Address offset: 0xB04 */ + __IO uint32_t P1CCRSZR; /*!< DCMIPP Pipe1 current crop window size register Address offset: 0xB08 */ + __IO uint32_t P1CDCCR; /*!< DCMIPP Pipe1 current decimation register Address offset: 0xB0C */ + __IO uint32_t P1CDSCR; /*!< DCMIPP Pipe1 current downsize configuration register Address offset: 0xB10 */ + __IO uint32_t P1CDSRTIOR; /*!< DCMIPP Pipe1 current downsize ratio register Address offset: 0xB14 */ + __IO uint32_t P1CDSSZR; /*!< DCMIPP Pipe1 current downsize destination size register Address offset: 0xB18 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0xB1C */ + uint32_t P1CCMRICR; /*!< DCMIPP Pipe1 current common ROI configuration register Address offset: 0xB20 */ + __IO uint32_t P1CRIxCR1; /*!< DCMIPP Pipe1 current ROIx configuration register 1 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */ + __IO uint32_t P1CRIxCR2; /*!< DCMIPP Pipe1 current ROIx configuration register 2 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */ + uint32_t RESERVED44[37]; /*!< Reserved Address offset: 0xB64-0xBBC */ + __IO uint32_t P1CPPCR; /*!< DCMIPP Pipe1 current pixel packer configuration register Address offset: 0xBC0 */ + __IO uint32_t P1CPPM0AR1; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC4 */ + __IO uint32_t P1CPPM0AR2; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC8 */ + __IO uint32_t P1CPPM0PR; /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register Address offset: 0xBCC */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0xBD0 */ + __IO uint32_t P1CPPM1AR1; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1 Address offset: 0xBD4 */ + __IO uint32_t P1CPPM1AR2; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2 Address offset: 0xBD8 */ + __IO uint32_t P1CPPM1PR; /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register Address offset: 0xBDC */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0xBE0 */ + __IO uint32_t P1CPPM2AR1; /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1 Address offset: 0xBE4 */ + __IO uint32_t P1CPPM2AR2; /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2 Address offset: 0xBE8 */ + uint32_t RESERVED48[6]; /*!< Reserved Address offset: 0xBE8-0xBFC */ + __IO uint32_t P2FSCR; /*!< DCMIPP Pipe2 flow selection configuration register Address offset: 0xC04 */ + uint32_t RESERVED49[62]; /*!< Reserved Address offset: 0xC08-0xCFC */ + __IO uint32_t P2FCTCR; /*!< DCMIPP Pipe2 flow control configuration register Address offset: 0xD00 */ + __IO uint32_t P2CRSTR; /*!< DCMIPP Pipe2 crop window start register Address offset: 0xD04 */ + __IO uint32_t P2CRSZR; /*!< DCMIPP Pipe2 crop window size register Address offset: 0xD08 */ + __IO uint32_t P2DCCR; /*!< DCMIPP Pipe2 decimation register Address offset: 0xD0C */ + __IO uint32_t P2DSCR; /*!< DCMIPP Pipe2 downsize configuration register Address offset: 0xD10 */ + __IO uint32_t P2DSRTIOR; /*!< DCMIPP Pipe2 downsize ratio register Address offset: 0xD14 */ + __IO uint32_t P2DSSZR; /*!< DCMIPP Pipe2 downsize destination size register Address offset: 0xD18 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0xD1C */ + __IO uint32_t P2CMRICR; /*!< DCMIPP Pipe2 common ROI configuration register Address offset: 0xD20 */ + __IO uint32_t P2RIxCR1; /*!< DCMIPP Pipe2 ROIx configuration register 1 Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */ + __IO uint32_t P2RIxCR2; /*!< DCMIPP Pipe2 ROIx configuration register 2 Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */ + uint32_t RESERVED53[17]; /*!< Reserved Address offset: */ + __IO uint32_t P2GMCR; /*!< DCMIPP Pipe2 gamma configuration register Address offset: 0xD70 */ + uint32_t RESERVED54[19]; /*!< Reserved Address offset: 0xD74-0xDBC */ + __IO uint32_t P2PPCR; /*!< DCMIPP Pipe2 pixel packer configuration register Address offset: 0xDC0 */ + __IO uint32_t P2PPM0AR1; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1 Address offset: 0xDC4 */ + __IO uint32_t P2PPM0AR2; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2 Address offset: 0xDC8 */ + __IO uint32_t P2PPM0PR; /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register Address offset: 0xDCC */ + __IO uint32_t P2STM0AR; /*!< DCMIPP Pipe2 status Memory0 address register Address offset: 0xDD0 */ + uint32_t RESERVED55[8]; /*!< Reserved Address offset: 0xDD4-0xDF0 */ + __IO uint32_t P2IER; /*!< DCMIPP Pipe2 interrupt enable register Address offset: 0xDF4 */ + __IO uint32_t P2SR; /*!< DCMIPP Pipe2 status register Address offset: 0xDF8 */ + __IO uint32_t P2FCR; /*!< DCMIPP Pipe2 interrupt clear register Address offset: 0xDFC */ + uint32_t RESERVED56; /*!< Reserved Address offset: 0xE00 */ + __IO uint32_t P2CFSCR; /*!< DCMIPP Pipe2 current flow selection configuration register Address offset: 0xE04 */ + uint32_t RESERVED57[62]; /*!< Reserved Address offset: 0xE08-0xEFC */ + __IO uint32_t P2CFCTCR; /*!< DCMIPP Pipe2 current flow control configuration register Address offset: 0xF00 */ + __IO uint32_t P2CCRSTR; /*!< DCMIPP Pipe2 current crop window start register Address offset: 0xF04 */ + __IO uint32_t P2CCRSZR; /*!< DCMIPP Pipe2 current crop window size register Address offset: 0xF08 */ + __IO uint32_t P2CDCCR; /*!< DCMIPP Pipe2 current decimation register Address offset: 0xF0C */ + __IO uint32_t P2CDSCR; /*!< DCMIPP Pipe2 current downsize configuration register Address offset: 0xF10 */ + __IO uint32_t P2CDSRTIOR; /*!< DCMIPP Pipe2 current downsize ratio register Address offset: 0xF14 */ + __IO uint32_t P2CDSSZR; /*!< DCMIPP Pipe2 current downsize destination size register Address offset: 0xF18 */ + __IO uint32_t RESERVED59[2]; /*!< Reserved Address offset: 0xF1C-0xF20 */ + __IO uint32_t P2CRIxCR1; /*!< Pipe2 current ROIx configuration register 1 Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/ + __IO uint32_t P2CRIxCR2; /*!< Pipe2 current ROIx configuration register 2 Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/ + uint32_t RESERVED60[37]; /*!< Reserved Address offset: 0xF64-0xFBC */ + __IO uint32_t P2CPPCR; /*!< DCMIPP Pipe2 current pixel packer configuration register Address offset: 0xFC0 */ + __IO uint32_t P2CPPM0AR1; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1 Address offset: 0xFC4 */ + __IO uint32_t P2CPPM0AR2; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2 Address offset: 0xFC8 */ + __IO uint32_t P2CPPM0PR; /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register Address offset: 0xFCC */ + uint32_t RESERVED61[7]; /*!< Reserved Address offset: 0xFD0-0xFE8 */ + __IO uint32_t HWCFGR2; /*!< DCMIPP hardware configuration register 2 Address offset: 0xFEC */ + __IO uint32_t HWCFGR1; /*!< DCMIPP hardware configuration register 1 Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< DCMIPP version register Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< DCMIPP identification register Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< DCMIPP size identification register Address offset: 0xFFC */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CFG; /*!< Delay Block Configuration Register, Address offset: 0x00 */ + __IO uint32_t STATUS; /*!< Delay Block Status Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + __IO uint32_t CCIDCFGR; /*!< DMA channel x CID register, Address offset: 0x54 + (x * 0x80) */ + uint32_t RESERVED1[1]; /*!< Reserved 1, Address offset: 0x58 + (x * 0x80) */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C + (x * 0x80) */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 + (x * 0x80) */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS Controller + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x00-0x0F */ + __IO uint32_t PVTREG_LOCKR; /*!< DTS PVT Register Lock Register, Address offset: 0x10 */ + __IO uint32_t PVTLOCK_SR; /*!< DTS PVT Lock Status Register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1F */ + __IO uint32_t PVTTMR_CR; /*!< DTS PVT Timer Control Register, Address offset: 0x20 */ + __IO uint32_t PVTTMR_SR; /*!< DTS PVT Timer Status Register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x28-0x3F */ + __IO uint32_t PVT_IER; /*!< DTS PVT IRQ Enable Register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4F */ + __IO uint32_t PVTIRQTRMASKR; /*!< DTS PVT IRQ Timer Mask Register, Address offset: 0x50 */ + __IO uint32_t TS_MR; /*!< DTS PVT IRQ TS Mask Register, Address offset: 0x54 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x58-0x5F */ + __IO uint32_t PVTTR_SR; /*!< DTS PVT IRQ Timer Status Register, Address offset: 0x60 */ + __IO uint32_t TS_ISR; /*!< DTS PVT IRQ TS Status Register, Address offset: 0x64 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x68-0x6F */ + __IO uint32_t PVTTMRRAW_ISR; /*!< DTS PVT IRQ Timer Raw Status Register, Address offset: 0x70 */ + __IO uint32_t TSRAW_ISR; /*!< DTS PVT IRQ TS Raw Status Register, Address offset: 0x74 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x78-0x7F */ + __IO uint32_t TSCCLKSYNTHR; /*!< DTS TSC Clock Synthesizer Register, Address offset: 0x80 */ + __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register, Address offset: 0x84 */ + __IO uint32_t TSCSDIF_SR; /*!< DTS TSC SDIF Status Register, Address offset: 0x88 */ + __IO uint32_t TSCSDIF_CR; /*!< DTS TSC SDIF Register, Address offset: 0x8C */ + __IO uint32_t TSCSDIFHALTR; /*!< DTS TSC SDIF Halt Register, Address offset: 0x90 */ + __IO uint32_t TSCSDIF_CFGR; /*!< DTS TSC SDIF Control Register, Address offset: 0x94 */ + uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x98-0x9F */ + __IO uint32_t TSCSMPL_CR; /*!< DTS TSC Sample Control Register, Address offset: 0xA0 */ + __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register, Address offset: 0xA4 */ + __IO uint32_t TSCSMPLCNTR; /*!< DTS TSC Sample Count Register, Address offset: 0xA8 */ +} DTS_TypeDef; + +/** + * @brief DTS Sensor Controller + */ +typedef struct +{ + __IO uint32_t TS_IER; /*!< DTS TSx IRQ Enable Register, Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TS_ISR; /*!< DTS TSx IRQ Status Register, Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TS_ICR; /*!< DTS TSx IRQ Clear Register, Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSIRQTESTR; /*!< DTS TSx IRQ Test Register, Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSSDIFRDATAR; /*!< DTS TSx SDIF RDATA Register, Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSSDIFDONER; /*!< DTS TSx SDIF Done Register, Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSSDIFDATAR; /*!< DTS TSx SDIF Data Register, Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */ + uint32_t RESERVED1[1]; /*!< Reserved, Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSALARMA_CFGR; /*!< DTS TSx Alarm A Configuration Register, Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSALARMB_CFGR; /*!< DTS TSx Alarm B Configuration Register, Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSHLSAMPLER; /*!< DTS TSx High/Low Sample Register, Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSHILORESETR; /*!< DTS TSx High/Low Reset Register, Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */ +} DTS_SensorTypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x00 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x04 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register , Address offset: 0x08 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register, Address offset: 0x0C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x10 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x14 */ + uint32_t RESERVED1[14]; + __IO uint32_t MACVTCR; /*!< VLAN tag Control register, Address offset: 0x50 */ + __IO uint32_t MACVTDR; /*!< VLAN tag data register, Address offset: 0x54 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x58 */ + uint32_t RESERVED2; + __IO uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x60 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x64 */ + uint32_t RESERVED3[2]; + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register, Address offset: 0x70 */ + uint32_t RESERVED4[7]; + __IO uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x90 */ + __IO uint32_t MACRXQCR; /*!< Rx Queue control register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register, Address offset: 0xA0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register, Address offset: 0xA4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register, Address offset: 0xA8 */ + uint32_t RESERVED6; + __IO uint32_t MACISR; /*!< Interrupt status register, Address offset: 0xB0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0xB4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0xB8 */ + uint32_t RESERVED7; + __IO uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0xC0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register, Address offset: 0xC4 */ + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0xD0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0xD4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0xD8 */ + __IO uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0xDC */ + uint32_t RESERVED9[6]; + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register, Address offset: 0xF8 */ + uint32_t RESERVED10[5]; + __IO uint32_t MACVR; /*!< Version register, Address offset: 0x110 */ + __IO uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */ + uint32_t RESERVED11; + __IO uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */ + uint32_t RESERVED12[53]; + __IO uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */ + uint32_t RESERVED13[2]; + __IO uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */ + uint32_t RESERVED14[7]; + __IO uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */ + __IO uint32_t MACFPECSR; /*!< FPE control and status register, Address offset: 0x234 */ + uint32_t RESERVED15[2]; + __IO uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x0240 */ + __IO uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x0244 */ + uint32_t RESERVED16[46]; + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x031C */ + uint32_t RESERVED17[248]; + __IO uint32_t MMCCR; /*!< MMC control register, Address offset: 0x0700 */ + __IO uint32_t MMCRIR; /*!< MMC Rx interrupt register, Address offset: 0x0704 */ + __IO uint32_t MMCTIR; /*!< MMC Tx interrupt register, Address offset: 0x0708 */ + __IO uint32_t MMCRIMR; /*!< MMC Rx interrupt mask register, Address offset: 0x070C */ + __IO uint32_t MMCTIMR; /*!< MMC Tx interrupt mask register, Address offset: 0x0710 */ + uint32_t RESERVED18[14]; + __IO uint32_t MMCTSCGPR; /*!< Tx single collision good packets register, Address offset: 0x074C */ + __IO uint32_t MMCTMCGPR; /*!< Tx multiple collision good packets register, Address offset: 0x0750 */ + uint32_t RESERVED19[5]; + __IO uint32_t MMCTPCGR; /*!< Tx packet count good register, Address offset: 0x0768 */ + uint32_t RESERVED20[10]; + __IO uint32_t MMCRCRCEPR; /*!< Rx CRC error packets register, Address offset: 0x0794 */ + __IO uint32_t MMCRAEPR; /*!< Rx alignment error packets register, Address offset: 0x0798 */ + uint32_t RESERVED21[10]; + __IO uint32_t MMCRUPGR; /*!< Rx unicast packets good register, Address offset: 0x07C4 */ + uint32_t RESERVED22[9]; + __IO uint32_t MMCTLPIMSTR; /*!< Tx LPI microsecond timer register, Address offset: 0x07EC */ + __IO uint32_t MMCTLPITCR; /*!< Tx LPI transition counter register, Address offset: 0x07F0 */ + __IO uint32_t MMCRLPIMSTR; /*!< Rx LPI microsecond counter register, Address offset: 0x07F4 */ + __IO uint32_t MMCRLPITCR; /*!< Rx LPI transition counter register, Address offset: 0x07F8 */ + uint32_t RESERVED23[41]; + __IO uint32_t MMCFPETISR; /*!< MMC FPE Tx interrupt status register, Address offset: 0x08A0 */ + __IO uint32_t MMCFPETIMR; /*!< MMC FPE Tx interrupt mask register, Address offset: 0x08A4 */ + __IO uint32_t MMCFPETFCR; /*!< MMC FPE Tx fragment counter register, - Address offset: 0x08A8 */ + __IO uint32_t MMCTHRCR; /*!< MMC Tx hold request counter register, Address offset: 0x08AC */ + uint32_t RESERVED24[4]; + __IO uint32_t MMCFPERISR; /*!< MMC FPE Rx interrupt status register, Address offset: 0x08C0 */ + __IO uint32_t MMCFPERIMR; /*!< MMC FPE Rx interrupt mask register, Address offset: 0x08C4 */ + __IO uint32_t MMCRPAER; /*!< MMC Rx packet assembly error register, Address offset: 0x08C8 */ + __IO uint32_t MMCRPSMDER; /*!< MMC Rx packet SMD error register, Address offset: 0x08CC */ + __IO uint32_t MMCRPAOKR; /*!< MMC Rx packet assembly OK register, Address offset: 0x08D0 */ + __IO uint32_t MMCFPERFCR; /*!< MMC Rx FPE fragments counter register, Address offset: 0x08D4 */ + uint32_t RESERVED25[10]; + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x0904 */ + uint32_t RESERVED26[2]; + __IO uint32_t MACL3A0R0R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x0910 */ + __IO uint32_t MACL3A1R0R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x0914 */ + __IO uint32_t MACL3A2R0R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x0918 */ + __IO uint32_t MACL3A3R0R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x091C */ + uint32_t RESERVED27[4]; + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x0934 */ + uint32_t RESERVED28[2]; + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x094C */ + uint32_t RESERVED29[72]; + __IO uint32_t MACIACR; /*!< MAC Indirect Access Control register, Address offset: 0x0A70 */ + __IO uint32_t MACTMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0x0A74 */ + uint32_t RESERVED30[34]; + __IO uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0x0B18 */ + uint32_t RESERVED31; + __IO uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0x0B20 */ + uint32_t RESERVED32[3]; + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0x0B34 */ + uint32_t RESERVED33[2]; + __IO uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0x0B40 */ + uint32_t RESERVED34; + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register, Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register, Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register, Address offset: 0x0B5C */ + uint32_t RESERVED35[2]; + __IO uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0x0B68 */ + __IO uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0x0B70 */ + uint32_t RESERVED36[3]; + __IO uint32_t MACPPSTTS0R; /*!< PPS 0 target time seconds register, Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTN0R; /*!< PPS 0 target time nanoseconds register, Address offset: 0x0B84 */ + __IO uint32_t MACPPSI0R; /*!< PPS 0 interval register, Address offset: 0x0B88 */ + __IO uint32_t MACPPSW0R; /*!< PPS 0 width register, Address offset: 0x0B8C */ + __IO uint32_t MACPPSTTS1R; /*!< PPS 1 target time seconds register, Address offset: 0x0B90 */ + __IO uint32_t MACPPSTTN1R; /*!< PPS 1 target time nanoseconds register, Address offset: 0x0B94 */ + __IO uint32_t MACPPSI1R; /*!< PPS 1 interval register, Address offset: 0x0B98 */ + __IO uint32_t MACPPSW1R; /*!< PPS 1 width register, Address offset: 0x0B9C */ + uint32_t RESERVED37[8]; + __IO uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0x0BD0 */ + uint32_t RESERVED38[11]; + __IO uint32_t MTLOMR; /*!< Operating mode Register, Address offset: 0x0C00 */ + uint32_t RESERVED39[7]; + __IO uint32_t MTLISR; /*!< Interrupt status Register, Address offset: 0x0C20 */ + uint32_t RESERVED40[3]; + __IO uint32_t MTLRXQDMAMR; /*!< Rx Queue and DMA Channel Mapping Register, Address offset: 0x0C30 */ + uint32_t RESERVED41[3]; + __IO uint32_t MTLTBSCR; /*!< TBS control register, Address offset: 0x0C40 */ + uint32_t RESERVED42[3]; + __IO uint32_t MTLESTCR; /*!< EST Control Register, Address offset: 0x0C50 */ + __IO uint32_t MTLESTECR; /*!< EST Extended Control Register, Address offset: 0x0C54 */ + __IO uint32_t MTLESTSR; /*!< EST Status Register, Address offset: 0x0C58 */ + uint32_t RESERVED43; + __IO uint32_t MTLESTSCHER; /*!< EST Schedule Error Register, Address offset: 0x0C60 */ + __IO uint32_t MTLESTFSER; /*!< EST Frame size Error Register, Address offset: 0x0C64 */ + __IO uint32_t MTLESTFSCR; /*!< EST Frame size Capture Register, Address offset: 0x0C68 */ + uint32_t RESERVED44; + __IO uint32_t MTLESTIER; /*!< EST Interrupt Enable Register, Address offset: 0x0C70 */ + uint32_t RESERVED45[3]; + __IO uint32_t MTLESTGCLCR; /*!< EST Gate Control List Register, Address offset: 0x0C80 */ + __IO uint32_t MTLESTGCLDR; /*!< EST Gate Control List Data Register, Address offset: 0x0C84 */ + uint32_t RESERVED46[2]; + __IO uint32_t MTLFPECSR; /*!< FPE Frame Preemption Control Status Register, Address offset: 0x0C90 */ + __IO uint32_t MTLFPEAR; /*!< FPE Frame Preemption Advance Register, Address offset: 0x0C94 */ + uint32_t RESERVED47[26]; + struct { + __IO uint32_t MTLTXQOMR; /*!< Tx queue x operating mode Register, Address offset: 0x0D00 */ + __IO uint32_t MTLTXQUR; /*!< Tx queue x underflow register, Address offset: 0x0D04 */ + __IO uint32_t MTLTXQDR; /*!< Tx queue x debug register, Address offset: 0x0D08 */ + uint32_t RESERVED48[1]; + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register, Address offset: 0x0D50 */ + __IO uint32_t MTLTXQESR; /*!< Tx queue x ETS status Register, Address offset: 0x0D14 */ + __IO uint32_t MTLTXQQWR; /*!< Tx queue x quantum weight register, Address offset: 0x0D18 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register, Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register, Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register, Address offset: 0x0D64 */ + uint32_t RESERVED49[1]; + __IO uint32_t MTLQICSR; /*!< Queue 0 interrupt control status Register, Address offset: 0x0D2C */ + __IO uint32_t MTLRXQOMR; /*!< Rx queue x operating mode register, Address offset: 0x0D30 */ + __IO uint32_t MTLRXQMPOCR; /*!< Rx queue x missed packet and overflow counter register, Address offset: 0x0D34 */ + __IO uint32_t MTLRXQDR; /*!< Rx queue x debug register, Address offset: 0x0D38 */ + __IO uint32_t MTLRXQCR; /*!< Rx queue x control register, Address offset: 0x0D3C */ + } MTL_QUEUE[2]; + uint32_t RESERVED52[160]; + __IO uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */ + uint32_t RESERVED53[4]; + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register, Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register, Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register, Address offset: 0x1028 */ + uint32_t RESERVED54[5]; + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register, Address offset: 0x1040 */ + uint32_t RESERVED55[3]; + __IO uint32_t DMATBSCTRL0R; /*!< DMA TBS control register 0, Address offset: 0x1050 */ + uint32_t RESERVED56[37]; + struct { + uint32_t RESERVED57[6]; + __IO uint32_t DMACCR; /*!< Channel x control register, Address offset: 0x1100 */ + __IO uint32_t DMACTXCR; /*!< Channel x transmit control register, Address offset: 0x1104 */ + __IO uint32_t DMACRXCR; /*!< Channel x receive control register, Address offset: 0x1108 */ + uint32_t RESERVED58[2]; + __IO uint32_t DMACTXDLAR; /*!< Channel x Tx descriptor list address register, Address offset: 0x1114 */ + uint32_t RESERVED59; + __IO uint32_t DMACRXDLAR; /*!< Channel x Rx descriptor list address register, Address offset: 0x111C */ + __IO uint32_t DMACTXDTPR; /*!< Channel x Tx descriptor tail pointer register, Address offset: 0x1120 */ + uint32_t RESERVED60; + __IO uint32_t DMACRXDTPR; /*!< Channel x Rx descriptor tail pointer register, Address offset: 0x1128 */ + __IO uint32_t DMACTXRLR; /*!< Channel x Tx descriptor ring length register, Address offset: 0x112C */ + __IO uint32_t DMACRXRLR; /*!< Channel x Rx descriptor ring length register, Address offset: 0x1130 */ + __IO uint32_t DMACIER; /*!< Channel x interrupt enable register, Address offset: 0x1134 */ + __IO uint32_t DMACRXIWTR; /*!< Channel x Rx interrupt watchdog timer register, Address offset: 0x1138 */ + __IO uint32_t DMACSFCSR; /*!< Channel x slot function control status register, Address offset: 0x113C */ + uint32_t RESERVED61; + __IO uint32_t DMACCATXDR; /*!< Channel x current application transmit descriptor register, Address offset: 0x1144 */ + uint32_t RESERVED62; + __IO uint32_t DMACCARXDR; /*!< Channel x current application receive descriptor register, Address offset: 0x114C */ + uint32_t RESERVED63; + __IO uint32_t DMACCATXBR; /*!< Channel x current application transmit buffer register, Address offset: 0x1154 */ + uint32_t RESERVED64; + __IO uint32_t DMACCARXBR; /*!< Channel x current application receive buffer register, Address offset: 0x115C */ + __IO uint32_t DMACSR; /*!< Channel x status register, Address offset: 0x1160 */ + __IO uint32_t DMACMFCR; /*!< Channel x missed frame count register, Address offset: 0x1164 */ + } DMA_CH[2]; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x3C */ + __IO uint32_t RTSR3; /*!< EXTI Rising Trigger Selection Register 3, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling Trigger Selection Register 3, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software Interrupt event Register 3, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Pending Register 3, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Pending Register 3, Address offset: 0x50 */ + __IO uint32_t SECCFGR3; /*!< EXTI Security Configuration Register 3, Address offset: 0x54 */ + __IO uint32_t PRIVCFGR3; /*!< EXTI Privilege Configuration Register 3, Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED4[3]; /*!< Reserved 4, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved 6, 0x98 -- 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt Mask Register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event Mask Register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111];/*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM device 1/2 control register Address offset: 0x140-0x144 */ + __IO uint32_t SDTR; /*!< SDRAM timing register Address offset: 0x148 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM command mode register Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM refresh timer register Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM status register Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash Programmable control register Address offset: 0x080 */ + __IO uint32_t SR; /*!< FMC status register Address offset: 0x084 */ + __IO uint32_t PMEM; /*!< Common memory space timing register Address offset: 0x088 */ + __IO uint32_t PATT; /*!< Attribute memory space timing registers Address offset: 0x08C */ + __IO uint32_t HPR; /*!< FMC Hamming parity result registers Address offset: 0x090 */ + __IO uint32_t HECCR; /*!< FMC Hamming code ECC result register Address offset: 0x094 */ + uint32_t RESERVED0[58]; /*!< Reserved Address offset: 0x098-0x17C */ + __IO uint32_t IER; /*!< FMC NAND Interrupt Enable Register Address offset: 0x180 */ + __IO uint32_t ISR; /*!< FMC Controller Interrupt Status Register Address offset: 0x184 */ + __IO uint32_t ICR; /*!< FMC NAND Controller Interrupt Clear Register Address offset: 0x188 */ + uint32_t RESERVED1[29]; /*!< Reserved Address offset: 0x18C-0x1FC */ + __IO uint32_t CSQCR; /*!< FMC NAND Command Sequencer Control Register Address offset: 0x200 */ + __IO uint32_t CSQCFGR1; /*!< FMC NAND Command Sequencer Configuration Register 1 Address offset: 0x204 */ + __IO uint32_t CSQCFGR2; /*!< FMC NAND Command Sequencer Configuration Register 2 Address offset: 0x208 */ + __IO uint32_t CSQCFGR3; /*!< FMC NAND sequencer configuration register 3 Address offset: 0x20C */ + __IO uint32_t CSQAR1; /*!< FMC NAND Command Sequencer Address Register 1 Address offset: 0x210 */ + __IO uint32_t CSQAR2; /*!< FMC NAND Command Sequencer Address Register 2 Address offset: 0x214 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x218-0x21C */ + __IO uint32_t CSQIER; /*!< FMC NAND Command Sequencer Interrupt Enable Register Address offset: 0x220 */ + __IO uint32_t CSQISR; /*!< FMC NAND Command Sequencer Interrupt Status Register Address offset: 0x224 */ + __IO uint32_t CSQICR; /*!< FMC NAND Command Sequencer Interrupt Clear Register Address offset: 0x228 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x22C */ + __IO uint32_t CSQEMSR; /*!< FMC Command Sequencer Error Mapping Status register Address offset: 0x230 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x234-0x24C */ + __IO uint32_t BCHIER; /*!< FMC BCH Interrupt enable register Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< FMC BCH Interrupt and Status Register Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< FMC BCH Interrupt Clear Register Address offset: 0x258 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x25C */ + __IO uint32_t BCHPBR1; /*!< FMC BCH Parity Bits Register 1 Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< FMC BCH Parity Bits Register 2 Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< FMC BCH Parity Bits Register 3 Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< FMC BCH Parity Bits Register 4 Address offset: 0x26C */ + uint32_t RESERVED6[3]; /*!< Reserved Address offset: 0x270-0x278 */ + __IO uint32_t BCHDSR0; /*!< FMC BCH Decoder Status register 0 Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< FMC BCH Decoder Status register for bank 1 Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< FMC BCH Decoder Status register for bank 2 Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< FMC BCH Decoder Status register for bank 3 Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< FMC BCH Decoder Status register for bank 4 Address offset: 0x28C */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Common + */ +typedef struct{ + __IO uint32_t CFGR; /*!< FMC common configuration register Address offset: 0x020 */ +} FMC_Common_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO port secure configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< GPIO port privileged configuration register, Address offset: 0x34 */ + __IO uint32_t RCFGLOCKR; /*!< GPIO port resource configuration register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t DELAYR[2]; /*!< GPIO port delay register, Address offset: 0x40-0x44 */ + __IO uint32_t ADVCFGR[2]; /*!< GPIO port advanced configuration register, Address offset: 0x48-0x4C */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Illegal Access Controller + */ +typedef struct +{ + __IO uint32_t IER[5]; /*!< Interrupt Enable register, Address offset: 0x000 */ + uint32_t RESERVED1[27]; /*!< Reserved, Address offset: 0x014-0x07C */ + __IO uint32_t ISR[5]; /*!< Interrupt Status register, Address offset: 0x080 */ + uint32_t RESERVED2[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t ICR[5]; /*!< Interrupt Clear register, Address offset: 0x100 */ +} IAC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ +} ICACHE_TypeDef; + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG key register Address offset: 0x000 */ + __IO uint32_t PR; /*!< IWDG prescaler register Address offset: 0x004 */ + __IO uint32_t RLR; /*!< IWDG reload register Address offset: 0x008 */ + __IO uint32_t SR; /*!< IWDG status register Address offset: 0x00C */ + __IO uint32_t WINR; /*!< IWDG window register Address offset: 0x010 */ + __IO uint32_t EWCR; /*!< IWDG early wakeup interrupt register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< IWDG interrupt clear register Address offset: 0x018 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller (LTDC) + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC synchronization size configuration register Address offset: 0x8 */ + __IO uint32_t BPCR; /*!< LTDC back porch configuration register Address offset: 0xc */ + __IO uint32_t AWCR; /*!< LTDC active width configuration register Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC total width configuration register Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC global control register Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: */ + __IO uint32_t SRCR; /*!< LTDC shadow reload configuration register Address offset: 0x24 */ + __IO uint32_t GCCR; /*!< LTDC gamma correction configuration register Address offset: 0x28 */ + __IO uint32_t BCCR; /*!< LTDC background color configuration register Address offset: 0x2c */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x30 */ + __IO uint32_t IER; /*!< LTDC interrupt enable register Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC interrupt status register Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register Address offset: 0x3c */ + __IO uint32_t LIPCR; /*!< LTDC line interrupt position configuration register Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC current position status register Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC current display status register Address offset: 0x48 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x4c */ + __IO uint32_t EDCR; /*!< LTDC external display control register Address offset: 0x60 */ + __IO uint32_t IER2; /*!< LTDC interrupt enable register 2 Address offset: 0x64 */ + __IO uint32_t ISR2; /*!< LTDC interrupt status register 2 Address offset: 0x68 */ + __IO uint32_t ICR2; /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */ + __IO uint32_t LIPCR2; /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x74 */ + __IO uint32_t ECRCR; /*!< LTDC expected CRC register Address offset: 0x78 */ + __IO uint32_t CCRCR; /*!< LTDC computed CRC register Address offset: 0x7c */ + __IO uint32_t RB0AR; /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */ + __IO uint32_t RB1AR; /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */ + __IO uint32_t RBPR; /*!< LTDC rotation buffer pitch register Address offset: 0x88 */ + __IO uint32_t RIFCR; /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */ + __IO uint32_t FUTR; /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller (LTDC) + */ +typedef struct +{ + __IO uint32_t C0R; /*!< LTDC layer x configuration 0 register Address offset: 0x100 */ + __IO uint32_t C1R; /*!< LTDC layer x configuration 1 register Address offset: 0x104 */ + __IO uint32_t RCR; /*!< LTDC layer x reload control register Address offset: 0x108 */ + __IO uint32_t CR; /*!< LTDC layer x control register Address offset: 0x10c */ + __IO uint32_t WHPCR; /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */ + __IO uint32_t WVPCR; /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */ + __IO uint32_t CKCR; /*!< LTDC layer x color keying configuration register Address offset: 0x118 */ + __IO uint32_t PFCR; /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */ + __IO uint32_t CACR; /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */ + __IO uint32_t DCCR; /*!< LTDC layer x default color configuration register Address offset: 0x124 */ + __IO uint32_t BFCR; /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */ + __IO uint32_t BLCR; /*!< LTDC layer x burst length configuration register Address offset: 0x12c */ + __IO uint32_t PCR; /*!< LTDC layer x planar configuration register Address offset: 0x130 */ + __IO uint32_t CFBAR; /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */ + __IO uint32_t CFBLR; /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */ + __IO uint32_t CFBLNR; /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */ + __IO uint32_t AFBA0R; /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */ + __IO uint32_t AFBA1R; /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */ + __IO uint32_t AFBLR; /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */ + __IO uint32_t AFBLNR; /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */ + __IO uint32_t CLUTWR; /*!< LTDC layer x CLUT write register Address offset: 0x150 */ + __IO uint32_t SISR; /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */ + __IO uint32_t SOSR; /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */ + __IO uint32_t SVSFR; /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */ + __IO uint32_t SVSPR; /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */ + __IO uint32_t SHSFR; /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */ + __IO uint32_t SHSPR; /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */ + __IO uint32_t CYR0R; /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */ + __IO uint32_t CYR1R; /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */ + __IO uint32_t FPF0R; /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */ + __IO uint32_t FPF1R; /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */ +} LTDC_Layer_TypeDef; + + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Control register 1 Address offset: 0x000 */ + __IO uint32_t CR2; /*!< PWR Control Register 2 Address offset: 0x004 */ + __IO uint32_t CR3; /*!< PWR Control Register 3 Address offset: 0x008 */ + __IO uint32_t CR4; /*!< PWR Control Register 4 Address offset: 0x00C */ + uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x010-0x01C */ + __IO uint32_t VOSCR; /*!< PWR Voltage scaling control register Address offset: 0x020 */ + __IO uint32_t BDCR1; /*!< PWR Backup domain control register 1 Address offset: 0x024 */ + __IO uint32_t BDCR2; /*!< PWR Backup domain control register 2 Address offset: 0x028 */ + __IO uint32_t DBPCR; /*!< PWR Disable backup protection control register Address offset: 0x02C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register Address offset: 0x030 */ + __IO uint32_t SVMCR1; /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */ + __IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */ + __IO uint32_t SVMCR3; /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */ + uint32_t RESERVED1[4]; /*!< Reserved Address offset: 0x040-0x04C */ + __IO uint32_t WKUPCR; /*!< PWR Wakeup control register 1 Address offset: 0x050 */ + __IO uint32_t WKUPSR; /*!< PWR Wakeup control register 2 Address offset: 0x054 */ + __IO uint32_t WKUPEPR; /*!< PWR Wakeup control register 3 Address offset: 0x058 */ + uint32_t RESERVED2[5]; /*!< Reserved Address offset: 0x05C-0x06C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register Address offset: 0x070 */ + __IO uint32_t PRIVCFGR; /*!< PWR Privilege configuration register Address offset: 0x074 */ +} PWR_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief RAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */ + __IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */ + __IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */ + __IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */ + uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */ + __IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */ + __IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */ + __IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */ + __IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */ + __IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */ + __IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */ + __IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */ + __IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */ + __IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */ + __IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */ + __IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */ + __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */ + __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */ + __IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */ + __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */ + __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */ + __IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */ + __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */ + __IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */ + __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */ + __IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */ + __IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */ + __IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */ + __IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */ + __IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */ + __IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */ + __IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */ + __IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */ + __IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */ + __IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */ + __IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */ + __IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */ + __IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */ + __IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */ + __IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */ + __IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */ + __IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */ + __IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */ + __IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */ + __IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */ + __IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */ + uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */ + __IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */ + __IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */ + __IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */ + __IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */ + __IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */ + __IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */ + __IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */ + __IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */ + __IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */ + __IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */ + __IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */ + __IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */ + uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */ + __IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */ + __IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */ + __IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */ + uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */ + __IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */ + __IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */ + __IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */ + __IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */ + __IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */ + __IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */ + __IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */ + __IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */ + __IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */ + __IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */ + __IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */ + __IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */ + __IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */ + __IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */ + __IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */ + __IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */ + uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */ + __IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */ + uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */ + __IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */ + __IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */ + __IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */ + __IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */ + __IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */ + __IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */ + __IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */ + __IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */ + __IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */ + __IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */ + __IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */ + __IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */ + __IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */ + __IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */ + __IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */ + __IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */ + __IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */ + __IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */ + __IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */ + __IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */ + __IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */ + uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */ + __IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */ + __IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */ + uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */ + __IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */ + __IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */ + __IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */ + __IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */ + __IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */ + __IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */ + __IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */ + __IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */ + __IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */ + __IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */ + __IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */ + __IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */ + __IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */ + __IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */ + __IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */ + __IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */ + __IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */ + __IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */ + __IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */ + __IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */ + __IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */ + __IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */ + __IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */ + __IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */ + __IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */ + __IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */ + __IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */ + __IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */ + __IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */ + __IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */ + __IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */ + __IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */ + __IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */ + __IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */ + __IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */ + __IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */ + __IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */ + __IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */ + __IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */ + __IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */ + __IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */ + __IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */ + __IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */ + __IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */ + uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */ + __IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */ + __IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */ + __IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */ + uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */ + __IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */ + __IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */ + uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */ + __IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */ + __IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */ + uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */ + __IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */ + uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */ + __IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */ + __IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */ + __IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */ + uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */ + __IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */ + uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */ + __IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */ + uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */ + __IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */ + __IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */ + __IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */ + __IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */ + __IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */ + __IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */ + __IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */ + __IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */ + __IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */ + __IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */ + __IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */ + __IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */ + __IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */ + __IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */ + __IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */ + __IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */ + __IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */ + __IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */ + __IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */ + __IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */ + __IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */ + __IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */ + __IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */ + __IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */ + __IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */ + __IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */ + __IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */ + __IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */ + __IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */ + __IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */ + __IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */ + __IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */ + __IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */ + __IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */ + __IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */ + __IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */ + __IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */ + __IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */ + __IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */ + __IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */ + __IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */ + __IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */ + __IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */ + __IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */ + uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */ + __IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */ + uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */ + __IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */ + __IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */ + __IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */ + __IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */ + __IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */ + __IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */ + __IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */ + __IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */ + __IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */ + __IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */ +} RCC_TypeDef; + +/* + * @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1) + */ +typedef struct +{ + __IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */ + __IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */ + __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */ + uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */ + __IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */ + __IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */ + uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */ + __IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */ + uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */ +} RIFSC_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) + */ +typedef struct +{ + __IO uint32_t CFGR; /*!< RISAF Region X configuration register */ + __IO uint32_t STARTR; /*!< RISAF Region X start address register */ + __IO uint32_t ENDR; /*!< RISAF Region X end address register */ + __IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */ + __IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */ + __IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */ + __IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */ + __IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */ + __IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */ + __IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */ + __IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */ + __IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */ + uint32_t RESERVED0[4]; /*!< Reserved */ +} RISAF_Region_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t IAESR; /*!< RISAF Illegal access error status register */ + __IO uint32_t IADDR; /*!< RISAF Illegal address register, */ +} RISAF_Illegal_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */ + RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */ + RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */ +} RISAF_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 7U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ +__IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + __IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */ +} USB_PHY_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + __IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + __IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + __IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + __IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + __IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */ +} USB_HS_PHYC_GlobalTypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */ + __IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */ + __IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */ + __IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */ + __IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */ + __IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */ + __IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */ + __IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */ + __IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */ + __IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */ + __IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */ + __IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x44 */ + __IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x48 */ + __IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x4C */ + __IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x50 */ + __IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x54 */ + __IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x58 */ + __IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x5C */ + __IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x60 */ + __IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */ + __IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */ + __IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */ + __IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */ + uint32_t RESERVED3[34]; /*!< Reserved, Address offset: 0x78-0xFC */ + __IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */ + __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */ + uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */ + __IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */ + uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */ + __IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Extended-SPI Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** @} */ /* End of group STM32N6xx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal RAMs sizes */ +#define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */ +#define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */ +#define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */ +#define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */ +#define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */ +#define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */ +#define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */ +#define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */ +#define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */ +#define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */ +#define SRAM7_AXI_SIZE 0x40000UL /*!< SRAM7_AXI = 256 Kbytes */ +#define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */ + + +#define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */ +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK5_1 FMC_BANK5 +#define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL) +#define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL) +#define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL) +#define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK6_1 FMC_BANK6 +#define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL) +#define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL) +#define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL) +#define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */ +#define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */ +#define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */ + +/**************************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */ +/* */ +/**************************************************************************/ + +#define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define SRAM7_AXI_BASE_NS 0x243C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */ +#define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL) +#define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL) +#define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL) +#define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL) +#define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL) +#define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL) +#define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL) +#define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL) +#define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL) +#define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL) +#define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) +#define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL) +#define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL) +#define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL) +#define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL) +#define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL) +#define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL) +#define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL) +#define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL) +#define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL) +#define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL) +#define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL) +#define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL) +#define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL) +#define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL) +#define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL) +#define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL) +#define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL) +#define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL) +#define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL) +#define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL) +#define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL) +#define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL) +#define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL) +#define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL) +#define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL) +#define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL) +#define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL) +#define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL) +#define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL) +#define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL) +#define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL) +#define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL) +#define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL) +#define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL) +#define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL) +#define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL) +#define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL) +#define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL) +#define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL) +#define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL) +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL) +#define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL) +#define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL) +#define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL) +#define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL) +#define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL) +#define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL) +#define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL) +#define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL) +#define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL) +#define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL) +#define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL) +#define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL) +#define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL) +#define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL) +#define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL) +#define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL) +#define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL) +#define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL) +#define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL) +#define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL) +#define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL) +#define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL) +#define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL) +#define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL) +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) +#define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL) +#define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL) +#define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL) +#define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL) +#define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL) +#define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL) +#define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL) +#define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL) +#define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL) +#define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL) +#define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL) +#define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL) +#define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL) +#define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL) +#define ETH1_MAC_BASE_NS (ETH1_BASE_NS) +#define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL) +#define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL) +#define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_NS (0x46009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_NS (BOOTROM_BASE_NS + 0x001004UL) + + +#if defined (CPU_IN_SECURE_STATE) +/*********************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */ +/* */ +/*********************************************************************/ +#define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define SRAM7_AXI_BASE_S 0x343C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */ +#define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL) +#define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL) +#define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL) +#define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL) +#define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL) +#define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL) +#define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL) +#define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL) +#define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL) +#define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL) +#define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) +#define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL) +#define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL) +#define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL) +#define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL) +#define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL) +#define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL) +#define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL) +#define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL) +#define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL) +#define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL) +#define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL) +#define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL) +#define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL) +#define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL) +#define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL) +#define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL) +#define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL) +#define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL) +#define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL) +#define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL) +#define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL) +#define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL) +#define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL) +#define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL) +#define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL) +#define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL) +#define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL) + +#define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL) +#define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL) +#define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL) +#define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL) +#define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL) +#define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL) +#define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL) +#define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL) +#define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL) +#define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL) +#define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL) +#define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL) +#define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL) +#define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL) +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL) +#define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL) +#define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL) +#define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL) +#define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL) +#define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL) +#define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL) +#define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL) +#define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL) +#define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL) +#define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL) +#define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL) +#define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL) +#define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL) +#define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL) +#define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL) +#define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL) +#define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL) +#define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL) +#define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL) +#define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL) +#define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL) +#define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL) +#define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL) +#define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) +#define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL) +#define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL) +#define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL) +#define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL) +#define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL) +#define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL) +#define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL) +#define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL) +#define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL) +#define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL) +#define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL) +#define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL) +#define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL) +#define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL) +#define ETH1_MAC_BASE_S (ETH1_BASE_S) +#define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL) +#define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL) +#define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_S (0x56009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_S (BOOTROM_BASE_S + 0x001004UL) + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS) +#define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS) +#define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS) +#define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS) +#define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS) +#define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS) +#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS) +#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) +#define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS) +#define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS) +#define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS) +#define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS) +#define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS) +#define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS) +#define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS) +#define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS) +#define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS) +#define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS) +#define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS) +#define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS) +#define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS) +#define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS) +#define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS) +#define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS) +#define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS) +#define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS) +#define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS) +#define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS) +#define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS) +#define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS) +#define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS) +#define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS) +#define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS) +#define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS) +#define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS) +#define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS) +#define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS) +#define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS) +#define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS) +#define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS) +#define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS) +#define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS) +#define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS) +#define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS) +#define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS) +#define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS) +#define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS) +#define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS) +#define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS) +#define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS) +#define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS) +#define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS) +#define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS) +#define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS) +#define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define UART7_NS ((USART_TypeDef *) UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *) UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *) UART9_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *) USART10_BASE_NS) +#define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS) +#define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS) +#define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS) +#define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS) +#define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS) +#define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS) +#define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS) +#define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S) +#define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CSI_S ((CSI_TypeDef *) CSI_BASE_S) +#define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define DTS_S ((DTS_TypeDef *) DTS_BASE_S) +#define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S) +#define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S) +#define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S) +#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S) +#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) +#define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPION_S ((GPIO_TypeDef *) GPION_BASE_S) +#define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S) +#define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S) +#define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S) +#define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S) +#define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S) +#define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S) +#define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S) +#define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S) +#define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S) +#define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S) +#define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S) +#define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S) +#define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S) +#define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S) +#define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S) +#define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S) +#define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S) +#define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S) +#define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define IAC_S ((IAC_TypeDef *) IAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S) +#define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S) +#define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S) +#define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S) +#define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S) +#define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S) +#define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S) +#define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S) +#define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S) +#define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S) +#define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S) +#define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S) +#define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S) +#define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S) +#define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S) +#define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S) +#define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S) +#define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S) +#define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S) +#define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S) +#define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S) +#define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S) +#define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S) +#define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S) +#define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S) +#define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S) +#define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S) +#define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define UART7_S ((USART_TypeDef *) UART7_BASE_S) +#define UART8_S ((USART_TypeDef *) UART8_BASE_S) +#define UART9_S ((USART_TypeDef *) UART9_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define USART10_S ((USART_TypeDef *) USART10_BASE_S) +#define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S) +#define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S) +#define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S) +#define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S) +#define VENC_S ((VENC_TypeDef *) VENC_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S) +#define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S) +#define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S) +#define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S) +#endif + +/*!< Peripheral Instance aliases for Non-Secure/Secure execution */ +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define BSEC BSEC_S +#define BSEC_BASE BSEC_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + + +#define CSI CSI_S +#define CSI_BASE CSI_BASE_S + +#define DBGMCU DBGMCU_S +#define DBGMCU_BASE DBGMCU_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define DCMIPP DCMIPP_S +#define DCMIPP_BASE DCMIPP_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define DTS_Sensor0 DTS_Sensor0_S +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_S + +#define DTS_Sensor1 DTS_Sensor1_S +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_S + +#define ETH1 ETH1_S +#define ETH1_BASE ETH1_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define FDCAN3 FDCAN3_S +#define FDCAN3_BASE FDCAN3_BASE_S + +#define FDCAN_CCU FDCAN_CCU_S +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S + +#define FMC_R_BASE FMC_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define FMC_Common_R FMC_Common_R_S +#define FMC_Common_R_BASE FMC_Common_R_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPION GPION_S +#define GPION_BASE GPION_BASE_S + +#define GPIOO GPIOO_S +#define GPIOO_BASE GPIOO_BASE_S + +#define GPIOP GPIOP_S +#define GPIOP_BASE GPIOP_BASE_S + +#define GPIOQ GPIOQ_S +#define GPIOQ_BASE GPIOQ_BASE_S + +#define GPU2D GPU2D_BASE_S +#define GPU2D_BASE GPU2D_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define HPDMA1 HPDMA1_S +#define HPDMA1_BASE HPDMA1_BASE_S + +#define HPDMA1_Channel0 HPDMA1_Channel0_S +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S + +#define HPDMA1_Channel1 HPDMA1_Channel1_S +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S + +#define HPDMA1_Channel2 HPDMA1_Channel2_S +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S + +#define HPDMA1_Channel3 HPDMA1_Channel3_S +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S + +#define HPDMA1_Channel4 HPDMA1_Channel4_S +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S + +#define HPDMA1_Channel5 HPDMA1_Channel5_S +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S + +#define HPDMA1_Channel6 HPDMA1_Channel6_S +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S + +#define HPDMA1_Channel7 HPDMA1_Channel7_S +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S + +#define HPDMA1_Channel8 HPDMA1_Channel8_S +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S + +#define HPDMA1_Channel9 HPDMA1_Channel9_S +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S + +#define HPDMA1_Channel10 HPDMA1_Channel10_S +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S + +#define HPDMA1_Channel11 HPDMA1_Channel11_S +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S + +#define HPDMA1_Channel12 HPDMA1_Channel12_S +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S + +#define HPDMA1_Channel13 HPDMA1_Channel13_S +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S + +#define HPDMA1_Channel14 HPDMA1_Channel14_S +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S + +#define HPDMA1_Channel15 HPDMA1_Channel15_S +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define IAC IAC_S +#define IAC_BASE IAC_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1 LTDC_Layer1_S +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S + +#define LTDC_Layer2 LTDC_Layer2_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define MDIOS MDIOS_S +#define MDIOS_BASE MDIOS_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG RAMCFG_S +#define RAMCFG_BASE RAMCFG_BASE_S + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define RIFSC RIFSC_S +#define RIFSC_BASE RIFSC_BASE_S + +#define RISAF1 RISAF1_S +#define RISAF1_BASE RISAF1_BASE_S + +#define RISAF2 RISAF2_S +#define RISAF2_BASE RISAF2_BASE_S + +#define RISAF3 RISAF3_S +#define RISAF3_BASE RISAF3_BASE_S + +#define RISAF6 RISAF6_S +#define RISAF6_BASE RISAF6_BASE_S + +#define RISAF7 RISAF7_S +#define RISAF7_BASE RISAF7_BASE_S + +#define RISAF8 RISAF8_S +#define RISAF8_BASE RISAF8_BASE_S + +#define RISAF9 RISAF9_S +#define RISAF9_BASE RISAF9_BASE_S + +#define RISAF11 RISAF11_S +#define RISAF11_BASE RISAF11_BASE_S + +#define RISAF12 RISAF12_S +#define RISAF12_BASE RISAF12_BASE_S + +#define RISAF13 RISAF13_S +#define RISAF13_BASE RISAF13_BASE_S + +#define RISAF14 RISAF14_S +#define RISAF14_BASE RISAF14_BASE_S + +#define RISAF21 RISAF21_S +#define RISAF21_BASE RISAF21_BASE_S + +#define RISAF22 RISAF22_S +#define RISAF22_BASE RISAF22_BASE_S + +#define RISAF23 RISAF23_S +#define RISAF23_BASE RISAF23_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define SPDIFRX SPDIFRX_S +#define SPDIFRX_BASE SPDIFRX_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM9 TIM9_S +#define TIM9_BASE TIM9_BASE_S + +#define TIM10 TIM10_S +#define TIM10_BASE TIM10_BASE_S + +#define TIM11 TIM11_S +#define TIM11_BASE TIM11_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define TIM18 TIM18_S +#define TIM18_BASE TIM18_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USB1_OTG_HS USB1_OTG_HS_S +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S + +#define USB2_OTG_HS USB2_OTG_HS_S +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S + +#define USB1_HS_PHYC USB1_HS_PHYC_S +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S + +#define USB2_HS_PHYC USB2_HS_PHYC_S +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S + +#define VENC VENC_S +#define VENC_BASE VENC_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define XSPI1 XSPI1_S + +#define XSPI2 XSPI2_S + +#define XSPI3 XSPI3_S + +#define XSPIM XSPIM_S +#define XSPIM_BASE XSPIM_BASE_S + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_S + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_S + +#else + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS + +#define BSEC BSEC_NS +#define BSEC_BASE BSEC_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + + +#define CSI CSI_NS +#define CSI_BASE CSI_BASE_NS + +#define DBGMCU DBGMCU_NS +#define DBGMCU_BASE DBGMCU_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define DCMIPP DCMIPP_NS +#define DCMIPP_BASE DCMIPP_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define DTS_Sensor0 DTS_Sensor0_NS +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS + +#define DTS_Sensor1 DTS_Sensor1_NS +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS + +#define ETH1 ETH1_NS +#define ETH1_BASE ETH1_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define FDCAN3 FDCAN3_NS +#define FDCAN3_BASE FDCAN3_BASE_NS + +#define FDCAN_CCU FDCAN_CCU_NS +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS + +#define FMC_R_BASE FMC_R_BASE_NS +#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define FMC_Common_R FMC_Common_R_NS +#define FMC_Common_R_BASE FMC_Common_R_BASE_NS + +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPION GPION_NS +#define GPION_BASE GPION_BASE_NS + +#define GPIOO GPIOO_NS +#define GPIOO_BASE GPIOO_BASE_NS + +#define GPIOP GPIOP_NS +#define GPIOP_BASE GPIOP_BASE_NS + +#define GPIOQ GPIOQ_NS +#define GPIOQ_BASE GPIOQ_BASE_NS + +#define GPU2D GPU2D_BASE_NS +#define GPU2D_BASE GPU2D_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define HPDMA1 HPDMA1_NS +#define HPDMA1_BASE HPDMA1_BASE_NS + +#define HPDMA1_Channel0 HPDMA1_Channel0_NS +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS + +#define HPDMA1_Channel1 HPDMA1_Channel1_NS +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS + +#define HPDMA1_Channel2 HPDMA1_Channel2_NS +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS + +#define HPDMA1_Channel3 HPDMA1_Channel3_NS +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS + +#define HPDMA1_Channel4 HPDMA1_Channel4_NS +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS + +#define HPDMA1_Channel5 HPDMA1_Channel5_NS +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS + +#define HPDMA1_Channel6 HPDMA1_Channel6_NS +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS + +#define HPDMA1_Channel7 HPDMA1_Channel7_NS +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS + +#define HPDMA1_Channel8 HPDMA1_Channel8_NS +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS + +#define HPDMA1_Channel9 HPDMA1_Channel9_NS +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS + +#define HPDMA1_Channel10 HPDMA1_Channel10_NS +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS + +#define HPDMA1_Channel11 HPDMA1_Channel11_NS +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS + +#define HPDMA1_Channel12 HPDMA1_Channel12_NS +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS + +#define HPDMA1_Channel13 HPDMA1_Channel13_NS +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS + +#define HPDMA1_Channel14 HPDMA1_Channel14_NS +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS + +#define HPDMA1_Channel15 HPDMA1_Channel15_NS +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define MDIOS MDIOS_NS +#define MDIOS_BASE MDIOS_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG RAMCFG_NS +#define RAMCFG_BASE RAMCFG_BASE_NS + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define RIFSC RIFSC_NS +#define RIFSC_BASE RIFSC_BASE_NS + +#define RISAF1 RISAF1_NS +#define RISAF1_BASE RISAF1_BASE_NS + +#define RISAF2 RISAF2_NS +#define RISAF2_BASE RISAF2_BASE_NS + +#define RISAF3 RISAF3_NS +#define RISAF3_BASE RISAF3_BASE_NS + +#define RISAF6 RISAF6_NS +#define RISAF6_BASE RISAF6_BASE_NS + +#define RISAF7 RISAF7_NS +#define RISAF7_BASE RISAF7_BASE_NS + +#define RISAF8 RISAF8_NS +#define RISAF8_BASE RISAF8_BASE_NS + +#define RISAF9 RISAF9_NS +#define RISAF9_BASE RISAF9_BASE_NS + +#define RISAF11 RISAF11_NS +#define RISAF11_BASE RISAF11_BASE_NS + +#define RISAF12 RISAF12_NS +#define RISAF12_BASE RISAF12_BASE_NS + +#define RISAF13 RISAF13_NS +#define RISAF13_BASE RISAF13_BASE_NS + +#define RISAF14 RISAF14_NS +#define RISAF14_BASE RISAF14_BASE_NS + +#define RISAF21 RISAF21_NS +#define RISAF21_BASE RISAF21_BASE_NS + +#define RISAF22 RISAF22_NS +#define RISAF22_BASE RISAF22_BASE_NS + +#define RISAF23 RISAF23_NS +#define RISAF23_BASE RISAF23_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define SPDIFRX SPDIFRX_NS +#define SPDIFRX_BASE SPDIFRX_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM9 TIM9_NS +#define TIM9_BASE TIM9_BASE_NS + +#define TIM10 TIM10_NS +#define TIM10_BASE TIM10_BASE_NS + +#define TIM11 TIM11_NS +#define TIM11_BASE TIM11_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define TIM18 TIM18_NS +#define TIM18_BASE TIM18_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USB1_OTG_HS USB1_OTG_HS_NS +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS + +#define USB2_OTG_HS USB2_OTG_HS_NS +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS + +#define USB1_HS_PHYC USB1_HS_PHYC_NS +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS + +#define USB2_HS_PHYC USB2_HS_PHYC_NS +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS + +#define VENC VENC_NS +#define VENC_BASE VENC_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define XSPI1 XSPI1_NS + +#define XSPI2 XSPI2_NS + +#define XSPI3 XSPI3_NS + +#define XSPIM XSPIM_NS +#define XSPIM_BASE XSPIM_BASE_NS + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_NS + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_NS + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_declaration */ + +/** @addtogroup STM32N6xx_Peripheral_Timing_Definition + * @{ + */ + +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ + +/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30UL) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0UL) +#define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16UL) +#define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ + +#define ADC_CALFACT_CALADDOS_Pos (31UL) +#define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */ +#define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */ + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_OP0_Pos (0UL) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */ + +#define ADC_OR_OP1_Pos (1UL) +#define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */ + +#define ADC_OR_OP2_Pos (2UL) +#define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */ +#define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */ + + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* BSEC unit (Boot and Security) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for BSEC_FVRw register *******************/ +#define BSEC_FVRw_FV_Pos (0UL) +#define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */ + +/***************** Bit definition for BSEC_SPLOCKx register *****************/ +#define BSEC_SPLOCKx_SPLOCK0_Pos (0UL) +#define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */ +#define BSEC_SPLOCKx_SPLOCK1_Pos (1UL) +#define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */ +#define BSEC_SPLOCKx_SPLOCK2_Pos (2UL) +#define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */ +#define BSEC_SPLOCKx_SPLOCK3_Pos (3UL) +#define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */ +#define BSEC_SPLOCKx_SPLOCK4_Pos (4UL) +#define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */ +#define BSEC_SPLOCKx_SPLOCK5_Pos (5UL) +#define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */ +#define BSEC_SPLOCKx_SPLOCK6_Pos (6UL) +#define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */ +#define BSEC_SPLOCKx_SPLOCK7_Pos (7UL) +#define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */ +#define BSEC_SPLOCKx_SPLOCK8_Pos (8UL) +#define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */ +#define BSEC_SPLOCKx_SPLOCK9_Pos (9UL) +#define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */ +#define BSEC_SPLOCKx_SPLOCK10_Pos (10UL) +#define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */ +#define BSEC_SPLOCKx_SPLOCK11_Pos (11UL) +#define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */ +#define BSEC_SPLOCKx_SPLOCK12_Pos (12UL) +#define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */ +#define BSEC_SPLOCKx_SPLOCK13_Pos (13UL) +#define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */ +#define BSEC_SPLOCKx_SPLOCK14_Pos (14UL) +#define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */ +#define BSEC_SPLOCKx_SPLOCK15_Pos (15UL) +#define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */ +#define BSEC_SPLOCKx_SPLOCK16_Pos (16UL) +#define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */ +#define BSEC_SPLOCKx_SPLOCK17_Pos (17UL) +#define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */ +#define BSEC_SPLOCKx_SPLOCK18_Pos (18UL) +#define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */ +#define BSEC_SPLOCKx_SPLOCK19_Pos (19UL) +#define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */ +#define BSEC_SPLOCKx_SPLOCK20_Pos (20UL) +#define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */ +#define BSEC_SPLOCKx_SPLOCK21_Pos (21UL) +#define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */ +#define BSEC_SPLOCKx_SPLOCK22_Pos (22UL) +#define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */ +#define BSEC_SPLOCKx_SPLOCK23_Pos (23UL) +#define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */ +#define BSEC_SPLOCKx_SPLOCK24_Pos (24UL) +#define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */ +#define BSEC_SPLOCKx_SPLOCK25_Pos (25UL) +#define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */ +#define BSEC_SPLOCKx_SPLOCK26_Pos (26UL) +#define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */ +#define BSEC_SPLOCKx_SPLOCK27_Pos (27UL) +#define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */ +#define BSEC_SPLOCKx_SPLOCK28_Pos (28UL) +#define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */ +#define BSEC_SPLOCKx_SPLOCK29_Pos (29UL) +#define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */ +#define BSEC_SPLOCKx_SPLOCK30_Pos (30UL) +#define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */ +#define BSEC_SPLOCKx_SPLOCK31_Pos (31UL) +#define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */ + +/***************** Bit definition for BSEC_SWLOCKx register *****************/ +#define BSEC_SWLOCKx_SWLOCK0_Pos (0UL) +#define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */ +#define BSEC_SWLOCKx_SWLOCK1_Pos (1UL) +#define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */ +#define BSEC_SWLOCKx_SWLOCK2_Pos (2UL) +#define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */ +#define BSEC_SWLOCKx_SWLOCK3_Pos (3UL) +#define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */ +#define BSEC_SWLOCKx_SWLOCK4_Pos (4UL) +#define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */ +#define BSEC_SWLOCKx_SWLOCK5_Pos (5UL) +#define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */ +#define BSEC_SWLOCKx_SWLOCK6_Pos (6UL) +#define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */ +#define BSEC_SWLOCKx_SWLOCK7_Pos (7UL) +#define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */ +#define BSEC_SWLOCKx_SWLOCK8_Pos (8UL) +#define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */ +#define BSEC_SWLOCKx_SWLOCK9_Pos (9UL) +#define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */ +#define BSEC_SWLOCKx_SWLOCK10_Pos (10UL) +#define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */ +#define BSEC_SWLOCKx_SWLOCK11_Pos (11UL) +#define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */ +#define BSEC_SWLOCKx_SWLOCK12_Pos (12UL) +#define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */ +#define BSEC_SWLOCKx_SWLOCK13_Pos (13UL) +#define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */ +#define BSEC_SWLOCKx_SWLOCK14_Pos (14UL) +#define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */ +#define BSEC_SWLOCKx_SWLOCK15_Pos (15UL) +#define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */ +#define BSEC_SWLOCKx_SWLOCK16_Pos (16UL) +#define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */ +#define BSEC_SWLOCKx_SWLOCK17_Pos (17UL) +#define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */ +#define BSEC_SWLOCKx_SWLOCK18_Pos (18UL) +#define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */ +#define BSEC_SWLOCKx_SWLOCK19_Pos (19UL) +#define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */ +#define BSEC_SWLOCKx_SWLOCK20_Pos (20UL) +#define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */ +#define BSEC_SWLOCKx_SWLOCK21_Pos (21UL) +#define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */ +#define BSEC_SWLOCKx_SWLOCK22_Pos (22UL) +#define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */ +#define BSEC_SWLOCKx_SWLOCK23_Pos (23UL) +#define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */ +#define BSEC_SWLOCKx_SWLOCK24_Pos (24UL) +#define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */ +#define BSEC_SWLOCKx_SWLOCK25_Pos (25UL) +#define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */ +#define BSEC_SWLOCKx_SWLOCK26_Pos (26UL) +#define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */ +#define BSEC_SWLOCKx_SWLOCK27_Pos (27UL) +#define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */ +#define BSEC_SWLOCKx_SWLOCK28_Pos (28UL) +#define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */ +#define BSEC_SWLOCKx_SWLOCK29_Pos (29UL) +#define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */ +#define BSEC_SWLOCKx_SWLOCK30_Pos (30UL) +#define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */ +#define BSEC_SWLOCKx_SWLOCK31_Pos (31UL) +#define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */ + +/***************** Bit definition for BSEC_SRLOCKx register *****************/ +#define BSEC_SRLOCKx_SRLOCK0_Pos (0UL) +#define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */ +#define BSEC_SRLOCKx_SRLOCK1_Pos (1UL) +#define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */ +#define BSEC_SRLOCKx_SRLOCK2_Pos (2UL) +#define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */ +#define BSEC_SRLOCKx_SRLOCK3_Pos (3UL) +#define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */ +#define BSEC_SRLOCKx_SRLOCK4_Pos (4UL) +#define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */ +#define BSEC_SRLOCKx_SRLOCK5_Pos (5UL) +#define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */ +#define BSEC_SRLOCKx_SRLOCK6_Pos (6UL) +#define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */ +#define BSEC_SRLOCKx_SRLOCK7_Pos (7UL) +#define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */ +#define BSEC_SRLOCKx_SRLOCK8_Pos (8UL) +#define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */ +#define BSEC_SRLOCKx_SRLOCK9_Pos (9UL) +#define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */ +#define BSEC_SRLOCKx_SRLOCK10_Pos (10UL) +#define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */ +#define BSEC_SRLOCKx_SRLOCK11_Pos (11UL) +#define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */ +#define BSEC_SRLOCKx_SRLOCK12_Pos (12UL) +#define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */ +#define BSEC_SRLOCKx_SRLOCK13_Pos (13UL) +#define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */ +#define BSEC_SRLOCKx_SRLOCK14_Pos (14UL) +#define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */ +#define BSEC_SRLOCKx_SRLOCK15_Pos (15UL) +#define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */ +#define BSEC_SRLOCKx_SRLOCK16_Pos (16UL) +#define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */ +#define BSEC_SRLOCKx_SRLOCK17_Pos (17UL) +#define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */ +#define BSEC_SRLOCKx_SRLOCK18_Pos (18UL) +#define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */ +#define BSEC_SRLOCKx_SRLOCK19_Pos (19UL) +#define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */ +#define BSEC_SRLOCKx_SRLOCK20_Pos (20UL) +#define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */ +#define BSEC_SRLOCKx_SRLOCK21_Pos (21UL) +#define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */ +#define BSEC_SRLOCKx_SRLOCK22_Pos (22UL) +#define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */ +#define BSEC_SRLOCKx_SRLOCK23_Pos (23UL) +#define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */ +#define BSEC_SRLOCKx_SRLOCK24_Pos (24UL) +#define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */ +#define BSEC_SRLOCKx_SRLOCK25_Pos (25UL) +#define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */ +#define BSEC_SRLOCKx_SRLOCK26_Pos (26UL) +#define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */ +#define BSEC_SRLOCKx_SRLOCK27_Pos (27UL) +#define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */ +#define BSEC_SRLOCKx_SRLOCK28_Pos (28UL) +#define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */ +#define BSEC_SRLOCKx_SRLOCK29_Pos (29UL) +#define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */ +#define BSEC_SRLOCKx_SRLOCK30_Pos (30UL) +#define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */ +#define BSEC_SRLOCKx_SRLOCK31_Pos (31UL) +#define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */ + +/**************** Bit definition for BSEC_OTPVLDRx register *****************/ +#define BSEC_OTPVLDRx_VLDF0_Pos (0UL) +#define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */ +#define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */ +#define BSEC_OTPVLDRx_VLDF1_Pos (1UL) +#define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */ +#define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */ +#define BSEC_OTPVLDRx_VLDF2_Pos (2UL) +#define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */ +#define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */ +#define BSEC_OTPVLDRx_VLDF3_Pos (3UL) +#define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */ +#define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */ +#define BSEC_OTPVLDRx_VLDF4_Pos (4UL) +#define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */ +#define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */ +#define BSEC_OTPVLDRx_VLDF5_Pos (5UL) +#define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */ +#define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */ +#define BSEC_OTPVLDRx_VLDF6_Pos (6UL) +#define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */ +#define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */ +#define BSEC_OTPVLDRx_VLDF7_Pos (7UL) +#define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */ +#define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */ +#define BSEC_OTPVLDRx_VLDF8_Pos (8UL) +#define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */ +#define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */ +#define BSEC_OTPVLDRx_VLDF9_Pos (9UL) +#define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */ +#define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */ +#define BSEC_OTPVLDRx_VLDF10_Pos (10UL) +#define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */ +#define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */ +#define BSEC_OTPVLDRx_VLDF11_Pos (11UL) +#define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */ +#define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */ +#define BSEC_OTPVLDRx_VLDF12_Pos (12UL) +#define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */ +#define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */ +#define BSEC_OTPVLDRx_VLDF13_Pos (13UL) +#define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */ +#define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */ +#define BSEC_OTPVLDRx_VLDF14_Pos (14UL) +#define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */ +#define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */ +#define BSEC_OTPVLDRx_VLDF15_Pos (15UL) +#define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */ +#define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */ +#define BSEC_OTPVLDRx_VLDF16_Pos (16UL) +#define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */ +#define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */ +#define BSEC_OTPVLDRx_VLDF17_Pos (17UL) +#define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */ +#define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */ +#define BSEC_OTPVLDRx_VLDF18_Pos (18UL) +#define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */ +#define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */ +#define BSEC_OTPVLDRx_VLDF19_Pos (19UL) +#define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */ +#define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */ +#define BSEC_OTPVLDRx_VLDF20_Pos (20UL) +#define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */ +#define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */ +#define BSEC_OTPVLDRx_VLDF21_Pos (21UL) +#define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */ +#define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */ +#define BSEC_OTPVLDRx_VLDF22_Pos (22UL) +#define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */ +#define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */ +#define BSEC_OTPVLDRx_VLDF23_Pos (23UL) +#define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */ +#define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */ +#define BSEC_OTPVLDRx_VLDF24_Pos (24UL) +#define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */ +#define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */ +#define BSEC_OTPVLDRx_VLDF25_Pos (25UL) +#define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */ +#define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */ +#define BSEC_OTPVLDRx_VLDF26_Pos (26UL) +#define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */ +#define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */ +#define BSEC_OTPVLDRx_VLDF27_Pos (27UL) +#define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */ +#define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */ +#define BSEC_OTPVLDRx_VLDF28_Pos (28UL) +#define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */ +#define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */ +#define BSEC_OTPVLDRx_VLDF29_Pos (29UL) +#define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */ +#define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */ +#define BSEC_OTPVLDRx_VLDF30_Pos (30UL) +#define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */ +#define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */ +#define BSEC_OTPVLDRx_VLDF31_Pos (31UL) +#define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */ +#define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */ + +/****************** Bit definition for BSEC_SFSRx register ******************/ +#define BSEC_SFSRx_SFW0_Pos (0UL) +#define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */ +#define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */ +#define BSEC_SFSRx_SFW1_Pos (1UL) +#define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */ +#define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */ +#define BSEC_SFSRx_SFW2_Pos (2UL) +#define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */ +#define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */ +#define BSEC_SFSRx_SFW3_Pos (3UL) +#define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */ +#define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */ +#define BSEC_SFSRx_SFW4_Pos (4UL) +#define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */ +#define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */ +#define BSEC_SFSRx_SFW5_Pos (5UL) +#define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */ +#define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */ +#define BSEC_SFSRx_SFW6_Pos (6UL) +#define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */ +#define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */ +#define BSEC_SFSRx_SFW7_Pos (7UL) +#define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */ +#define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */ +#define BSEC_SFSRx_SFW8_Pos (8UL) +#define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */ +#define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */ +#define BSEC_SFSRx_SFW9_Pos (9UL) +#define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */ +#define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */ +#define BSEC_SFSRx_SFW10_Pos (10UL) +#define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */ +#define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */ +#define BSEC_SFSRx_SFW11_Pos (11UL) +#define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */ +#define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */ +#define BSEC_SFSRx_SFW12_Pos (12UL) +#define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */ +#define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */ +#define BSEC_SFSRx_SFW13_Pos (13UL) +#define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */ +#define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */ +#define BSEC_SFSRx_SFW14_Pos (14UL) +#define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */ +#define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */ +#define BSEC_SFSRx_SFW15_Pos (15UL) +#define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */ +#define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */ +#define BSEC_SFSRx_SFW16_Pos (16UL) +#define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */ +#define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */ +#define BSEC_SFSRx_SFW17_Pos (17UL) +#define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */ +#define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */ +#define BSEC_SFSRx_SFW18_Pos (18UL) +#define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */ +#define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */ +#define BSEC_SFSRx_SFW19_Pos (19UL) +#define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */ +#define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */ +#define BSEC_SFSRx_SFW20_Pos (20UL) +#define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */ +#define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */ +#define BSEC_SFSRx_SFW21_Pos (21UL) +#define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */ +#define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */ +#define BSEC_SFSRx_SFW22_Pos (22UL) +#define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */ +#define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */ +#define BSEC_SFSRx_SFW23_Pos (23UL) +#define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */ +#define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */ +#define BSEC_SFSRx_SFW24_Pos (24UL) +#define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */ +#define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */ +#define BSEC_SFSRx_SFW25_Pos (25UL) +#define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */ +#define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */ +#define BSEC_SFSRx_SFW26_Pos (26UL) +#define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */ +#define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */ +#define BSEC_SFSRx_SFW27_Pos (27UL) +#define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */ +#define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */ +#define BSEC_SFSRx_SFW28_Pos (28UL) +#define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */ +#define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */ +#define BSEC_SFSRx_SFW29_Pos (29UL) +#define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */ +#define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */ +#define BSEC_SFSRx_SFW30_Pos (30UL) +#define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */ +#define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */ +#define BSEC_SFSRx_SFW31_Pos (31UL) +#define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */ +#define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */ + +/****************** Bit definition for BSEC_OTPCR register ******************/ +#define BSEC_OTPCR_ADDR_Pos (0UL) +#define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */ +#define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */ +#define BSEC_OTPCR_PROG_Pos (13UL) +#define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */ +#define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */ +#define BSEC_OTPCR_PPLOCK_Pos (14UL) +#define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */ +#define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */ +#define BSEC_OTPCR_LASTCID_Pos (19UL) +#define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */ +#define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */ + +/******************* Bit definition for BSEC_WDR register *******************/ +#define BSEC_WDR_WRDATA_Pos (0UL) +#define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */ + +/**************** Bit definition for BSEC_SCRATCHRx register ****************/ +#define BSEC_SCRATCHRx_SDATA_Pos (0UL) +#define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */ + +/****************** Bit definition for BSEC_LOCKR register ******************/ +#define BSEC_LOCKR_GWLOCK_Pos (0UL) +#define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */ +#define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */ +#define BSEC_LOCKR_HKLOCK_Pos (2UL) +#define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */ +#define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */ + +/***************** Bit definition for BSEC_JTAGINR register *****************/ +#define BSEC_JTAGINR_JDATAIN_Pos (0UL) +#define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */ + +/**************** Bit definition for BSEC_JTAGOUTR register *****************/ +#define BSEC_JTAGOUTR_JDATAOUT_Pos (0UL) +#define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */ + +/***************** Bit definition for BSEC_UNMAPR register ******************/ +#define BSEC_UNMAPR_UNMAP_Pos (0UL) +#define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */ + +/******************* Bit definition for BSEC_SR register ********************/ +#define BSEC_SR_HVALID_Pos (1UL) +#define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */ +#define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */ +#define BSEC_SR_DBGREQ_Pos (16UL) +#define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */ +#define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */ +#define BSEC_SR_NVSTATE_Pos (26UL) +#define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */ +#define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */ + +/****************** Bit definition for BSEC_OTPSR register ******************/ +#define BSEC_OTPSR_BUSY_Pos (0UL) +#define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */ +#define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */ +#define BSEC_OTPSR_INIT_DONE_Pos (1UL) +#define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */ +#define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */ +#define BSEC_OTPSR_HIDEUP_Pos (2UL) +#define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */ +#define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */ +#define BSEC_OTPSR_OTPNVIR_Pos (4UL) +#define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */ +#define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */ +#define BSEC_OTPSR_OTPERR_Pos (5UL) +#define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */ +#define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */ +#define BSEC_OTPSR_OTPSEC_Pos (6UL) +#define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */ +#define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */ +#define BSEC_OTPSR_PROGFAIL_Pos (16UL) +#define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */ +#define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */ +#define BSEC_OTPSR_DISTURBF_Pos (17UL) +#define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */ +#define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */ +#define BSEC_OTPSR_DEDF_Pos (18UL) +#define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */ +#define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */ +#define BSEC_OTPSR_SECF_Pos (19UL) +#define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */ +#define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */ +#define BSEC_OTPSR_PPLF_Pos (20UL) +#define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */ +#define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */ +#define BSEC_OTPSR_PPLMF_Pos (21UL) +#define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */ +#define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */ +#define BSEC_OTPSR_AMEF_Pos (22UL) +#define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */ +#define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */ + +/***************** Bit definition for BSEC_EPOCHRx register *****************/ +#define BSEC_EPOCHRx_EPOCH_Pos (0UL) +#define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */ + +/**************** Bit definition for BSEC_EPOCHSELR register ****************/ +#define BSEC_EPOCHSELR_EPSEL_Pos (0UL) +#define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */ +#define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */ + +/****************** Bit definition for BSEC_DBGCR register ******************/ +#define BSEC_DBGCR_UNLOCK_Pos (8UL) +#define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */ +#define BSEC_DBGCR_AUTH_HDPL_Pos (16UL) +#define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */ +#define BSEC_DBGCR_AUTH_SEC_Pos (24UL) +#define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */ + +/*************** Bit definition for BSEC_AP_UNLOCK register *****************/ +#define BSEC_AP_UNLOCK_UNLOCK_Pos (0UL) +#define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */ +#define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */ + +/***************** Bit definition for BSEC_HDPLSR register ******************/ +#define BSEC_HDPLSR_HDPL_Pos (0UL) +#define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */ + +/***************** Bit definition for BSEC_HDPLCR register ******************/ +#define BSEC_HDPLCR_INCR_HDPL_Pos (0UL) +#define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */ + +/***************** Bit definition for BSEC_NEXTLR register ******************/ +#define BSEC_NEXTLR_INCR_Pos (0UL) +#define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */ +#define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */ + +/***************** Bit definition for BSEC_WOSCRx register ******************/ +#define BSEC_WOSCRx_WOSDATA_Pos (0UL) +#define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */ + +/****************** Bit definition for BSEC_HRCR register *******************/ +#define BSEC_HRCR_HRC_Pos (0UL) +#define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */ + +/****************** Bit definition for BSEC_WRCR register *******************/ +#define BSEC_WRCR_WRC_Pos (0UL) +#define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* (CSI) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CSI_CR register ********************/ +#define CSI_CR_CSIEN_Pos (0UL) +#define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */ +#define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */ +#define CSI_CR_VC0START_Pos (2UL) +#define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */ +#define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */ +#define CSI_CR_VC0STOP_Pos (3UL) +#define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */ +#define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */ +#define CSI_CR_VC1START_Pos (6UL) +#define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */ +#define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */ +#define CSI_CR_VC1STOP_Pos (7UL) +#define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */ +#define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */ +#define CSI_CR_VC2START_Pos (10UL) +#define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */ +#define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */ +#define CSI_CR_VC2STOP_Pos (11UL) +#define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */ +#define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */ +#define CSI_CR_VC3START_Pos (14UL) +#define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */ +#define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */ +#define CSI_CR_VC3STOP_Pos (15UL) +#define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */ +#define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */ + +/******************* Bit definition for CSI_PCR register ********************/ +#define CSI_PCR_PWRDOWN_Pos (0UL) +#define CSI_PCR_PWRDOWN_Msk (0x1UL << CSI_PCR_PWRDOWN_Pos) /*!< 0x00000001 */ +#define CSI_PCR_PWRDOWN CSI_PCR_PWRDOWN_Msk /*!< Virtual channel 3 start */ +#define CSI_PCR_CLEN_Pos (1UL) +#define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */ +#define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */ +#define CSI_PCR_DL0EN_Pos (2UL) +#define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */ +#define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */ +#define CSI_PCR_DL1EN_Pos (3UL) +#define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */ +#define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */ + +/***************** Bit definition for CSI_VC0CFGR1 register *****************/ +#define CSI_VC0CFGR1_ALLDT_Pos (0UL) +#define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC0CFGR1_DT0EN_Pos (1UL) +#define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC0CFGR1_DT1EN_Pos (2UL) +#define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC0CFGR1_DT2EN_Pos (3UL) +#define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC0CFGR1_DT3EN_Pos (4UL) +#define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC0CFGR1_DT4EN_Pos (5UL) +#define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC0CFGR1_DT5EN_Pos (6UL) +#define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC0CFGR1_DT6EN_Pos (7UL) +#define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC0CFGR1_CDTFT_Pos (8UL) +#define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC0CFGR1_DT0_Pos (16UL) +#define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC0CFGR1_DT0FT_Pos (24UL) +#define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC0CFGR2 register *****************/ +#define CSI_VC0CFGR2_DT1_Pos (0UL) +#define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT1FT_Pos (8UL) +#define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC0CFGR2_DT2_Pos (16UL) +#define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT2FT_Pos (24UL) +#define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC0CFGR3 register *****************/ +#define CSI_VC0CFGR3_DT3_Pos (0UL) +#define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT3FT_Pos (8UL) +#define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC0CFGR3_DT4_Pos (16UL) +#define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT4FT_Pos (24UL) +#define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC0CFGR4 register *****************/ +#define CSI_VC0CFGR4_DT5_Pos (0UL) +#define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT5FT_Pos (8UL) +#define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC0CFGR4_DT6_Pos (16UL) +#define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT6FT_Pos (24UL) +#define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC1CFGR1 register *****************/ +#define CSI_VC1CFGR1_ALLDT_Pos (0UL) +#define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC1CFGR1_DT0EN_Pos (1UL) +#define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC1CFGR1_DT1EN_Pos (2UL) +#define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC1CFGR1_DT2EN_Pos (3UL) +#define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC1CFGR1_DT3EN_Pos (4UL) +#define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC1CFGR1_DT4EN_Pos (5UL) +#define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC1CFGR1_DT5EN_Pos (6UL) +#define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC1CFGR1_DT6EN_Pos (7UL) +#define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC1CFGR1_CDTFT_Pos (8UL) +#define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC1CFGR1_DT0_Pos (16UL) +#define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC1CFGR1_DT0FT_Pos (24UL) +#define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC1CFGR2 register *****************/ +#define CSI_VC1CFGR2_DT1_Pos (0UL) +#define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT1FT_Pos (8UL) +#define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC1CFGR2_DT2_Pos (16UL) +#define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT2FT_Pos (24UL) +#define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC1CFGR3 register *****************/ +#define CSI_VC1CFGR3_DT3_Pos (0UL) +#define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT3FT_Pos (8UL) +#define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC1CFGR3_DT4_Pos (16UL) +#define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT4FT_Pos (24UL) +#define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC1CFGR4 register *****************/ +#define CSI_VC1CFGR4_DT5_Pos (0UL) +#define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT5FT_Pos (8UL) +#define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC1CFGR4_DT6_Pos (16UL) +#define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT6FT_Pos (24UL) +#define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC2CFGR1 register *****************/ +#define CSI_VC2CFGR1_ALLDT_Pos (0UL) +#define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC2CFGR1_DT0EN_Pos (1UL) +#define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC2CFGR1_DT1EN_Pos (2UL) +#define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC2CFGR1_DT2EN_Pos (3UL) +#define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC2CFGR1_DT3EN_Pos (4UL) +#define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC2CFGR1_DT4EN_Pos (5UL) +#define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC2CFGR1_DT5EN_Pos (6UL) +#define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC2CFGR1_DT6EN_Pos (7UL) +#define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC2CFGR1_CDTFT_Pos (8UL) +#define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC2CFGR1_DT0_Pos (16UL) +#define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC2CFGR1_DT0FT_Pos (24UL) +#define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC2CFGR2 register *****************/ +#define CSI_VC2CFGR2_DT1_Pos (0UL) +#define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT1FT_Pos (8UL) +#define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC2CFGR2_DT2_Pos (16UL) +#define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT2FT_Pos (24UL) +#define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC2CFGR3 register *****************/ +#define CSI_VC2CFGR3_DT3_Pos (0UL) +#define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT3FT_Pos (8UL) +#define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC2CFGR3_DT4_Pos (16UL) +#define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT4FT_Pos (24UL) +#define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC2CFGR4 register *****************/ +#define CSI_VC2CFGR4_DT5_Pos (0UL) +#define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT5FT_Pos (8UL) +#define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC2CFGR4_DT6_Pos (16UL) +#define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT6FT_Pos (24UL) +#define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC3CFGR1 register *****************/ +#define CSI_VC3CFGR1_ALLDT_Pos (0UL) +#define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC3CFGR1_DT0EN_Pos (1UL) +#define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC3CFGR1_DT1EN_Pos (2UL) +#define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC3CFGR1_DT2EN_Pos (3UL) +#define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC3CFGR1_DT3EN_Pos (4UL) +#define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC3CFGR1_DT4EN_Pos (5UL) +#define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC3CFGR1_DT5EN_Pos (6UL) +#define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC3CFGR1_DT6EN_Pos (7UL) +#define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC3CFGR1_CDTFT_Pos (8UL) +#define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC3CFGR1_DT0_Pos (16UL) +#define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC3CFGR1_DT0FT_Pos (24UL) +#define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC3CFGR2 register *****************/ +#define CSI_VC3CFGR2_DT1_Pos (0UL) +#define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT1FT_Pos (8UL) +#define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC3CFGR2_DT2_Pos (16UL) +#define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT2FT_Pos (24UL) +#define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC3CFGR3 register *****************/ +#define CSI_VC3CFGR3_DT3_Pos (0UL) +#define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT3FT_Pos (8UL) +#define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC3CFGR3_DT4_Pos (16UL) +#define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT4FT_Pos (24UL) +#define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC3CFGR4 register *****************/ +#define CSI_VC3CFGR4_DT5_Pos (0UL) +#define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT5FT_Pos (8UL) +#define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC3CFGR4_DT6_Pos (16UL) +#define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT6FT_Pos (24UL) +#define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_LB0CFGR register ******************/ +#define CSI_LB0CFGR_BYTECNT_Pos (0UL) +#define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB0CFGR_LINECNT_Pos (16UL) +#define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB1CFGR register ******************/ +#define CSI_LB1CFGR_BYTECNT_Pos (0UL) +#define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB1CFGR_LINECNT_Pos (16UL) +#define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB2CFGR register ******************/ +#define CSI_LB2CFGR_BYTECNT_Pos (0UL) +#define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB2CFGR_LINECNT_Pos (16UL) +#define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB3CFGR register ******************/ +#define CSI_LB3CFGR_BYTECNT_Pos (0UL) +#define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB3CFGR_LINECNT_Pos (16UL) +#define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_TIM0CFGR register *****************/ +#define CSI_TIM0CFGR_COUNT_Pos (0UL) +#define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM1CFGR register *****************/ +#define CSI_TIM1CFGR_COUNT_Pos (0UL) +#define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM2CFGR register *****************/ +#define CSI_TIM2CFGR_COUNT_Pos (0UL) +#define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM3CFGR register *****************/ +#define CSI_TIM3CFGR_COUNT_Pos (0UL) +#define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/****************** Bit definition for CSI_LMCFGR register ******************/ +#define CSI_LMCFGR_LANENB_Pos (8UL) +#define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */ +#define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */ +#define CSI_LMCFGR_DL0MAP_Pos (16UL) +#define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */ +#define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */ +#define CSI_LMCFGR_DL1MAP_Pos (20UL) +#define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */ +#define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */ + +/****************** Bit definition for CSI_PRGITR register ******************/ +#define CSI_PRGITR_LB0VC_Pos (0UL) +#define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */ +#define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */ +#define CSI_PRGITR_LB0EN_Pos (3UL) +#define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */ +#define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */ +#define CSI_PRGITR_LB1VC_Pos (4UL) +#define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */ +#define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */ +#define CSI_PRGITR_LB1EN_Pos (7UL) +#define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */ +#define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */ +#define CSI_PRGITR_LB2VC_Pos (8UL) +#define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */ +#define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */ +#define CSI_PRGITR_LB2EN_Pos (11UL) +#define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */ +#define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */ +#define CSI_PRGITR_LB3VC_Pos (12UL) +#define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */ +#define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */ +#define CSI_PRGITR_LB3EN_Pos (15UL) +#define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */ +#define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */ +#define CSI_PRGITR_TIM0VC_Pos (16UL) +#define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */ +#define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM0EOF_Pos (18UL) +#define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */ +#define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */ +#define CSI_PRGITR_TIM0EN_Pos (19UL) +#define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */ +#define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */ +#define CSI_PRGITR_TIM1VC_Pos (20UL) +#define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */ +#define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM1EOF_Pos (22UL) +#define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */ +#define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */ +#define CSI_PRGITR_TIM1EN_Pos (23UL) +#define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */ +#define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */ +#define CSI_PRGITR_TIM2VC_Pos (24UL) +#define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */ +#define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM2EOF_Pos (26UL) +#define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */ +#define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */ +#define CSI_PRGITR_TIM2EN_Pos (27UL) +#define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */ +#define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */ +#define CSI_PRGITR_TIM3VC_Pos (28UL) +#define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */ +#define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM3EOF_Pos (30UL) +#define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */ +#define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */ +#define CSI_PRGITR_TIM3EN_Pos (31UL) +#define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */ +#define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */ + +/******************* Bit definition for CSI_WDR register ********************/ +#define CSI_WDR_CNT_Pos (0UL) +#define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */ +#define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */ + +/******************* Bit definition for CSI_IER0 register *******************/ +#define CSI_IER0_LB0IE_Pos (0UL) +#define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */ +#define CSI_IER0_LB1IE_Pos (1UL) +#define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */ +#define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */ +#define CSI_IER0_LB2IE_Pos (2UL) +#define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */ +#define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */ +#define CSI_IER0_LB3IE_Pos (3UL) +#define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */ +#define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */ +#define CSI_IER0_TIM0IE_Pos (4UL) +#define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */ +#define CSI_IER0_TIM1IE_Pos (5UL) +#define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */ +#define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */ +#define CSI_IER0_TIM2IE_Pos (6UL) +#define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */ +#define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */ +#define CSI_IER0_TIM3IE_Pos (7UL) +#define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */ +#define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */ +#define CSI_IER0_SOF0IE_Pos (8UL) +#define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */ +#define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_SOF1IE_Pos (9UL) +#define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_SOF2IE_Pos (10UL) +#define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */ +#define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_SOF3IE_Pos (11UL) +#define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */ +#define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_EOF0IE_Pos (12UL) +#define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */ +#define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_EOF1IE_Pos (13UL) +#define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */ +#define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_EOF2IE_Pos (14UL) +#define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */ +#define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_EOF3IE_Pos (15UL) +#define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */ +#define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_SPKTIE_Pos (16UL) +#define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */ +#define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */ +#define CSI_IER0_CCFIFOFIE_Pos (21UL) +#define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */ +#define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */ +#define CSI_IER0_CRCERRIE_Pos (24UL) +#define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */ +#define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */ +#define CSI_IER0_ECCERRIE_Pos (25UL) +#define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */ +#define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */ +#define CSI_IER0_CECCERRIE_Pos (26UL) +#define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */ +#define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */ +#define CSI_IER0_IDERRIE_Pos (27UL) +#define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */ +#define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */ +#define CSI_IER0_SPKTERRIE_Pos (28UL) +#define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */ +#define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */ +#define CSI_IER0_WDERRIE_Pos (29UL) +#define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */ +#define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */ +#define CSI_IER0_SYNCERRIE_Pos (30UL) +#define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */ +#define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */ + +/******************* Bit definition for CSI_IER1 register *******************/ +#define CSI_IER1_ESOTDL0IE_Pos (0UL) +#define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */ +#define CSI_IER1_ESOTSYNCDL0IE_Pos (1UL) +#define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */ +#define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */ +#define CSI_IER1_EESCDL0IE_Pos (2UL) +#define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */ +#define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL0IE_Pos (3UL) +#define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */ +#define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL0IE_Pos (4UL) +#define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */ +#define CSI_IER1_ESOTDL1IE_Pos (8UL) +#define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */ +#define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */ +#define CSI_IER1_ESOTSYNCDL1IE_Pos (9UL) +#define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */ +#define CSI_IER1_EESCDL1IE_Pos (10UL) +#define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */ +#define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL1IE_Pos (11UL) +#define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */ +#define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL1IE_Pos (12UL) +#define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */ +#define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */ + +/******************* Bit definition for CSI_SR0 register ********************/ +#define CSI_SR0_LB0F_Pos (0UL) +#define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */ +#define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */ +#define CSI_SR0_LB1F_Pos (1UL) +#define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */ +#define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */ +#define CSI_SR0_LB2F_Pos (2UL) +#define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */ +#define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */ +#define CSI_SR0_LB3F_Pos (3UL) +#define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */ +#define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */ +#define CSI_SR0_TIM0F_Pos (4UL) +#define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */ +#define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */ +#define CSI_SR0_TIM1F_Pos (5UL) +#define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */ +#define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */ +#define CSI_SR0_TIM2F_Pos (6UL) +#define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */ +#define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */ +#define CSI_SR0_TIM3F_Pos (7UL) +#define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */ +#define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */ +#define CSI_SR0_SOF0F_Pos (8UL) +#define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */ +#define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */ +#define CSI_SR0_SOF1F_Pos (9UL) +#define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */ +#define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */ +#define CSI_SR0_SOF2F_Pos (10UL) +#define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */ +#define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */ +#define CSI_SR0_SOF3F_Pos (11UL) +#define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */ +#define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */ +#define CSI_SR0_EOF0F_Pos (12UL) +#define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */ +#define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */ +#define CSI_SR0_EOF1F_Pos (13UL) +#define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */ +#define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */ +#define CSI_SR0_EOF2F_Pos (14UL) +#define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */ +#define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */ +#define CSI_SR0_EOF3F_Pos (15UL) +#define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */ +#define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */ +#define CSI_SR0_SPKTF_Pos (16UL) +#define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */ +#define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */ +#define CSI_SR0_VC0STATEF_Pos (17UL) +#define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */ +#define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */ +#define CSI_SR0_VC1STATEF_Pos (18UL) +#define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */ +#define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */ +#define CSI_SR0_VC2STATEF_Pos (19UL) +#define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */ +#define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */ +#define CSI_SR0_VC3STATEF_Pos (20UL) +#define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */ +#define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */ +#define CSI_SR0_CCFIFOFF_Pos (21UL) +#define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */ +#define CSI_SR0_CRCERRF_Pos (24UL) +#define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */ +#define CSI_SR0_ECCERRF_Pos (25UL) +#define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */ +#define CSI_SR0_CECCERRF_Pos (26UL) +#define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */ +#define CSI_SR0_IDERRF_Pos (27UL) +#define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */ +#define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */ +#define CSI_SR0_SPKTERRF_Pos (28UL) +#define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */ +#define CSI_SR0_WDERRF_Pos (29UL) +#define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */ +#define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */ +#define CSI_SR0_SYNCERRF_Pos (30UL) +#define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */ + +/******************* Bit definition for CSI_SR1 register ********************/ +#define CSI_SR1_ESOTDL0F_Pos (0UL) +#define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */ +#define CSI_SR1_ESOTSYNCDL0F_Pos (1UL) +#define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */ +#define CSI_SR1_EESCDL0F_Pos (2UL) +#define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL0F_Pos (3UL) +#define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL0F_Pos (4UL) +#define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */ +#define CSI_SR1_ESOTDL1F_Pos (8UL) +#define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */ +#define CSI_SR1_ESOTSYNCDL1F_Pos (9UL) +#define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */ +#define CSI_SR1_EESCDL1F_Pos (10UL) +#define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL1F_Pos (11UL) +#define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL1F_Pos (12UL) +#define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */ +#define CSI_SR1_ACTDL0F_Pos (16UL) +#define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */ +#define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */ +#define CSI_SR1_SYNCDL0F_Pos (17UL) +#define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */ +#define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */ +#define CSI_SR1_SKCALDL0F_Pos (18UL) +#define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */ +#define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */ +#define CSI_SR1_STOPDL0F_Pos (19UL) +#define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */ +#define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */ +#define CSI_SR1_ULPNDL0F_Pos (20UL) +#define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */ +#define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */ +#define CSI_SR1_ACTDL1F_Pos (22UL) +#define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */ +#define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */ +#define CSI_SR1_SYNCDL1F_Pos (23UL) +#define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */ +#define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */ +#define CSI_SR1_SKCALDL1F_Pos (24UL) +#define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */ +#define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */ +#define CSI_SR1_STOPDL1F_Pos (25UL) +#define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */ +#define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */ +#define CSI_SR1_ULPNDL1F_Pos (26UL) +#define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */ +#define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */ +#define CSI_SR1_STOPCLF_Pos (28UL) +#define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */ +#define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */ +#define CSI_SR1_ULPNACTF_Pos (29UL) +#define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */ +#define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */ +#define CSI_SR1_ULPNCLF_Pos (30UL) +#define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */ +#define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */ +#define CSI_SR1_ACTCLF_Pos (31UL) +#define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */ +#define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */ + +/******************* Bit definition for CSI_FCR0 register *******************/ +#define CSI_FCR0_CLB0F_Pos (0UL) +#define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */ +#define CSI_FCR0_CLB1F_Pos (1UL) +#define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */ +#define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */ +#define CSI_FCR0_CLB2F_Pos (2UL) +#define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */ +#define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */ +#define CSI_FCR0_CLB3F_Pos (3UL) +#define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */ +#define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */ +#define CSI_FCR0_CTIM0F_Pos (4UL) +#define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */ +#define CSI_FCR0_CTIM1F_Pos (5UL) +#define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */ +#define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */ +#define CSI_FCR0_CTIM2F_Pos (6UL) +#define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */ +#define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */ +#define CSI_FCR0_CTIM3F_Pos (7UL) +#define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */ +#define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */ +#define CSI_FCR0_CSOF0F_Pos (8UL) +#define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */ +#define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */ +#define CSI_FCR0_CSOF1F_Pos (9UL) +#define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */ +#define CSI_FCR0_CSOF2F_Pos (10UL) +#define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */ +#define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */ +#define CSI_FCR0_CSOF3F_Pos (11UL) +#define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */ +#define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */ +#define CSI_FCR0_CEOF0F_Pos (12UL) +#define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */ +#define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */ +#define CSI_FCR0_CEOF1F_Pos (13UL) +#define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */ +#define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */ +#define CSI_FCR0_CEOF2F_Pos (14UL) +#define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */ +#define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */ +#define CSI_FCR0_CEOF3F_Pos (15UL) +#define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */ +#define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */ +#define CSI_FCR0_CSPKTF_Pos (16UL) +#define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */ +#define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */ +#define CSI_FCR0_CCCFIFOFF_Pos (21UL) +#define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */ +#define CSI_FCR0_CCRCERRF_Pos (24UL) +#define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */ +#define CSI_FCR0_CECCERRF_Pos (25UL) +#define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */ +#define CSI_FCR0_CCECCERRF_Pos (26UL) +#define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */ +#define CSI_FCR0_CIDERRF_Pos (27UL) +#define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */ +#define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */ +#define CSI_FCR0_CSPKTERRF_Pos (28UL) +#define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */ +#define CSI_FCR0_CWDERRF_Pos (29UL) +#define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */ +#define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */ +#define CSI_FCR0_CSYNCERRF_Pos (30UL) +#define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */ + +/******************* Bit definition for CSI_FCR1 register *******************/ +#define CSI_FCR1_CESOTDL0F_Pos (0UL) +#define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */ +#define CSI_FCR1_CESOTSYNCDL0F_Pos (1UL) +#define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */ +#define CSI_FCR1_CEESCDL0F_Pos (2UL) +#define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL0F_Pos (3UL) +#define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL0F_Pos (4UL) +#define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */ +#define CSI_FCR1_CESOTDL1F_Pos (8UL) +#define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */ +#define CSI_FCR1_CESOTSYNCDL1F_Pos (9UL) +#define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */ +#define CSI_FCR1_CEESCDL1F_Pos (10UL) +#define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL1F_Pos (11UL) +#define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL1F_Pos (12UL) +#define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */ + +/****************** Bit definition for CSI_SPDFR register *******************/ +#define CSI_SPDFR_DATAFIELD_Pos (0UL) +#define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */ +#define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */ +#define CSI_SPDFR_DATATYPE_Pos (16UL) +#define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */ +#define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */ +#define CSI_SPDFR_VCHANNEL_Pos (22UL) +#define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */ +#define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */ + +/******************* Bit definition for CSI_ERR1 register *******************/ +#define CSI_ERR1_CRCDTERR_Pos (0UL) +#define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */ +#define CSI_ERR1_CRCVCERR_Pos (6UL) +#define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */ +#define CSI_ERR1_CECCDTERR_Pos (8UL) +#define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */ +#define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */ +#define CSI_ERR1_CECCVCERR_Pos (14UL) +#define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */ +#define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */ +#define CSI_ERR1_IDDTERR_Pos (16UL) +#define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */ +#define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */ +#define CSI_ERR1_IDVCERR_Pos (22UL) +#define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */ +#define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */ + +/******************* Bit definition for CSI_ERR2 register *******************/ +#define CSI_ERR2_SPKTDTERR_Pos (0UL) +#define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */ +#define CSI_ERR2_SPKTVCERR_Pos (6UL) +#define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */ +#define CSI_ERR2_WDVCERR_Pos (16UL) +#define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */ +#define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */ +#define CSI_ERR2_SYNCVCERR_Pos (18UL) +#define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */ +#define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */ + +/******************* Bit definition for CSI_PRCR register *******************/ +#define CSI_PRCR_PEN_Pos (1UL) +#define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */ +#define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */ + +/******************* Bit definition for CSI_PMCR register *******************/ +#define CSI_PMCR_FRXMDL0_Pos (0UL) +#define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */ +#define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */ +#define CSI_PMCR_FRXMDL1_Pos (1UL) +#define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */ +#define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */ +#define CSI_PMCR_FTXSMDL0_Pos (2UL) +#define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */ +#define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */ +#define CSI_PMCR_DTDL_Pos (4UL) +#define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */ +#define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */ +#define CSI_PMCR_RTDL0_Pos (8UL) +#define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */ +#define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */ +#define CSI_PMCR_TUESDL0_Pos (12UL) +#define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */ +#define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */ +#define CSI_PMCR_TUEXDL0_Pos (16UL) +#define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */ +#define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */ + +/******************* Bit definition for CSI_PFCR register *******************/ +#define CSI_PFCR_CCFR_Pos (0UL) +#define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */ +#define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */ +#define CSI_PFCR_HSFR_Pos (8UL) +#define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */ +#define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */ +#define CSI_PFCR_DLD_Pos (16UL) +#define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */ +#define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */ + +/****************** Bit definition for CSI_PTCR0 register *******************/ +#define CSI_PTCR0_TCKEN_Pos (0UL) +#define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */ +#define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */ +#define CSI_PTCR0_TRSEN_Pos (1UL) +#define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */ +#define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */ + +/****************** Bit definition for CSI_PTCR1 register *******************/ +#define CSI_PTCR1_TDI_Pos (0UL) +#define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */ +#define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */ +#define CSI_PTCR1_TWM_Pos (16UL) +#define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */ +#define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */ + +/******************* Bit definition for CSI_PTSR register *******************/ +#define CSI_PTSR_TDO_Pos (0UL) +#define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */ +#define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */ + + +/*********************************************************************************/ +/* */ +/* DBGMCU */ +/* */ +/*********************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register ****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */ +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */ + +/******************** Bit definition for DBGMCU_CR register ********************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0UL) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1UL) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2UL) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */ +#define DBGMCU_CR_DBGCLKEN_Pos (20UL) +#define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */ +#define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */ +#define DBGMCU_CR_TRACECLKEN_Pos (21UL) +#define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */ +#define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */ +#define DBGMCU_CR_DBTRGOEN_Pos (28UL) +#define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */ +#define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */ +#define DBGMCU_CR_HLT_TSGEN_EN_Pos (31UL) +#define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */ +#define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */ + +/******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0UL) +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1UL) +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2UL) +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3UL) +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4UL) +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5UL) +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6UL) +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7UL) +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8UL) +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9UL) +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11UL) +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12UL) +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13UL) +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21UL) +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22UL) +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23UL) +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24UL) +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25UL) +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */ + +/******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8UL) +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */ + +/******************** Bit definition for DBGMCU_APB2FZ1 register ***************/ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0UL) +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1UL) +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15UL) +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16UL) +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17UL) +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18UL) +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19UL) +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */ + +/******************** Bit definition for DBGMCU_APB4FZ1 register ***************/ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8UL) +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16UL) +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18UL) +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */ + +/******************** Bit definition for DBGMCU_APB5FZ1 register ***************/ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4UL) +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */ + +/******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_SR register ***************/ +#define DBGMCU_SR_AP0_PRESENT_Pos (0UL) +#define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */ +#define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */ +#define DBGMCU_SR_AP1_PRESENT_Pos (1UL) +#define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */ +#define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */ +#define DBGMCU_SR_AP0_ENABLE_Pos (16UL) +#define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */ +#define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */ +#define DBGMCU_SR_AP1_ENABLE_Pos (17UL) +#define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */ +#define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */ + +/******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0UL) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1UL) +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */ + + +/******************************************************************************/ +/* */ +/* DCMI */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DCMI_CR register ******************/ +#define DCMI_CR_CAPTURE_Pos (0UL) +#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ +#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk +#define DCMI_CR_CM_Pos (1UL) +#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ +#define DCMI_CR_CM DCMI_CR_CM_Msk +#define DCMI_CR_CROP_Pos (2UL) +#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ +#define DCMI_CR_CROP DCMI_CR_CROP_Msk +#define DCMI_CR_JPEG_Pos (3UL) +#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ +#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk +#define DCMI_CR_ESS_Pos (4UL) +#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ +#define DCMI_CR_ESS DCMI_CR_ESS_Msk +#define DCMI_CR_PCKPOL_Pos (5UL) +#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk +#define DCMI_CR_HSPOL_Pos (6UL) +#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk +#define DCMI_CR_VSPOL_Pos (7UL) +#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk +#define DCMI_CR_FCRC_Pos (8UL) +#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ +#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ +#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ +#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ +#define DCMI_CR_EDM_Pos (10UL) +#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ +#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ +#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ +#define DCMI_CR_ENABLE_Pos (14UL) +#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk +#define DCMI_CR_BSM_Pos (16UL) +#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ +#define DCMI_CR_BSM DCMI_CR_BSM_Msk +#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ +#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ +#define DCMI_CR_OEBS_Pos (18UL) +#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ +#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk +#define DCMI_CR_LSM_Pos (19UL) +#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ +#define DCMI_CR_LSM DCMI_CR_LSM_Msk +#define DCMI_CR_OELS_Pos (20UL) +#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ +#define DCMI_CR_OELS DCMI_CR_OELS_Msk +#define DCMI_CR_PSDM_Pos (31UL) +#define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */ +#define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ + +/******************** Bits definition for DCMI_SR register ******************/ +#define DCMI_SR_HSYNC_Pos (0UL) +#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ +#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk +#define DCMI_SR_VSYNC_Pos (1UL) +#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ +#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk +#define DCMI_SR_FNE_Pos (2UL) +#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ +#define DCMI_SR_FNE DCMI_SR_FNE_Msk + +/******************** Bits definition for DCMI_RIS register ****************/ +#define DCMI_RIS_FRAME_RIS_Pos (0UL) +#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ +#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk +#define DCMI_RIS_OVR_RIS_Pos (1UL) +#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk +#define DCMI_RIS_ERR_RIS_Pos (2UL) +#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ +#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk +#define DCMI_RIS_VSYNC_RIS_Pos (3UL) +#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ +#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk +#define DCMI_RIS_LINE_RIS_Pos (4UL) +#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ +#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk + +/******************** Bits definition for DCMI_IER register *****************/ +#define DCMI_IER_FRAME_IE_Pos (0UL) +#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ +#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk +#define DCMI_IER_OVR_IE_Pos (1UL) +#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk +#define DCMI_IER_ERR_IE_Pos (2UL) +#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ +#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk +#define DCMI_IER_VSYNC_IE_Pos (3UL) +#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ +#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk +#define DCMI_IER_LINE_IE_Pos (4UL) +#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ +#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk + +/******************** Bits definition for DCMI_MIS register *****************/ +#define DCMI_MIS_FRAME_MIS_Pos (0UL) +#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ +#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk +#define DCMI_MIS_OVR_MIS_Pos (1UL) +#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk +#define DCMI_MIS_ERR_MIS_Pos (2UL) +#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ +#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk +#define DCMI_MIS_VSYNC_MIS_Pos (3UL) +#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ +#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk +#define DCMI_MIS_LINE_MIS_Pos (4UL) +#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ +#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk + +/******************** Bits definition for DCMI_ICR register *****************/ +#define DCMI_ICR_FRAME_ISC_Pos (0UL) +#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ +#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk +#define DCMI_ICR_OVR_ISC_Pos (1UL) +#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk +#define DCMI_ICR_ERR_ISC_Pos (2UL) +#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ +#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk +#define DCMI_ICR_VSYNC_ISC_Pos (3UL) +#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ +#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk +#define DCMI_ICR_LINE_ISC_Pos (4UL) +#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ +#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk + +/******************** Bits definition for DCMI_ESCR register ******************/ +#define DCMI_ESCR_FSC_Pos (0UL) +#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk +#define DCMI_ESCR_LSC_Pos (8UL) +#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk +#define DCMI_ESCR_LEC_Pos (16UL) +#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk +#define DCMI_ESCR_FEC_Pos (24UL) +#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk + +/******************** Bits definition for DCMI_ESUR register ******************/ +#define DCMI_ESUR_FSU_Pos (0UL) +#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk +#define DCMI_ESUR_LSU_Pos (8UL) +#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk +#define DCMI_ESUR_LEU_Pos (16UL) +#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk +#define DCMI_ESUR_FEU_Pos (24UL) +#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk + +/******************** Bits definition for DCMI_CWSTRT register ******************/ +#define DCMI_CWSTRT_HOFFCNT_Pos (0UL) +#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk +#define DCMI_CWSTRT_VST_Pos (16UL) +#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ +#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk + +/******************** Bits definition for DCMI_CWSIZE register ******************/ +#define DCMI_CWSIZE_CAPCNT_Pos (0UL) +#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk +#define DCMI_CWSIZE_VLINE_Pos (16UL) +#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ +#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk + +/******************** Bits definition for DCMI_DR register ******************/ +#define DCMI_DR_BYTE0_Pos (0UL) +#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ +#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk +#define DCMI_DR_BYTE1_Pos (8UL) +#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ +#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk +#define DCMI_DR_BYTE2_Pos (16UL) +#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ +#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk +#define DCMI_DR_BYTE3_Pos (24UL) +#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ +#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk + + +/******************************************************************************/ +/* */ +/* DCMIPP */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DCMIPP_IPGR1 register *****************/ +#define DCMIPP_IPGR1_MEMORYPAGE_Pos (0UL) +#define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */ +#define DCMIPP_IPGR1_QOS_MODE_Pos (24UL) +#define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */ +#define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */ + +/***************** Bit definition for DCMIPP_IPGR2 register *****************/ +#define DCMIPP_IPGR2_PSTART_Pos (0UL) +#define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */ + +/***************** Bit definition for DCMIPP_IPGR3 register *****************/ +#define DCMIPP_IPGR3_IDLE_Pos (0UL) +#define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */ + +/***************** Bit definition for DCMIPP_IPGR8 register *****************/ +#define DCMIPP_IPGR8_DID_Pos (0UL) +#define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */ +#define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */ +#define DCMIPP_IPGR8_REVID_Pos (8UL) +#define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */ +#define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */ +#define DCMIPP_IPGR8_ARCHIID_Pos (16UL) +#define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */ +#define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */ +#define DCMIPP_IPGR8_IPPID_Pos (24UL) +#define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */ +#define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */ + +/**************** Bit definition for DCMIPP_IPC1R1 register *****************/ +#define DCMIPP_IPC1R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC1R1_OTR_Pos (8UL) +#define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC1R2 register *****************/ +#define DCMIPP_IPC1R2_WLRU_Pos (16UL) +#define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC1R3 register *****************/ +#define DCMIPP_IPC1R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC1R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC2R1 register *****************/ +#define DCMIPP_IPC2R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC2R1_OTR_Pos (8UL) +#define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC2R2 register *****************/ +#define DCMIPP_IPC2R2_WLRU_Pos (16UL) +#define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC2R3 register *****************/ +#define DCMIPP_IPC2R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC2R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC3R1 register *****************/ +#define DCMIPP_IPC3R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC3R1_OTR_Pos (8UL) +#define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC3R2 register *****************/ +#define DCMIPP_IPC3R2_WLRU_Pos (16UL) +#define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC3R3 register *****************/ +#define DCMIPP_IPC3R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC3R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC4R1 register *****************/ +#define DCMIPP_IPC4R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC4R1_OTR_Pos (8UL) +#define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC4R2 register *****************/ +#define DCMIPP_IPC4R2_WLRU_Pos (16UL) +#define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC4R3 register *****************/ +#define DCMIPP_IPC4R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC4R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC5R1 register *****************/ +#define DCMIPP_IPC5R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC5R1_OTR_Pos (8UL) +#define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC5R2 register *****************/ +#define DCMIPP_IPC5R2_WLRU_Pos (16UL) +#define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC5R3 register *****************/ +#define DCMIPP_IPC5R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC5R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/*************** Bit definition for DCMIPP_PRHWCFGR register ****************/ + +/***************** Bit definition for DCMIPP_PRCR register ******************/ +#define DCMIPP_PRCR_ESS_Pos (4UL) +#define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */ +#define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */ +#define DCMIPP_PRCR_PCKPOL_Pos (5UL) +#define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */ +#define DCMIPP_PRCR_HSPOL_Pos (6UL) +#define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */ +#define DCMIPP_PRCR_VSPOL_Pos (7UL) +#define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */ +#define DCMIPP_PRCR_EDM_Pos (10UL) +#define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */ +#define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */ +#define DCMIPP_PRCR_ENABLE_Pos (14UL) +#define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */ +#define DCMIPP_PRCR_FORMAT_Pos (16UL) +#define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */ +#define DCMIPP_PRCR_SWAPCYCLES_Pos (25UL) +#define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */ +#define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */ +#define DCMIPP_PRCR_SWAPBITS_Pos (26UL) +#define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */ +#define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */ + +/**************** Bit definition for DCMIPP_PRESCR register *****************/ +#define DCMIPP_PRESCR_FSC_Pos (0UL) +#define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */ +#define DCMIPP_PRESCR_LSC_Pos (8UL) +#define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */ +#define DCMIPP_PRESCR_LEC_Pos (16UL) +#define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */ +#define DCMIPP_PRESCR_FEC_Pos (24UL) +#define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */ + +/**************** Bit definition for DCMIPP_PRESUR register *****************/ +#define DCMIPP_PRESUR_FSU_Pos (0UL) +#define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */ +#define DCMIPP_PRESUR_LSU_Pos (8UL) +#define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */ +#define DCMIPP_PRESUR_LEU_Pos (16UL) +#define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */ +#define DCMIPP_PRESUR_FEU_Pos (24UL) +#define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */ + +/***************** Bit definition for DCMIPP_PRIER register *****************/ +#define DCMIPP_PRIER_ERRIE_Pos (6UL) +#define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */ + +/***************** Bit definition for DCMIPP_PRSR register ******************/ +#define DCMIPP_PRSR_ERRF_Pos (6UL) +#define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */ +#define DCMIPP_PRSR_HSYNC_Pos (16UL) +#define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */ +#define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */ +#define DCMIPP_PRSR_VSYNC_Pos (17UL) +#define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */ +#define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */ + +/***************** Bit definition for DCMIPP_PRFCR register *****************/ +#define DCMIPP_PRFCR_CERRF_Pos (6UL) +#define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */ + +/***************** Bit definition for DCMIPP_CMCR register ******************/ +#define DCMIPP_CMCR_INSEL_Pos (0UL) +#define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */ +#define DCMIPP_CMCR_PSFC_Pos (1UL) +#define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */ +#define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */ +#define DCMIPP_CMCR_CFC_Pos (4UL) +#define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */ +#define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */ +#define DCMIPP_CMCR_SWAPRB_Pos (7UL) +#define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */ +#define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */ + +/**************** Bit definition for DCMIPP_CMFRCR register *****************/ +#define DCMIPP_CMFRCR_FRMCNT_Pos (0UL) +#define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */ + +/***************** Bit definition for DCMIPP_CMIER register *****************/ +#define DCMIPP_CMIER_ATXERRIE_Pos (5UL) +#define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */ +#define DCMIPP_CMIER_PRERRIE_Pos (6UL) +#define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */ +#define DCMIPP_CMIER_P0LINEIE_Pos (8UL) +#define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0FRAMEIE_Pos (9UL) +#define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0VSYNCIE_Pos (10UL) +#define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0LIMITIE_Pos (14UL) +#define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0OVRIE_Pos (15UL) +#define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P1LINEIE_Pos (16UL) +#define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */ +#define DCMIPP_CMIER_P1FRAMEIE_Pos (17UL) +#define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1VSYNCIE_Pos (18UL) +#define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1OVRIE_Pos (23UL) +#define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P2LINEIE_Pos (24UL) +#define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2FRAMEIE_Pos (25UL) +#define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2VSYNCIE_Pos (26UL) +#define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2OVRIE_Pos (31UL) +#define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR1 register *****************/ +#define DCMIPP_CMSR1_PRHSYNC_Pos (0UL) +#define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_PRVSYNC_Pos (1UL) +#define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */ +#define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_P0LSTLINE_Pos (8UL) +#define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0LSTFRM_Pos (9UL) +#define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0CPTACT_Pos (15UL) +#define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */ +#define DCMIPP_CMSR1_P1LSTLINE_Pos (16UL) +#define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1LSTFRM_Pos (17UL) +#define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1CPTACT_Pos (23UL) +#define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */ +#define DCMIPP_CMSR1_P2LSTLINE_Pos (24UL) +#define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2LSTFRM_Pos (25UL) +#define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2CPTACT_Pos (31UL) +#define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR2 register *****************/ +#define DCMIPP_CMSR2_ATXERRF_Pos (5UL) +#define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */ +#define DCMIPP_CMSR2_PRERRF_Pos (6UL) +#define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */ +#define DCMIPP_CMSR2_P0LINEF_Pos (8UL) +#define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0FRAMEF_Pos (9UL) +#define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0VSYNCF_Pos (10UL) +#define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0LIMITF_Pos (14UL) +#define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0OVRF_Pos (15UL) +#define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P1LINEF_Pos (16UL) +#define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1FRAMEF_Pos (17UL) +#define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1VSYNCF_Pos (18UL) +#define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1OVRF_Pos (23UL) +#define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P2LINEF_Pos (24UL) +#define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2FRAMEF_Pos (25UL) +#define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2VSYNCF_Pos (26UL) +#define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2OVRF_Pos (31UL) +#define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMFCR register *****************/ +#define DCMIPP_CMFCR_CATXERRF_Pos (5UL) +#define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */ +#define DCMIPP_CMFCR_CPRERRF_Pos (6UL) +#define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */ +#define DCMIPP_CMFCR_CP0LINEF_Pos (8UL) +#define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0FRAMEF_Pos (9UL) +#define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0VSYNCF_Pos (10UL) +#define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP0LIMITF_Pos (14UL) +#define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_CMFCR_CP0OVRF_Pos (15UL) +#define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP1LINEF_Pos (16UL) +#define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1FRAMEF_Pos (17UL) +#define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1VSYNCF_Pos (18UL) +#define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP1OVRF_Pos (23UL) +#define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP2LINEF_Pos (24UL) +#define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2FRAMEF_Pos (25UL) +#define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2VSYNCF_Pos (26UL) +#define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP2OVRF_Pos (31UL) +#define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0FSCR register *****************/ +#define DCMIPP_P0FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */ +#define DCMIPP_P0FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */ +#define DCMIPP_P0FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_VC_Pos (19UL) +#define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P0FCTCR register ****************/ +#define DCMIPP_P0FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P0SCSTR register ****************/ +#define DCMIPP_P0SCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0SCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P0SCSZR register ****************/ +#define DCMIPP_P0SCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0SCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0SCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */ +#define DCMIPP_P0SCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */ + +/*************** Bit definition for DCMIPP_P0DCCNTR register ****************/ +#define DCMIPP_P0DCCNTR_CNT_Pos (0UL) +#define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */ +#define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */ + +/*************** Bit definition for DCMIPP_P0DCLMTR register ****************/ +#define DCMIPP_P0DCLMTR_LIMIT_Pos (0UL) +#define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */ +#define DCMIPP_P0DCLMTR_ENABLE_Pos (31UL) +#define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P0PPCR register *****************/ +#define DCMIPP_P0PPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0PPCR_PAD_Pos (5UL) +#define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0PPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */ +#define DCMIPP_P0PPCR_BSM_Pos (7UL) +#define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */ +#define DCMIPP_P0PPCR_OEBS_Pos (9UL) +#define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */ +#define DCMIPP_P0PPCR_LSM_Pos (10UL) +#define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */ +#define DCMIPP_P0PPCR_OELS_Pos (11UL) +#define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */ +#define DCMIPP_P0PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0PPCR_DBM_Pos (16UL) +#define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */ + +/*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/ +#define DCMIPP_P0PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/ +#define DCMIPP_P0PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */ + +/***************** Bit definition for DCMIPP_P0IER register *****************/ +#define DCMIPP_P0IER_LINEIE_Pos (0UL) +#define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P0IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P0IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P0IER_LIMITIE_Pos (6UL) +#define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */ +#define DCMIPP_P0IER_OVRIE_Pos (7UL) +#define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P0SR register ******************/ +#define DCMIPP_P0SR_LINEF_Pos (0UL) +#define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P0SR_FRAMEF_Pos (1UL) +#define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P0SR_VSYNCF_Pos (2UL) +#define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P0SR_LIMITF_Pos (6UL) +#define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */ +#define DCMIPP_P0SR_OVRF_Pos (7UL) +#define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P0SR_LSTLINE_Pos (16UL) +#define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_LSTFRM_Pos (17UL) +#define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_CPTACT_Pos (23UL) +#define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P0FCR register *****************/ +#define DCMIPP_P0FCR_CLINEF_Pos (0UL) +#define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P0FCR_CLIMITF_Pos (6UL) +#define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_P0FCR_COVRF_Pos (7UL) +#define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0CFSCR register ****************/ +#define DCMIPP_P0CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */ +#define DCMIPP_P0CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */ +#define DCMIPP_P0CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0CFSCR_VC_Pos (19UL) +#define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P0CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P0CFCTCR register ****************/ +#define DCMIPP_P0CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P0CSCSTR register ****************/ +#define DCMIPP_P0CSCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0CSCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P0CSCSZR register ****************/ +#define DCMIPP_P0CSCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0CSCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0CSCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */ +#define DCMIPP_P0CSCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */ + +/**************** Bit definition for DCMIPP_P0CPPCR register ****************/ +#define DCMIPP_P0CPPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0CPPCR_PAD_Pos (5UL) +#define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0CPPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */ +#define DCMIPP_P0CPPCR_BSM_Pos (7UL) +#define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */ +#define DCMIPP_P0CPPCR_OEBS_Pos (9UL) +#define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */ +#define DCMIPP_P0CPPCR_LSM_Pos (10UL) +#define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */ +#define DCMIPP_P0CPPCR_OELS_Pos (11UL) +#define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */ +#define DCMIPP_P0CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0CPPCR_DBM_Pos (16UL) +#define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */ + +/************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/ +#define DCMIPP_P0CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/**************** Bit definition for DCMIPP_P1FSCR register *****************/ +#define DCMIPP_P1FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */ +#define DCMIPP_P1FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */ +#define DCMIPP_P1FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */ +#define DCMIPP_P1FSCR_VC_Pos (19UL) +#define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_FDTF_Pos (24UL) +#define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P1FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P1FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P1SRCR register *****************/ +#define DCMIPP_P1SRCR_LASTLINE_Pos (0UL) +#define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12UL) +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */ +#define DCMIPP_P1SRCR_CROPEN_Pos (15UL) +#define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */ +#define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */ + +/**************** Bit definition for DCMIPP_P1BPRCR register ****************/ +#define DCMIPP_P1BPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */ +#define DCMIPP_P1BPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */ + +/**************** Bit definition for DCMIPP_P1BPRSR register ****************/ +#define DCMIPP_P1BPRSR_BADCNT_Pos (0UL) +#define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */ + +/**************** Bit definition for DCMIPP_P1DECR register *****************/ +#define DCMIPP_P1DECR_ENABLE_Pos (0UL) +#define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DECR_HDEC_Pos (1UL) +#define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DECR_VDEC_Pos (3UL) +#define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1BLCCR register ****************/ +#define DCMIPP_P1BLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */ +#define DCMIPP_P1BLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */ +#define DCMIPP_P1BLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */ +#define DCMIPP_P1BLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR1 register ****************/ +#define DCMIPP_P1EXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */ +#define DCMIPP_P1EXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */ +#define DCMIPP_P1EXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR2 register ****************/ +#define DCMIPP_P1EXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */ +#define DCMIPP_P1EXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */ +#define DCMIPP_P1EXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */ +#define DCMIPP_P1EXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */ + +/**************** Bit definition for DCMIPP_P1ST1CR register ****************/ +#define DCMIPP_P1ST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST1CR_BINS_Pos (2UL) +#define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST1CR_SRC_Pos (4UL) +#define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST1CR_MODE_Pos (7UL) +#define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST2CR register ****************/ +#define DCMIPP_P1ST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST2CR_BINS_Pos (2UL) +#define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST2CR_SRC_Pos (4UL) +#define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST2CR_MODE_Pos (7UL) +#define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST3CR register ****************/ +#define DCMIPP_P1ST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST3CR_BINS_Pos (2UL) +#define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST3CR_SRC_Pos (4UL) +#define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST3CR_MODE_Pos (7UL) +#define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1STSTR register ****************/ +#define DCMIPP_P1STSTR_HSTART_Pos (0UL) +#define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSTR_VSTART_Pos (16UL) +#define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1STSZR register ****************/ +#define DCMIPP_P1STSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1STSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1ST1SR register ****************/ +#define DCMIPP_P1ST1SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST2SR register ****************/ +#define DCMIPP_P1ST2SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST3SR register ****************/ +#define DCMIPP_P1ST3SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1DMCR register *****************/ +#define DCMIPP_P1DMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DMCR_TYPE_Pos (1UL) +#define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */ +#define DCMIPP_P1DMCR_PEAK_Pos (16UL) +#define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */ +#define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */ +#define DCMIPP_P1DMCR_LINEV_Pos (20UL) +#define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */ +#define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */ +#define DCMIPP_P1DMCR_LINEH_Pos (24UL) +#define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */ +#define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */ +#define DCMIPP_P1DMCR_EDGE_Pos (28UL) +#define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */ + +/**************** Bit definition for DCMIPP_P1CCCR register *****************/ +#define DCMIPP_P1CCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/**************** Bit definition for DCMIPP_P1CCRR1 register ****************/ +#define DCMIPP_P1CCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCRR2 register ****************/ +#define DCMIPP_P1CCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCGR1 register ****************/ +#define DCMIPP_P1CCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCGR2 register ****************/ +#define DCMIPP_P1CCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCBR1 register ****************/ +#define DCMIPP_P1CCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCBR2 register ****************/ +#define DCMIPP_P1CCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CTCR1 register ****************/ +#define DCMIPP_P1CTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */ +#define DCMIPP_P1CTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR2 register ****************/ +#define DCMIPP_P1CTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR3 register ****************/ +#define DCMIPP_P1CTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1FCTCR register ****************/ +#define DCMIPP_P1FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P1CRSTR register ****************/ +#define DCMIPP_P1CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CRSZR register ****************/ +#define DCMIPP_P1CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1DCCR register *****************/ +#define DCMIPP_P1DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1DCCR_HDEC_Pos (1UL) +#define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DCCR_VDEC_Pos (3UL) +#define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1DSCR register *****************/ +#define DCMIPP_P1DSCR_HDIV_Pos (0UL) +#define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_VDIV_Pos (16UL) +#define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */ + +/*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/ +#define DCMIPP_P1DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P1DSSZR register ****************/ +#define DCMIPP_P1DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CMRICR register ***************/ +#define DCMIPP_P1CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P1CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P1CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P1CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P1CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P1CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P1CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P1CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P1CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/ +#define DCMIPP_P1RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P1RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P1RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P1RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P1RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/ +#define DCMIPP_P1RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P1RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P1GMCR register *****************/ +#define DCMIPP_P1GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/ + +/**************** Bit definition for DCMIPP_P1YUVCR register ****************/ +#define DCMIPP_P1YUVCR_ENABLE_Pos (0UL) +#define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1YUVCR_TYPE_Pos (1UL) +#define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */ +#define DCMIPP_P1YUVCR_CLAMP_Pos (2UL) +#define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/ +#define DCMIPP_P1YUVRR1_RR_Pos (0UL) +#define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1YUVRR1_RG_Pos (16UL) +#define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/ +#define DCMIPP_P1YUVRR2_RB_Pos (0UL) +#define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1YUVRR2_RA_Pos (16UL) +#define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/ +#define DCMIPP_P1YUVGR1_GR_Pos (0UL) +#define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1YUVGR1_GG_Pos (16UL) +#define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/ +#define DCMIPP_P1YUVGR2_GB_Pos (0UL) +#define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1YUVGR2_GA_Pos (16UL) +#define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/ +#define DCMIPP_P1YUVBR1_BR_Pos (0UL) +#define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1YUVBR1_BG_Pos (16UL) +#define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/ +#define DCMIPP_P1YUVBR2_BB_Pos (0UL) +#define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1YUVBR2_BA_Pos (16UL) +#define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1PPCR register *****************/ +#define DCMIPP_P1PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P1PPCR_DBM_Pos (16UL) +#define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P1PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P1PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/ +#define DCMIPP_P1PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/ +#define DCMIPP_P1PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */ + +/*************** Bit definition for DCMIPP_P1PPM0PR register ****************/ +#define DCMIPP_P1PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/ +#define DCMIPP_P1PPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/ +#define DCMIPP_P1PPM1AR2_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1PR register ****************/ +#define DCMIPP_P1PPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1STM1AR register ****************/ +#define DCMIPP_P1STM1AR_M1A_Pos (0UL) +#define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */ + +/*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/ +#define DCMIPP_P1PPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/ +#define DCMIPP_P1PPM2AR2_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */ + +/*************** Bit definition for DCMIPP_P1STM2AR register ****************/ +#define DCMIPP_P1STM2AR_M2A_Pos (0UL) +#define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */ + +/***************** Bit definition for DCMIPP_P1IER register *****************/ +#define DCMIPP_P1IER_LINEIE_Pos (0UL) +#define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P1IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P1IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P1IER_OVRIE_Pos (7UL) +#define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P1SR register ******************/ +#define DCMIPP_P1SR_LINEF_Pos (0UL) +#define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P1SR_FRAMEF_Pos (1UL) +#define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P1SR_VSYNCF_Pos (2UL) +#define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P1SR_OVRF_Pos (7UL) +#define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P1SR_LSTLINE_Pos (16UL) +#define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_LSTFRM_Pos (17UL) +#define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_CPTACT_Pos (23UL) +#define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P1FCR register *****************/ +#define DCMIPP_P1FCR_CLINEF_Pos (0UL) +#define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P1FCR_COVRF_Pos (7UL) +#define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P1CFSCR register ****************/ +#define DCMIPP_P1CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */ +#define DCMIPP_P1CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */ +#define DCMIPP_P1CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */ +#define DCMIPP_P1CFSCR_VC_Pos (19UL) +#define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P1CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P1CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P1CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P1CBPRCR register ****************/ +#define DCMIPP_P1CBPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */ +#define DCMIPP_P1CBPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */ + +/*************** Bit definition for DCMIPP_P1CBLCCR register ****************/ +#define DCMIPP_P1CBLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */ +#define DCMIPP_P1CBLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */ +#define DCMIPP_P1CBLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */ +#define DCMIPP_P1CBLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/ +#define DCMIPP_P1CEXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */ +#define DCMIPP_P1CEXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */ +#define DCMIPP_P1CEXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/ +#define DCMIPP_P1CEXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */ +#define DCMIPP_P1CEXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */ +#define DCMIPP_P1CEXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */ +#define DCMIPP_P1CEXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */ + +/*************** Bit definition for DCMIPP_P1CST1CR register ****************/ +#define DCMIPP_P1CST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */ +#define DCMIPP_P1CST1CR_BINS_Pos (2UL) +#define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */ +#define DCMIPP_P1CST1CR_SRC_Pos (4UL) +#define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */ +#define DCMIPP_P1CST1CR_MODE_Pos (7UL) +#define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */ +#define DCMIPP_P1CST1CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST2CR register ****************/ +#define DCMIPP_P1CST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST2CR_BINS_Pos (2UL) +#define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST2CR_SRC_Pos (4UL) +#define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */ +#define DCMIPP_P1CST2CR_MODE_Pos (7UL) +#define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */ +#define DCMIPP_P1CST2CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST3CR register ****************/ +#define DCMIPP_P1CST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST3CR_BINS_Pos (2UL) +#define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST3CR_SRC_Pos (4UL) +#define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1CST3CR_MODE_Pos (7UL) +#define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */ +#define DCMIPP_P1CST3CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CSTSTR register ****************/ +#define DCMIPP_P1CSTSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CSTSZR register ****************/ +#define DCMIPP_P1CSTSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CSTSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */ + +/**************** Bit definition for DCMIPP_P1CCCCR register ****************/ +#define DCMIPP_P1CCCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */ +#define DCMIPP_P1CCCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/ +#define DCMIPP_P1CCCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/ +#define DCMIPP_P1CCCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/ +#define DCMIPP_P1CCCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/ +#define DCMIPP_P1CCCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/ +#define DCMIPP_P1CCCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/ +#define DCMIPP_P1CCCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/ +#define DCMIPP_P1CCTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */ +#define DCMIPP_P1CCTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/ +#define DCMIPP_P1CCTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/ +#define DCMIPP_P1CCTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CFCTCR register ****************/ +#define DCMIPP_P1CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P1CCRSTR register ****************/ +#define DCMIPP_P1CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CCRSZR register ****************/ +#define DCMIPP_P1CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P1CDCCR register *****************/ +#define DCMIPP_P1CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1CDSCR register ****************/ +#define DCMIPP_P1CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/ +#define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P1CDSSZR register ****************/ +#define DCMIPP_P1CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CPPCR register ****************/ +#define DCMIPP_P1CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ + +/************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/ +#define DCMIPP_P1CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/ +#define DCMIPP_P1CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/ +#define DCMIPP_P1CPPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/ +#define DCMIPP_P1CPPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/ +#define DCMIPP_P1CPPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */ + +/**************** Bit definition for DCMIPP_P2FSCR register *****************/ +#define DCMIPP_P2FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */ +#define DCMIPP_P2FSCR_VC_Pos (19UL) +#define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P2FSCR_FDTF_Pos (24UL) +#define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P2FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P2FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P2FCTCR register ****************/ +#define DCMIPP_P2FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P2CRSTR register ****************/ +#define DCMIPP_P2CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CRSZR register ****************/ +#define DCMIPP_P2CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P2DCCR register *****************/ +#define DCMIPP_P2DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2DCCR_HDEC_Pos (1UL) +#define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2DCCR_VDEC_Pos (3UL) +#define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2DSCR register *****************/ +#define DCMIPP_P2DSCR_HDIV_Pos (0UL) +#define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_VDIV_Pos (16UL) +#define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/ +#define DCMIPP_P2DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P2DSSZR register ****************/ +#define DCMIPP_P2DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2GMCR register *****************/ +#define DCMIPP_P2GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2CMRICR register ***************/ +#define DCMIPP_P2CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P2CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P2CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P2CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P2CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P2CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P2CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P2CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P2CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/ +#define DCMIPP_P2RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P2RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P2RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P2RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P2RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/ +#define DCMIPP_P2RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P2RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P2PPCR register *****************/ +#define DCMIPP_P2PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2PPCR_DBM_Pos (16UL) +#define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/ +#define DCMIPP_P2PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */ + +/*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/ +#define DCMIPP_P2PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2STM0AR_Pos (0UL) +#define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */ + +/***************** Bit definition for DCMIPP_P2IER register *****************/ +#define DCMIPP_P2IER_LINEIE_Pos (0UL) +#define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P2IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P2IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P2IER_OVRIE_Pos (7UL) +#define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P2SR register ******************/ +#define DCMIPP_P2SR_LINEF_Pos (0UL) +#define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P2SR_FRAMEF_Pos (1UL) +#define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P2SR_VSYNCF_Pos (2UL) +#define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P2SR_OVRF_Pos (7UL) +#define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P2SR_LSTLINE_Pos (16UL) +#define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_LSTFRM_Pos (17UL) +#define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_CPTACT_Pos (23UL) +#define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P2FCR register *****************/ +#define DCMIPP_P2FCR_CLINEF_Pos (0UL) +#define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P2FCR_COVRF_Pos (7UL) +#define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P2CFSCR register ****************/ +#define DCMIPP_P2CFSCR_DTID_Pos (0UL) +#define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */ +#define DCMIPP_P2CFSCR_VC_Pos (19UL) +#define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P2CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P2CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P2CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P2CFCTCR register ****************/ +#define DCMIPP_P2CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P2CCRSTR register ****************/ +#define DCMIPP_P2CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P2CCRSZR register ****************/ +#define DCMIPP_P2CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P2CDCCR register *****************/ +#define DCMIPP_P2CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2CDSCR register ****************/ +#define DCMIPP_P2CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/ +#define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P2CDSSZR register ****************/ +#define DCMIPP_P2CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CPPCR register ****************/ +#define DCMIPP_P2CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2CPPCR_DBM_Pos (16UL) +#define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2CPPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2CPPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/ +#define DCMIPP_P2CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/ +#define DCMIPP_P2CPPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */ + +/*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/ +#define DCMIPP_P2CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/**************** Bit definition for DCMIPP_HWCFGR2 register ****************/ +#define DCMIPP_HWCFGR2_VPFT_Pos (0UL) +#define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */ +#define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */ +#define DCMIPP_HWCFGR2_DBMFT_Pos (4UL) +#define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */ +#define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */ +#define DCMIPP_HWCFGR2_PROCCLK_Pos (8UL) +#define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */ +#define DCMIPP_HWCFGR2_ADDMOD_Pos (12UL) +#define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */ +#define DCMIPP_HWCFGR2_DEC1_Pos (16UL) +#define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */ +#define DCMIPP_HWCFGR2_DEC2_Pos (17UL) +#define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */ +#define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */ +#define DCMIPP_HWCFGR2_MCU_Pos (20UL) +#define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */ +#define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */ +#define DCMIPP_HWCFGR2_TPG_Pos (24UL) +#define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */ +#define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */ +#define DCMIPP_HWCFGR2_STV_Pos (28UL) +#define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */ +#define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */ + +/**************** Bit definition for DCMIPP_HWCFGR1 register ****************/ +#define DCMIPP_HWCFGR1_CSIFT_Pos (0UL) +#define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */ +#define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */ +#define DCMIPP_HWCFGR1_PIPENB_Pos (4UL) +#define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */ +#define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */ +#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8UL) +#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */ +#define DCMIPP_HWCFGR1_DSP1FT_Pos (12UL) +#define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */ +#define DCMIPP_HWCFGR1_DSP2FT_Pos (13UL) +#define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */ +#define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */ +#define DCMIPP_HWCFGR1_RB2RGB_Pos (16UL) +#define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */ +#define DCMIPP_HWCFGR1_PLANARFT_Pos (20UL) +#define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */ +#define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI1NB_Pos (24UL) +#define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */ +#define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI2NB_Pos (28UL) +#define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */ +#define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */ + +/***************** Bit definition for DCMIPP_VERR register ******************/ +#define DCMIPP_VERR_MINREV_Pos (0UL) +#define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */ +#define DCMIPP_VERR_MAJREV_Pos (4UL) +#define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */ + +/***************** Bit definition for DCMIPP_IPIDR register *****************/ +#define DCMIPP_IPIDR_IDR_Pos (0UL) +#define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */ + +/***************** Bit definition for DCMIPP_SIDR register ******************/ +#define DCMIPP_SIDR_SID_Pos (0UL) +#define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */ + +/******************************************************************************/ +/* */ +/* Delay Block Interface (DLYBSD) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DLYBSD_CFGR register ********************/ +#define DLYB_CFGR_SDMMC_DLL_EN_Pos (0UL) +#define DLYB_CFGR_SDMMC_DLL_EN_Msk (0x1UL << DLYB_CFGR_SDMMC_DLL_EN_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SDMMC_DLL_EN DLYB_CFGR_SDMMC_DLL_EN_Msk /*!= AAW[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWHPCR_WHSPPOS_Pos (16UL) +#define LTDC_LxWHPCR_WHSPPOS_Msk (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos) +#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxWVPCR register */ +#define LTDC_LxWVPCR_WVSTPOS_Pos (0UL) +#define LTDC_LxWVPCR_WVSTPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos) +#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWVPCR_WVSPPOS_Pos (16UL) +#define LTDC_LxWVPCR_WVSPPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos) +#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxCKCR register */ +#define LTDC_LxCKCR_CKBLUE_Pos (0UL) +#define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos) +#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */ +#define LTDC_LxCKCR_CKGREEN_Pos (8UL) +#define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos) +#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */ +#define LTDC_LxCKCR_CKRED_Pos (16UL) +#define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos) +#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */ + +/* Bit fields for LTDC_LxPFCR register */ +#define LTDC_LxPFCR_PF_Pos (0UL) +#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) +#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */ + +/* Bit fields for LTDC_LxCACR register */ +#define LTDC_LxCACR_CONSTA_Pos (0UL) +#define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos) +#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */ + +/* Bit fields for LTDC_LxDCCR register */ +#define LTDC_LxDCCR_DCBLUE_Pos (0UL) +#define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos) +#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */ +#define LTDC_LxDCCR_DCGREEN_Pos (8UL) +#define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos) +#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */ +#define LTDC_LxDCCR_DCRED_Pos (16UL) +#define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos) +#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */ +#define LTDC_LxDCCR_DCALPHA_Pos (24UL) +#define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos) +#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */ + +/* Bit fields for LTDC_LxBFCR register */ +#define LTDC_LxBFCR_BF2_Pos (0UL) +#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) +#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */ +#define LTDC_LxBFCR_BF1_Pos (8UL) +#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) +#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */ +#define LTDC_LxBFCR_BOR_Pos (16UL) +#define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos) +#define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */ + +/* Bit fields for LTDC_LxBLCR register */ +#define LTDC_LxBLCR_BL_Pos (0UL) +#define LTDC_LxBLCR_BL_Msk (0x1fUL << LTDC_LxBLCR_BL_Pos) +#define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */ + +/* Bit fields for LTDC_LxPCR register */ +#define LTDC_LxPCR_YCEN_Pos (3UL) +#define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos) +#define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */ +#define LTDC_LxPCR_YCM_Pos (4UL) +#define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos) +#define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */ +#define LTDC_LxPCR_YF_Pos (6UL) +#define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos) +#define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */ +#define LTDC_LxPCR_CBF_Pos (7UL) +#define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos) +#define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */ +#define LTDC_LxPCR_OF_Pos (8UL) +#define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos) +#define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */ +#define LTDC_LxPCR_YREN_Pos (9UL) +#define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos) +#define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */ + +/* Bit fields for LTDC_LxCFBAR register */ +#define LTDC_LxCFBAR_CFBADD_Pos (0UL) +#define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos) +#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxCFBLR register */ +#define LTDC_LxCFBLR_CFBLL_Pos (0UL) +#define LTDC_LxCFBLR_CFBLL_Msk (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos) +#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_LxCFBLR_CFBP_Pos (16UL) +#define LTDC_LxCFBLR_CFBP_Msk (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos) +#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxCFBLNR register */ +#define LTDC_LxCFBLNR_CFBLNBR_Pos (0UL) +#define LTDC_LxCFBLNR_CFBLNBR_Msk (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos) +#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_L1AFBA0R register */ +#define LTDC_L1AFBA0R_AFBADD0_Pos (0UL) +#define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos) +#define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBA1R register */ +#define LTDC_L1AFBA1R_AFBADD1_Pos (0UL) +#define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos) +#define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBLR register */ +#define LTDC_L1AFBLR_AFBLL_Pos (0UL) +#define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos) +#define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_L1AFBLR_AFBP_Pos (16UL) +#define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos) +#define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxAFBLNR register */ +#define LTDC_L1AFBLNR_AFBLNBR_Pos (0UL) +#define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos) +#define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_LxCLUTWR register */ +#define LTDC_LxCLUTWR_BLUE_Pos (0UL) +#define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos) +#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */ +#define LTDC_LxCLUTWR_GREEN_Pos (8UL) +#define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos) +#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */ +#define LTDC_LxCLUTWR_RED_Pos (16UL) +#define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos) +#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */ +#define LTDC_LxCLUTWR_CLUTADD_Pos (24UL) +#define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos) +#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */ + +/* Bit fields for LTDC_LxCYR0R register */ +#define LTDC_LxCYR0R_CR2R_Pos (0UL) +#define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos) +#define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR0R_CB2B_Pos (16UL) +#define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos) +#define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxCYR1R register */ +#define LTDC_LxCYR1R_CR2G_Pos (0UL) +#define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos) +#define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR1R_CB2G_Pos (16UL) +#define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos) +#define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxFPF0R register */ +#define LTDC_LxFPF0R_APOS_Pos (0UL) +#define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos) +#define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_ALEN_Pos (5UL) +#define LTDC_LxFPF0R_ALEN_Msk (0xfUL << LTDC_LxFPF0R_ALEN_Pos) +#define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF0R_RPOS_Pos (9UL) +#define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos) +#define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_RLEN_Pos (14UL) +#define LTDC_LxFPF0R_RLEN_Msk (0xfUL << LTDC_LxFPF0R_RLEN_Pos) +#define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */ + +/* Bit fields for LTDC_LxFPF1R register */ +#define LTDC_LxFPF1R_GPOS_Pos (0UL) +#define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos) +#define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_GLEN_Pos (5UL) +#define LTDC_LxFPF1R_GLEN_Msk (0xfUL << LTDC_LxFPF1R_GLEN_Pos) +#define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF1R_BPOS_Pos (9UL) +#define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos) +#define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_BLEN_Pos (14UL) +#define LTDC_LxFPF1R_BLEN_Msk (0xfUL << LTDC_LxFPF1R_BLEN_Pos) +#define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */ + +#define LTDC_LxFPF1R_PSIZE_Pos (18UL) +#define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos) +#define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */ + + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ****************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */ +#define MDF_GCR_ILVNB_Pos (4UL) +#define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */ +#define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */ + +/******************* Bit definition for MDF/ADF_CKGCR register ********************/ +#define MDF_CKGCR_CKDEN_Pos (0UL) +#define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */ +#define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5UL) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6UL) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8UL) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10UL) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14UL) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18UL) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29UL) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30UL) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31UL) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2UL) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3UL) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register *******************/ +#define PSSI_RIS_OVR_RIS_Pos (1UL) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register *******************/ +#define PSSI_IER_OVR_IE_Pos (1UL) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register *******************/ +#define PSSI_MIS_OVR_MIS_Pos (1UL) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register *******************/ +#define PSSI_ICR_OVR_ISC_Pos (1UL) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0UL) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************* Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_SDEN_Pos (2UL) +#define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */ +#define PWR_CR1_MODE_PDN_Pos (4UL) +#define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */ +#define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */ +#define PWR_CR1_LPDS08V_Pos (5UL) +#define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */ +#define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */ +#define PWR_CR1_VDD18SMPSVMEN_Pos (8UL) +#define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */ +#define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */ +#define PWR_CR1_VDD18SMPSRDY_Pos (15UL) +#define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */ +#define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */ +#define PWR_CR1_POPL_Pos (16UL) +#define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */ +#define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */ +#define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */ +#define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */ +#define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */ +#define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */ +#define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */ + +/******************* Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDEN_Pos (0UL) +#define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */ +#define PWR_CR2_PVDO_Pos (8UL) +#define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */ +#define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +/******************* Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_VCOREMONEN_Pos (0UL) +#define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */ +#define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */ +#define PWR_CR3_VCORELLS_Pos (4UL) +#define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */ +#define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */ +#define PWR_CR3_VCOREL_Pos (8UL) +#define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */ +#define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */ +#define PWR_CR3_VCOREH_Pos (9UL) +#define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */ +#define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */ + +/******************* Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_TCMRBSEN_Pos (0UL) +#define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */ +#define PWR_CR4_TCMFLXRBSEN_Pos (4UL) +#define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */ +#define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */ + +/****************** Bit definition for PWR_VOSCR register *******************/ +#define PWR_VOSCR_VOS_Pos (0UL) +#define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */ +#define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */ +#define PWR_VOSCR_VOSRDY_Pos (1UL) +#define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSCR_ACTVOS_Pos (16UL) +#define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ +#define PWR_VOSCR_ACTVOSRDY_Pos (17UL) +#define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */ +#define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */ + +/****************** Bit definition for PWR_BDCR1 register *******************/ +#define PWR_BDCR1_MONEN_Pos (0UL) +#define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ +#define PWR_BDCR1_VBATL_Pos (16UL) +#define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */ +#define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */ +#define PWR_BDCR1_VBATH_Pos (17UL) +#define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */ +#define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */ +#define PWR_BDCR1_TEMPL_Pos (18UL) +#define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */ +#define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */ +#define PWR_BDCR1_TEMPH_Pos (19UL) +#define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */ +#define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */ + +/****************** Bit definition for PWR_BDCR2 register *******************/ +#define PWR_BDCR2_BKPRBSEN_Pos (0UL) +#define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */ + +/****************** Bit definition for PWR_DBPCR register *******************/ +#define PWR_DBPCR_DBP_Pos (0UL) +#define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */ + +/****************** Bit definition for PWR_CPUCR register *******************/ +#define PWR_CPUCR_PDDS_Pos (0UL) +#define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */ +#define PWR_CPUCR_CSSF_Pos (1UL) +#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */ +#define PWR_CPUCR_STOPF_Pos (8UL) +#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */ +#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */ +#define PWR_CPUCR_SBF_Pos (9UL) +#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */ +#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */ +#define PWR_CPUCR_SVOS_Pos (16UL) +#define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */ +#define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */ + +/****************** Bit definition for PWR_SVMCR1 register ******************/ +#define PWR_SVMCR1_VDDIO4VMEN_Pos (0UL) +#define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */ +#define PWR_SVMCR1_VDDIO4SV_Pos (8UL) +#define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */ +#define PWR_SVMCR1_VDDIO4RDY_Pos (16UL) +#define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */ +#define PWR_SVMCR1_VDDIO4VRSEL_Pos (24UL) +#define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */ +#define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25UL) +#define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR2 register ******************/ +#define PWR_SVMCR2_VDDIO5VMEN_Pos (0UL) +#define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */ +#define PWR_SVMCR2_VDDIO5SV_Pos (8UL) +#define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */ +#define PWR_SVMCR2_VDDIO5RDY_Pos (16UL) +#define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */ +#define PWR_SVMCR2_VDDIO5VRSEL_Pos (24UL) +#define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */ +#define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25UL) +#define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR3 register ******************/ +#define PWR_SVMCR3_VDDIO2VMEN_Pos (0UL) +#define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */ +#define PWR_SVMCR3_VDDIO3VMEN_Pos (1UL) +#define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */ +#define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */ +#define PWR_SVMCR3_USB33VMEN_Pos (2UL) +#define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */ +#define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */ +#define PWR_SVMCR3_AVMEN_Pos (4UL) +#define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */ +#define PWR_SVMCR3_VDDIO2SV_Pos (8UL) +#define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */ +#define PWR_SVMCR3_VDDIO3SV_Pos (9UL) +#define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */ +#define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */ +#define PWR_SVMCR3_USB33SV_Pos (10UL) +#define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */ +#define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */ +#define PWR_SVMCR3_ASV_Pos (12UL) +#define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */ +#define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */ +#define PWR_SVMCR3_VDDIO2RDY_Pos (16UL) +#define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */ +#define PWR_SVMCR3_VDDIO3RDY_Pos (17UL) +#define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */ +#define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */ +#define PWR_SVMCR3_USB33RDY_Pos (18UL) +#define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */ +#define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */ +#define PWR_SVMCR3_ARDY_Pos (20UL) +#define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */ +#define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */ +#define PWR_SVMCR3_VDDIOVRSEL_Pos (24UL) +#define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */ +#define PWR_SVMCR3_VDDIO2VRSEL_Pos (25UL) +#define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */ +#define PWR_SVMCR3_VDDIO3VRSEL_Pos (26UL) +#define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */ + +/***************** Bit definition for PWR_WKUPCR register *******************/ +#define PWR_WKUPCR_WKUPC1_Pos (0UL) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPCR_WKUPC2_Pos (1UL) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPCR_WKUPC3_Pos (2UL) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPCR_WKUPC4_Pos (3UL) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */ +#define PWR_WKUPCR_WKUPC_Pos (0UL) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */ + +/***************** Bit definition for PWR_WKUPSR register *******************/ +#define PWR_WKUPSR_WKUPF1_Pos (0UL) +#define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPSR_WKUPF2_Pos (1UL) +#define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPSR_WKUPF3_Pos (2UL) +#define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPSR_WKUPF4_Pos (3UL) +#define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */ + +/***************** Bit definition for PWR_WKUPEPR register *******************/ +#define PWR_WKUPEPR_WKUPEN1_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1UL) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2UL) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3UL) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8UL) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPP2_Pos (9UL) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPP3_Pos (10UL) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPP4_Pos (11UL) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPP_Pos (8UL) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16UL) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18UL) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20UL) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22UL) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WKUPEPR_WKUPEN_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ + +/***************** Bit definition for PWR_SECCFGR register ******************/ +#define PWR_SECCFGR_SEC0_Pos (0UL) +#define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */ +#define PWR_SECCFGR_SEC1_Pos (1UL) +#define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */ +#define PWR_SECCFGR_SEC2_Pos (2UL) +#define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */ +#define PWR_SECCFGR_SEC3_Pos (3UL) +#define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */ +#define PWR_SECCFGR_SEC4_Pos (4UL) +#define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */ +#define PWR_SECCFGR_SEC5_Pos (5UL) +#define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */ +#define PWR_SECCFGR_SEC6_Pos (6UL) +#define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */ +#define PWR_SECCFGR_SEC7_Pos (7UL) +#define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */ +#define PWR_SECCFGR_WKUPSEC1_Pos (16UL) +#define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */ +#define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */ +#define PWR_SECCFGR_WKUPSEC2_Pos (17UL) +#define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */ +#define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */ +#define PWR_SECCFGR_WKUPSEC3_Pos (18UL) +#define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */ +#define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */ +#define PWR_SECCFGR_WKUPSEC4_Pos (19UL) +#define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */ +#define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */ + +/***************** Bit definition for PWR_PRIVCFGR register *****************/ +#define PWR_PRIVCFGR_PRIV0_Pos (0UL) +#define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */ +#define PWR_PRIVCFGR_PRIV1_Pos (1UL) +#define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */ +#define PWR_PRIVCFGR_PRIV2_Pos (2UL) +#define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */ +#define PWR_PRIVCFGR_PRIV3_Pos (3UL) +#define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */ +#define PWR_PRIVCFGR_PRIV4_Pos (4UL) +#define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */ +#define PWR_PRIVCFGR_PRIV5_Pos (5UL) +#define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */ +#define PWR_PRIVCFGR_PRIV6_Pos (6UL) +#define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */ +#define PWR_PRIVCFGR_PRIV7_Pos (7UL) +#define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV1_Pos (16UL) +#define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */ +#define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV2_Pos (17UL) +#define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */ +#define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV3_Pos (18UL) +#define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */ +#define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV4_Pos (19UL) +#define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */ +#define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */ + + +/******************************************************************************/ +/* */ +/* RAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_CR register ******************/ +#define RAMCFG_CR_ECCE_Pos (0UL) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */ +#define RAMCFG_CR_ALE_Pos (4UL) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8UL) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_SRAMHWERDIS_Pos (12UL) +#define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */ +#define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */ +#define RAMCFG_CR_ITCMCFG_Pos (16UL) +#define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */ +#define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ +#define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_SRAMSD_Pos (20UL) +#define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */ +#define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */ +#define RAMCFG_CR_DTCMCFG_Pos (24UL) +#define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */ +#define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ + +/******************* Bit definition for RAMCFG_IER register *****************/ +#define RAMCFG_IER_SEIE_Pos (0UL) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */ +#define RAMCFG_IER_DEIE_Pos (1UL) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */ + +/******************* Bit definition for RAMCFG_ISR register *****************/ +#define RAMCFG_ISR_SEDC_Pos (0UL) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */ +#define RAMCFG_ISR_DED_Pos (1UL) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8UL) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */ + +/******************* Bit definition for RAMCFG_ESEAR register ****************/ +#define RAMCFG_ESEAR_ESEA_Pos (0UL) +#define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */ + +/******************* Bit definition for RAMCFG_EDEAR register ****************/ +#define RAMCFG_EDEAR_EDEA_Pos (0UL) +#define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */ + +/******************* Bit definition for RAMCFG_ICR register *****************/ +#define RAMCFG_ICR_CSEDC_Pos (0UL) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */ +#define RAMCFG_ICR_CDED_Pos (1UL) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/ + +/***************** Bit definition for RAMCFG_ECCKEYR register ***************/ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0UL) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */ + +/***************** Bit definition for RAMCFG_ERKEYR register ****************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0UL) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */ + + +/******************************************************************************/ +/* */ +/* (RCC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_LSION_Pos (0UL) +#define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_CR_LSEON_Pos (1UL) +#define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */ +#define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */ +#define RCC_CR_MSION_Pos (2UL) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */ +#define RCC_CR_HSION_Pos (3UL) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */ +#define RCC_CR_HSEON_Pos (4UL) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */ +#define RCC_CR_PLL1ON_Pos (8UL) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */ +#define RCC_CR_PLL2ON_Pos (9UL) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ +#define RCC_CR_PLL3ON_Pos (10UL) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ +#define RCC_CR_PLL4ON_Pos (11UL) +#define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */ +#define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */ + +/******************** Bit definition for RCC_SR register ********************/ +#define RCC_SR_LSIRDY_Pos (0UL) +#define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */ +#define RCC_SR_LSERDY_Pos (1UL) +#define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */ +#define RCC_SR_MSIRDY_Pos (2UL) +#define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */ +#define RCC_SR_HSIRDY_Pos (3UL) +#define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */ +#define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_SR_HSERDY_Pos (4UL) +#define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */ +#define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_SR_PLL1RDY_Pos (8UL) +#define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */ +#define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_SR_PLL2RDY_Pos (9UL) +#define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */ +#define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_SR_PLL3RDY_Pos (10UL) +#define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */ +#define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_SR_PLL4RDY_Pos (11UL) +#define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */ +#define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ + +/****************** Bit definition for RCC_STOPCR register ******************/ +#define RCC_STOPCR_MSISTOPEN_Pos (0UL) +#define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */ +#define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCR_HSISTOPEN_Pos (1UL) +#define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */ +#define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */ + +/****************** Bit definition for RCC_CFGR1 register *******************/ +#define RCC_CFGR1_STOPWUCK_Pos (0UL) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */ +#define RCC_CFGR1_CPUSW_Pos (16UL) +#define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */ +#define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */ +#define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */ +#define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */ +#define RCC_CFGR1_CPUSWS_Pos (20UL) +#define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */ +#define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */ +#define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_SYSSW_Pos (24UL) +#define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */ +#define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */ +#define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_SYSSWS_Pos (28UL) +#define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */ +#define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for RCC_CFGR2 register *******************/ +#define RCC_CFGR2_PPRE1_Pos (0UL) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE2_Pos (4UL) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE4_Pos (12UL) +#define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */ +#define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_PPRE5_Pos (16UL) +#define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */ +#define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */ +#define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */ +#define RCC_CFGR2_HPRE_Pos (20UL) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_TIMPRE_Pos (24UL) +#define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */ +#define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */ +#define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */ +#define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_VSWRST_Pos (31UL) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */ + +/****************** Bit definition for RCC_HWRSR register *******************/ +#define RCC_HWRSR_RMVF_Pos (16UL) +#define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_HWRSR_LCKRSTF_Pos (17UL) +#define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_HWRSR_BORRSTF_Pos (21UL) +#define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_HWRSR_PINRSTF_Pos (22UL) +#define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_HWRSR_PORRSTF_Pos (23UL) +#define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_HWRSR_SFTRSTF_Pos (24UL) +#define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_HWRSR_IWDGRSTF_Pos (26UL) +#define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_HWRSR_WWDGRSTF_Pos (28UL) +#define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_HWRSR_LPWRRSTF_Pos (30UL) +#define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/******************* Bit definition for RCC_RSR register ********************/ +#define RCC_RSR_RMVF_Pos (16UL) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_LCKRSTF_Pos (17UL) +#define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_RSR_BORRSTF_Pos (21UL) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_RSR_PINRSTF_Pos (22UL) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_PORRSTF_Pos (23UL) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (24UL) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_RSR_IWDGRSTF_Pos (26UL) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (28UL) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (30UL) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/***************** Bit definition for RCC_LSECFGR register ******************/ +#define RCC_LSECFGR_LSECSSON_Pos (7UL) +#define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */ +#define RCC_LSECFGR_LSECSSRA_Pos (8UL) +#define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */ +#define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */ +#define RCC_LSECFGR_LSECSSD_Pos (9UL) +#define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */ +#define RCC_LSECFGR_LSEBYP_Pos (15UL) +#define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */ +#define RCC_LSECFGR_LSEEXT_Pos (16UL) +#define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */ +#define RCC_LSECFGR_LSEGFON_Pos (17UL) +#define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */ +#define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */ +#define RCC_LSECFGR_LSEDRV_Pos (18UL) +#define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */ +#define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */ +#define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for RCC_MSICFGR register ******************/ +#define RCC_MSICFGR_MSIFREQSEL_Pos (9UL) +#define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */ +#define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */ +#define RCC_MSICFGR_MSITRIM_Pos (16UL) +#define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */ +#define RCC_MSICFGR_MSICAL_Pos (23UL) +#define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */ +#define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (7UL) +#define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_Pos (16UL) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSICAL_Pos (23UL) +#define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ + +/****************** Bit definition for RCC_HSIMCR register ******************/ +#define RCC_HSIMCR_HSIREF_Pos (0UL) +#define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */ +#define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */ +#define RCC_HSIMCR_HSIDEV_Pos (16UL) +#define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */ +#define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */ +#define RCC_HSIMCR_HSIMONEN_Pos (31UL) +#define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */ +#define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */ + +/****************** Bit definition for RCC_HSIMSR register ******************/ +#define RCC_HSIMSR_HSIVAL_Pos (0UL) +#define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */ +#define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */ + +/***************** Bit definition for RCC_HSECFGR register ******************/ +#define RCC_HSECFGR_HSEDIV2SEL_Pos (6UL) +#define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */ +#define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */ +#define RCC_HSECFGR_HSECSSON_Pos (7UL) +#define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */ +#define RCC_HSECFGR_HSECSSD_Pos (9UL) +#define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */ +#define RCC_HSECFGR_HSECSSBYP_Pos (10UL) +#define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */ +#define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */ +#define RCC_HSECFGR_HSECSSBPRE_Pos (11UL) +#define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */ +#define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */ +#define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */ +#define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */ +#define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */ +#define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */ +#define RCC_HSECFGR_HSEBYP_Pos (15UL) +#define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_HSECFGR_HSEEXT_Pos (16UL) +#define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_PLL1DIVN_Pos (8UL) +#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */ +#define RCC_PLL1CFGR1_PLL1DIVM_Pos (20UL) +#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */ +#define RCC_PLL1CFGR1_PLL1BYP_Pos (27UL) +#define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */ +#define RCC_PLL1CFGR1_PLL1SEL_Pos (28UL) +#define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */ +#define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0UL) +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL1CFGR3 register *****************/ +#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0UL) +#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */ +#define RCC_PLL1CFGR3_PLL1DACEN_Pos (1UL) +#define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2UL) +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */ +#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3UL) +#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4UL) +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */ +#define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8UL) +#define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */ +#define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16UL) +#define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */ +#define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24UL) +#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */ +#define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27UL) +#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30UL) +#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_PLL2DIVN_Pos (8UL) +#define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */ +#define RCC_PLL2CFGR1_PLL2DIVM_Pos (20UL) +#define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */ +#define RCC_PLL2CFGR1_PLL2BYP_Pos (27UL) +#define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */ +#define RCC_PLL2CFGR1_PLL2SEL_Pos (28UL) +#define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */ +#define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0UL) +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL2CFGR3 register *****************/ +#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0UL) +#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */ +#define RCC_PLL2CFGR3_PLL2DACEN_Pos (1UL) +#define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2UL) +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */ +#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3UL) +#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4UL) +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */ +#define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8UL) +#define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */ +#define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16UL) +#define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */ +#define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24UL) +#define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */ +#define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27UL) +#define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30UL) +#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_PLL3DIVN_Pos (8UL) +#define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */ +#define RCC_PLL3CFGR1_PLL3DIVM_Pos (20UL) +#define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */ +#define RCC_PLL3CFGR1_PLL3BYP_Pos (27UL) +#define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */ +#define RCC_PLL3CFGR1_PLL3SEL_Pos (28UL) +#define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */ +#define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0UL) +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL3CFGR3 register *****************/ +#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0UL) +#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */ +#define RCC_PLL3CFGR3_PLL3DACEN_Pos (1UL) +#define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2UL) +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */ +#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3UL) +#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4UL) +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */ +#define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8UL) +#define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */ +#define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16UL) +#define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */ +#define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24UL) +#define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */ +#define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27UL) +#define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30UL) +#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_PLL4DIVN_Pos (8UL) +#define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */ +#define RCC_PLL4CFGR1_PLL4DIVM_Pos (20UL) +#define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */ +#define RCC_PLL4CFGR1_PLL4BYP_Pos (27UL) +#define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */ +#define RCC_PLL4CFGR1_PLL4SEL_Pos (28UL) +#define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */ +#define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0UL) +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL4CFGR3 register *****************/ +#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0UL) +#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */ +#define RCC_PLL4CFGR3_PLL4DACEN_Pos (1UL) +#define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2UL) +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */ +#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3UL) +#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4UL) +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */ +#define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8UL) +#define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */ +#define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16UL) +#define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */ +#define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24UL) +#define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */ +#define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27UL) +#define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30UL) +#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/***************** Bit definition for RCC_IC1CFGR register ******************/ +#define RCC_IC1CFGR_IC1INT_Pos (16UL) +#define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */ +#define RCC_IC1CFGR_IC1SEL_Pos (28UL) +#define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */ +#define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC2CFGR register ******************/ +#define RCC_IC2CFGR_IC2INT_Pos (16UL) +#define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */ +#define RCC_IC2CFGR_IC2SEL_Pos (28UL) +#define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */ +#define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC3CFGR register ******************/ +#define RCC_IC3CFGR_IC3INT_Pos (16UL) +#define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */ +#define RCC_IC3CFGR_IC3SEL_Pos (28UL) +#define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */ +#define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC4CFGR register ******************/ +#define RCC_IC4CFGR_IC4INT_Pos (16UL) +#define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */ +#define RCC_IC4CFGR_IC4SEL_Pos (28UL) +#define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */ +#define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC5CFGR register ******************/ +#define RCC_IC5CFGR_IC5INT_Pos (16UL) +#define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */ +#define RCC_IC5CFGR_IC5SEL_Pos (28UL) +#define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */ +#define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC6CFGR register ******************/ +#define RCC_IC6CFGR_IC6INT_Pos (16UL) +#define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */ +#define RCC_IC6CFGR_IC6SEL_Pos (28UL) +#define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */ +#define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC7CFGR register ******************/ +#define RCC_IC7CFGR_IC7INT_Pos (16UL) +#define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */ +#define RCC_IC7CFGR_IC7SEL_Pos (28UL) +#define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */ +#define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC8CFGR register ******************/ +#define RCC_IC8CFGR_IC8INT_Pos (16UL) +#define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */ +#define RCC_IC8CFGR_IC8SEL_Pos (28UL) +#define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */ +#define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC9CFGR register ******************/ +#define RCC_IC9CFGR_IC9INT_Pos (16UL) +#define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */ +#define RCC_IC9CFGR_IC9SEL_Pos (28UL) +#define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */ +#define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC10CFGR register *****************/ +#define RCC_IC10CFGR_IC10INT_Pos (16UL) +#define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */ +#define RCC_IC10CFGR_IC10SEL_Pos (28UL) +#define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */ +#define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC11CFGR register *****************/ +#define RCC_IC11CFGR_IC11INT_Pos (16UL) +#define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */ +#define RCC_IC11CFGR_IC11SEL_Pos (28UL) +#define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */ +#define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC12CFGR register *****************/ +#define RCC_IC12CFGR_IC12INT_Pos (16UL) +#define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */ +#define RCC_IC12CFGR_IC12SEL_Pos (28UL) +#define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */ +#define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC13CFGR register *****************/ +#define RCC_IC13CFGR_IC13INT_Pos (16UL) +#define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */ +#define RCC_IC13CFGR_IC13SEL_Pos (28UL) +#define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */ +#define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC14CFGR register *****************/ +#define RCC_IC14CFGR_IC14INT_Pos (16UL) +#define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */ +#define RCC_IC14CFGR_IC14SEL_Pos (28UL) +#define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */ +#define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC15CFGR register *****************/ +#define RCC_IC15CFGR_IC15INT_Pos (16UL) +#define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */ +#define RCC_IC15CFGR_IC15SEL_Pos (28UL) +#define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */ +#define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC16CFGR register *****************/ +#define RCC_IC16CFGR_IC16INT_Pos (16UL) +#define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */ +#define RCC_IC16CFGR_IC16SEL_Pos (28UL) +#define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */ +#define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC17CFGR register *****************/ +#define RCC_IC17CFGR_IC17INT_Pos (16UL) +#define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */ +#define RCC_IC17CFGR_IC17SEL_Pos (28UL) +#define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */ +#define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC18CFGR register *****************/ +#define RCC_IC18CFGR_IC18INT_Pos (16UL) +#define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */ +#define RCC_IC18CFGR_IC18SEL_Pos (28UL) +#define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */ +#define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC19CFGR register *****************/ +#define RCC_IC19CFGR_IC19INT_Pos (16UL) +#define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */ +#define RCC_IC19CFGR_IC19SEL_Pos (28UL) +#define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */ +#define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC20CFGR register *****************/ +#define RCC_IC20CFGR_IC20INT_Pos (16UL) +#define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */ +#define RCC_IC20CFGR_IC20SEL_Pos (28UL) +#define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */ +#define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for RCC_CIER register *******************/ +#define RCC_CIER_LSIRDYIE_Pos (0UL) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1UL) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_MSIRDYIE_Pos (2UL) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */ +#define RCC_CIER_HSIRDYIE_Pos (3UL) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (4UL) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ +#define RCC_CIER_PLL1RDYIE_Pos (8UL) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */ +#define RCC_CIER_PLL2RDYIE_Pos (9UL) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */ +#define RCC_CIER_PLL3RDYIE_Pos (10UL) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */ +#define RCC_CIER_PLL4RDYIE_Pos (11UL) +#define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */ +#define RCC_CIER_LSECSSIE_Pos (16UL) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */ +#define RCC_CIER_HSECSSIE_Pos (17UL) +#define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */ +#define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */ +#define RCC_CIER_WKUPIE_Pos (24UL) +#define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */ +#define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */ + +/******************* Bit definition for RCC_CIFR register *******************/ +#define RCC_CIFR_LSIRDYF_Pos (0UL) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1UL) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (2UL) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (3UL) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (4UL) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_PLL1RDYF_Pos (8UL) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */ +#define RCC_CIFR_PLL2RDYF_Pos (9UL) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */ +#define RCC_CIFR_PLL3RDYF_Pos (10UL) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */ +#define RCC_CIFR_PLL4RDYF_Pos (11UL) +#define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (16UL) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (17UL) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_WKUPF_Pos (24UL) +#define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */ +#define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */ + +/******************* Bit definition for RCC_CICR register *******************/ +#define RCC_CICR_LSIRDYC_Pos (0UL) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1UL) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_MSIRDYC_Pos (2UL) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */ +#define RCC_CICR_HSIRDYC_Pos (3UL) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (4UL) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_PLL1RDYC_Pos (8UL) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */ +#define RCC_CICR_PLL2RDYC_Pos (9UL) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */ +#define RCC_CICR_PLL3RDYC_Pos (10UL) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */ +#define RCC_CICR_PLL4RDYC_Pos (11UL) +#define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (16UL) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (17UL) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_WKUPFC_Pos (24UL) +#define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */ +#define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */ + +/****************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_ADF1SEL_Pos (0UL) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */ +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_ADC12SEL_Pos (4UL) +#define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */ +#define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_ADCPRE_Pos (8UL) +#define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */ +#define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */ +#define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_DCMIPPSEL_Pos (20UL) +#define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */ +#define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_ETH1PTPSEL_Pos (0UL) +#define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_ETH1PTPDIV_Pos (4UL) +#define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */ +#define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8UL) +#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1CLKSEL_Pos (12UL) +#define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ETH1SEL_Pos (16UL) +#define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20UL) +#define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24UL) +#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR3 register ******************/ +#define RCC_CCIPR3_FDCANSEL_Pos (0UL) +#define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */ +#define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_FMCSEL_Pos (4UL) +#define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */ +#define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_DFTSEL_Pos (8UL) +#define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */ + +/****************** Bit definition for RCC_CCIPR4 register ******************/ +#define RCC_CCIPR4_I2C1SEL_Pos (0UL) +#define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */ +#define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR4_I2C2SEL_Pos (4UL) +#define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */ +#define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR4_I2C3SEL_Pos (8UL) +#define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */ +#define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR4_I2C4SEL_Pos (12UL) +#define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */ +#define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR4_I3C1SEL_Pos (16UL) +#define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */ +#define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR4_I3C2SEL_Pos (20UL) +#define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */ +#define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR4_LTDCSEL_Pos (24UL) +#define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */ +#define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */ + +/****************** Bit definition for RCC_CCIPR5 register ******************/ +#define RCC_CCIPR5_MCO1SEL_Pos (0UL) +#define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */ +#define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR5_MCO1PRE_Pos (4UL) +#define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */ +#define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR5_MCO2SEL_Pos (8UL) +#define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */ +#define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR5_MCO2PRE_Pos (12UL) +#define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */ +#define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */ +#define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR5_MDF1SEL_Pos (16UL) +#define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */ +#define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for RCC_CCIPR6 register ******************/ +#define RCC_CCIPR6_XSPI1SEL_Pos (0UL) +#define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */ +#define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR6_XSPI2SEL_Pos (4UL) +#define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */ +#define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR6_XSPI3SEL_Pos (8UL) +#define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */ +#define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR6_OTGPHY1SEL_Pos (12UL) +#define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */ +#define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16UL) +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR6_OTGPHY2SEL_Pos (20UL) +#define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */ +#define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24UL) +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR7 register ******************/ +#define RCC_CCIPR7_PERSEL_Pos (0UL) +#define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */ +#define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR7_PSSISEL_Pos (4UL) +#define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */ +#define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR7_RTCSEL_Pos (8UL) +#define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */ +#define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR7_RTCPRE_Pos (12UL) +#define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */ +#define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */ +#define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR7_SAI1SEL_Pos (20UL) +#define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */ +#define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR7_SAI2SEL_Pos (24UL) +#define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */ +#define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */ + +/****************** Bit definition for RCC_CCIPR8 register ******************/ +#define RCC_CCIPR8_SDMMC1SEL_Pos (0UL) +#define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */ +#define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR8_SDMMC2SEL_Pos (4UL) +#define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */ +#define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */ + +/****************** Bit definition for RCC_CCIPR9 register ******************/ +#define RCC_CCIPR9_SPDIFRX1SEL_Pos (0UL) +#define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */ +#define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR9_SPI1SEL_Pos (4UL) +#define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */ +#define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR9_SPI2SEL_Pos (8UL) +#define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */ +#define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR9_SPI3SEL_Pos (12UL) +#define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */ +#define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR9_SPI4SEL_Pos (16UL) +#define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */ +#define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR9_SPI5SEL_Pos (20UL) +#define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */ +#define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR9_SPI6SEL_Pos (24UL) +#define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */ +#define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR12 register ******************/ +#define RCC_CCIPR12_LPTIM1SEL_Pos (8UL) +#define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */ +#define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR12_LPTIM2SEL_Pos (12UL) +#define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */ +#define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR12_LPTIM3SEL_Pos (16UL) +#define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */ +#define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR12_LPTIM4SEL_Pos (20UL) +#define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */ +#define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR12_LPTIM5SEL_Pos (24UL) +#define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */ +#define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR13 register ******************/ +#define RCC_CCIPR13_USART1SEL_Pos (0UL) +#define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */ +#define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR13_USART2SEL_Pos (4UL) +#define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */ +#define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR13_USART3SEL_Pos (8UL) +#define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */ +#define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR13_UART4SEL_Pos (12UL) +#define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */ +#define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR13_UART5SEL_Pos (16UL) +#define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */ +#define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR13_USART6SEL_Pos (20UL) +#define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */ +#define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR13_UART7SEL_Pos (24UL) +#define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */ +#define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR13_UART8SEL_Pos (28UL) +#define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */ +#define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */ +#define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */ + +/***************** Bit definition for RCC_CCIPR14 register ******************/ +#define RCC_CCIPR14_UART9SEL_Pos (0UL) +#define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */ +#define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR14_USART10SEL_Pos (4UL) +#define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */ +#define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR14_LPUART1SEL_Pos (8UL) +#define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */ +#define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */ + +/***************** Bit definition for RCC_MISCRSTR register *****************/ +#define RCC_MISCRSTR_DBGRST_Pos (0UL) +#define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */ +#define RCC_MISCRSTR_XSPIPHY1RST_Pos (4UL) +#define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTR_XSPIPHY2RST_Pos (5UL) +#define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7UL) +#define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8UL) +#define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTR register ******************/ +#define RCC_MEMRSTR_AXISRAM3RST_Pos (0UL) +#define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */ +#define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTR_AXISRAM4RST_Pos (1UL) +#define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */ +#define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTR_AXISRAM5RST_Pos (2UL) +#define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */ +#define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTR_AXISRAM6RST_Pos (3UL) +#define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */ +#define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTR_AHBSRAM1RST_Pos (4UL) +#define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */ +#define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTR_AHBSRAM2RST_Pos (5UL) +#define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */ +#define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTR_AXISRAM1RST_Pos (7UL) +#define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */ +#define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTR_AXISRAM2RST_Pos (8UL) +#define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */ +#define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTR_FLEXRAMRST_Pos (9UL) +#define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTR_VENCRAMRST_Pos (11UL) +#define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTR_BOOTROMRST_Pos (12UL) +#define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */ + +/***************** Bit definition for RCC_AHB1RSTR register *****************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4UL) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTR_ADC12RST_Pos (5UL) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */ + +/***************** Bit definition for RCC_AHB2RSTR register *****************/ +#define RCC_AHB2RSTR_RAMCFGRST_Pos (12UL) +#define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTR_MDF1RST_Pos (16UL) +#define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTR_ADF1RST_Pos (17UL) +#define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */ + +/***************** Bit definition for RCC_AHB3RSTR register *****************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0UL) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */ +#define RCC_AHB3RSTR_HASHRST_Pos (1UL) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB3RSTR_PKARST_Pos (8UL) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */ +#define RCC_AHB3RSTR_IACRST_Pos (10UL) +#define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */ + +/***************** Bit definition for RCC_AHB4RSTR register *****************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0UL) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTR_GPIOBRST_Pos (1UL) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTR_GPIOCRST_Pos (2UL) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTR_GPIODRST_Pos (3UL) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTR_GPIOERST_Pos (4UL) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTR_GPIOFRST_Pos (5UL) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTR_GPIOGRST_Pos (6UL) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTR_GPIOHRST_Pos (7UL) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTR_GPIONRST_Pos (13UL) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTR_GPIOORST_Pos (14UL) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTR_GPIOPRST_Pos (15UL) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTR_GPIOQRST_Pos (16UL) +#define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTR_PWRRST_Pos (18UL) +#define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */ +#define RCC_AHB4RSTR_CRCRST_Pos (19UL) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */ + +/***************** Bit definition for RCC_AHB5RSTR register *****************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0UL) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTR_DMA2DRST_Pos (1UL) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTR_JPEGRST_Pos (3UL) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTR_FMCRST_Pos (4UL) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */ +#define RCC_AHB5RSTR_XSPI1RST_Pos (5UL) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTR_PSSIRST_Pos (6UL) +#define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTR_SDMMC2RST_Pos (7UL) +#define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8UL) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTR_XSPI2RST_Pos (12UL) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTR_XSPIMRST_Pos (13UL) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTR_XSPI3RST_Pos (17UL) +#define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTR_GFXMMURST_Pos (19UL) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTR_GPU2DRST_Pos (20UL) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23UL) +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24UL) +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTR_ETH1RST_Pos (25UL) +#define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTR_OTG1RST_Pos (26UL) +#define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTR_OTGPHY1RST_Pos (27UL) +#define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */ +#define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTR_OTGPHY2RST_Pos (28UL) +#define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */ +#define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTR_OTG2RST_Pos (29UL) +#define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */ + +/**************** Bit definition for RCC_APB1RSTR1 register *****************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0UL) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTR1_TIM3RST_Pos (1UL) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTR1_TIM4RST_Pos (2UL) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTR1_TIM5RST_Pos (3UL) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTR1_TIM6RST_Pos (4UL) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTR1_TIM7RST_Pos (5UL) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTR1_TIM12RST_Pos (6UL) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTR1_TIM13RST_Pos (7UL) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTR1_TIM14RST_Pos (8UL) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9UL) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTR1_WWDGRST_Pos (11UL) +#define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */ +#define RCC_APB1RSTR1_TIM10RST_Pos (12UL) +#define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTR1_TIM11RST_Pos (13UL) +#define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTR1_SPI2RST_Pos (14UL) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTR1_SPI3RST_Pos (15UL) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16UL) +#define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTR1_USART2RST_Pos (17UL) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1RSTR1_USART3RST_Pos (18UL) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1RSTR1_UART4RST_Pos (19UL) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1RSTR1_UART5RST_Pos (20UL) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1RSTR1_I2C1RST_Pos (21UL) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTR1_I2C2RST_Pos (22UL) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTR1_I2C3RST_Pos (23UL) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTR1_I3C1RST_Pos (24UL) +#define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTR1_I3C2RST_Pos (25UL) +#define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTR1_UART7RST_Pos (30UL) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */ +#define RCC_APB1RSTR1_UART8RST_Pos (31UL) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTR2 register *****************/ +#define RCC_APB1RSTR2_MDIOSRST_Pos (5UL) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTR2_FDCANRST_Pos (8UL) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTR2_UCPD1RST_Pos (18UL) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0UL) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (1UL) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (4UL) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_USART6RST_Pos (5UL) +#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ +#define RCC_APB2RSTR_UART9RST_Pos (6UL) +#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */ +#define RCC_APB2RSTR_USART10RST_Pos (7UL) +#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */ +#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12UL) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST_Pos (13UL) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTR_TIM18RST_Pos (15UL) +#define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */ +#define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16UL) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17UL) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18UL) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_TIM9RST_Pos (19UL) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTR_SPI5RST_Pos (20UL) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTR_SAI1RST_Pos (21UL) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST_Pos (22UL) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTR1 register *****************/ +#define RCC_APB4RSTR1_HDPRST_Pos (2UL) +#define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */ +#define RCC_APB4RSTR1_LPUART1RST_Pos (3UL) +#define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTR1_SPI6RST_Pos (5UL) +#define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTR1_I2C4RST_Pos (7UL) +#define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */ +#define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTR1_LPTIM2RST_Pos (9UL) +#define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */ +#define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTR1_LPTIM3RST_Pos (10UL) +#define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */ +#define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTR1_LPTIM4RST_Pos (11UL) +#define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */ +#define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTR1_LPTIM5RST_Pos (12UL) +#define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */ +#define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTR1_VREFBUFRST_Pos (15UL) +#define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTR1_RTCRST_Pos (16UL) +#define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTR2 register *****************/ +#define RCC_APB4RSTR2_SYSCFGRST_Pos (0UL) +#define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */ +#define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTR2_DTSRST_Pos (2UL) +#define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */ + +/***************** Bit definition for RCC_APB5RSTR register *****************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1UL) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2UL) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTR_GFXTIMRST_Pos (4UL) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTR_VENCRST_Pos (5UL) +#define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */ +#define RCC_APB5RSTR_CSIRST_Pos (6UL) +#define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */ + +/****************** Bit definition for RCC_DIVENR register ******************/ +#define RCC_DIVENR_IC1EN_Pos (0UL) +#define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */ +#define RCC_DIVENR_IC2EN_Pos (1UL) +#define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */ +#define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */ +#define RCC_DIVENR_IC3EN_Pos (2UL) +#define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */ +#define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */ +#define RCC_DIVENR_IC4EN_Pos (3UL) +#define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */ +#define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */ +#define RCC_DIVENR_IC5EN_Pos (4UL) +#define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */ +#define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */ +#define RCC_DIVENR_IC6EN_Pos (5UL) +#define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */ +#define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */ +#define RCC_DIVENR_IC7EN_Pos (6UL) +#define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */ +#define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */ +#define RCC_DIVENR_IC8EN_Pos (7UL) +#define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */ +#define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */ +#define RCC_DIVENR_IC9EN_Pos (8UL) +#define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */ +#define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */ +#define RCC_DIVENR_IC10EN_Pos (9UL) +#define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */ +#define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */ +#define RCC_DIVENR_IC11EN_Pos (10UL) +#define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */ +#define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */ +#define RCC_DIVENR_IC12EN_Pos (11UL) +#define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */ +#define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */ +#define RCC_DIVENR_IC13EN_Pos (12UL) +#define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */ +#define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */ +#define RCC_DIVENR_IC14EN_Pos (13UL) +#define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */ +#define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */ +#define RCC_DIVENR_IC15EN_Pos (14UL) +#define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */ +#define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */ +#define RCC_DIVENR_IC16EN_Pos (15UL) +#define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */ +#define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */ +#define RCC_DIVENR_IC17EN_Pos (16UL) +#define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */ +#define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */ +#define RCC_DIVENR_IC18EN_Pos (17UL) +#define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */ +#define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */ +#define RCC_DIVENR_IC19EN_Pos (18UL) +#define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */ +#define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */ +#define RCC_DIVENR_IC20EN_Pos (19UL) +#define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */ +#define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */ + +/****************** Bit definition for RCC_BUSENR register ******************/ +#define RCC_BUSENR_ACLKNEN_Pos (0UL) +#define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */ +#define RCC_BUSENR_ACLKNCEN_Pos (1UL) +#define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */ +#define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */ +#define RCC_BUSENR_AHBMEN_Pos (2UL) +#define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */ +#define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */ +#define RCC_BUSENR_AHB1EN_Pos (3UL) +#define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */ +#define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */ +#define RCC_BUSENR_AHB2EN_Pos (4UL) +#define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */ +#define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */ +#define RCC_BUSENR_AHB3EN_Pos (5UL) +#define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */ +#define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */ +#define RCC_BUSENR_AHB4EN_Pos (6UL) +#define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */ +#define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */ +#define RCC_BUSENR_AHB5EN_Pos (7UL) +#define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */ +#define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */ +#define RCC_BUSENR_APB1EN_Pos (8UL) +#define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */ +#define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */ +#define RCC_BUSENR_APB2EN_Pos (9UL) +#define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */ +#define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */ +#define RCC_BUSENR_APB3EN_Pos (10UL) +#define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */ +#define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */ +#define RCC_BUSENR_APB4EN_Pos (11UL) +#define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */ +#define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */ +#define RCC_BUSENR_APB5EN_Pos (12UL) +#define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */ +#define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENR register ******************/ +#define RCC_MISCENR_DBGEN_Pos (0UL) +#define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */ +#define RCC_MISCENR_MCO1EN_Pos (1UL) +#define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */ +#define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */ +#define RCC_MISCENR_MCO2EN_Pos (2UL) +#define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */ +#define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */ +#define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3UL) +#define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENR_PEREN_Pos (6UL) +#define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */ +#define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */ + +/****************** Bit definition for RCC_MEMENR register ******************/ +#define RCC_MEMENR_AXISRAM3EN_Pos (0UL) +#define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */ +#define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENR_AXISRAM4EN_Pos (1UL) +#define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */ +#define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENR_AXISRAM5EN_Pos (2UL) +#define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */ +#define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENR_AXISRAM6EN_Pos (3UL) +#define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */ +#define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENR_AHBSRAM1EN_Pos (4UL) +#define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */ +#define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENR_AHBSRAM2EN_Pos (5UL) +#define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */ +#define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENR_BKPSRAMEN_Pos (6UL) +#define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENR_AXISRAM1EN_Pos (7UL) +#define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */ +#define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENR_AXISRAM2EN_Pos (8UL) +#define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */ +#define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENR_FLEXRAMEN_Pos (9UL) +#define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENR_VENCRAMEN_Pos (11UL) +#define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMENR_BOOTROMEN_Pos (12UL) +#define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENR register ******************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4UL) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENR_ADC12EN_Pos (5UL) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENR register ******************/ +#define RCC_AHB2ENR_RAMCFGEN_Pos (12UL) +#define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENR_MDF1EN_Pos (16UL) +#define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENR_ADF1EN_Pos (17UL) +#define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENR register ******************/ +#define RCC_AHB3ENR_RNGEN_Pos (0UL) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */ +#define RCC_AHB3ENR_HASHEN_Pos (1UL) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */ +#define RCC_AHB3ENR_PKAEN_Pos (8UL) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */ +#define RCC_AHB3ENR_RIFSCEN_Pos (9UL) +#define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENR_IACEN_Pos (10UL) +#define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */ +#define RCC_AHB3ENR_RISAFEN_Pos (14UL) +#define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENR register ******************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0UL) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENR_GPIOBEN_Pos (1UL) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENR_GPIOCEN_Pos (2UL) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENR_GPIODEN_Pos (3UL) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENR_GPIOEEN_Pos (4UL) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENR_GPIOFEN_Pos (5UL) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENR_GPIOGEN_Pos (6UL) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENR_GPIOHEN_Pos (7UL) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENR_GPIONEN_Pos (13UL) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENR_GPIOOEN_Pos (14UL) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENR_GPIOPEN_Pos (15UL) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENR_GPIOQEN_Pos (16UL) +#define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENR_PWREN_Pos (18UL) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */ +#define RCC_AHB4ENR_CRCEN_Pos (19UL) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENR register ******************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0UL) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENR_DMA2DEN_Pos (1UL) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENR_JPEGEN_Pos (3UL) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */ +#define RCC_AHB5ENR_FMCEN_Pos (4UL) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */ +#define RCC_AHB5ENR_XSPI1EN_Pos (5UL) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENR_PSSIEN_Pos (6UL) +#define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */ +#define RCC_AHB5ENR_SDMMC2EN_Pos (7UL) +#define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENR_SDMMC1EN_Pos (8UL) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENR_XSPI2EN_Pos (12UL) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENR_XSPIMEN_Pos (13UL) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENR_XSPI3EN_Pos (17UL) +#define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENR_GFXMMUEN_Pos (19UL) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENR_GPU2DEN_Pos (20UL) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENR_ETH1MACEN_Pos (22UL) +#define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENR_ETH1TXEN_Pos (23UL) +#define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENR_ETH1RXEN_Pos (24UL) +#define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENR_ETH1EN_Pos (25UL) +#define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENR_OTG1EN_Pos (26UL) +#define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENR_OTGPHY1EN_Pos (27UL) +#define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENR_OTGPHY2EN_Pos (28UL) +#define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENR_OTG2EN_Pos (29UL) +#define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */ + +/***************** Bit definition for RCC_APB1ENR1 register *****************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0UL) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */ +#define RCC_APB1ENR1_TIM3EN_Pos (1UL) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */ +#define RCC_APB1ENR1_TIM4EN_Pos (2UL) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */ +#define RCC_APB1ENR1_TIM5EN_Pos (3UL) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */ +#define RCC_APB1ENR1_TIM6EN_Pos (4UL) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */ +#define RCC_APB1ENR1_TIM7EN_Pos (5UL) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */ +#define RCC_APB1ENR1_TIM12EN_Pos (6UL) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */ +#define RCC_APB1ENR1_TIM13EN_Pos (7UL) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */ +#define RCC_APB1ENR1_TIM14EN_Pos (8UL) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */ +#define RCC_APB1ENR1_LPTIM1EN_Pos (9UL) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENR1_WWDGEN_Pos (11UL) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */ +#define RCC_APB1ENR1_TIM10EN_Pos (12UL) +#define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */ +#define RCC_APB1ENR1_TIM11EN_Pos (13UL) +#define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */ +#define RCC_APB1ENR1_SPI2EN_Pos (14UL) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */ +#define RCC_APB1ENR1_SPI3EN_Pos (15UL) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */ +#define RCC_APB1ENR1_SPDIFRX1EN_Pos (16UL) +#define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENR1_USART2EN_Pos (17UL) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */ +#define RCC_APB1ENR1_USART3EN_Pos (18UL) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */ +#define RCC_APB1ENR1_UART4EN_Pos (19UL) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */ +#define RCC_APB1ENR1_UART5EN_Pos (20UL) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */ +#define RCC_APB1ENR1_I2C1EN_Pos (21UL) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */ +#define RCC_APB1ENR1_I2C2EN_Pos (22UL) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */ +#define RCC_APB1ENR1_I2C3EN_Pos (23UL) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */ +#define RCC_APB1ENR1_I3C1EN_Pos (24UL) +#define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */ +#define RCC_APB1ENR1_I3C2EN_Pos (25UL) +#define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */ +#define RCC_APB1ENR1_UART7EN_Pos (30UL) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */ +#define RCC_APB1ENR1_UART8EN_Pos (31UL) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */ + +/***************** Bit definition for RCC_APB1ENR2 register *****************/ +#define RCC_APB1ENR2_MDIOSEN_Pos (5UL) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */ +#define RCC_APB1ENR2_FDCANEN_Pos (8UL) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */ +#define RCC_APB1ENR2_UCPD1EN_Pos (18UL) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENR register ******************/ +#define RCC_APB2ENR_TIM1EN_Pos (0UL) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */ +#define RCC_APB2ENR_TIM8EN_Pos (1UL) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */ +#define RCC_APB2ENR_USART1EN_Pos (4UL) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */ +#define RCC_APB2ENR_USART6EN_Pos (5UL) +#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */ +#define RCC_APB2ENR_UART9EN_Pos (6UL) +#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */ +#define RCC_APB2ENR_USART10EN_Pos (7UL) +#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12UL) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */ +#define RCC_APB2ENR_SPI4EN_Pos (13UL) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */ +#define RCC_APB2ENR_TIM18EN_Pos (15UL) +#define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16UL) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17UL) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18UL) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */ +#define RCC_APB2ENR_TIM9EN_Pos (19UL) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */ +#define RCC_APB2ENR_SPI5EN_Pos (20UL) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */ +#define RCC_APB2ENR_SAI1EN_Pos (21UL) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */ +#define RCC_APB2ENR_SAI2EN_Pos (22UL) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENR register ******************/ +#define RCC_APB3ENR_DFTEN_Pos (2UL) +#define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */ + +/***************** Bit definition for RCC_APB4ENR1 register *****************/ +#define RCC_APB4ENR1_HDPEN_Pos (2UL) +#define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */ +#define RCC_APB4ENR1_LPUART1EN_Pos (3UL) +#define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENR1_SPI6EN_Pos (5UL) +#define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */ +#define RCC_APB4ENR1_I2C4EN_Pos (7UL) +#define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */ +#define RCC_APB4ENR1_LPTIM2EN_Pos (9UL) +#define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENR1_LPTIM3EN_Pos (10UL) +#define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENR1_LPTIM4EN_Pos (11UL) +#define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENR1_LPTIM5EN_Pos (12UL) +#define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENR1_VREFBUFEN_Pos (15UL) +#define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENR1_RTCEN_Pos (16UL) +#define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */ +#define RCC_APB4ENR1_RTCAPBEN_Pos (17UL) +#define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */ + +/***************** Bit definition for RCC_APB4ENR2 register *****************/ +#define RCC_APB4ENR2_SYSCFGEN_Pos (0UL) +#define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENR2_BSECEN_Pos (1UL) +#define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */ +#define RCC_APB4ENR2_DTSEN_Pos (2UL) +#define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENR register ******************/ +#define RCC_APB5ENR_LTDCEN_Pos (1UL) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */ +#define RCC_APB5ENR_DCMIPPEN_Pos (2UL) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENR_GFXTIMEN_Pos (4UL) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENR_VENCEN_Pos (5UL) +#define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */ +#define RCC_APB5ENR_CSIEN_Pos (6UL) +#define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */ + +/***************** Bit definition for RCC_BUSLPENR register *****************/ +#define RCC_BUSLPENR_ACLKNLPEN_Pos (0UL) +#define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENR_ACLKNCLPEN_Pos (1UL) +#define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */ +#define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENR register *****************/ +#define RCC_MISCLPENR_DBGLPEN_Pos (0UL) +#define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3UL) +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENR_PERLPEN_Pos (6UL) +#define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMLPENR register *****************/ +#define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0UL) +#define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1UL) +#define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2UL) +#define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3UL) +#define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4UL) +#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5UL) +#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6UL) +#define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7UL) +#define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8UL) +#define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9UL) +#define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENR_VENCRAMLPEN_Pos (11UL) +#define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENR_BOOTROMLPEN_Pos (12UL) +#define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENR register *****************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4UL) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5UL) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENR register *****************/ +#define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12UL) +#define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENR_MDF1LPEN_Pos (16UL) +#define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENR_ADF1LPEN_Pos (17UL) +#define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENR register *****************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0UL) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */ +#define RCC_AHB3LPENR_HASHLPEN_Pos (1UL) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */ +#define RCC_AHB3LPENR_PKALPEN_Pos (8UL) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */ +#define RCC_AHB3LPENR_RIFSCLPEN_Pos (9UL) +#define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */ +#define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENR_IACLPEN_Pos (10UL) +#define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */ +#define RCC_AHB3LPENR_RISAFLPEN_Pos (14UL) +#define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENR register *****************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0UL) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1UL) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2UL) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3UL) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4UL) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5UL) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6UL) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7UL) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13UL) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14UL) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15UL) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENR_GPIOQLPEN_Pos (16UL) +#define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */ +#define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENR_PWRLPEN_Pos (18UL) +#define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */ +#define RCC_AHB4LPENR_CRCLPEN_Pos (19UL) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENR register *****************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0UL) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1UL) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3UL) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENR_FMCLPEN_Pos (4UL) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */ +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5UL) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENR_PSSILPEN_Pos (6UL) +#define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7UL) +#define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8UL) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12UL) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (13UL) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENR_XSPI3LPEN_Pos (17UL) +#define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19UL) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20UL) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22UL) +#define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23UL) +#define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24UL) +#define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENR_ETH1LPEN_Pos (25UL) +#define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENR_OTG1LPEN_Pos (26UL) +#define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27UL) +#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28UL) +#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENR_OTG2LPEN_Pos (29UL) +#define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */ + +/**************** Bit definition for RCC_APB1LPENR1 register ****************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0UL) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1UL) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2UL) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3UL) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4UL) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5UL) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6UL) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7UL) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8UL) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9UL) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11UL) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */ +#define RCC_APB1LPENR1_TIM10LPEN_Pos (12UL) +#define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENR1_TIM11LPEN_Pos (13UL) +#define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14UL) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15UL) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16UL) +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENR1_USART2LPEN_Pos (17UL) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */ +#define RCC_APB1LPENR1_USART3LPEN_Pos (18UL) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */ +#define RCC_APB1LPENR1_UART4LPEN_Pos (19UL) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */ +#define RCC_APB1LPENR1_UART5LPEN_Pos (20UL) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */ +#define RCC_APB1LPENR1_I2C1LPEN_Pos (21UL) +#define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22UL) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23UL) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENR1_I3C1LPEN_Pos (24UL) +#define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */ +#define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENR1_I3C2LPEN_Pos (25UL) +#define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */ +#define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENR1_UART7LPEN_Pos (30UL) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */ +#define RCC_APB1LPENR1_UART8LPEN_Pos (31UL) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1LPENR2 register ****************/ +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5UL) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */ +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8UL) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */ +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (18UL) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */ + +/**************** Bit definition for RCC_APB2LPENR register *****************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0UL) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (1UL) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENR_USART1LPEN_Pos (4UL) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */ +#define RCC_APB2LPENR_USART6LPEN_Pos (5UL) +#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */ +#define RCC_APB2LPENR_UART9LPEN_Pos (6UL) +#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */ +#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */ +#define RCC_APB2LPENR_USART10LPEN_Pos (7UL) +#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12UL) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENR_SPI4LPEN_Pos (13UL) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENR_TIM18LPEN_Pos (15UL) +#define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16UL) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17UL) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18UL) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENR_TIM9LPEN_Pos (19UL) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENR_SPI5LPEN_Pos (20UL) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENR_SAI1LPEN_Pos (21UL) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENR_SAI2LPEN_Pos (22UL) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENR register *****************/ +#define RCC_APB3LPENR_DFTLPEN_Pos (2UL) +#define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4LPENR1 register ****************/ +#define RCC_APB4LPENR1_HDPLPEN_Pos (2UL) +#define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */ +#define RCC_APB4LPENR1_LPUART1LPEN_Pos (3UL) +#define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENR1_SPI6LPEN_Pos (5UL) +#define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENR1_I2C4LPEN_Pos (7UL) +#define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */ +#define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9UL) +#define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10UL) +#define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11UL) +#define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12UL) +#define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15UL) +#define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENR1_RTCLPEN_Pos (16UL) +#define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */ +#define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17UL) +#define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4LPENR2 register ****************/ +#define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0UL) +#define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENR2_BSECLPEN_Pos (1UL) +#define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */ +#define RCC_APB4LPENR2_DTSLPEN_Pos (2UL) +#define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENR register *****************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1UL) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2UL) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4UL) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENR_VENCLPEN_Pos (5UL) +#define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */ +#define RCC_APB5LPENR_CSILPEN_Pos (6UL) +#define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */ + +/******************* Bit definition for RCC_RDCR register *******************/ +#define RCC_RDCR_MRD_Pos (16UL) +#define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */ + +/***************** Bit definition for RCC_SECCFGR0 register *****************/ +#define RCC_SECCFGR0_LSISEC_Pos (0UL) +#define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */ +#define RCC_SECCFGR0_LSESEC_Pos (1UL) +#define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */ +#define RCC_SECCFGR0_MSISEC_Pos (2UL) +#define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSISEC_Pos (3UL) +#define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSESEC_Pos (4UL) +#define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR0 register *****************/ +#define RCC_PRIVCFGR0_LSIPRIV_Pos (0UL) +#define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_LSEPRIV_Pos (1UL) +#define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */ +#define RCC_PRIVCFGR0_MSIPRIV_Pos (2UL) +#define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSIPRIV_Pos (3UL) +#define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSEPRIV_Pos (4UL) +#define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR0 register *****************/ +#define RCC_LOCKCFGR0_LSILOCK_Pos (0UL) +#define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_LSELOCK_Pos (1UL) +#define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */ +#define RCC_LOCKCFGR0_MSILOCK_Pos (2UL) +#define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSILOCK_Pos (3UL) +#define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSELOCK_Pos (4UL) +#define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR0 register *****************/ +#define RCC_PUBCFGR0_LSIPUB_Pos (0UL) +#define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */ +#define RCC_PUBCFGR0_LSEPUB_Pos (1UL) +#define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */ +#define RCC_PUBCFGR0_MSIPUB_Pos (2UL) +#define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSIPUB_Pos (3UL) +#define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSEPUB_Pos (4UL) +#define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_SECCFGR1 register *****************/ +#define RCC_SECCFGR1_PLL1SEC_Pos (0UL) +#define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */ +#define RCC_SECCFGR1_PLL2SEC_Pos (1UL) +#define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */ +#define RCC_SECCFGR1_PLL3SEC_Pos (2UL) +#define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */ +#define RCC_SECCFGR1_PLL4SEC_Pos (3UL) +#define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR1 register *****************/ +#define RCC_PRIVCFGR1_PLL1PRIV_Pos (0UL) +#define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */ +#define RCC_PRIVCFGR1_PLL2PRIV_Pos (1UL) +#define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */ +#define RCC_PRIVCFGR1_PLL3PRIV_Pos (2UL) +#define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */ +#define RCC_PRIVCFGR1_PLL4PRIV_Pos (3UL) +#define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR1 register *****************/ +#define RCC_LOCKCFGR1_PLL1LOCK_Pos (0UL) +#define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */ +#define RCC_LOCKCFGR1_PLL2LOCK_Pos (1UL) +#define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */ +#define RCC_LOCKCFGR1_PLL3LOCK_Pos (2UL) +#define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */ +#define RCC_LOCKCFGR1_PLL4LOCK_Pos (3UL) +#define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR1 register *****************/ +#define RCC_PUBCFGR1_PLL1PUB_Pos (0UL) +#define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */ +#define RCC_PUBCFGR1_PLL2PUB_Pos (1UL) +#define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */ +#define RCC_PUBCFGR1_PLL3PUB_Pos (2UL) +#define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */ +#define RCC_PUBCFGR1_PLL4PUB_Pos (3UL) +#define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_SECCFGR2 register *****************/ +#define RCC_SECCFGR2_IC1SEC_Pos (0UL) +#define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */ +#define RCC_SECCFGR2_IC2SEC_Pos (1UL) +#define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */ +#define RCC_SECCFGR2_IC3SEC_Pos (2UL) +#define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */ +#define RCC_SECCFGR2_IC4SEC_Pos (3UL) +#define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */ +#define RCC_SECCFGR2_IC5SEC_Pos (4UL) +#define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */ +#define RCC_SECCFGR2_IC6SEC_Pos (5UL) +#define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */ +#define RCC_SECCFGR2_IC7SEC_Pos (6UL) +#define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */ +#define RCC_SECCFGR2_IC8SEC_Pos (7UL) +#define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */ +#define RCC_SECCFGR2_IC9SEC_Pos (8UL) +#define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */ +#define RCC_SECCFGR2_IC10SEC_Pos (9UL) +#define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */ +#define RCC_SECCFGR2_IC11SEC_Pos (10UL) +#define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */ +#define RCC_SECCFGR2_IC12SEC_Pos (11UL) +#define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */ +#define RCC_SECCFGR2_IC13SEC_Pos (12UL) +#define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */ +#define RCC_SECCFGR2_IC14SEC_Pos (13UL) +#define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */ +#define RCC_SECCFGR2_IC15SEC_Pos (14UL) +#define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */ +#define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */ +#define RCC_SECCFGR2_IC16SEC_Pos (15UL) +#define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */ +#define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */ +#define RCC_SECCFGR2_IC17SEC_Pos (16UL) +#define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */ +#define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */ +#define RCC_SECCFGR2_IC18SEC_Pos (17UL) +#define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */ +#define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */ +#define RCC_SECCFGR2_IC19SEC_Pos (18UL) +#define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */ +#define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */ +#define RCC_SECCFGR2_IC20SEC_Pos (19UL) +#define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */ +#define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR2 register *****************/ +#define RCC_PRIVCFGR2_IC1PRIV_Pos (0UL) +#define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */ +#define RCC_PRIVCFGR2_IC2PRIV_Pos (1UL) +#define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */ +#define RCC_PRIVCFGR2_IC3PRIV_Pos (2UL) +#define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */ +#define RCC_PRIVCFGR2_IC4PRIV_Pos (3UL) +#define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */ +#define RCC_PRIVCFGR2_IC5PRIV_Pos (4UL) +#define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */ +#define RCC_PRIVCFGR2_IC6PRIV_Pos (5UL) +#define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */ +#define RCC_PRIVCFGR2_IC7PRIV_Pos (6UL) +#define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */ +#define RCC_PRIVCFGR2_IC8PRIV_Pos (7UL) +#define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */ +#define RCC_PRIVCFGR2_IC9PRIV_Pos (8UL) +#define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */ +#define RCC_PRIVCFGR2_IC10PRIV_Pos (9UL) +#define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */ +#define RCC_PRIVCFGR2_IC11PRIV_Pos (10UL) +#define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */ +#define RCC_PRIVCFGR2_IC12PRIV_Pos (11UL) +#define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */ +#define RCC_PRIVCFGR2_IC13PRIV_Pos (12UL) +#define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */ +#define RCC_PRIVCFGR2_IC14PRIV_Pos (13UL) +#define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */ +#define RCC_PRIVCFGR2_IC15PRIV_Pos (14UL) +#define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */ +#define RCC_PRIVCFGR2_IC16PRIV_Pos (15UL) +#define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */ +#define RCC_PRIVCFGR2_IC17PRIV_Pos (16UL) +#define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */ +#define RCC_PRIVCFGR2_IC18PRIV_Pos (17UL) +#define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */ +#define RCC_PRIVCFGR2_IC19PRIV_Pos (18UL) +#define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */ +#define RCC_PRIVCFGR2_IC20PRIV_Pos (19UL) +#define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR2 register *****************/ +#define RCC_LOCKCFGR2_IC1LOCK_Pos (0UL) +#define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */ +#define RCC_LOCKCFGR2_IC2LOCK_Pos (1UL) +#define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */ +#define RCC_LOCKCFGR2_IC3LOCK_Pos (2UL) +#define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */ +#define RCC_LOCKCFGR2_IC4LOCK_Pos (3UL) +#define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */ +#define RCC_LOCKCFGR2_IC5LOCK_Pos (4UL) +#define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */ +#define RCC_LOCKCFGR2_IC6LOCK_Pos (5UL) +#define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */ +#define RCC_LOCKCFGR2_IC7LOCK_Pos (6UL) +#define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */ +#define RCC_LOCKCFGR2_IC8LOCK_Pos (7UL) +#define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */ +#define RCC_LOCKCFGR2_IC9LOCK_Pos (8UL) +#define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */ +#define RCC_LOCKCFGR2_IC10LOCK_Pos (9UL) +#define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */ +#define RCC_LOCKCFGR2_IC11LOCK_Pos (10UL) +#define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */ +#define RCC_LOCKCFGR2_IC12LOCK_Pos (11UL) +#define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */ +#define RCC_LOCKCFGR2_IC13LOCK_Pos (12UL) +#define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */ +#define RCC_LOCKCFGR2_IC14LOCK_Pos (13UL) +#define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */ +#define RCC_LOCKCFGR2_IC15LOCK_Pos (14UL) +#define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */ +#define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */ +#define RCC_LOCKCFGR2_IC16LOCK_Pos (15UL) +#define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */ +#define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */ +#define RCC_LOCKCFGR2_IC17LOCK_Pos (16UL) +#define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */ +#define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */ +#define RCC_LOCKCFGR2_IC18LOCK_Pos (17UL) +#define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */ +#define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */ +#define RCC_LOCKCFGR2_IC19LOCK_Pos (18UL) +#define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */ +#define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */ +#define RCC_LOCKCFGR2_IC20LOCK_Pos (19UL) +#define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */ +#define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR2 register *****************/ +#define RCC_PUBCFGR2_IC1PUB_Pos (0UL) +#define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */ +#define RCC_PUBCFGR2_IC2PUB_Pos (1UL) +#define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */ +#define RCC_PUBCFGR2_IC3PUB_Pos (2UL) +#define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */ +#define RCC_PUBCFGR2_IC4PUB_Pos (3UL) +#define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */ +#define RCC_PUBCFGR2_IC5PUB_Pos (4UL) +#define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */ +#define RCC_PUBCFGR2_IC6PUB_Pos (5UL) +#define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */ +#define RCC_PUBCFGR2_IC7PUB_Pos (6UL) +#define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */ +#define RCC_PUBCFGR2_IC8PUB_Pos (7UL) +#define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */ +#define RCC_PUBCFGR2_IC9PUB_Pos (8UL) +#define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */ +#define RCC_PUBCFGR2_IC10PUB_Pos (9UL) +#define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */ +#define RCC_PUBCFGR2_IC11PUB_Pos (10UL) +#define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */ +#define RCC_PUBCFGR2_IC12PUB_Pos (11UL) +#define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */ +#define RCC_PUBCFGR2_IC13PUB_Pos (12UL) +#define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */ +#define RCC_PUBCFGR2_IC14PUB_Pos (13UL) +#define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */ +#define RCC_PUBCFGR2_IC15PUB_Pos (14UL) +#define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */ +#define RCC_PUBCFGR2_IC16PUB_Pos (15UL) +#define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */ +#define RCC_PUBCFGR2_IC17PUB_Pos (16UL) +#define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */ +#define RCC_PUBCFGR2_IC18PUB_Pos (17UL) +#define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */ +#define RCC_PUBCFGR2_IC19PUB_Pos (18UL) +#define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */ +#define RCC_PUBCFGR2_IC20PUB_Pos (19UL) +#define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_SECCFGR3 register *****************/ +#define RCC_SECCFGR3_MODSEC_Pos (0UL) +#define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */ +#define RCC_SECCFGR3_SYSSEC_Pos (1UL) +#define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */ +#define RCC_SECCFGR3_BUSSEC_Pos (2UL) +#define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */ +#define RCC_SECCFGR3_PERSEC_Pos (3UL) +#define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */ +#define RCC_SECCFGR3_INTSEC_Pos (4UL) +#define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */ +#define RCC_SECCFGR3_RSTSEC_Pos (5UL) +#define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR3 register *****************/ +#define RCC_PRIVCFGR3_MODPRIV_Pos (0UL) +#define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */ +#define RCC_PRIVCFGR3_SYSPRIV_Pos (1UL) +#define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */ +#define RCC_PRIVCFGR3_BUSPRIV_Pos (2UL) +#define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */ +#define RCC_PRIVCFGR3_PERPRIV_Pos (3UL) +#define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */ +#define RCC_PRIVCFGR3_INTPRIV_Pos (4UL) +#define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */ +#define RCC_PRIVCFGR3_RSTPRIV_Pos (5UL) +#define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR3 register *****************/ +#define RCC_LOCKCFGR3_MODLOCK_Pos (0UL) +#define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */ +#define RCC_LOCKCFGR3_SYSLOCK_Pos (1UL) +#define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */ +#define RCC_LOCKCFGR3_BUSLOCK_Pos (2UL) +#define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */ +#define RCC_LOCKCFGR3_PERLOCK_Pos (3UL) +#define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */ +#define RCC_LOCKCFGR3_INTLOCK_Pos (4UL) +#define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */ +#define RCC_LOCKCFGR3_RSTLOCK_Pos (5UL) +#define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR3 register *****************/ +#define RCC_PUBCFGR3_MODPUB_Pos (0UL) +#define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */ +#define RCC_PUBCFGR3_SYSPUB_Pos (1UL) +#define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */ +#define RCC_PUBCFGR3_BUSPUB_Pos (2UL) +#define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */ +#define RCC_PUBCFGR3_PERPUB_Pos (3UL) +#define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */ +#define RCC_PUBCFGR3_INTPUB_Pos (4UL) +#define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */ +#define RCC_PUBCFGR3_RSTPUB_Pos (5UL) +#define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */ + +/***************** Bit definition for RCC_SECCFGR4 register *****************/ +#define RCC_SECCFGR4_ACLKNSEC_Pos (0UL) +#define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */ +#define RCC_SECCFGR4_ACLKNCSEC_Pos (1UL) +#define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */ +#define RCC_SECCFGR4_AHBMSEC_Pos (2UL) +#define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */ +#define RCC_SECCFGR4_AHB1SEC_Pos (3UL) +#define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */ +#define RCC_SECCFGR4_AHB2SEC_Pos (4UL) +#define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */ +#define RCC_SECCFGR4_AHB3SEC_Pos (5UL) +#define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */ +#define RCC_SECCFGR4_AHB4SEC_Pos (6UL) +#define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */ +#define RCC_SECCFGR4_AHB5SEC_Pos (7UL) +#define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */ +#define RCC_SECCFGR4_APB1SEC_Pos (8UL) +#define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */ +#define RCC_SECCFGR4_APB2SEC_Pos (9UL) +#define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */ +#define RCC_SECCFGR4_APB3SEC_Pos (10UL) +#define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */ +#define RCC_SECCFGR4_APB4SEC_Pos (11UL) +#define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */ +#define RCC_SECCFGR4_APB5SEC_Pos (12UL) +#define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */ +#define RCC_SECCFGR4_NOCSEC_Pos (13UL) +#define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR4 register *****************/ +#define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0UL) +#define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */ +#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1UL) +#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */ +#define RCC_PRIVCFGR4_AHBMPRIV_Pos (2UL) +#define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */ +#define RCC_PRIVCFGR4_AHB1PRIV_Pos (3UL) +#define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB2PRIV_Pos (4UL) +#define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB3PRIV_Pos (5UL) +#define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB4PRIV_Pos (6UL) +#define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB5PRIV_Pos (7UL) +#define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */ +#define RCC_PRIVCFGR4_APB1PRIV_Pos (8UL) +#define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */ +#define RCC_PRIVCFGR4_APB2PRIV_Pos (9UL) +#define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */ +#define RCC_PRIVCFGR4_APB3PRIV_Pos (10UL) +#define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */ +#define RCC_PRIVCFGR4_APB4PRIV_Pos (11UL) +#define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */ +#define RCC_PRIVCFGR4_APB5PRIV_Pos (12UL) +#define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */ +#define RCC_PRIVCFGR4_NOCPRIV_Pos (13UL) +#define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR4 register *****************/ +#define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0UL) +#define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */ +#define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */ +#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1UL) +#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */ +#define RCC_LOCKCFGR4_AHBMLOCK_Pos (2UL) +#define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */ +#define RCC_LOCKCFGR4_AHB1LOCK_Pos (3UL) +#define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB2LOCK_Pos (4UL) +#define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB3LOCK_Pos (5UL) +#define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB4LOCK_Pos (6UL) +#define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB5LOCK_Pos (7UL) +#define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */ +#define RCC_LOCKCFGR4_APB1LOCK_Pos (8UL) +#define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */ +#define RCC_LOCKCFGR4_APB2LOCK_Pos (9UL) +#define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */ +#define RCC_LOCKCFGR4_APB3LOCK_Pos (10UL) +#define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */ +#define RCC_LOCKCFGR4_APB4LOCK_Pos (11UL) +#define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */ +#define RCC_LOCKCFGR4_APB5LOCK_Pos (12UL) +#define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */ +#define RCC_LOCKCFGR4_NOCLOCK_Pos (13UL) +#define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR4 register *****************/ +#define RCC_PUBCFGR4_ACLKNPUB_Pos (0UL) +#define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */ +#define RCC_PUBCFGR4_ACLKNCPUB_Pos (1UL) +#define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */ +#define RCC_PUBCFGR4_AHBMPUB_Pos (2UL) +#define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */ +#define RCC_PUBCFGR4_AHB1PUB_Pos (3UL) +#define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */ +#define RCC_PUBCFGR4_AHB2PUB_Pos (4UL) +#define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */ +#define RCC_PUBCFGR4_AHB3PUB_Pos (5UL) +#define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */ +#define RCC_PUBCFGR4_AHB4PUB_Pos (6UL) +#define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */ +#define RCC_PUBCFGR4_AHB5PUB_Pos (7UL) +#define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */ +#define RCC_PUBCFGR4_APB1PUB_Pos (8UL) +#define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */ +#define RCC_PUBCFGR4_APB2PUB_Pos (9UL) +#define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */ +#define RCC_PUBCFGR4_APB3PUB_Pos (10UL) +#define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */ +#define RCC_PUBCFGR4_APB4PUB_Pos (11UL) +#define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */ +#define RCC_PUBCFGR4_APB5PUB_Pos (12UL) +#define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */ +#define RCC_PUBCFGR4_NOCPUB_Pos (13UL) +#define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR5 register *****************/ +#define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0UL) +#define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1UL) +#define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2UL) +#define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3UL) +#define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4UL) +#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5UL) +#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6UL) +#define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */ +#define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7UL) +#define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8UL) +#define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9UL) +#define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */ +#define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */ +#define RCC_PUBCFGR5_VENCRAMPUB_Pos (11UL) +#define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */ +#define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSIONS_Pos (0UL) +#define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */ +#define RCC_CSR_LSEONS_Pos (1UL) +#define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */ +#define RCC_CSR_MSIONS_Pos (2UL) +#define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */ +#define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */ +#define RCC_CSR_HSIONS_Pos (3UL) +#define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */ +#define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */ +#define RCC_CSR_HSEONS_Pos (4UL) +#define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */ +#define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */ +#define RCC_CSR_PLL1ONS_Pos (8UL) +#define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */ +#define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */ +#define RCC_CSR_PLL2ONS_Pos (9UL) +#define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */ +#define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */ +#define RCC_CSR_PLL3ONS_Pos (10UL) +#define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */ +#define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */ +#define RCC_CSR_PLL4ONS_Pos (11UL) +#define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */ +#define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCSR register ******************/ +#define RCC_STOPCSR_MSISTOPENS_Pos (0UL) +#define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */ +#define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCSR_HSISTOPENS_Pos (1UL) +#define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */ +#define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTSR register *****************/ +#define RCC_MISCRSTSR_DBGRSTS_Pos (0UL) +#define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4UL) +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5UL) +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7UL) +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8UL) +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTSR register *****************/ +#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0UL) +#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1UL) +#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2UL) +#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3UL) +#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4UL) +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5UL) +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7UL) +#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8UL) +#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9UL) +#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11UL) +#define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12UL) +#define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTSR register *****************/ +#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4UL) +#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTSR_ADC12RSTS_Pos (5UL) +#define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTSR register *****************/ +#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12UL) +#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTSR_MDF1RSTS_Pos (16UL) +#define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTSR_ADF1RSTS_Pos (17UL) +#define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTSR register *****************/ +#define RCC_AHB3RSTSR_RNGRSTS_Pos (0UL) +#define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */ +#define RCC_AHB3RSTSR_HASHRSTS_Pos (1UL) +#define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */ +#define RCC_AHB3RSTSR_PKARSTS_Pos (8UL) +#define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */ +#define RCC_AHB3RSTSR_IACRSTS_Pos (10UL) +#define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTSR register *****************/ +#define RCC_AHB4RSTSR_GPIOARSTS_Pos (0UL) +#define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1UL) +#define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2UL) +#define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTSR_GPIODRSTS_Pos (3UL) +#define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTSR_GPIOERSTS_Pos (4UL) +#define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5UL) +#define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6UL) +#define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7UL) +#define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTSR_GPIONRSTS_Pos (13UL) +#define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTSR_GPIOORSTS_Pos (14UL) +#define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15UL) +#define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16UL) +#define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTSR_PWRRSTS_Pos (18UL) +#define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */ +#define RCC_AHB4RSTSR_CRCRSTS_Pos (19UL) +#define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTSR register *****************/ +#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0UL) +#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1UL) +#define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTSR_JPEGRSTS_Pos (3UL) +#define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTSR_FMCRSTS_Pos (4UL) +#define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */ +#define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5UL) +#define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTSR_PSSIRSTS_Pos (6UL) +#define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7UL) +#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8UL) +#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12UL) +#define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13UL) +#define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17UL) +#define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19UL) +#define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20UL) +#define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23UL) +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24UL) +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTSR_ETH1RSTS_Pos (25UL) +#define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTSR_OTG1RSTS_Pos (26UL) +#define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27UL) +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28UL) +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTSR_OTG2RSTS_Pos (29UL) +#define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */ + +/**************** Bit definition for RCC_APB1RSTSR1 register ****************/ +#define RCC_APB1RSTSR1_TIM2RSTS_Pos (0UL) +#define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTSR1_TIM3RSTS_Pos (1UL) +#define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTSR1_TIM4RSTS_Pos (2UL) +#define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTSR1_TIM5RSTS_Pos (3UL) +#define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTSR1_TIM6RSTS_Pos (4UL) +#define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTSR1_TIM7RSTS_Pos (5UL) +#define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTSR1_TIM12RSTS_Pos (6UL) +#define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTSR1_TIM13RSTS_Pos (7UL) +#define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTSR1_TIM14RSTS_Pos (8UL) +#define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9UL) +#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTSR1_WWDGRSTS_Pos (11UL) +#define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */ +#define RCC_APB1RSTSR1_TIM10RSTS_Pos (12UL) +#define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTSR1_TIM11RSTS_Pos (13UL) +#define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTSR1_SPI2RSTS_Pos (14UL) +#define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTSR1_SPI3RSTS_Pos (15UL) +#define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16UL) +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTSR1_USART2RSTS_Pos (17UL) +#define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */ +#define RCC_APB1RSTSR1_USART3RSTS_Pos (18UL) +#define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */ +#define RCC_APB1RSTSR1_UART4RSTS_Pos (19UL) +#define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */ +#define RCC_APB1RSTSR1_UART5RSTS_Pos (20UL) +#define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */ +#define RCC_APB1RSTSR1_I2C1RSTS_Pos (21UL) +#define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTSR1_I2C2RSTS_Pos (22UL) +#define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTSR1_I2C3RSTS_Pos (23UL) +#define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTSR1_I3C1RSTS_Pos (24UL) +#define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTSR1_I3C2RSTS_Pos (25UL) +#define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTSR1_UART7RSTS_Pos (30UL) +#define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */ +#define RCC_APB1RSTSR1_UART8RSTS_Pos (31UL) +#define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTSR2 register ****************/ +#define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5UL) +#define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTSR2_FDCANRSTS_Pos (8UL) +#define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18UL) +#define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTSR register *****************/ +#define RCC_APB2RSTSR_TIM1RSTS_Pos (0UL) +#define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTSR_TIM8RSTS_Pos (1UL) +#define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTSR_USART1RSTS_Pos (4UL) +#define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */ +#define RCC_APB2RSTSR_USART6RSTS_Pos (5UL) +#define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */ +#define RCC_APB2RSTSR_UART9RSTS_Pos (6UL) +#define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */ +#define RCC_APB2RSTSR_USART10RSTS_Pos (7UL) +#define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */ +#define RCC_APB2RSTSR_SPI1RSTS_Pos (12UL) +#define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTSR_SPI4RSTS_Pos (13UL) +#define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTSR_TIM18RSTS_Pos (15UL) +#define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTSR_TIM15RSTS_Pos (16UL) +#define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTSR_TIM16RSTS_Pos (17UL) +#define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTSR_TIM17RSTS_Pos (18UL) +#define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTSR_TIM9RSTS_Pos (19UL) +#define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTSR_SPI5RSTS_Pos (20UL) +#define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTSR_SAI1RSTS_Pos (21UL) +#define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTSR_SAI2RSTS_Pos (22UL) +#define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTSR1 register ****************/ +#define RCC_APB4RSTSR1_HDPRSTS_Pos (2UL) +#define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */ +#define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3UL) +#define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTSR1_SPI6RSTS_Pos (5UL) +#define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTSR1_I2C4RSTS_Pos (7UL) +#define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9UL) +#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10UL) +#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11UL) +#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12UL) +#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15UL) +#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTSR1_RTCRSTS_Pos (16UL) +#define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTSR2 register ****************/ +#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0UL) +#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTSR2_DTSRSTS_Pos (2UL) +#define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTSR register *****************/ +#define RCC_APB5RSTSR_LTDCRSTS_Pos (1UL) +#define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */ +#define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2UL) +#define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4UL) +#define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTSR_VENCRSTS_Pos (5UL) +#define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */ +#define RCC_APB5RSTSR_CSIRSTS_Pos (6UL) +#define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENSR register ******************/ +#define RCC_DIVENSR_IC1ENS_Pos (0UL) +#define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */ +#define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */ +#define RCC_DIVENSR_IC2ENS_Pos (1UL) +#define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */ +#define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */ +#define RCC_DIVENSR_IC3ENS_Pos (2UL) +#define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */ +#define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */ +#define RCC_DIVENSR_IC4ENS_Pos (3UL) +#define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */ +#define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */ +#define RCC_DIVENSR_IC5ENS_Pos (4UL) +#define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */ +#define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */ +#define RCC_DIVENSR_IC6ENS_Pos (5UL) +#define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */ +#define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */ +#define RCC_DIVENSR_IC7ENS_Pos (6UL) +#define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */ +#define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */ +#define RCC_DIVENSR_IC8ENS_Pos (7UL) +#define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */ +#define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */ +#define RCC_DIVENSR_IC9ENS_Pos (8UL) +#define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */ +#define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */ +#define RCC_DIVENSR_IC10ENS_Pos (9UL) +#define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */ +#define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */ +#define RCC_DIVENSR_IC11ENS_Pos (10UL) +#define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */ +#define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */ +#define RCC_DIVENSR_IC12ENS_Pos (11UL) +#define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */ +#define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */ +#define RCC_DIVENSR_IC13ENS_Pos (12UL) +#define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */ +#define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */ +#define RCC_DIVENSR_IC14ENS_Pos (13UL) +#define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */ +#define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */ +#define RCC_DIVENSR_IC15ENS_Pos (14UL) +#define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */ +#define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */ +#define RCC_DIVENSR_IC16ENS_Pos (15UL) +#define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */ +#define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */ +#define RCC_DIVENSR_IC17ENS_Pos (16UL) +#define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */ +#define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */ +#define RCC_DIVENSR_IC18ENS_Pos (17UL) +#define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */ +#define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */ +#define RCC_DIVENSR_IC19ENS_Pos (18UL) +#define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */ +#define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */ +#define RCC_DIVENSR_IC20ENS_Pos (19UL) +#define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */ +#define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENSR register ******************/ +#define RCC_BUSENSR_ACLKNENS_Pos (0UL) +#define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */ +#define RCC_BUSENSR_ACLKNCENS_Pos (1UL) +#define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */ +#define RCC_BUSENSR_AHBMENS_Pos (2UL) +#define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */ +#define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */ +#define RCC_BUSENSR_AHB1ENS_Pos (3UL) +#define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */ +#define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */ +#define RCC_BUSENSR_AHB2ENS_Pos (4UL) +#define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */ +#define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */ +#define RCC_BUSENSR_AHB3ENS_Pos (5UL) +#define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */ +#define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */ +#define RCC_BUSENSR_AHB4ENS_Pos (6UL) +#define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */ +#define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */ +#define RCC_BUSENSR_AHB5ENS_Pos (7UL) +#define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */ +#define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */ +#define RCC_BUSENSR_APB1ENS_Pos (8UL) +#define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */ +#define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */ +#define RCC_BUSENSR_APB2ENS_Pos (9UL) +#define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */ +#define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */ +#define RCC_BUSENSR_APB3ENS_Pos (10UL) +#define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */ +#define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */ +#define RCC_BUSENSR_APB4ENS_Pos (11UL) +#define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */ +#define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */ +#define RCC_BUSENSR_APB5ENS_Pos (12UL) +#define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */ +#define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENSR register *****************/ +#define RCC_MISCENSR_DBGENS_Pos (0UL) +#define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */ +#define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */ +#define RCC_MISCENSR_MCO1ENS_Pos (1UL) +#define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */ +#define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */ +#define RCC_MISCENSR_MCO2ENS_Pos (2UL) +#define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */ +#define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */ +#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3UL) +#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENSR_PERENS_Pos (6UL) +#define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */ +#define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENSR register ******************/ +#define RCC_MEMENSR_AXISRAM3ENS_Pos (0UL) +#define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */ +#define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENSR_AXISRAM4ENS_Pos (1UL) +#define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */ +#define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENSR_AXISRAM5ENS_Pos (2UL) +#define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */ +#define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENSR_AXISRAM6ENS_Pos (3UL) +#define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */ +#define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENSR_AHBSRAM1ENS_Pos (4UL) +#define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */ +#define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENSR_AHBSRAM2ENS_Pos (5UL) +#define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */ +#define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENSR_BKPSRAMENS_Pos (6UL) +#define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENSR_AXISRAM1ENS_Pos (7UL) +#define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */ +#define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENSR_AXISRAM2ENS_Pos (8UL) +#define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */ +#define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENSR_FLEXRAMENS_Pos (9UL) +#define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENSR_VENCRAMENS_Pos (11UL) +#define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMENSR_BOOTROMENS_Pos (12UL) +#define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENSR register *****************/ +#define RCC_AHB1ENSR_GPDMA1ENS_Pos (4UL) +#define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENSR_ADC12ENS_Pos (5UL) +#define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENSR register *****************/ +#define RCC_AHB2ENSR_RAMCFGENS_Pos (12UL) +#define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENSR_MDF1ENS_Pos (16UL) +#define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENSR_ADF1ENS_Pos (17UL) +#define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENSR register *****************/ +#define RCC_AHB3ENSR_RNGENS_Pos (0UL) +#define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */ +#define RCC_AHB3ENSR_HASHENS_Pos (1UL) +#define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */ +#define RCC_AHB3ENSR_PKAENS_Pos (8UL) +#define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */ +#define RCC_AHB3ENSR_RIFSCENS_Pos (9UL) +#define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENSR_IACENS_Pos (10UL) +#define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */ +#define RCC_AHB3ENSR_RISAFENS_Pos (14UL) +#define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENSR register *****************/ +#define RCC_AHB4ENSR_GPIOAENS_Pos (0UL) +#define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENSR_GPIOBENS_Pos (1UL) +#define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENSR_GPIOCENS_Pos (2UL) +#define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENSR_GPIODENS_Pos (3UL) +#define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENSR_GPIOEENS_Pos (4UL) +#define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENSR_GPIOFENS_Pos (5UL) +#define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENSR_GPIOGENS_Pos (6UL) +#define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENSR_GPIOHENS_Pos (7UL) +#define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENSR_GPIONENS_Pos (13UL) +#define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENSR_GPIOOENS_Pos (14UL) +#define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENSR_GPIOPENS_Pos (15UL) +#define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENSR_GPIOQENS_Pos (16UL) +#define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENSR_PWRENS_Pos (18UL) +#define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */ +#define RCC_AHB4ENSR_CRCENS_Pos (19UL) +#define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENSR register *****************/ +#define RCC_AHB5ENSR_HPDMA1ENS_Pos (0UL) +#define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENSR_DMA2DENS_Pos (1UL) +#define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENSR_JPEGENS_Pos (3UL) +#define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */ +#define RCC_AHB5ENSR_FMCENS_Pos (4UL) +#define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */ +#define RCC_AHB5ENSR_XSPI1ENS_Pos (5UL) +#define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENSR_PSSIENS_Pos (6UL) +#define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */ +#define RCC_AHB5ENSR_SDMMC2ENS_Pos (7UL) +#define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENSR_SDMMC1ENS_Pos (8UL) +#define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENSR_XSPI2ENS_Pos (12UL) +#define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENSR_XSPIMENS_Pos (13UL) +#define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENSR_XSPI3ENS_Pos (17UL) +#define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENSR_GFXMMUENS_Pos (19UL) +#define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENSR_GPU2DENS_Pos (20UL) +#define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENSR_ETH1MACENS_Pos (22UL) +#define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENSR_ETH1TXENS_Pos (23UL) +#define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENSR_ETH1RXENS_Pos (24UL) +#define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENSR_ETH1ENS_Pos (25UL) +#define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENSR_OTG1ENS_Pos (26UL) +#define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27UL) +#define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28UL) +#define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENSR_OTG2ENS_Pos (29UL) +#define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */ + +/**************** Bit definition for RCC_APB1ENSR1 register *****************/ +#define RCC_APB1ENSR1_TIM2ENS_Pos (0UL) +#define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */ +#define RCC_APB1ENSR1_TIM3ENS_Pos (1UL) +#define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */ +#define RCC_APB1ENSR1_TIM4ENS_Pos (2UL) +#define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */ +#define RCC_APB1ENSR1_TIM5ENS_Pos (3UL) +#define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */ +#define RCC_APB1ENSR1_TIM6ENS_Pos (4UL) +#define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */ +#define RCC_APB1ENSR1_TIM7ENS_Pos (5UL) +#define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */ +#define RCC_APB1ENSR1_TIM12ENS_Pos (6UL) +#define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */ +#define RCC_APB1ENSR1_TIM13ENS_Pos (7UL) +#define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */ +#define RCC_APB1ENSR1_TIM14ENS_Pos (8UL) +#define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */ +#define RCC_APB1ENSR1_LPTIM1ENS_Pos (9UL) +#define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENSR1_WWDGENS_Pos (11UL) +#define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */ +#define RCC_APB1ENSR1_TIM10ENS_Pos (12UL) +#define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */ +#define RCC_APB1ENSR1_TIM11ENS_Pos (13UL) +#define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */ +#define RCC_APB1ENSR1_SPI2ENS_Pos (14UL) +#define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */ +#define RCC_APB1ENSR1_SPI3ENS_Pos (15UL) +#define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */ +#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16UL) +#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENSR1_USART2ENS_Pos (17UL) +#define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */ +#define RCC_APB1ENSR1_USART3ENS_Pos (18UL) +#define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */ +#define RCC_APB1ENSR1_UART4ENS_Pos (19UL) +#define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */ +#define RCC_APB1ENSR1_UART5ENS_Pos (20UL) +#define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */ +#define RCC_APB1ENSR1_I2C1ENS_Pos (21UL) +#define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */ +#define RCC_APB1ENSR1_I2C2ENS_Pos (22UL) +#define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */ +#define RCC_APB1ENSR1_I2C3ENS_Pos (23UL) +#define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */ +#define RCC_APB1ENSR1_I3C1ENS_Pos (24UL) +#define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */ +#define RCC_APB1ENSR1_I3C2ENS_Pos (25UL) +#define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */ +#define RCC_APB1ENSR1_UART7ENS_Pos (30UL) +#define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */ +#define RCC_APB1ENSR1_UART8ENS_Pos (31UL) +#define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENSR2 register *****************/ +#define RCC_APB1ENSR2_MDIOSENS_Pos (5UL) +#define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */ +#define RCC_APB1ENSR2_FDCANENS_Pos (8UL) +#define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */ +#define RCC_APB1ENSR2_UCPD1ENS_Pos (18UL) +#define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENSR register *****************/ +#define RCC_APB2ENSR_TIM1ENS_Pos (0UL) +#define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */ +#define RCC_APB2ENSR_TIM8ENS_Pos (1UL) +#define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */ +#define RCC_APB2ENSR_USART1ENS_Pos (4UL) +#define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */ +#define RCC_APB2ENSR_USART6ENS_Pos (5UL) +#define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */ +#define RCC_APB2ENSR_UART9ENS_Pos (6UL) +#define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */ +#define RCC_APB2ENSR_USART10ENS_Pos (7UL) +#define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */ +#define RCC_APB2ENSR_SPI1ENS_Pos (12UL) +#define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */ +#define RCC_APB2ENSR_SPI4ENS_Pos (13UL) +#define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */ +#define RCC_APB2ENSR_TIM18ENS_Pos (15UL) +#define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */ +#define RCC_APB2ENSR_TIM15ENS_Pos (16UL) +#define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */ +#define RCC_APB2ENSR_TIM16ENS_Pos (17UL) +#define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */ +#define RCC_APB2ENSR_TIM17ENS_Pos (18UL) +#define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */ +#define RCC_APB2ENSR_TIM9ENS_Pos (19UL) +#define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */ +#define RCC_APB2ENSR_SPI5ENS_Pos (20UL) +#define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */ +#define RCC_APB2ENSR_SAI1ENS_Pos (21UL) +#define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */ +#define RCC_APB2ENSR_SAI2ENS_Pos (22UL) +#define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENSR register *****************/ +#define RCC_APB3ENSR_DFTENS_Pos (2UL) +#define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENSR1 register *****************/ +#define RCC_APB4ENSR1_HDPENS_Pos (2UL) +#define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */ +#define RCC_APB4ENSR1_LPUART1ENS_Pos (3UL) +#define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENSR1_SPI6ENS_Pos (5UL) +#define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */ +#define RCC_APB4ENSR1_I2C4ENS_Pos (7UL) +#define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */ +#define RCC_APB4ENSR1_LPTIM2ENS_Pos (9UL) +#define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENSR1_LPTIM3ENS_Pos (10UL) +#define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENSR1_LPTIM4ENS_Pos (11UL) +#define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENSR1_LPTIM5ENS_Pos (12UL) +#define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENSR1_VREFBUFENS_Pos (15UL) +#define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENSR1_RTCENS_Pos (16UL) +#define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */ +#define RCC_APB4ENSR1_RTCAPBENS_Pos (17UL) +#define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENSR2 register *****************/ +#define RCC_APB4ENSR2_SYSCFGENS_Pos (0UL) +#define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENSR2_BSECENS_Pos (1UL) +#define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */ +#define RCC_APB4ENSR2_DTSENS_Pos (2UL) +#define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENSR register *****************/ +#define RCC_APB5ENSR_LTDCENS_Pos (1UL) +#define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */ +#define RCC_APB5ENSR_DCMIPPENS_Pos (2UL) +#define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENSR_GFXTIMENS_Pos (4UL) +#define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENSR_VENCENS_Pos (5UL) +#define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */ +#define RCC_APB5ENSR_CSIENS_Pos (6UL) +#define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENSR register *****************/ +#define RCC_BUSLPENSR_ACLKNLPENS_Pos (0UL) +#define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1UL) +#define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENSR register ****************/ +#define RCC_MISCLPENSR_DBGLPENS_Pos (0UL) +#define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3UL) +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENSR_PERLPENS_Pos (6UL) +#define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */ + +/**************** Bit definition for RCC_MEMLPENSR register *****************/ +#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0UL) +#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1UL) +#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2UL) +#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3UL) +#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4UL) +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5UL) +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6UL) +#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7UL) +#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8UL) +#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9UL) +#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11UL) +#define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12UL) +#define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENSR register ****************/ +#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4UL) +#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENSR_ADC12LPENS_Pos (5UL) +#define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENSR register ****************/ +#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12UL) +#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENSR_MDF1LPENS_Pos (16UL) +#define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENSR_ADF1LPENS_Pos (17UL) +#define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENSR register ****************/ +#define RCC_AHB3LPENSR_RNGLPENS_Pos (0UL) +#define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */ +#define RCC_AHB3LPENSR_HASHLPENS_Pos (1UL) +#define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */ +#define RCC_AHB3LPENSR_PKALPENS_Pos (8UL) +#define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */ +#define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9UL) +#define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENSR_IACLPENS_Pos (10UL) +#define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENSR_RISAFLPENS_Pos (14UL) +#define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENSR register ****************/ +#define RCC_AHB4LPENSR_GPIOALPENS_Pos (0UL) +#define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1UL) +#define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2UL) +#define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENSR_GPIODLPENS_Pos (3UL) +#define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENSR_GPIOELPENS_Pos (4UL) +#define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5UL) +#define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6UL) +#define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7UL) +#define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENSR_GPIONLPENS_Pos (13UL) +#define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14UL) +#define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15UL) +#define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16UL) +#define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENSR_PWRLPENS_Pos (18UL) +#define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */ +#define RCC_AHB4LPENSR_CRCLPENS_Pos (19UL) +#define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENSR register ****************/ +#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0UL) +#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1UL) +#define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENSR_JPEGLPENS_Pos (3UL) +#define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENSR_FMCLPENS_Pos (4UL) +#define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */ +#define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5UL) +#define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENSR_PSSILPENS_Pos (6UL) +#define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7UL) +#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8UL) +#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12UL) +#define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13UL) +#define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17UL) +#define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19UL) +#define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20UL) +#define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22UL) +#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23UL) +#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24UL) +#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENSR_ETH1LPENS_Pos (25UL) +#define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENSR_OTG1LPENS_Pos (26UL) +#define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27UL) +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28UL) +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENSR_OTG2LPENS_Pos (29UL) +#define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */ + +/*************** Bit definition for RCC_APB1LPENSR1 register ****************/ +#define RCC_APB1LPENSR1_TIM2LPENS_Pos (0UL) +#define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENSR1_TIM3LPENS_Pos (1UL) +#define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENSR1_TIM4LPENS_Pos (2UL) +#define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENSR1_TIM5LPENS_Pos (3UL) +#define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENSR1_TIM6LPENS_Pos (4UL) +#define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENSR1_TIM7LPENS_Pos (5UL) +#define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENSR1_TIM12LPENS_Pos (6UL) +#define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENSR1_TIM13LPENS_Pos (7UL) +#define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENSR1_TIM14LPENS_Pos (8UL) +#define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9UL) +#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENSR1_WWDGLPENS_Pos (11UL) +#define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */ +#define RCC_APB1LPENSR1_TIM10LPENS_Pos (12UL) +#define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENSR1_TIM11LPENS_Pos (13UL) +#define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENSR1_SPI2LPENS_Pos (14UL) +#define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENSR1_SPI3LPENS_Pos (15UL) +#define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16UL) +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENSR1_USART2LPENS_Pos (17UL) +#define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */ +#define RCC_APB1LPENSR1_USART3LPENS_Pos (18UL) +#define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */ +#define RCC_APB1LPENSR1_UART4LPENS_Pos (19UL) +#define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */ +#define RCC_APB1LPENSR1_UART5LPENS_Pos (20UL) +#define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */ +#define RCC_APB1LPENSR1_I2C1LPENS_Pos (21UL) +#define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENSR1_I2C2LPENS_Pos (22UL) +#define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENSR1_I2C3LPENS_Pos (23UL) +#define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENSR1_I3C1LPENS_Pos (24UL) +#define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENSR1_I3C2LPENS_Pos (25UL) +#define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENSR1_UART7LPENS_Pos (30UL) +#define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */ +#define RCC_APB1LPENSR1_UART8LPENS_Pos (31UL) +#define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENSR2 register ****************/ +#define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5UL) +#define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENSR2_FDCANLPENS_Pos (8UL) +#define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18UL) +#define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENSR register ****************/ +#define RCC_APB2LPENSR_TIM1LPENS_Pos (0UL) +#define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENSR_TIM8LPENS_Pos (1UL) +#define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENSR_USART1LPENS_Pos (4UL) +#define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */ +#define RCC_APB2LPENSR_USART6LPENS_Pos (5UL) +#define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */ +#define RCC_APB2LPENSR_UART9LPENS_Pos (6UL) +#define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */ +#define RCC_APB2LPENSR_USART10LPENS_Pos (7UL) +#define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */ +#define RCC_APB2LPENSR_SPI1LPENS_Pos (12UL) +#define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENSR_SPI4LPENS_Pos (13UL) +#define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENSR_TIM18LPENS_Pos (15UL) +#define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENSR_TIM15LPENS_Pos (16UL) +#define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENSR_TIM16LPENS_Pos (17UL) +#define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENSR_TIM17LPENS_Pos (18UL) +#define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENSR_TIM9LPENS_Pos (19UL) +#define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENSR_SPI5LPENS_Pos (20UL) +#define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENSR_SAI1LPENS_Pos (21UL) +#define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENSR_SAI2LPENS_Pos (22UL) +#define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENSR register ****************/ +#define RCC_APB3LPENSR_DFTLPENS_Pos (2UL) +#define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENSR1 register ****************/ +#define RCC_APB4LPENSR1_HDPLPENS_Pos (2UL) +#define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */ +#define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3UL) +#define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENSR1_SPI6LPENS_Pos (5UL) +#define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENSR1_I2C4LPENS_Pos (7UL) +#define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9UL) +#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10UL) +#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11UL) +#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12UL) +#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15UL) +#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENSR1_RTCLPENS_Pos (16UL) +#define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */ +#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17UL) +#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENSR2 register ****************/ +#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0UL) +#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENSR2_BSECLPENS_Pos (1UL) +#define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */ +#define RCC_APB4LPENSR2_DTSLPENS_Pos (2UL) +#define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENSR register ****************/ +#define RCC_APB5LPENSR_LTDCLPENS_Pos (1UL) +#define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */ +#define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2UL) +#define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4UL) +#define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENSR_VENCLPENS_Pos (5UL) +#define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */ +#define RCC_APB5LPENSR_CSILPENS_Pos (6UL) +#define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_PRIVCFGSR0 register ****************/ +#define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR0 register *****************/ +#define RCC_PUBCFGSR0_LSIPUBS_Pos (0UL) +#define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_LSEPUBS_Pos (1UL) +#define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_MSIPUBS_Pos (2UL) +#define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSIPUBS_Pos (3UL) +#define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSEPUBS_Pos (4UL) +#define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR1 register ****************/ +#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR1 register *****************/ +#define RCC_PUBCFGSR1_PLL1PUBS_Pos (0UL) +#define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL2PUBS_Pos (1UL) +#define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL3PUBS_Pos (2UL) +#define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL4PUBS_Pos (3UL) +#define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR2 register ****************/ +#define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13UL) +#define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14UL) +#define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15UL) +#define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16UL) +#define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17UL) +#define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18UL) +#define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19UL) +#define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR2 register *****************/ +#define RCC_PUBCFGSR2_IC1PUBS_Pos (0UL) +#define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC2PUBS_Pos (1UL) +#define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC3PUBS_Pos (2UL) +#define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC4PUBS_Pos (3UL) +#define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC5PUBS_Pos (4UL) +#define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC6PUBS_Pos (5UL) +#define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC7PUBS_Pos (6UL) +#define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC8PUBS_Pos (7UL) +#define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC9PUBS_Pos (8UL) +#define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC10PUBS_Pos (9UL) +#define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC11PUBS_Pos (10UL) +#define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC12PUBS_Pos (11UL) +#define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC13PUBS_Pos (12UL) +#define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC14PUBS_Pos (13UL) +#define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC15PUBS_Pos (14UL) +#define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC16PUBS_Pos (15UL) +#define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */ +#define RCC_PUBCFGSR2_IC17PUBS_Pos (16UL) +#define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC18PUBS_Pos (17UL) +#define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC19PUBS_Pos (18UL) +#define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC20PUBS_Pos (19UL) +#define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR3 register ****************/ +#define RCC_PRIVCFGSR3_MODPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_PERPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_INTPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5UL) +#define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR3 register *****************/ +#define RCC_PUBCFGSR3_MODPUBS_Pos (0UL) +#define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_SYSPUBS_Pos (1UL) +#define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_BUSPUBS_Pos (2UL) +#define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_PERPUBS_Pos (3UL) +#define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_INTPUBS_Pos (4UL) +#define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_RSTPUBS_Pos (5UL) +#define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR4 register ****************/ +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13UL) +#define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR4 register *****************/ +#define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0UL) +#define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1UL) +#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHBMPUBS_Pos (2UL) +#define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB1PUBS_Pos (3UL) +#define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB2PUBS_Pos (4UL) +#define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB3PUBS_Pos (5UL) +#define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB4PUBS_Pos (6UL) +#define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB5PUBS_Pos (7UL) +#define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB1PUBS_Pos (8UL) +#define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB2PUBS_Pos (9UL) +#define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB3PUBS_Pos (10UL) +#define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB4PUBS_Pos (11UL) +#define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB5PUBS_Pos (12UL) +#define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_NOCPUBS_Pos (13UL) +#define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR5 register *****************/ +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0UL) +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1UL) +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2UL) +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3UL) +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4UL) +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5UL) +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6UL) +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7UL) +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8UL) +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9UL) +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11UL) +#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + +/******************* Bit definition for RCC_CCR register ********************/ +#define RCC_CCR_LSIONC_Pos (0UL) +#define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */ +#define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */ +#define RCC_CCR_LSEONC_Pos (1UL) +#define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */ +#define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */ +#define RCC_CCR_MSIONC_Pos (2UL) +#define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */ +#define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */ +#define RCC_CCR_HSIONC_Pos (3UL) +#define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */ +#define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */ +#define RCC_CCR_HSEONC_Pos (4UL) +#define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */ +#define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */ +#define RCC_CCR_PLL1ONC_Pos (8UL) +#define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */ +#define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */ +#define RCC_CCR_PLL2ONC_Pos (9UL) +#define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */ +#define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */ +#define RCC_CCR_PLL3ONC_Pos (10UL) +#define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */ +#define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */ +#define RCC_CCR_PLL4ONC_Pos (11UL) +#define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */ +#define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCCR register ******************/ +#define RCC_STOPCCR_MSISTOPENC_Pos (0UL) +#define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */ +#define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCCR_HSISTOPENC_Pos (1UL) +#define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */ +#define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTCR register *****************/ +#define RCC_MISCRSTCR_DBGRSTC_Pos (0UL) +#define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4UL) +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5UL) +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7UL) +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8UL) +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTCR register *****************/ +#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0UL) +#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1UL) +#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2UL) +#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3UL) +#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4UL) +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5UL) +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7UL) +#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8UL) +#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9UL) +#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11UL) +#define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12UL) +#define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTCR register *****************/ +#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4UL) +#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTCR_ADC12RSTC_Pos (5UL) +#define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTCR register *****************/ +#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12UL) +#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTCR_MDF1RSTC_Pos (16UL) +#define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTCR_ADF1RSTC_Pos (17UL) +#define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTCR register *****************/ +#define RCC_AHB3RSTCR_RNGRSTC_Pos (0UL) +#define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */ +#define RCC_AHB3RSTCR_HASHRSTC_Pos (1UL) +#define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */ +#define RCC_AHB3RSTCR_PKARSTC_Pos (8UL) +#define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */ +#define RCC_AHB3RSTCR_IACRSTC_Pos (10UL) +#define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTCR register *****************/ +#define RCC_AHB4RSTCR_GPIOARSTC_Pos (0UL) +#define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1UL) +#define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2UL) +#define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTCR_GPIODRSTC_Pos (3UL) +#define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTCR_GPIOERSTC_Pos (4UL) +#define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5UL) +#define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6UL) +#define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7UL) +#define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTCR_GPIONRSTC_Pos (13UL) +#define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTCR_GPIOORSTC_Pos (14UL) +#define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15UL) +#define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16UL) +#define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTCR_PWRRSTC_Pos (18UL) +#define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */ +#define RCC_AHB4RSTCR_CRCRSTC_Pos (19UL) +#define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTCR register *****************/ +#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0UL) +#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1UL) +#define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTCR_JPEGRSTC_Pos (3UL) +#define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTCR_FMCRSTC_Pos (4UL) +#define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */ +#define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5UL) +#define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTCR_PSSIRSTC_Pos (6UL) +#define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7UL) +#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8UL) +#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12UL) +#define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13UL) +#define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17UL) +#define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19UL) +#define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20UL) +#define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23UL) +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24UL) +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTCR_ETH1RSTC_Pos (25UL) +#define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTCR_OTG1RSTC_Pos (26UL) +#define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27UL) +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28UL) +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTCR_OTG2RSTC_Pos (29UL) +#define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */ + +/**************** Bit definition for RCC_APB1RSTCR1 register ****************/ +#define RCC_APB1RSTCR1_TIM2RSTC_Pos (0UL) +#define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTCR1_TIM3RSTC_Pos (1UL) +#define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTCR1_TIM4RSTC_Pos (2UL) +#define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTCR1_TIM5RSTC_Pos (3UL) +#define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTCR1_TIM6RSTC_Pos (4UL) +#define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTCR1_TIM7RSTC_Pos (5UL) +#define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTCR1_TIM12RSTC_Pos (6UL) +#define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTCR1_TIM13RSTC_Pos (7UL) +#define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTCR1_TIM14RSTC_Pos (8UL) +#define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9UL) +#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTCR1_WWDGRSTC_Pos (11UL) +#define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */ +#define RCC_APB1RSTCR1_TIM10RSTC_Pos (12UL) +#define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTCR1_TIM11RSTC_Pos (13UL) +#define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTCR1_SPI2RSTC_Pos (14UL) +#define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTCR1_SPI3RSTC_Pos (15UL) +#define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16UL) +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTCR1_USART2RSTC_Pos (17UL) +#define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */ +#define RCC_APB1RSTCR1_USART3RSTC_Pos (18UL) +#define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */ +#define RCC_APB1RSTCR1_UART4RSTC_Pos (19UL) +#define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */ +#define RCC_APB1RSTCR1_UART5RSTC_Pos (20UL) +#define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */ +#define RCC_APB1RSTCR1_I2C1RSTC_Pos (21UL) +#define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTCR1_I2C2RSTC_Pos (22UL) +#define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTCR1_I2C3RSTC_Pos (23UL) +#define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTCR1_I3C1RSTC_Pos (24UL) +#define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTCR1_I3C2RSTC_Pos (25UL) +#define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTCR1_UART7RSTC_Pos (30UL) +#define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */ +#define RCC_APB1RSTCR1_UART8RSTC_Pos (31UL) +#define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTCR2 register ****************/ +#define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5UL) +#define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTCR2_FDCANRSTC_Pos (8UL) +#define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18UL) +#define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTCR register *****************/ +#define RCC_APB2RSTCR_TIM1RSTC_Pos (0UL) +#define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTCR_TIM8RSTC_Pos (1UL) +#define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTCR_USART1RSTC_Pos (4UL) +#define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */ +#define RCC_APB2RSTCR_USART6RSTC_Pos (5UL) +#define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */ +#define RCC_APB2RSTCR_UART9RSTC_Pos (6UL) +#define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */ +#define RCC_APB2RSTCR_USART10RSTC_Pos (7UL) +#define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */ +#define RCC_APB2RSTCR_SPI1RSTC_Pos (12UL) +#define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTCR_SPI4RSTC_Pos (13UL) +#define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTCR_TIM18RSTC_Pos (15UL) +#define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTCR_TIM15RSTC_Pos (16UL) +#define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTCR_TIM16RSTC_Pos (17UL) +#define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTCR_TIM17RSTC_Pos (18UL) +#define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTCR_TIM9RSTC_Pos (19UL) +#define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTCR_SPI5RSTC_Pos (20UL) +#define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTCR_SAI1RSTC_Pos (21UL) +#define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTCR_SAI2RSTC_Pos (22UL) +#define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTCR1 register ****************/ +#define RCC_APB4RSTCR1_HDPRSTC_Pos (2UL) +#define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */ +#define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3UL) +#define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTCR1_SPI6RSTC_Pos (5UL) +#define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTCR1_I2C4RSTC_Pos (7UL) +#define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9UL) +#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10UL) +#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11UL) +#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12UL) +#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15UL) +#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTCR1_RTCRSTC_Pos (16UL) +#define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTCR2 register ****************/ +#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0UL) +#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTCR2_DTSRSTC_Pos (2UL) +#define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTCR register *****************/ +#define RCC_APB5RSTCR_LTDCRSTC_Pos (1UL) +#define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */ +#define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2UL) +#define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4UL) +#define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTCR_VENCRSTC_Pos (5UL) +#define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */ +#define RCC_APB5RSTCR_CSIRSTC_Pos (6UL) +#define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENCR register ******************/ +#define RCC_DIVENCR_IC1ENC_Pos (0UL) +#define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */ +#define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */ +#define RCC_DIVENCR_IC2ENC_Pos (1UL) +#define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */ +#define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */ +#define RCC_DIVENCR_IC3ENC_Pos (2UL) +#define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */ +#define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */ +#define RCC_DIVENCR_IC4ENC_Pos (3UL) +#define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */ +#define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */ +#define RCC_DIVENCR_IC5ENC_Pos (4UL) +#define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */ +#define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */ +#define RCC_DIVENCR_IC6ENC_Pos (5UL) +#define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */ +#define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */ +#define RCC_DIVENCR_IC7ENC_Pos (6UL) +#define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */ +#define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */ +#define RCC_DIVENCR_IC8ENC_Pos (7UL) +#define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */ +#define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */ +#define RCC_DIVENCR_IC9ENC_Pos (8UL) +#define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */ +#define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */ +#define RCC_DIVENCR_IC10ENC_Pos (9UL) +#define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */ +#define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */ +#define RCC_DIVENCR_IC11ENC_Pos (10UL) +#define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */ +#define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */ +#define RCC_DIVENCR_IC12ENC_Pos (11UL) +#define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */ +#define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */ +#define RCC_DIVENCR_IC13ENC_Pos (12UL) +#define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */ +#define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */ +#define RCC_DIVENCR_IC14ENC_Pos (13UL) +#define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */ +#define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */ +#define RCC_DIVENCR_IC15ENC_Pos (14UL) +#define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */ +#define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */ +#define RCC_DIVENCR_IC16ENC_Pos (15UL) +#define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */ +#define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */ +#define RCC_DIVENCR_IC17ENC_Pos (16UL) +#define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */ +#define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */ +#define RCC_DIVENCR_IC18ENC_Pos (17UL) +#define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */ +#define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */ +#define RCC_DIVENCR_IC19ENC_Pos (18UL) +#define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */ +#define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */ +#define RCC_DIVENCR_IC20ENC_Pos (19UL) +#define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */ +#define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENCR register ******************/ +#define RCC_BUSENCR_ACLKNENC_Pos (0UL) +#define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */ +#define RCC_BUSENCR_ACLKNCENC_Pos (1UL) +#define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */ +#define RCC_BUSENCR_AHBMENC_Pos (2UL) +#define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */ +#define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */ +#define RCC_BUSENCR_AHB1ENC_Pos (3UL) +#define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */ +#define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */ +#define RCC_BUSENCR_AHB2ENC_Pos (4UL) +#define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */ +#define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */ +#define RCC_BUSENCR_AHB3ENC_Pos (5UL) +#define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */ +#define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */ +#define RCC_BUSENCR_AHB4ENC_Pos (6UL) +#define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */ +#define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */ +#define RCC_BUSENCR_AHB5ENC_Pos (7UL) +#define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */ +#define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */ +#define RCC_BUSENCR_APB1ENC_Pos (8UL) +#define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */ +#define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */ +#define RCC_BUSENCR_APB2ENC_Pos (9UL) +#define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */ +#define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */ +#define RCC_BUSENCR_APB3ENC_Pos (10UL) +#define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */ +#define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */ +#define RCC_BUSENCR_APB4ENC_Pos (11UL) +#define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */ +#define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */ +#define RCC_BUSENCR_APB5ENC_Pos (12UL) +#define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */ +#define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENCR register *****************/ +#define RCC_MISCENCR_DBGENC_Pos (0UL) +#define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */ +#define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */ +#define RCC_MISCENCR_MCO1ENC_Pos (1UL) +#define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */ +#define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */ +#define RCC_MISCENCR_MCO2ENC_Pos (2UL) +#define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */ +#define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */ +#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3UL) +#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENCR_PERENC_Pos (6UL) +#define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */ +#define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENCR register ******************/ +#define RCC_MEMENCR_AXISRAM3ENC_Pos (0UL) +#define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */ +#define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENCR_AXISRAM4ENC_Pos (1UL) +#define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */ +#define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENCR_AXISRAM5ENC_Pos (2UL) +#define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */ +#define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENCR_AXISRAM6ENC_Pos (3UL) +#define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */ +#define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENCR_AHBSRAM1ENC_Pos (4UL) +#define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */ +#define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENCR_AHBSRAM2ENC_Pos (5UL) +#define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */ +#define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENCR_BKPSRAMENC_Pos (6UL) +#define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENCR_AXISRAM1ENC_Pos (7UL) +#define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */ +#define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENCR_AXISRAM2ENC_Pos (8UL) +#define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */ +#define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENCR_FLEXRAMENC_Pos (9UL) +#define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENCR_VENCRAMENC_Pos (11UL) +#define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */ +#define RCC_MEMENCR_BOOTROMENC_Pos (12UL) +#define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENCR register *****************/ +#define RCC_AHB1ENCR_GPDMA1ENC_Pos (4UL) +#define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENCR_ADC12ENC_Pos (5UL) +#define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENCR register *****************/ +#define RCC_AHB2ENCR_RAMCFGENC_Pos (12UL) +#define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENCR_MDF1ENC_Pos (16UL) +#define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENCR_ADF1ENC_Pos (17UL) +#define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENCR register *****************/ +#define RCC_AHB3ENCR_RNGENC_Pos (0UL) +#define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */ +#define RCC_AHB3ENCR_HASHENC_Pos (1UL) +#define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */ +#define RCC_AHB3ENCR_PKAENC_Pos (8UL) +#define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */ +#define RCC_AHB3ENCR_RIFSCENC_Pos (9UL) +#define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENCR_IACENC_Pos (10UL) +#define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */ +#define RCC_AHB3ENCR_RISAFENC_Pos (14UL) +#define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENCR register *****************/ +#define RCC_AHB4ENCR_GPIOAENC_Pos (0UL) +#define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENCR_GPIOBENC_Pos (1UL) +#define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENCR_GPIOCENC_Pos (2UL) +#define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENCR_GPIODENC_Pos (3UL) +#define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENCR_GPIOEENC_Pos (4UL) +#define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENCR_GPIOFENC_Pos (5UL) +#define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENCR_GPIOGENC_Pos (6UL) +#define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENCR_GPIOHENC_Pos (7UL) +#define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENCR_GPIONENC_Pos (13UL) +#define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENCR_GPIOOENC_Pos (14UL) +#define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENCR_GPIOPENC_Pos (15UL) +#define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENCR_GPIOQENC_Pos (16UL) +#define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENCR_PWRENC_Pos (18UL) +#define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */ +#define RCC_AHB4ENCR_CRCENC_Pos (19UL) +#define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENCR register *****************/ +#define RCC_AHB5ENCR_HPDMA1ENC_Pos (0UL) +#define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENCR_DMA2DENC_Pos (1UL) +#define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENCR_JPEGENC_Pos (3UL) +#define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */ +#define RCC_AHB5ENCR_FMCENC_Pos (4UL) +#define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */ +#define RCC_AHB5ENCR_XSPI1ENC_Pos (5UL) +#define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENCR_PSSIENC_Pos (6UL) +#define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */ +#define RCC_AHB5ENCR_SDMMC2ENC_Pos (7UL) +#define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENCR_SDMMC1ENC_Pos (8UL) +#define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENCR_XSPI2ENC_Pos (12UL) +#define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENCR_XSPIMENC_Pos (13UL) +#define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENCR_XSPI3ENC_Pos (17UL) +#define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENCR_GFXMMUENC_Pos (19UL) +#define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENCR_GPU2DENC_Pos (20UL) +#define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENCR_ETH1MACENC_Pos (22UL) +#define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENCR_ETH1TXENC_Pos (23UL) +#define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENCR_ETH1RXENC_Pos (24UL) +#define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENCR_ETH1ENC_Pos (25UL) +#define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENCR_OTG1ENC_Pos (26UL) +#define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27UL) +#define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28UL) +#define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENCR_OTG2ENC_Pos (29UL) +#define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */ + +/**************** Bit definition for RCC_APB1ENCR1 register *****************/ +#define RCC_APB1ENCR1_TIM2ENC_Pos (0UL) +#define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */ +#define RCC_APB1ENCR1_TIM3ENC_Pos (1UL) +#define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */ +#define RCC_APB1ENCR1_TIM4ENC_Pos (2UL) +#define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */ +#define RCC_APB1ENCR1_TIM5ENC_Pos (3UL) +#define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */ +#define RCC_APB1ENCR1_TIM6ENC_Pos (4UL) +#define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */ +#define RCC_APB1ENCR1_TIM7ENC_Pos (5UL) +#define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */ +#define RCC_APB1ENCR1_TIM12ENC_Pos (6UL) +#define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */ +#define RCC_APB1ENCR1_TIM13ENC_Pos (7UL) +#define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */ +#define RCC_APB1ENCR1_TIM14ENC_Pos (8UL) +#define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */ +#define RCC_APB1ENCR1_LPTIM1ENC_Pos (9UL) +#define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENCR1_TIM10ENC_Pos (12UL) +#define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */ +#define RCC_APB1ENCR1_TIM11ENC_Pos (13UL) +#define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */ +#define RCC_APB1ENCR1_SPI2ENC_Pos (14UL) +#define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */ +#define RCC_APB1ENCR1_SPI3ENC_Pos (15UL) +#define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */ +#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16UL) +#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENCR1_USART2ENC_Pos (17UL) +#define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */ +#define RCC_APB1ENCR1_USART3ENC_Pos (18UL) +#define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */ +#define RCC_APB1ENCR1_UART4ENC_Pos (19UL) +#define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */ +#define RCC_APB1ENCR1_UART5ENC_Pos (20UL) +#define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */ +#define RCC_APB1ENCR1_I2C1ENC_Pos (21UL) +#define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */ +#define RCC_APB1ENCR1_I2C2ENC_Pos (22UL) +#define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */ +#define RCC_APB1ENCR1_I2C3ENC_Pos (23UL) +#define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */ +#define RCC_APB1ENCR1_I3C1ENC_Pos (24UL) +#define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */ +#define RCC_APB1ENCR1_I3C2ENC_Pos (25UL) +#define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */ +#define RCC_APB1ENCR1_UART7ENC_Pos (30UL) +#define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */ +#define RCC_APB1ENCR1_UART8ENC_Pos (31UL) +#define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENCR2 register *****************/ +#define RCC_APB1ENCR2_MDIOSENC_Pos (5UL) +#define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */ +#define RCC_APB1ENCR2_FDCANENC_Pos (8UL) +#define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */ +#define RCC_APB1ENCR2_UCPD1ENC_Pos (18UL) +#define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENCR register *****************/ +#define RCC_APB2ENCR_TIM1ENC_Pos (0UL) +#define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */ +#define RCC_APB2ENCR_TIM8ENC_Pos (1UL) +#define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */ +#define RCC_APB2ENCR_USART1ENC_Pos (4UL) +#define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */ +#define RCC_APB2ENCR_USART6ENC_Pos (5UL) +#define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */ +#define RCC_APB2ENCR_UART9ENC_Pos (6UL) +#define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */ +#define RCC_APB2ENCR_USART10ENC_Pos (7UL) +#define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */ +#define RCC_APB2ENCR_SPI1ENC_Pos (12UL) +#define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */ +#define RCC_APB2ENCR_SPI4ENC_Pos (13UL) +#define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */ +#define RCC_APB2ENCR_TIM18ENC_Pos (15UL) +#define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */ +#define RCC_APB2ENCR_TIM15ENC_Pos (16UL) +#define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */ +#define RCC_APB2ENCR_TIM16ENC_Pos (17UL) +#define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */ +#define RCC_APB2ENCR_TIM17ENC_Pos (18UL) +#define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */ +#define RCC_APB2ENCR_TIM9ENC_Pos (19UL) +#define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */ +#define RCC_APB2ENCR_SPI5ENC_Pos (20UL) +#define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */ +#define RCC_APB2ENCR_SAI1ENC_Pos (21UL) +#define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */ +#define RCC_APB2ENCR_SAI2ENC_Pos (22UL) +#define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENCR register *****************/ +#define RCC_APB3ENCR_DFTENC_Pos (2UL) +#define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENCR1 register *****************/ +#define RCC_APB4ENCR1_HDPENC_Pos (2UL) +#define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */ +#define RCC_APB4ENCR1_LPUART1ENC_Pos (3UL) +#define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENCR1_SPI6ENC_Pos (5UL) +#define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */ +#define RCC_APB4ENCR1_I2C4ENC_Pos (7UL) +#define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */ +#define RCC_APB4ENCR1_LPTIM2ENC_Pos (9UL) +#define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENCR1_LPTIM3ENC_Pos (10UL) +#define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENCR1_LPTIM4ENC_Pos (11UL) +#define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENCR1_LPTIM5ENC_Pos (12UL) +#define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENCR1_VREFBUFENC_Pos (15UL) +#define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENCR1_RTCENC_Pos (16UL) +#define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */ +#define RCC_APB4ENCR1_RTCAPBENC_Pos (17UL) +#define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENCR2 register *****************/ +#define RCC_APB4ENCR2_SYSCFGENC_Pos (0UL) +#define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENCR2_BSECENC_Pos (1UL) +#define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */ +#define RCC_APB4ENCR2_DTSENC_Pos (2UL) +#define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENCR register *****************/ +#define RCC_APB5ENCR_LTDCENC_Pos (1UL) +#define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */ +#define RCC_APB5ENCR_DCMIPPENC_Pos (2UL) +#define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENCR_GFXTIMENC_Pos (4UL) +#define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENCR_VENCENC_Pos (5UL) +#define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */ +#define RCC_APB5ENCR_CSIENC_Pos (6UL) +#define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENCR register *****************/ +#define RCC_BUSLPENCR_ACLKNLPENC_Pos (0UL) +#define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */ +#define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1UL) +#define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */ + +/**************** Bit definition for RCC_MISCLPENCR register ****************/ +#define RCC_MISCLPENCR_DBGLPENC_Pos (0UL) +#define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3UL) +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */ +#define RCC_MISCLPENCR_PERLPENC_Pos (6UL) +#define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */ + +/**************** Bit definition for RCC_MEMLPENCR register *****************/ +#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0UL) +#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1UL) +#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2UL) +#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3UL) +#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4UL) +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5UL) +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6UL) +#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7UL) +#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8UL) +#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9UL) +#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11UL) +#define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12UL) +#define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB1LPENCR register ****************/ +#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4UL) +#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */ +#define RCC_AHB1LPENCR_ADC12LPENC_Pos (5UL) +#define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB2LPENCR register ****************/ +#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12UL) +#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */ +#define RCC_AHB2LPENCR_MDF1LPENC_Pos (16UL) +#define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */ +#define RCC_AHB2LPENCR_ADF1LPENC_Pos (17UL) +#define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB3LPENCR register ****************/ +#define RCC_AHB3LPENCR_RNGLPENC_Pos (0UL) +#define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */ +#define RCC_AHB3LPENCR_HASHLPENC_Pos (1UL) +#define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */ +#define RCC_AHB3LPENCR_PKALPENC_Pos (8UL) +#define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */ +#define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9UL) +#define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */ +#define RCC_AHB3LPENCR_IACLPENC_Pos (10UL) +#define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENCR_RISAFLPENC_Pos (14UL) +#define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB4LPENCR register ****************/ +#define RCC_AHB4LPENCR_GPIOALPENC_Pos (0UL) +#define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1UL) +#define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2UL) +#define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIODLPENC_Pos (3UL) +#define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOELPENC_Pos (4UL) +#define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5UL) +#define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6UL) +#define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7UL) +#define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIONLPENC_Pos (13UL) +#define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14UL) +#define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15UL) +#define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16UL) +#define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */ +#define RCC_AHB4LPENCR_PWRLPENC_Pos (18UL) +#define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */ +#define RCC_AHB4LPENCR_CRCLPENC_Pos (19UL) +#define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB5LPENCR register ****************/ +#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0UL) +#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1UL) +#define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_JPEGLPENC_Pos (3UL) +#define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */ +#define RCC_AHB5LPENCR_FMCLPENC_Pos (4UL) +#define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5UL) +#define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_PSSILPENC_Pos (6UL) +#define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7UL) +#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8UL) +#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12UL) +#define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13UL) +#define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17UL) +#define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19UL) +#define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */ +#define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20UL) +#define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22UL) +#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23UL) +#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24UL) +#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1LPENC_Pos (25UL) +#define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG1LPENC_Pos (26UL) +#define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27UL) +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28UL) +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG2LPENC_Pos (29UL) +#define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */ + +/*************** Bit definition for RCC_APB1LPENCR1 register ****************/ +#define RCC_APB1LPENCR1_TIM2LPENC_Pos (0UL) +#define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENCR1_TIM3LPENC_Pos (1UL) +#define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENCR1_TIM4LPENC_Pos (2UL) +#define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENCR1_TIM5LPENC_Pos (3UL) +#define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENCR1_TIM6LPENC_Pos (4UL) +#define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENCR1_TIM7LPENC_Pos (5UL) +#define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENCR1_TIM12LPENC_Pos (6UL) +#define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENCR1_TIM13LPENC_Pos (7UL) +#define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENCR1_TIM14LPENC_Pos (8UL) +#define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9UL) +#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENCR1_WWDGLPENC_Pos (11UL) +#define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */ +#define RCC_APB1LPENCR1_TIM10LPENC_Pos (12UL) +#define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENCR1_TIM11LPENC_Pos (13UL) +#define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENCR1_SPI2LPENC_Pos (14UL) +#define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENCR1_SPI3LPENC_Pos (15UL) +#define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16UL) +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENCR1_USART2LPENC_Pos (17UL) +#define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */ +#define RCC_APB1LPENCR1_USART3LPENC_Pos (18UL) +#define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */ +#define RCC_APB1LPENCR1_UART4LPENC_Pos (19UL) +#define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */ +#define RCC_APB1LPENCR1_UART5LPENC_Pos (20UL) +#define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */ +#define RCC_APB1LPENCR1_I2C1LPENC_Pos (21UL) +#define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENCR1_I2C2LPENC_Pos (22UL) +#define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENCR1_I2C3LPENC_Pos (23UL) +#define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENCR1_I3C1LPENC_Pos (24UL) +#define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENCR1_I3C2LPENC_Pos (25UL) +#define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENCR1_UART7LPENC_Pos (30UL) +#define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */ +#define RCC_APB1LPENCR1_UART8LPENC_Pos (31UL) +#define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENCR2 register ****************/ +#define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5UL) +#define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENCR2_FDCANLPENC_Pos (8UL) +#define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18UL) +#define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENCR register ****************/ +#define RCC_APB2LPENCR_TIM1LPENC_Pos (0UL) +#define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENCR_TIM8LPENC_Pos (1UL) +#define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENCR_USART1LPENC_Pos (4UL) +#define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */ +#define RCC_APB2LPENCR_USART6LPENC_Pos (5UL) +#define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */ +#define RCC_APB2LPENCR_UART9LPENC_Pos (6UL) +#define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */ +#define RCC_APB2LPENCR_USART10LPENC_Pos (7UL) +#define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */ +#define RCC_APB2LPENCR_SPI1LPENC_Pos (12UL) +#define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENCR_SPI4LPENC_Pos (13UL) +#define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENCR_TIM18LPENC_Pos (15UL) +#define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENCR_TIM15LPENC_Pos (16UL) +#define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENCR_TIM16LPENC_Pos (17UL) +#define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENCR_TIM17LPENC_Pos (18UL) +#define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENCR_TIM9LPENC_Pos (19UL) +#define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENCR_SPI5LPENC_Pos (20UL) +#define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENCR_SAI1LPENC_Pos (21UL) +#define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENCR_SAI2LPENC_Pos (22UL) +#define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENCR register ****************/ +#define RCC_APB3LPENCR_DFTLPENC_Pos (2UL) +#define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENCR1 register ****************/ +#define RCC_APB4LPENCR1_HDPLPENC_Pos (2UL) +#define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */ +#define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3UL) +#define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENCR1_SPI6LPENC_Pos (5UL) +#define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENCR1_I2C4LPENC_Pos (7UL) +#define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9UL) +#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10UL) +#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11UL) +#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12UL) +#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15UL) +#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENCR1_RTCLPENC_Pos (16UL) +#define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */ +#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17UL) +#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENCR2 register ****************/ +#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0UL) +#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENCR2_BSECLPENC_Pos (1UL) +#define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */ +#define RCC_APB4LPENCR2_DTSLPENC_Pos (2UL) +#define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENCR register ****************/ +#define RCC_APB5LPENCR_LTDCLPENC_Pos (1UL) +#define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */ +#define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2UL) +#define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */ +#define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4UL) +#define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */ +#define RCC_APB5LPENCR_VENCLPENC_Pos (5UL) +#define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */ +#define RCC_APB5LPENCR_CSILPENC_Pos (6UL) +#define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */ + +/**************** Bit definition for RCC_PRIVCFGCR0 register ****************/ +#define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR0 register *****************/ +#define RCC_PUBCFGCR0_LSIPUBC_Pos (0UL) +#define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_LSEPUBC_Pos (1UL) +#define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_MSIPUBC_Pos (2UL) +#define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSIPUBC_Pos (3UL) +#define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSEPUBC_Pos (4UL) +#define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR1 register ****************/ +#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR1 register *****************/ +#define RCC_PUBCFGCR1_PLL1PUBC_Pos (0UL) +#define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL2PUBC_Pos (1UL) +#define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL3PUBC_Pos (2UL) +#define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL4PUBC_Pos (3UL) +#define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR2 register ****************/ +#define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13UL) +#define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14UL) +#define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15UL) +#define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16UL) +#define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17UL) +#define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18UL) +#define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19UL) +#define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR2 register *****************/ +#define RCC_PUBCFGCR2_IC1PUBC_Pos (0UL) +#define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC2PUBC_Pos (1UL) +#define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC3PUBC_Pos (2UL) +#define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC4PUBC_Pos (3UL) +#define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC5PUBC_Pos (4UL) +#define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC6PUBC_Pos (5UL) +#define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC7PUBC_Pos (6UL) +#define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC8PUBC_Pos (7UL) +#define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC9PUBC_Pos (8UL) +#define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC10PUBC_Pos (9UL) +#define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC11PUBC_Pos (10UL) +#define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC12PUBC_Pos (11UL) +#define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC13PUBC_Pos (12UL) +#define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC14PUBC_Pos (13UL) +#define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC15PUBC_Pos (14UL) +#define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC16PUBC_Pos (15UL) +#define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC17PUBC_Pos (16UL) +#define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC18PUBC_Pos (17UL) +#define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC19PUBC_Pos (18UL) +#define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC20PUBC_Pos (19UL) +#define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR3 register ****************/ +#define RCC_PRIVCFGCR3_MODPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_PERPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_INTPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5UL) +#define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR3 register *****************/ +#define RCC_PUBCFGCR3_MODPUBC_Pos (0UL) +#define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_SYSPUBC_Pos (1UL) +#define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_BUSPUBC_Pos (2UL) +#define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_PERPUBC_Pos (3UL) +#define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_INTPUBC_Pos (4UL) +#define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_RSTPUBC_Pos (5UL) +#define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR4 register ****************/ +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13UL) +#define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR4 register *****************/ +#define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0UL) +#define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1UL) +#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHBMPUBC_Pos (2UL) +#define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB1PUBC_Pos (3UL) +#define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB2PUBC_Pos (4UL) +#define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB3PUBC_Pos (5UL) +#define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB4PUBC_Pos (6UL) +#define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB5PUBC_Pos (7UL) +#define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB1PUBC_Pos (8UL) +#define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB2PUBC_Pos (9UL) +#define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB3PUBC_Pos (10UL) +#define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB4PUBC_Pos (11UL) +#define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB5PUBC_Pos (12UL) +#define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_NOCPUBC_Pos (13UL) +#define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR5 register *****************/ +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0UL) +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1UL) +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2UL) +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3UL) +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4UL) +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5UL) +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6UL) +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7UL) +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8UL) +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9UL) +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11UL) +#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + + +/******************************************************************************/ +/* */ +/* Resource Isolation Framework Security Controller (RIFSC) */ +/* */ +/******************************************************************************/ +/**************** Bit definition for RIFSC_RISC_CR register *****************/ +#define RIFSC_RISC_CR_GLOCK_Pos (0UL) +#define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */ + +/************* Bit definition for RIFSC_RISC_SECCFGRx register **************/ +#define RIFSC_RISC_SECCFGRx_SEC0_Pos (0UL) +#define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */ +#define RIFSC_RISC_SECCFGRx_SEC1_Pos (1UL) +#define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */ +#define RIFSC_RISC_SECCFGRx_SEC2_Pos (2UL) +#define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */ +#define RIFSC_RISC_SECCFGRx_SEC3_Pos (3UL) +#define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */ +#define RIFSC_RISC_SECCFGRx_SEC4_Pos (4UL) +#define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */ +#define RIFSC_RISC_SECCFGRx_SEC5_Pos (5UL) +#define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */ +#define RIFSC_RISC_SECCFGRx_SEC6_Pos (6UL) +#define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */ +#define RIFSC_RISC_SECCFGRx_SEC7_Pos (7UL) +#define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */ +#define RIFSC_RISC_SECCFGRx_SEC8_Pos (8UL) +#define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */ +#define RIFSC_RISC_SECCFGRx_SEC9_Pos (9UL) +#define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */ +#define RIFSC_RISC_SECCFGRx_SEC10_Pos (10UL) +#define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */ +#define RIFSC_RISC_SECCFGRx_SEC11_Pos (11UL) +#define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */ +#define RIFSC_RISC_SECCFGRx_SEC12_Pos (12UL) +#define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */ +#define RIFSC_RISC_SECCFGRx_SEC13_Pos (13UL) +#define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */ +#define RIFSC_RISC_SECCFGRx_SEC14_Pos (14UL) +#define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */ +#define RIFSC_RISC_SECCFGRx_SEC15_Pos (15UL) +#define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */ +#define RIFSC_RISC_SECCFGRx_SEC16_Pos (16UL) +#define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */ +#define RIFSC_RISC_SECCFGRx_SEC17_Pos (17UL) +#define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */ +#define RIFSC_RISC_SECCFGRx_SEC18_Pos (18UL) +#define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */ +#define RIFSC_RISC_SECCFGRx_SEC19_Pos (19UL) +#define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */ +#define RIFSC_RISC_SECCFGRx_SEC20_Pos (20UL) +#define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */ +#define RIFSC_RISC_SECCFGRx_SEC21_Pos (21UL) +#define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */ +#define RIFSC_RISC_SECCFGRx_SEC22_Pos (22UL) +#define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */ +#define RIFSC_RISC_SECCFGRx_SEC23_Pos (23UL) +#define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */ +#define RIFSC_RISC_SECCFGRx_SEC24_Pos (24UL) +#define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */ +#define RIFSC_RISC_SECCFGRx_SEC25_Pos (25UL) +#define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */ +#define RIFSC_RISC_SECCFGRx_SEC26_Pos (26UL) +#define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */ +#define RIFSC_RISC_SECCFGRx_SEC27_Pos (27UL) +#define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */ +#define RIFSC_RISC_SECCFGRx_SEC28_Pos (28UL) +#define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */ +#define RIFSC_RISC_SECCFGRx_SEC29_Pos (29UL) +#define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */ +#define RIFSC_RISC_SECCFGRx_SEC30_Pos (30UL) +#define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */ +#define RIFSC_RISC_SECCFGRx_SEC31_Pos (31UL) +#define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/ +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */ + +/**************** Bit definition for RIFSC_RIMC_CR register *****************/ +#define RIFSC_RIMC_CR_GLOCK_Pos (0UL) +#define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */ +#define RIFSC_RIMC_CR_DAPCID_Pos (8UL) +#define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */ +#define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */ +#define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */ + +/*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/ +#define RIFSC_RIMC_ATTRx_MCID_Pos (4UL) +#define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */ +#define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */ +#define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */ +#define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */ +#define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */ +#define RIFSC_RIMC_ATTRx_MSEC_Pos (8UL) +#define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */ +#define RIFSC_RIMC_ATTRx_MPRIV_Pos (9UL) +#define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */ + +/******************************************************************************/ +/* */ +/* Resource Isolation Slave unit for Address space protection (RISAF) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RISAF_CR register *******************/ +#define RISAF_CR_GLOCK_Pos (0UL) +#define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */ + +/****************** Bit definition for RISAF_IASR register ******************/ +#define RISAF_IASR_CAEF_Pos (0UL) +#define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IASR_IAEF_Pos (1UL) +#define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */ + +/****************** Bit definition for RISAF_IACR register ******************/ +#define RISAF_IACR_CAEF_Pos (0UL) +#define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IACR_IAEF_Pos (1UL) +#define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */ + +/***************** Bit definition for RISAF_IAESR register *****************/ +#define RISAF_IAESR_IACID_Pos (0UL) +#define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */ +#define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */ +#define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */ +#define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */ +#define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */ +#define RISAF_IAESR_IAPRIV_Pos (4UL) +#define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */ +#define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */ +#define RISAF_IAESR_IASEC_Pos (5UL) +#define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */ +#define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */ +#define RISAF_IAESR_IANRW_Pos (7UL) +#define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */ +#define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */ + +/***************** Bit definition for RISAF_IADDR register *****************/ +#define RISAF_IADDR_IADD_Pos (0UL) +#define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */ +#define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */ +#define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */ +#define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */ +#define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */ +#define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */ +#define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */ +#define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */ +#define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */ +#define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */ +#define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */ +#define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */ +#define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */ +#define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */ +#define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */ +#define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */ +#define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */ +#define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */ +#define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */ +#define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */ +#define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */ +#define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */ +#define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */ +#define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */ +#define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */ +#define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */ +#define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */ +#define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */ +#define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */ +#define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */ +#define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */ +#define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */ +#define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_CFGR register ****************/ +#define RISAF_REGx_CFGR_BREN_Pos (0UL) +#define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */ +#define RISAF_REGx_CFGR_SEC_Pos (8UL) +#define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */ +#define RISAF_REGx_CFGR_PRIVC0_Pos (16UL) +#define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */ +#define RISAF_REGx_CFGR_PRIVC1_Pos (17UL) +#define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */ +#define RISAF_REGx_CFGR_PRIVC2_Pos (18UL) +#define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */ +#define RISAF_REGx_CFGR_PRIVC3_Pos (19UL) +#define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */ +#define RISAF_REGx_CFGR_PRIVC4_Pos (20UL) +#define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */ +#define RISAF_REGx_CFGR_PRIVC5_Pos (21UL) +#define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */ +#define RISAF_REGx_CFGR_PRIVC6_Pos (22UL) +#define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */ +#define RISAF_REGx_CFGR_PRIVC7_Pos (23UL) +#define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */ + +/************** Bit definition for RISAF_REGx_STARTR register ***************/ +#define RISAF_REGx_STARTR_BADDSTART_Pos (0UL) +#define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */ +#define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_ENDR register ****************/ +#define RISAF_REGx_ENDR_BADDEND_Pos (0UL) +#define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */ +#define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_CIDCFGR register **************/ +#define RISAF_REGx_CIDCFGR_RDENC0_Pos (0UL) +#define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_RDENC1_Pos (1UL) +#define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_RDENC2_Pos (2UL) +#define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_RDENC3_Pos (3UL) +#define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_RDENC4_Pos (4UL) +#define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_RDENC5_Pos (5UL) +#define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_RDENC6_Pos (6UL) +#define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_RDENC7_Pos (7UL) +#define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */ +#define RISAF_REGx_CIDCFGR_WRENC0_Pos (16UL) +#define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_WRENC1_Pos (17UL) +#define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_WRENC2_Pos (18UL) +#define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_WRENC3_Pos (19UL) +#define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_WRENC4_Pos (20UL) +#define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_WRENC5_Pos (21UL) +#define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_WRENC6_Pos (22UL) +#define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_WRENC7_Pos (23UL) +#define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */ + +/*************** Bit definition for RISAF_REGx_zCFGR register ***************/ +#define RISAF_REGx_zCFGR_SREN_Pos (0UL) +#define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */ +#define RISAF_REGx_zCFGR_RLOCK_Pos (1UL) +#define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */ +#define RISAF_REGx_zCFGR_SRCID_Pos (4UL) +#define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */ +#define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zCFGR_SEC_Pos (8UL) +#define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */ +#define RISAF_REGx_zCFGR_PRIV_Pos (9UL) +#define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */ +#define RISAF_REGx_zCFGR_RDEN_Pos (12UL) +#define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */ +#define RISAF_REGx_zCFGR_WREN_Pos (13UL) +#define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */ + +/************** Bit definition for RISAF_REGx_zSTARTR register **************/ +#define RISAF_REGx_zSTARTR_SADDSTART_Pos (0UL) +#define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */ +#define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_zENDR register ***************/ +#define RISAF_REGx_zENDR_SADDEND_Pos (0UL) +#define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */ +#define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_zNESTR register ***************/ +#define RISAF_REGx_zNESTR_DCEN_Pos (2UL) +#define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */ +#define RISAF_REGx_zNESTR_DCCID_Pos (4UL) +#define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */ +#define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */ + +/******************************************************************************/ +/* */ +/* (IAC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IAC_IER0 register *******************/ +#define IAC_IERx_IAIE0_Pos (0UL) +#define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */ +#define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_IERx_IAIE1_Pos (1UL) +#define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */ +#define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_IERx_IAIE2_Pos (2UL) +#define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */ +#define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_IERx_IAIE3_Pos (3UL) +#define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */ +#define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_IERx_IAIE4_Pos (4UL) +#define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */ +#define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_IERx_IAIE5_Pos (5UL) +#define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */ +#define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_IERx_IAIE6_Pos (6UL) +#define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */ +#define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_IERx_IAIE7_Pos (7UL) +#define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */ +#define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_IERx_IAIE8_Pos (8UL) +#define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */ +#define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_IERx_IAIE9_Pos (9UL) +#define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */ +#define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_IERx_IAIE10_Pos (10UL) +#define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */ +#define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_IERx_IAIE11_Pos (11UL) +#define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */ +#define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_IERx_IAIE12_Pos (12UL) +#define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */ +#define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_IERx_IAIE13_Pos (13UL) +#define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */ +#define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_IERx_IAIE14_Pos (14UL) +#define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */ +#define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_IERx_IAIE15_Pos (15UL) +#define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */ +#define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_IERx_IAIE16_Pos (16UL) +#define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */ +#define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_IERx_IAIE17_Pos (17UL) +#define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */ +#define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_IERx_IAIE18_Pos (18UL) +#define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */ +#define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_IERx_IAIE19_Pos (19UL) +#define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */ +#define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_IERx_IAIE20_Pos (20UL) +#define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */ +#define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_IERx_IAIE21_Pos (21UL) +#define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */ +#define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_IERx_IAIE22_Pos (22UL) +#define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */ +#define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_IERx_IAIE23_Pos (23UL) +#define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */ +#define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_IERx_IAIE24_Pos (24UL) +#define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */ +#define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_IERx_IAIE25_Pos (25UL) +#define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */ +#define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_IERx_IAIE26_Pos (26UL) +#define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */ +#define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_IERx_IAIE27_Pos (27UL) +#define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */ +#define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_IERx_IAIE28_Pos (28UL) +#define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */ +#define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_IERx_IAIE29_Pos (29UL) +#define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */ +#define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_IERx_IAIE30_Pos (30UL) +#define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */ +#define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_IERx_IAIE31_Pos (31UL) +#define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */ +#define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ISRx register *******************/ +#define IAC_ISRx_IAF0_Pos (0UL) +#define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_ISRx_IAF1_Pos (1UL) +#define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_ISRx_IAF2_Pos (2UL) +#define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_ISRx_IAF3_Pos (3UL) +#define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_ISRx_IAF4_Pos (4UL) +#define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_ISRx_IAF5_Pos (5UL) +#define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_ISRx_IAF6_Pos (6UL) +#define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_ISRx_IAF7_Pos (7UL) +#define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_ISRx_IAF8_Pos (8UL) +#define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_ISRx_IAF9_Pos (9UL) +#define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_ISRx_IAF10_Pos (10UL) +#define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_ISRx_IAF11_Pos (11UL) +#define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_ISRx_IAF12_Pos (12UL) +#define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_ISRx_IAF13_Pos (13UL) +#define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_ISRx_IAF14_Pos (14UL) +#define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_ISRx_IAF15_Pos (15UL) +#define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_ISRx_IAF16_Pos (16UL) +#define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_ISRx_IAF17_Pos (17UL) +#define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_ISRx_IAF18_Pos (18UL) +#define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_ISRx_IAF19_Pos (19UL) +#define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_ISRx_IAF20_Pos (20UL) +#define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_ISRx_IAF21_Pos (21UL) +#define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_ISRx_IAF22_Pos (22UL) +#define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_ISRx_IAF23_Pos (23UL) +#define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_ISRx_IAF24_Pos (24UL) +#define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_ISRx_IAF25_Pos (25UL) +#define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_ISRx_IAF26_Pos (26UL) +#define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_ISRx_IAF27_Pos (27UL) +#define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_ISRx_IAF28_Pos (28UL) +#define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_ISRx_IAF29_Pos (29UL) +#define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_ISRx_IAF30_Pos (30UL) +#define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_ISRx_IAF31_Pos (31UL) +#define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ICRx register *******************/ +#define IAC_ICRx_IAF0_Pos (0UL) +#define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */ +#define IAC_ICRx_IAF1_Pos (1UL) +#define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */ +#define IAC_ICRx_IAF2_Pos (2UL) +#define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */ +#define IAC_ICRx_IAF3_Pos (3UL) +#define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */ +#define IAC_ICRx_IAF4_Pos (4UL) +#define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */ +#define IAC_ICRx_IAF5_Pos (5UL) +#define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */ +#define IAC_ICRx_IAF6_Pos (6UL) +#define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */ +#define IAC_ICRx_IAF7_Pos (7UL) +#define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */ +#define IAC_ICRx_IAF8_Pos (8UL) +#define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */ +#define IAC_ICRx_IAF9_Pos (9UL) +#define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */ +#define IAC_ICRx_IAF10_Pos (10UL) +#define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */ +#define IAC_ICRx_IAF11_Pos (11UL) +#define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */ +#define IAC_ICRx_IAF12_Pos (12UL) +#define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */ +#define IAC_ICRx_IAF13_Pos (13UL) +#define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */ +#define IAC_ICRx_IAF14_Pos (14UL) +#define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */ +#define IAC_ICRx_IAF15_Pos (15UL) +#define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */ +#define IAC_ICRx_IAF16_Pos (16UL) +#define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */ +#define IAC_ICRx_IAF17_Pos (17UL) +#define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */ +#define IAC_ICRx_IAF18_Pos (18UL) +#define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */ +#define IAC_ICRx_IAF19_Pos (19UL) +#define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */ +#define IAC_ICRx_IAF20_Pos (20UL) +#define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */ +#define IAC_ICRx_IAF21_Pos (21UL) +#define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */ +#define IAC_ICRx_IAF22_Pos (22UL) +#define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */ +#define IAC_ICRx_IAF23_Pos (23UL) +#define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */ +#define IAC_ICRx_IAF24_Pos (24UL) +#define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */ +#define IAC_ICRx_IAF25_Pos (25UL) +#define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */ +#define IAC_ICRx_IAF26_Pos (26UL) +#define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */ +#define IAC_ICRx_IAF27_Pos (27UL) +#define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */ +#define IAC_ICRx_IAF28_Pos (28UL) +#define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */ +#define IAC_ICRx_IAF29_Pos (29UL) +#define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */ +#define IAC_ICRx_IAF30_Pos (30UL) +#define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */ +#define IAC_ICRx_IAF31_Pos (31UL) +#define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */ + +/****************** Bit definition for IAC_IISRx register *******************/ +#define IAC_IISRx_ILACIN0_Pos (0UL) +#define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */ +#define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN1_Pos (1UL) +#define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */ +#define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN2_Pos (2UL) +#define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */ +#define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN3_Pos (3UL) +#define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */ +#define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN4_Pos (4UL) +#define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */ +#define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN5_Pos (5UL) +#define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */ +#define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN6_Pos (6UL) +#define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */ +#define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN7_Pos (7UL) +#define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */ +#define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN8_Pos (8UL) +#define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */ +#define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN9_Pos (9UL) +#define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */ +#define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN10_Pos (10UL) +#define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */ +#define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN11_Pos (11UL) +#define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */ +#define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN12_Pos (12UL) +#define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */ +#define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN13_Pos (13UL) +#define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */ +#define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN14_Pos (14UL) +#define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */ +#define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN15_Pos (15UL) +#define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */ +#define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN16_Pos (16UL) +#define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */ +#define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN17_Pos (17UL) +#define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */ +#define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN18_Pos (18UL) +#define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */ +#define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN19_Pos (19UL) +#define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */ +#define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN20_Pos (20UL) +#define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */ +#define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN21_Pos (21UL) +#define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */ +#define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN22_Pos (22UL) +#define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */ +#define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN23_Pos (23UL) +#define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */ +#define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN24_Pos (24UL) +#define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */ +#define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN25_Pos (25UL) +#define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */ +#define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN26_Pos (26UL) +#define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */ +#define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN27_Pos (27UL) +#define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */ +#define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN28_Pos (28UL) +#define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */ +#define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN29_Pos (29UL) +#define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */ +#define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN30_Pos (30UL) +#define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */ +#define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN31_Pos (31UL) +#define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */ +#define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0UL) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4UL) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8UL) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12UL) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16UL) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20UL) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22UL) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0UL) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4UL) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8UL) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12UL) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13UL) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16UL) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20UL) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0UL) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2UL) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3UL) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4UL) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5UL) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6UL) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7UL) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8UL) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10UL) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16UL) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0UL) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16UL) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0UL) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16UL) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0UL) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3UL) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4UL) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5UL) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6UL) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7UL) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8UL) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9UL) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10UL) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11UL) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12UL) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13UL) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14UL) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15UL) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16UL) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17UL) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18UL) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19UL) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20UL) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21UL) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23UL) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24UL) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0UL) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief RAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */ + __IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */ + __IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */ + __IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */ + uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */ + __IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */ + __IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */ + __IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */ + __IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */ + __IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */ + __IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */ + __IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */ + __IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */ + __IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */ + __IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */ + __IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */ + __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */ + __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */ + __IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */ + __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */ + __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */ + __IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */ + __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */ + __IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */ + __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */ + __IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */ + __IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */ + __IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */ + __IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */ + __IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */ + __IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */ + __IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */ + __IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */ + __IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */ + __IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */ + __IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */ + __IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */ + __IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */ + __IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */ + __IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */ + __IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */ + __IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */ + __IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */ + __IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */ + __IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */ + __IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */ + uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */ + __IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */ + __IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */ + __IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */ + __IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */ + __IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */ + __IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */ + __IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */ + __IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */ + __IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */ + __IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */ + __IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */ + __IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */ + uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */ + __IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */ + __IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */ + __IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */ + uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */ + __IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */ + __IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */ + __IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */ + __IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */ + __IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */ + __IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */ + __IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */ + __IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */ + __IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */ + __IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */ + __IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */ + __IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */ + __IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */ + __IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */ + __IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */ + __IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */ + uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */ + __IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */ + uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */ + __IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */ + __IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */ + __IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */ + __IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */ + __IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */ + __IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */ + __IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */ + __IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */ + __IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */ + __IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */ + __IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */ + __IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */ + __IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */ + __IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */ + __IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */ + __IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */ + __IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */ + __IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */ + __IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */ + __IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */ + __IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */ + uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */ + __IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */ + __IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */ + uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */ + __IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */ + __IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */ + __IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */ + __IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */ + __IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */ + __IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */ + __IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */ + __IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */ + __IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */ + __IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */ + __IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */ + __IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */ + __IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */ + __IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */ + __IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */ + __IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */ + __IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */ + __IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */ + __IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */ + __IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */ + __IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */ + __IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */ + __IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */ + __IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */ + __IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */ + __IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */ + __IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */ + __IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */ + __IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */ + __IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */ + __IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */ + __IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */ + __IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */ + __IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */ + __IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */ + __IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */ + __IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */ + __IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */ + __IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */ + __IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */ + __IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */ + __IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */ + __IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */ + __IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */ + uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */ + __IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */ + __IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */ + __IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */ + uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */ + __IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */ + __IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */ + uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */ + __IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */ + __IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */ + uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */ + __IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */ + uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */ + __IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */ + __IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */ + __IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */ + uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */ + __IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */ + uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */ + __IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */ + uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */ + __IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */ + __IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */ + __IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */ + __IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */ + __IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */ + __IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */ + __IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */ + __IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */ + __IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */ + __IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */ + __IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */ + __IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */ + __IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */ + __IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */ + __IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */ + __IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */ + __IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */ + __IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */ + __IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */ + __IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */ + __IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */ + __IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */ + __IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */ + __IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */ + __IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */ + __IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */ + __IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */ + __IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */ + __IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */ + __IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */ + __IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */ + __IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */ + __IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */ + __IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */ + __IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */ + __IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */ + __IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */ + __IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */ + __IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */ + __IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */ + __IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */ + __IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */ + __IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */ + __IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */ + uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */ + __IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */ + uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */ + __IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */ + __IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */ + __IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */ + __IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */ + __IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */ + __IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */ + __IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */ + __IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */ + __IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */ + __IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */ +} RCC_TypeDef; + +/* + * @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1) + */ +typedef struct +{ + __IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */ + __IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */ + __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */ + uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */ + __IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */ + __IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */ + uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */ + __IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */ + uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */ +} RIFSC_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) + */ +typedef struct +{ + __IO uint32_t CFGR; /*!< RISAF Region X configuration register */ + __IO uint32_t STARTR; /*!< RISAF Region X start address register */ + __IO uint32_t ENDR; /*!< RISAF Region X end address register */ + __IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */ + __IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */ + __IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */ + __IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */ + __IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */ + __IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */ + __IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */ + __IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */ + __IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */ + uint32_t RESERVED0[4]; /*!< Reserved */ +} RISAF_Region_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t IAESR; /*!< RISAF Illegal access error status register */ + __IO uint32_t IADDR; /*!< RISAF Illegal address register, */ +} RISAF_Illegal_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */ + RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */ + RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */ +} RISAF_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 7U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ +__IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + __IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */ +} USB_PHY_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + __IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + __IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + __IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + __IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + __IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */ +} USB_HS_PHYC_GlobalTypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */ + __IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */ + __IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */ + __IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */ + __IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */ + __IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */ + __IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */ + __IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */ + __IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */ + __IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */ + __IO uint32_t NPUNICQOSCR; /*!< SYSCFG NPUNIC QoS control register, Address offset: 0x28 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2C-0x30 */ + __IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */ + __IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */ + __IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x44 */ + __IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x48 */ + __IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x4C */ + __IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x50 */ + __IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x54 */ + __IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x58 */ + __IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x5C */ + __IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x60 */ + __IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */ + __IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */ + __IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */ + __IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */ + __IO uint32_t NPU_ICNCR; /*!< SYSCFG NPU RAM interleaving control register, Address offset: 0x78 */ + uint32_t RESERVED3[33]; /*!< Reserved, Address offset: 0x7C-0xFC */ + __IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */ + __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */ + uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */ + __IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */ + uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */ + __IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Extended-SPI Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** @} */ /* End of group STM32N6xx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal RAMs sizes */ +#define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */ +#define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */ +#define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */ +#define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */ +#define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */ +#define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */ +#define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */ +#define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */ +#define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */ +#define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */ +#define CACHEAXI_RAM_SIZE 0x40000UL /*!< CACHEAXI RAM = 256 Kbytes */ +#define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */ + + +#define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */ +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK5_1 FMC_BANK5 +#define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL) +#define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL) +#define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL) +#define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK6_1 FMC_BANK6 +#define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL) +#define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL) +#define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL) +#define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */ +#define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */ +#define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */ + +/**************************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */ +/* */ +/**************************************************************************/ + +#define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define CACHEAXI_RAM_BASE_NS 0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ +#define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL) +#define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL) +#define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL) +#define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL) +#define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL) +#define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL) +#define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL) +#define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL) +#define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL) +#define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL) +#define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) +#define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL) +#define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL) +#define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL) +#define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL) +#define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL) +#define RISAF4_BASE_NS (AHB3PERIPH_BASE_NS + 0x9000UL) +#define RISAF5_BASE_NS (AHB3PERIPH_BASE_NS + 0xA000UL) +#define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL) +#define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL) +#define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL) +#define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL) +#define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL) +#define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL) +#define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL) +#define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL) +#define RISAF15_BASE_NS (AHB3PERIPH_BASE_NS + 0x014000UL) +#define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL) +#define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL) +#define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL) +#define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL) +#define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL) +#define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL) +#define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL) +#define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL) +#define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL) +#define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL) +#define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL) +#define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL) +#define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL) +#define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL) +#define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL) +#define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL) +#define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL) +#define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL) +#define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL) +#define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL) +#define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL) +#define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL) +#define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL) +#define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL) +#define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL) +#define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL) +#define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL) +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL) +#define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL) +#define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL) +#define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL) +#define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL) +#define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL) +#define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL) +#define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL) +#define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL) +#define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL) +#define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL) +#define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL) +#define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL) +#define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL) +#define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL) +#define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL) +#define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL) +#define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL) +#define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL) +#define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL) +#define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL) +#define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL) +#define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL) +#define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL) +#define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL) +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) +#define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL) +#define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL) +#define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL) +#define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL) +#define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL) +#define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL) +#define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL) +#define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL) +#define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL) +#define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL) +#define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL) +#define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL) +#define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL) +#define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL) +#define ETH1_MAC_BASE_NS (ETH1_BASE_NS) +#define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL) +#define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL) +#define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL) +#define CACHEAXI_BASE_NS (AHB5PERIPH_BASE_NS + 0x0BFC00UL) +#define NPU_BASE_NS (AHB5PERIPH_BASE_NS + 0x0C0000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_NS (0x46009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_NS (BOOTROM_BASE_NS + 0x001004UL) + + +#if defined (CPU_IN_SECURE_STATE) +/*********************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */ +/* */ +/*********************************************************************/ +#define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define CACHEAXI_RAM_BASE_S 0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ +#define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL) +#define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL) +#define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL) +#define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL) +#define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL) +#define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL) +#define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL) +#define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL) +#define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL) +#define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL) +#define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) +#define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL) +#define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL) +#define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL) +#define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL) +#define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL) +#define RISAF4_BASE_S (AHB3PERIPH_BASE_S + 0x9000UL) +#define RISAF5_BASE_S (AHB3PERIPH_BASE_S + 0xA000UL) +#define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL) +#define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL) +#define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL) +#define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL) +#define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL) +#define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL) +#define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL) +#define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL) +#define RISAF15_BASE_S (AHB3PERIPH_BASE_S + 0x014000UL) +#define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL) +#define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL) +#define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL) +#define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL) +#define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL) +#define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL) +#define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL) +#define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL) +#define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL) +#define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL) +#define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL) +#define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL) +#define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL) +#define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL) + +#define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL) +#define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL) +#define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL) +#define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL) +#define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL) +#define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL) +#define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL) +#define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL) +#define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL) +#define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL) +#define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL) +#define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL) +#define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL) +#define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL) +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL) +#define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL) +#define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL) +#define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL) +#define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL) +#define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL) +#define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL) +#define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL) +#define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL) +#define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL) +#define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL) +#define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL) +#define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL) +#define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL) +#define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL) +#define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL) +#define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL) +#define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL) +#define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL) +#define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL) +#define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL) +#define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL) +#define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL) +#define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL) +#define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) +#define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL) +#define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL) +#define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL) +#define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL) +#define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL) +#define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL) +#define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL) +#define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL) +#define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL) +#define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL) +#define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL) +#define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL) +#define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL) +#define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL) +#define ETH1_MAC_BASE_S (ETH1_BASE_S) +#define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL) +#define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL) +#define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL) +#define CACHEAXI_BASE_S (AHB5PERIPH_BASE_S + 0x0BFC00UL) +#define NPU_BASE_S (AHB5PERIPH_BASE_S + 0x0C0000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_S (0x56009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_S (BOOTROM_BASE_S + 0x001004UL) + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS) +#define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS) +#define CACHEAXI_NS ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS) +#define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS) +#define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS) +#define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS) +#define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS) +#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS) +#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) +#define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS) +#define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS) +#define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS) +#define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS) +#define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS) +#define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS) +#define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS) +#define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS) +#define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS) +#define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS) +#define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS) +#define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS) +#define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS) +#define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS) +#define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS) +#define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS) +#define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS) +#define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS) +#define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS) +#define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS) +#define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS) +#define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS) +#define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS) +#define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS) +#define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS) +#define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS) +#define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS) +#define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS) +#define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS) +#define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS) +#define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS) +#define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS) +#define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS) +#define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS) +#define RISAF4_NS ((RISAF_TypeDef *) RISAF4_BASE_NS) +#define RISAF5_NS ((RISAF_TypeDef *) RISAF5_BASE_NS) +#define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS) +#define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS) +#define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS) +#define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS) +#define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS) +#define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS) +#define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS) +#define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS) +#define RISAF15_NS ((RISAF_TypeDef *) RISAF15_BASE_NS) +#define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS) +#define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS) +#define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS) +#define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS) +#define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define UART7_NS ((USART_TypeDef *) UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *) UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *) UART9_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *) USART10_BASE_NS) +#define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS) +#define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS) +#define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS) +#define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS) +#define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS) +#define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS) +#define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS) +#define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S) +#define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S) +#define CACHEAXI_S ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CSI_S ((CSI_TypeDef *) CSI_BASE_S) +#define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define DTS_S ((DTS_TypeDef *) DTS_BASE_S) +#define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S) +#define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S) +#define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S) +#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S) +#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) +#define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPION_S ((GPIO_TypeDef *) GPION_BASE_S) +#define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S) +#define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S) +#define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S) +#define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S) +#define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S) +#define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S) +#define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S) +#define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S) +#define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S) +#define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S) +#define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S) +#define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S) +#define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S) +#define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S) +#define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S) +#define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S) +#define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S) +#define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S) +#define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define IAC_S ((IAC_TypeDef *) IAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S) +#define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S) +#define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S) +#define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S) +#define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S) +#define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S) +#define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S) +#define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S) +#define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S) +#define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S) +#define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S) +#define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S) +#define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S) +#define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S) +#define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S) +#define RISAF4_S ((RISAF_TypeDef *) RISAF4_BASE_S) +#define RISAF5_S ((RISAF_TypeDef *) RISAF5_BASE_S) +#define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S) +#define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S) +#define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S) +#define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S) +#define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S) +#define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S) +#define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S) +#define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S) +#define RISAF15_S ((RISAF_TypeDef *) RISAF15_BASE_S) +#define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S) +#define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S) +#define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S) +#define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S) +#define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define UART7_S ((USART_TypeDef *) UART7_BASE_S) +#define UART8_S ((USART_TypeDef *) UART8_BASE_S) +#define UART9_S ((USART_TypeDef *) UART9_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define USART10_S ((USART_TypeDef *) USART10_BASE_S) +#define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S) +#define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S) +#define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S) +#define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S) +#define VENC_S ((VENC_TypeDef *) VENC_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S) +#define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S) +#define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S) +#define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S) +#endif + +/*!< Peripheral Instance aliases for Non-Secure/Secure execution */ +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define BSEC BSEC_S +#define BSEC_BASE BSEC_BASE_S + +#define CACHEAXI CACHEAXI_S +#define CACHEAXI_BASE CACHEAXI_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + + +#define CSI CSI_S +#define CSI_BASE CSI_BASE_S + +#define DBGMCU DBGMCU_S +#define DBGMCU_BASE DBGMCU_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define DCMIPP DCMIPP_S +#define DCMIPP_BASE DCMIPP_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define DTS_Sensor0 DTS_Sensor0_S +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_S + +#define DTS_Sensor1 DTS_Sensor1_S +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_S + +#define ETH1 ETH1_S +#define ETH1_BASE ETH1_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define FDCAN3 FDCAN3_S +#define FDCAN3_BASE FDCAN3_BASE_S + +#define FDCAN_CCU FDCAN_CCU_S +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S + +#define FMC_R_BASE FMC_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define FMC_Common_R FMC_Common_R_S +#define FMC_Common_R_BASE FMC_Common_R_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPION GPION_S +#define GPION_BASE GPION_BASE_S + +#define GPIOO GPIOO_S +#define GPIOO_BASE GPIOO_BASE_S + +#define GPIOP GPIOP_S +#define GPIOP_BASE GPIOP_BASE_S + +#define GPIOQ GPIOQ_S +#define GPIOQ_BASE GPIOQ_BASE_S + +#define GPU2D GPU2D_BASE_S +#define GPU2D_BASE GPU2D_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define HPDMA1 HPDMA1_S +#define HPDMA1_BASE HPDMA1_BASE_S + +#define HPDMA1_Channel0 HPDMA1_Channel0_S +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S + +#define HPDMA1_Channel1 HPDMA1_Channel1_S +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S + +#define HPDMA1_Channel2 HPDMA1_Channel2_S +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S + +#define HPDMA1_Channel3 HPDMA1_Channel3_S +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S + +#define HPDMA1_Channel4 HPDMA1_Channel4_S +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S + +#define HPDMA1_Channel5 HPDMA1_Channel5_S +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S + +#define HPDMA1_Channel6 HPDMA1_Channel6_S +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S + +#define HPDMA1_Channel7 HPDMA1_Channel7_S +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S + +#define HPDMA1_Channel8 HPDMA1_Channel8_S +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S + +#define HPDMA1_Channel9 HPDMA1_Channel9_S +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S + +#define HPDMA1_Channel10 HPDMA1_Channel10_S +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S + +#define HPDMA1_Channel11 HPDMA1_Channel11_S +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S + +#define HPDMA1_Channel12 HPDMA1_Channel12_S +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S + +#define HPDMA1_Channel13 HPDMA1_Channel13_S +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S + +#define HPDMA1_Channel14 HPDMA1_Channel14_S +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S + +#define HPDMA1_Channel15 HPDMA1_Channel15_S +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define IAC IAC_S +#define IAC_BASE IAC_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1 LTDC_Layer1_S +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S + +#define LTDC_Layer2 LTDC_Layer2_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define MDIOS MDIOS_S +#define MDIOS_BASE MDIOS_BASE_S + +#define NPU_PRESENT +#define NPU_BASE NPU_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG RAMCFG_S +#define RAMCFG_BASE RAMCFG_BASE_S + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define RIFSC RIFSC_S +#define RIFSC_BASE RIFSC_BASE_S + +#define RISAF1 RISAF1_S +#define RISAF1_BASE RISAF1_BASE_S + +#define RISAF2 RISAF2_S +#define RISAF2_BASE RISAF2_BASE_S + +#define RISAF3 RISAF3_S +#define RISAF3_BASE RISAF3_BASE_S + +#define RISAF4 RISAF4_S +#define RISAF4_BASE RISAF4_BASE_S + +#define RISAF5 RISAF5_S +#define RISAF5_BASE RISAF5_BASE_S + +#define RISAF6 RISAF6_S +#define RISAF6_BASE RISAF6_BASE_S + +#define RISAF7 RISAF7_S +#define RISAF7_BASE RISAF7_BASE_S + +#define RISAF8 RISAF8_S +#define RISAF8_BASE RISAF8_BASE_S + +#define RISAF9 RISAF9_S +#define RISAF9_BASE RISAF9_BASE_S + +#define RISAF11 RISAF11_S +#define RISAF11_BASE RISAF11_BASE_S + +#define RISAF12 RISAF12_S +#define RISAF12_BASE RISAF12_BASE_S + +#define RISAF13 RISAF13_S +#define RISAF13_BASE RISAF13_BASE_S + +#define RISAF14 RISAF14_S +#define RISAF14_BASE RISAF14_BASE_S + +#define RISAF15 RISAF15_S +#define RISAF15_BASE RISAF15_BASE_S + +#define RISAF21 RISAF21_S +#define RISAF21_BASE RISAF21_BASE_S + +#define RISAF22 RISAF22_S +#define RISAF22_BASE RISAF22_BASE_S + +#define RISAF23 RISAF23_S +#define RISAF23_BASE RISAF23_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define SPDIFRX SPDIFRX_S +#define SPDIFRX_BASE SPDIFRX_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM9 TIM9_S +#define TIM9_BASE TIM9_BASE_S + +#define TIM10 TIM10_S +#define TIM10_BASE TIM10_BASE_S + +#define TIM11 TIM11_S +#define TIM11_BASE TIM11_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define TIM18 TIM18_S +#define TIM18_BASE TIM18_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USB1_OTG_HS USB1_OTG_HS_S +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S + +#define USB2_OTG_HS USB2_OTG_HS_S +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S + +#define USB1_HS_PHYC USB1_HS_PHYC_S +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S + +#define USB2_HS_PHYC USB2_HS_PHYC_S +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S + +#define VENC VENC_S +#define VENC_BASE VENC_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define XSPI1 XSPI1_S + +#define XSPI2 XSPI2_S + +#define XSPI3 XSPI3_S + +#define XSPIM XSPIM_S +#define XSPIM_BASE XSPIM_BASE_S + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_S + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_S + +#else + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS + +#define BSEC BSEC_NS +#define BSEC_BASE BSEC_BASE_NS + +#define CACHEAXI CACHEAXI_NS +#define CACHEAXI_BASE CACHEAXI_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + + +#define CSI CSI_NS +#define CSI_BASE CSI_BASE_NS + +#define DBGMCU DBGMCU_NS +#define DBGMCU_BASE DBGMCU_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define DCMIPP DCMIPP_NS +#define DCMIPP_BASE DCMIPP_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define DTS_Sensor0 DTS_Sensor0_NS +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS + +#define DTS_Sensor1 DTS_Sensor1_NS +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS + +#define ETH1 ETH1_NS +#define ETH1_BASE ETH1_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define FDCAN3 FDCAN3_NS +#define FDCAN3_BASE FDCAN3_BASE_NS + +#define FDCAN_CCU FDCAN_CCU_NS +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS + +#define FMC_R_BASE FMC_R_BASE_NS +#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define FMC_Common_R FMC_Common_R_NS +#define FMC_Common_R_BASE FMC_Common_R_BASE_NS + +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPION GPION_NS +#define GPION_BASE GPION_BASE_NS + +#define GPIOO GPIOO_NS +#define GPIOO_BASE GPIOO_BASE_NS + +#define GPIOP GPIOP_NS +#define GPIOP_BASE GPIOP_BASE_NS + +#define GPIOQ GPIOQ_NS +#define GPIOQ_BASE GPIOQ_BASE_NS + +#define GPU2D GPU2D_BASE_NS +#define GPU2D_BASE GPU2D_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define HPDMA1 HPDMA1_NS +#define HPDMA1_BASE HPDMA1_BASE_NS + +#define HPDMA1_Channel0 HPDMA1_Channel0_NS +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS + +#define HPDMA1_Channel1 HPDMA1_Channel1_NS +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS + +#define HPDMA1_Channel2 HPDMA1_Channel2_NS +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS + +#define HPDMA1_Channel3 HPDMA1_Channel3_NS +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS + +#define HPDMA1_Channel4 HPDMA1_Channel4_NS +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS + +#define HPDMA1_Channel5 HPDMA1_Channel5_NS +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS + +#define HPDMA1_Channel6 HPDMA1_Channel6_NS +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS + +#define HPDMA1_Channel7 HPDMA1_Channel7_NS +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS + +#define HPDMA1_Channel8 HPDMA1_Channel8_NS +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS + +#define HPDMA1_Channel9 HPDMA1_Channel9_NS +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS + +#define HPDMA1_Channel10 HPDMA1_Channel10_NS +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS + +#define HPDMA1_Channel11 HPDMA1_Channel11_NS +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS + +#define HPDMA1_Channel12 HPDMA1_Channel12_NS +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS + +#define HPDMA1_Channel13 HPDMA1_Channel13_NS +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS + +#define HPDMA1_Channel14 HPDMA1_Channel14_NS +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS + +#define HPDMA1_Channel15 HPDMA1_Channel15_NS +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define MDIOS MDIOS_NS +#define MDIOS_BASE MDIOS_BASE_NS + +#define NPU_PRESENT +#define NPU_BASE NPU_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG RAMCFG_NS +#define RAMCFG_BASE RAMCFG_BASE_NS + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define RIFSC RIFSC_NS +#define RIFSC_BASE RIFSC_BASE_NS + +#define RISAF1 RISAF1_NS +#define RISAF1_BASE RISAF1_BASE_NS + +#define RISAF2 RISAF2_NS +#define RISAF2_BASE RISAF2_BASE_NS + +#define RISAF3 RISAF3_NS +#define RISAF3_BASE RISAF3_BASE_NS + +#define RISAF4 RISAF4_NS +#define RISAF4_BASE RISAF4_BASE_NS + +#define RISAF5 RISAF5_NS +#define RISAF5_BASE RISAF5_BASE_NS + +#define RISAF6 RISAF6_NS +#define RISAF6_BASE RISAF6_BASE_NS + +#define RISAF7 RISAF7_NS +#define RISAF7_BASE RISAF7_BASE_NS + +#define RISAF8 RISAF8_NS +#define RISAF8_BASE RISAF8_BASE_NS + +#define RISAF9 RISAF9_NS +#define RISAF9_BASE RISAF9_BASE_NS + +#define RISAF11 RISAF11_NS +#define RISAF11_BASE RISAF11_BASE_NS + +#define RISAF12 RISAF12_NS +#define RISAF12_BASE RISAF12_BASE_NS + +#define RISAF13 RISAF13_NS +#define RISAF13_BASE RISAF13_BASE_NS + +#define RISAF14 RISAF14_NS +#define RISAF14_BASE RISAF14_BASE_NS + +#define RISAF15 RISAF15_NS +#define RISAF15_BASE RISAF15_BASE_NS + +#define RISAF21 RISAF21_NS +#define RISAF21_BASE RISAF21_BASE_NS + +#define RISAF22 RISAF22_NS +#define RISAF22_BASE RISAF22_BASE_NS + +#define RISAF23 RISAF23_NS +#define RISAF23_BASE RISAF23_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define SPDIFRX SPDIFRX_NS +#define SPDIFRX_BASE SPDIFRX_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM9 TIM9_NS +#define TIM9_BASE TIM9_BASE_NS + +#define TIM10 TIM10_NS +#define TIM10_BASE TIM10_BASE_NS + +#define TIM11 TIM11_NS +#define TIM11_BASE TIM11_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define TIM18 TIM18_NS +#define TIM18_BASE TIM18_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USB1_OTG_HS USB1_OTG_HS_NS +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS + +#define USB2_OTG_HS USB2_OTG_HS_NS +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS + +#define USB1_HS_PHYC USB1_HS_PHYC_NS +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS + +#define USB2_HS_PHYC USB2_HS_PHYC_NS +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS + +#define VENC VENC_NS +#define VENC_BASE VENC_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define XSPI1 XSPI1_NS + +#define XSPI2 XSPI2_NS + +#define XSPI3 XSPI3_NS + +#define XSPIM XSPIM_NS +#define XSPIM_BASE XSPIM_BASE_NS + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_NS + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_NS + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_declaration */ + +/** @addtogroup STM32N6xx_Peripheral_Timing_Definition + * @{ + */ + +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ + +/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30UL) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0UL) +#define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16UL) +#define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ + +#define ADC_CALFACT_CALADDOS_Pos (31UL) +#define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */ +#define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */ + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_OP0_Pos (0UL) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */ + +#define ADC_OR_OP1_Pos (1UL) +#define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */ + +#define ADC_OR_OP2_Pos (2UL) +#define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */ +#define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */ + + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* BSEC unit (Boot and Security) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for BSEC_FVRw register *******************/ +#define BSEC_FVRw_FV_Pos (0UL) +#define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */ + +/***************** Bit definition for BSEC_SPLOCKx register *****************/ +#define BSEC_SPLOCKx_SPLOCK0_Pos (0UL) +#define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */ +#define BSEC_SPLOCKx_SPLOCK1_Pos (1UL) +#define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */ +#define BSEC_SPLOCKx_SPLOCK2_Pos (2UL) +#define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */ +#define BSEC_SPLOCKx_SPLOCK3_Pos (3UL) +#define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */ +#define BSEC_SPLOCKx_SPLOCK4_Pos (4UL) +#define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */ +#define BSEC_SPLOCKx_SPLOCK5_Pos (5UL) +#define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */ +#define BSEC_SPLOCKx_SPLOCK6_Pos (6UL) +#define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */ +#define BSEC_SPLOCKx_SPLOCK7_Pos (7UL) +#define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */ +#define BSEC_SPLOCKx_SPLOCK8_Pos (8UL) +#define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */ +#define BSEC_SPLOCKx_SPLOCK9_Pos (9UL) +#define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */ +#define BSEC_SPLOCKx_SPLOCK10_Pos (10UL) +#define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */ +#define BSEC_SPLOCKx_SPLOCK11_Pos (11UL) +#define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */ +#define BSEC_SPLOCKx_SPLOCK12_Pos (12UL) +#define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */ +#define BSEC_SPLOCKx_SPLOCK13_Pos (13UL) +#define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */ +#define BSEC_SPLOCKx_SPLOCK14_Pos (14UL) +#define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */ +#define BSEC_SPLOCKx_SPLOCK15_Pos (15UL) +#define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */ +#define BSEC_SPLOCKx_SPLOCK16_Pos (16UL) +#define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */ +#define BSEC_SPLOCKx_SPLOCK17_Pos (17UL) +#define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */ +#define BSEC_SPLOCKx_SPLOCK18_Pos (18UL) +#define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */ +#define BSEC_SPLOCKx_SPLOCK19_Pos (19UL) +#define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */ +#define BSEC_SPLOCKx_SPLOCK20_Pos (20UL) +#define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */ +#define BSEC_SPLOCKx_SPLOCK21_Pos (21UL) +#define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */ +#define BSEC_SPLOCKx_SPLOCK22_Pos (22UL) +#define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */ +#define BSEC_SPLOCKx_SPLOCK23_Pos (23UL) +#define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */ +#define BSEC_SPLOCKx_SPLOCK24_Pos (24UL) +#define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */ +#define BSEC_SPLOCKx_SPLOCK25_Pos (25UL) +#define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */ +#define BSEC_SPLOCKx_SPLOCK26_Pos (26UL) +#define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */ +#define BSEC_SPLOCKx_SPLOCK27_Pos (27UL) +#define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */ +#define BSEC_SPLOCKx_SPLOCK28_Pos (28UL) +#define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */ +#define BSEC_SPLOCKx_SPLOCK29_Pos (29UL) +#define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */ +#define BSEC_SPLOCKx_SPLOCK30_Pos (30UL) +#define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */ +#define BSEC_SPLOCKx_SPLOCK31_Pos (31UL) +#define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */ + +/***************** Bit definition for BSEC_SWLOCKx register *****************/ +#define BSEC_SWLOCKx_SWLOCK0_Pos (0UL) +#define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */ +#define BSEC_SWLOCKx_SWLOCK1_Pos (1UL) +#define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */ +#define BSEC_SWLOCKx_SWLOCK2_Pos (2UL) +#define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */ +#define BSEC_SWLOCKx_SWLOCK3_Pos (3UL) +#define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */ +#define BSEC_SWLOCKx_SWLOCK4_Pos (4UL) +#define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */ +#define BSEC_SWLOCKx_SWLOCK5_Pos (5UL) +#define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */ +#define BSEC_SWLOCKx_SWLOCK6_Pos (6UL) +#define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */ +#define BSEC_SWLOCKx_SWLOCK7_Pos (7UL) +#define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */ +#define BSEC_SWLOCKx_SWLOCK8_Pos (8UL) +#define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */ +#define BSEC_SWLOCKx_SWLOCK9_Pos (9UL) +#define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */ +#define BSEC_SWLOCKx_SWLOCK10_Pos (10UL) +#define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */ +#define BSEC_SWLOCKx_SWLOCK11_Pos (11UL) +#define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */ +#define BSEC_SWLOCKx_SWLOCK12_Pos (12UL) +#define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */ +#define BSEC_SWLOCKx_SWLOCK13_Pos (13UL) +#define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */ +#define BSEC_SWLOCKx_SWLOCK14_Pos (14UL) +#define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */ +#define BSEC_SWLOCKx_SWLOCK15_Pos (15UL) +#define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */ +#define BSEC_SWLOCKx_SWLOCK16_Pos (16UL) +#define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */ +#define BSEC_SWLOCKx_SWLOCK17_Pos (17UL) +#define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */ +#define BSEC_SWLOCKx_SWLOCK18_Pos (18UL) +#define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */ +#define BSEC_SWLOCKx_SWLOCK19_Pos (19UL) +#define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */ +#define BSEC_SWLOCKx_SWLOCK20_Pos (20UL) +#define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */ +#define BSEC_SWLOCKx_SWLOCK21_Pos (21UL) +#define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */ +#define BSEC_SWLOCKx_SWLOCK22_Pos (22UL) +#define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */ +#define BSEC_SWLOCKx_SWLOCK23_Pos (23UL) +#define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */ +#define BSEC_SWLOCKx_SWLOCK24_Pos (24UL) +#define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */ +#define BSEC_SWLOCKx_SWLOCK25_Pos (25UL) +#define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */ +#define BSEC_SWLOCKx_SWLOCK26_Pos (26UL) +#define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */ +#define BSEC_SWLOCKx_SWLOCK27_Pos (27UL) +#define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */ +#define BSEC_SWLOCKx_SWLOCK28_Pos (28UL) +#define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */ +#define BSEC_SWLOCKx_SWLOCK29_Pos (29UL) +#define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */ +#define BSEC_SWLOCKx_SWLOCK30_Pos (30UL) +#define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */ +#define BSEC_SWLOCKx_SWLOCK31_Pos (31UL) +#define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */ + +/***************** Bit definition for BSEC_SRLOCKx register *****************/ +#define BSEC_SRLOCKx_SRLOCK0_Pos (0UL) +#define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */ +#define BSEC_SRLOCKx_SRLOCK1_Pos (1UL) +#define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */ +#define BSEC_SRLOCKx_SRLOCK2_Pos (2UL) +#define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */ +#define BSEC_SRLOCKx_SRLOCK3_Pos (3UL) +#define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */ +#define BSEC_SRLOCKx_SRLOCK4_Pos (4UL) +#define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */ +#define BSEC_SRLOCKx_SRLOCK5_Pos (5UL) +#define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */ +#define BSEC_SRLOCKx_SRLOCK6_Pos (6UL) +#define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */ +#define BSEC_SRLOCKx_SRLOCK7_Pos (7UL) +#define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */ +#define BSEC_SRLOCKx_SRLOCK8_Pos (8UL) +#define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */ +#define BSEC_SRLOCKx_SRLOCK9_Pos (9UL) +#define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */ +#define BSEC_SRLOCKx_SRLOCK10_Pos (10UL) +#define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */ +#define BSEC_SRLOCKx_SRLOCK11_Pos (11UL) +#define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */ +#define BSEC_SRLOCKx_SRLOCK12_Pos (12UL) +#define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */ +#define BSEC_SRLOCKx_SRLOCK13_Pos (13UL) +#define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */ +#define BSEC_SRLOCKx_SRLOCK14_Pos (14UL) +#define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */ +#define BSEC_SRLOCKx_SRLOCK15_Pos (15UL) +#define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */ +#define BSEC_SRLOCKx_SRLOCK16_Pos (16UL) +#define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */ +#define BSEC_SRLOCKx_SRLOCK17_Pos (17UL) +#define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */ +#define BSEC_SRLOCKx_SRLOCK18_Pos (18UL) +#define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */ +#define BSEC_SRLOCKx_SRLOCK19_Pos (19UL) +#define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */ +#define BSEC_SRLOCKx_SRLOCK20_Pos (20UL) +#define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */ +#define BSEC_SRLOCKx_SRLOCK21_Pos (21UL) +#define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */ +#define BSEC_SRLOCKx_SRLOCK22_Pos (22UL) +#define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */ +#define BSEC_SRLOCKx_SRLOCK23_Pos (23UL) +#define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */ +#define BSEC_SRLOCKx_SRLOCK24_Pos (24UL) +#define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */ +#define BSEC_SRLOCKx_SRLOCK25_Pos (25UL) +#define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */ +#define BSEC_SRLOCKx_SRLOCK26_Pos (26UL) +#define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */ +#define BSEC_SRLOCKx_SRLOCK27_Pos (27UL) +#define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */ +#define BSEC_SRLOCKx_SRLOCK28_Pos (28UL) +#define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */ +#define BSEC_SRLOCKx_SRLOCK29_Pos (29UL) +#define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */ +#define BSEC_SRLOCKx_SRLOCK30_Pos (30UL) +#define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */ +#define BSEC_SRLOCKx_SRLOCK31_Pos (31UL) +#define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */ + +/**************** Bit definition for BSEC_OTPVLDRx register *****************/ +#define BSEC_OTPVLDRx_VLDF0_Pos (0UL) +#define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */ +#define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */ +#define BSEC_OTPVLDRx_VLDF1_Pos (1UL) +#define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */ +#define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */ +#define BSEC_OTPVLDRx_VLDF2_Pos (2UL) +#define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */ +#define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */ +#define BSEC_OTPVLDRx_VLDF3_Pos (3UL) +#define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */ +#define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */ +#define BSEC_OTPVLDRx_VLDF4_Pos (4UL) +#define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */ +#define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */ +#define BSEC_OTPVLDRx_VLDF5_Pos (5UL) +#define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */ +#define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */ +#define BSEC_OTPVLDRx_VLDF6_Pos (6UL) +#define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */ +#define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */ +#define BSEC_OTPVLDRx_VLDF7_Pos (7UL) +#define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */ +#define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */ +#define BSEC_OTPVLDRx_VLDF8_Pos (8UL) +#define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */ +#define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */ +#define BSEC_OTPVLDRx_VLDF9_Pos (9UL) +#define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */ +#define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */ +#define BSEC_OTPVLDRx_VLDF10_Pos (10UL) +#define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */ +#define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */ +#define BSEC_OTPVLDRx_VLDF11_Pos (11UL) +#define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */ +#define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */ +#define BSEC_OTPVLDRx_VLDF12_Pos (12UL) +#define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */ +#define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */ +#define BSEC_OTPVLDRx_VLDF13_Pos (13UL) +#define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */ +#define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */ +#define BSEC_OTPVLDRx_VLDF14_Pos (14UL) +#define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */ +#define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */ +#define BSEC_OTPVLDRx_VLDF15_Pos (15UL) +#define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */ +#define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */ +#define BSEC_OTPVLDRx_VLDF16_Pos (16UL) +#define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */ +#define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */ +#define BSEC_OTPVLDRx_VLDF17_Pos (17UL) +#define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */ +#define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */ +#define BSEC_OTPVLDRx_VLDF18_Pos (18UL) +#define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */ +#define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */ +#define BSEC_OTPVLDRx_VLDF19_Pos (19UL) +#define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */ +#define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */ +#define BSEC_OTPVLDRx_VLDF20_Pos (20UL) +#define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */ +#define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */ +#define BSEC_OTPVLDRx_VLDF21_Pos (21UL) +#define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */ +#define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */ +#define BSEC_OTPVLDRx_VLDF22_Pos (22UL) +#define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */ +#define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */ +#define BSEC_OTPVLDRx_VLDF23_Pos (23UL) +#define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */ +#define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */ +#define BSEC_OTPVLDRx_VLDF24_Pos (24UL) +#define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */ +#define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */ +#define BSEC_OTPVLDRx_VLDF25_Pos (25UL) +#define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */ +#define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */ +#define BSEC_OTPVLDRx_VLDF26_Pos (26UL) +#define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */ +#define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */ +#define BSEC_OTPVLDRx_VLDF27_Pos (27UL) +#define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */ +#define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */ +#define BSEC_OTPVLDRx_VLDF28_Pos (28UL) +#define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */ +#define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */ +#define BSEC_OTPVLDRx_VLDF29_Pos (29UL) +#define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */ +#define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */ +#define BSEC_OTPVLDRx_VLDF30_Pos (30UL) +#define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */ +#define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */ +#define BSEC_OTPVLDRx_VLDF31_Pos (31UL) +#define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */ +#define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */ + +/****************** Bit definition for BSEC_SFSRx register ******************/ +#define BSEC_SFSRx_SFW0_Pos (0UL) +#define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */ +#define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */ +#define BSEC_SFSRx_SFW1_Pos (1UL) +#define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */ +#define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */ +#define BSEC_SFSRx_SFW2_Pos (2UL) +#define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */ +#define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */ +#define BSEC_SFSRx_SFW3_Pos (3UL) +#define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */ +#define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */ +#define BSEC_SFSRx_SFW4_Pos (4UL) +#define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */ +#define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */ +#define BSEC_SFSRx_SFW5_Pos (5UL) +#define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */ +#define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */ +#define BSEC_SFSRx_SFW6_Pos (6UL) +#define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */ +#define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */ +#define BSEC_SFSRx_SFW7_Pos (7UL) +#define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */ +#define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */ +#define BSEC_SFSRx_SFW8_Pos (8UL) +#define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */ +#define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */ +#define BSEC_SFSRx_SFW9_Pos (9UL) +#define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */ +#define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */ +#define BSEC_SFSRx_SFW10_Pos (10UL) +#define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */ +#define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */ +#define BSEC_SFSRx_SFW11_Pos (11UL) +#define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */ +#define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */ +#define BSEC_SFSRx_SFW12_Pos (12UL) +#define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */ +#define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */ +#define BSEC_SFSRx_SFW13_Pos (13UL) +#define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */ +#define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */ +#define BSEC_SFSRx_SFW14_Pos (14UL) +#define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */ +#define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */ +#define BSEC_SFSRx_SFW15_Pos (15UL) +#define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */ +#define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */ +#define BSEC_SFSRx_SFW16_Pos (16UL) +#define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */ +#define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */ +#define BSEC_SFSRx_SFW17_Pos (17UL) +#define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */ +#define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */ +#define BSEC_SFSRx_SFW18_Pos (18UL) +#define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */ +#define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */ +#define BSEC_SFSRx_SFW19_Pos (19UL) +#define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */ +#define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */ +#define BSEC_SFSRx_SFW20_Pos (20UL) +#define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */ +#define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */ +#define BSEC_SFSRx_SFW21_Pos (21UL) +#define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */ +#define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */ +#define BSEC_SFSRx_SFW22_Pos (22UL) +#define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */ +#define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */ +#define BSEC_SFSRx_SFW23_Pos (23UL) +#define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */ +#define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */ +#define BSEC_SFSRx_SFW24_Pos (24UL) +#define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */ +#define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */ +#define BSEC_SFSRx_SFW25_Pos (25UL) +#define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */ +#define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */ +#define BSEC_SFSRx_SFW26_Pos (26UL) +#define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */ +#define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */ +#define BSEC_SFSRx_SFW27_Pos (27UL) +#define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */ +#define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */ +#define BSEC_SFSRx_SFW28_Pos (28UL) +#define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */ +#define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */ +#define BSEC_SFSRx_SFW29_Pos (29UL) +#define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */ +#define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */ +#define BSEC_SFSRx_SFW30_Pos (30UL) +#define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */ +#define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */ +#define BSEC_SFSRx_SFW31_Pos (31UL) +#define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */ +#define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */ + +/****************** Bit definition for BSEC_OTPCR register ******************/ +#define BSEC_OTPCR_ADDR_Pos (0UL) +#define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */ +#define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */ +#define BSEC_OTPCR_PROG_Pos (13UL) +#define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */ +#define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */ +#define BSEC_OTPCR_PPLOCK_Pos (14UL) +#define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */ +#define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */ +#define BSEC_OTPCR_LASTCID_Pos (19UL) +#define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */ +#define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */ + +/******************* Bit definition for BSEC_WDR register *******************/ +#define BSEC_WDR_WRDATA_Pos (0UL) +#define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */ + +/**************** Bit definition for BSEC_SCRATCHRx register ****************/ +#define BSEC_SCRATCHRx_SDATA_Pos (0UL) +#define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */ + +/****************** Bit definition for BSEC_LOCKR register ******************/ +#define BSEC_LOCKR_GWLOCK_Pos (0UL) +#define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */ +#define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */ +#define BSEC_LOCKR_HKLOCK_Pos (2UL) +#define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */ +#define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */ + +/***************** Bit definition for BSEC_JTAGINR register *****************/ +#define BSEC_JTAGINR_JDATAIN_Pos (0UL) +#define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */ + +/**************** Bit definition for BSEC_JTAGOUTR register *****************/ +#define BSEC_JTAGOUTR_JDATAOUT_Pos (0UL) +#define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */ + +/***************** Bit definition for BSEC_UNMAPR register ******************/ +#define BSEC_UNMAPR_UNMAP_Pos (0UL) +#define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */ + +/******************* Bit definition for BSEC_SR register ********************/ +#define BSEC_SR_HVALID_Pos (1UL) +#define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */ +#define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */ +#define BSEC_SR_DBGREQ_Pos (16UL) +#define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */ +#define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */ +#define BSEC_SR_NVSTATE_Pos (26UL) +#define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */ +#define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */ + +/****************** Bit definition for BSEC_OTPSR register ******************/ +#define BSEC_OTPSR_BUSY_Pos (0UL) +#define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */ +#define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */ +#define BSEC_OTPSR_INIT_DONE_Pos (1UL) +#define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */ +#define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */ +#define BSEC_OTPSR_HIDEUP_Pos (2UL) +#define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */ +#define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */ +#define BSEC_OTPSR_OTPNVIR_Pos (4UL) +#define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */ +#define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */ +#define BSEC_OTPSR_OTPERR_Pos (5UL) +#define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */ +#define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */ +#define BSEC_OTPSR_OTPSEC_Pos (6UL) +#define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */ +#define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */ +#define BSEC_OTPSR_PROGFAIL_Pos (16UL) +#define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */ +#define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */ +#define BSEC_OTPSR_DISTURBF_Pos (17UL) +#define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */ +#define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */ +#define BSEC_OTPSR_DEDF_Pos (18UL) +#define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */ +#define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */ +#define BSEC_OTPSR_SECF_Pos (19UL) +#define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */ +#define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */ +#define BSEC_OTPSR_PPLF_Pos (20UL) +#define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */ +#define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */ +#define BSEC_OTPSR_PPLMF_Pos (21UL) +#define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */ +#define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */ +#define BSEC_OTPSR_AMEF_Pos (22UL) +#define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */ +#define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */ + +/***************** Bit definition for BSEC_EPOCHRx register *****************/ +#define BSEC_EPOCHRx_EPOCH_Pos (0UL) +#define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */ + +/**************** Bit definition for BSEC_EPOCHSELR register ****************/ +#define BSEC_EPOCHSELR_EPSEL_Pos (0UL) +#define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */ +#define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */ + +/****************** Bit definition for BSEC_DBGCR register ******************/ +#define BSEC_DBGCR_UNLOCK_Pos (8UL) +#define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */ +#define BSEC_DBGCR_AUTH_HDPL_Pos (16UL) +#define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */ +#define BSEC_DBGCR_AUTH_SEC_Pos (24UL) +#define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */ + +/*************** Bit definition for BSEC_AP_UNLOCK register *****************/ +#define BSEC_AP_UNLOCK_UNLOCK_Pos (0UL) +#define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */ +#define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */ + +/***************** Bit definition for BSEC_HDPLSR register ******************/ +#define BSEC_HDPLSR_HDPL_Pos (0UL) +#define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */ + +/***************** Bit definition for BSEC_HDPLCR register ******************/ +#define BSEC_HDPLCR_INCR_HDPL_Pos (0UL) +#define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */ + +/***************** Bit definition for BSEC_NEXTLR register ******************/ +#define BSEC_NEXTLR_INCR_Pos (0UL) +#define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */ +#define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */ + +/***************** Bit definition for BSEC_WOSCRx register ******************/ +#define BSEC_WOSCRx_WOSDATA_Pos (0UL) +#define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */ + +/****************** Bit definition for BSEC_HRCR register *******************/ +#define BSEC_HRCR_HRC_Pos (0UL) +#define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */ + +/****************** Bit definition for BSEC_WRCR register *******************/ +#define BSEC_WRCR_WRC_Pos (0UL) +#define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */ + + +/******************************************************************************/ +/* */ +/* CACHEAXI */ +/* */ +/******************************************************************************/ +/**************** Bit definition for CACHEAXI_CR1 register ******************/ +#define CACHEAXI_CR1_EN_Pos (0UL) +#define CACHEAXI_CR1_EN_Msk (0x1UL << CACHEAXI_CR1_EN_Pos) /*!< 0x00000001 */ +#define CACHEAXI_CR1_EN CACHEAXI_CR1_EN_Msk /*!< Enable */ +#define CACHEAXI_CR1_CACHEINV_Pos (1UL) +#define CACHEAXI_CR1_CACHEINV_Msk (0x1UL << CACHEAXI_CR1_CACHEINV_Pos) /*!< 0x00000002 */ +#define CACHEAXI_CR1_CACHEINV CACHEAXI_CR1_CACHEINV_Msk /*!< Cache invalidation */ +#define CACHEAXI_CR1_RHITMEN_Pos (16UL) +#define CACHEAXI_CR1_RHITMEN_Msk (0x1UL << CACHEAXI_CR1_RHITMEN_Pos) /*!< 0x00010000 */ +#define CACHEAXI_CR1_RHITMEN CACHEAXI_CR1_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define CACHEAXI_CR1_RMISSMEN_Pos (17UL) +#define CACHEAXI_CR1_RMISSMEN_Msk (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos) /*!< 0x00020000 */ +#define CACHEAXI_CR1_RMISSMEN CACHEAXI_CR1_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define CACHEAXI_CR1_RHITMRST_Pos (18UL) +#define CACHEAXI_CR1_RHITMRST_Msk (0x1UL << CACHEAXI_CR1_RHITMRST_Pos) /*!< 0x00040000 */ +#define CACHEAXI_CR1_RHITMRST CACHEAXI_CR1_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define CACHEAXI_CR1_RMISSMRST_Pos (19UL) +#define CACHEAXI_CR1_RMISSMRST_Msk (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos) /*!< 0x00080000 */ +#define CACHEAXI_CR1_RMISSMRST CACHEAXI_CR1_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define CACHEAXI_CR1_WHITMEN_Pos (20UL) +#define CACHEAXI_CR1_WHITMEN_Msk (0x1UL << CACHEAXI_CR1_WHITMEN_Pos) /*!< 0x00100000 */ +#define CACHEAXI_CR1_WHITMEN CACHEAXI_CR1_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define CACHEAXI_CR1_WMISSMEN_Pos (21UL) +#define CACHEAXI_CR1_WMISSMEN_Msk (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos) /*!< 0x00200000 */ +#define CACHEAXI_CR1_WMISSMEN CACHEAXI_CR1_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define CACHEAXI_CR1_WHITMRST_Pos (22UL) +#define CACHEAXI_CR1_WHITMRST_Msk (0x1UL << CACHEAXI_CR1_WHITMRST_Pos) /*!< 0x00400000 */ +#define CACHEAXI_CR1_WHITMRST CACHEAXI_CR1_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define CACHEAXI_CR1_WMISSMRST_Pos (23UL) +#define CACHEAXI_CR1_WMISSMRST_Msk (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos) /*!< 0x00800000 */ +#define CACHEAXI_CR1_WMISSMRST CACHEAXI_CR1_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define CACHEAXI_CR1_RAMMEN_Pos (24UL) +#define CACHEAXI_CR1_RAMMEN_Msk (0x1UL << CACHEAXI_CR1_RAMMEN_Pos) /*!< 0x01000000 */ +#define CACHEAXI_CR1_RAMMEN CACHEAXI_CR1_RAMMEN_Msk /*!< Read-allocate miss monitor enable */ +#define CACHEAXI_CR1_WAMMEN_Pos (25UL) +#define CACHEAXI_CR1_WAMMEN_Msk (0x1UL << CACHEAXI_CR1_WAMMEN_Pos) /*!< 0x02000000 */ +#define CACHEAXI_CR1_WAMMEN CACHEAXI_CR1_WAMMEN_Msk /*!< Write-allocate miss monitor enable */ +#define CACHEAXI_CR1_RAMMRST_Pos (26UL) +#define CACHEAXI_CR1_RAMMRST_Msk (0x1UL << CACHEAXI_CR1_RAMMRST_Pos) /*!< 0x04000000 */ +#define CACHEAXI_CR1_RAMMRST CACHEAXI_CR1_RAMMRST_Msk /*!< Read-allocate miss monitor reset */ +#define CACHEAXI_CR1_WAMMRST_Pos (27UL) +#define CACHEAXI_CR1_WAMMRST_Msk (0x1UL << CACHEAXI_CR1_WAMMRST_Pos) /*!< 0x08000000 */ +#define CACHEAXI_CR1_WAMMRST CACHEAXI_CR1_WAMMRST_Msk /*!< Write-allocate miss monitor reset */ +#define CACHEAXI_CR1_WTMEN_Pos (28UL) +#define CACHEAXI_CR1_WTMEN_Msk (0x1UL << CACHEAXI_CR1_WTMEN_Pos) /*!< 0x10000000 */ +#define CACHEAXI_CR1_WTMEN CACHEAXI_CR1_WTMEN_Msk /*!< Write-through monitor enable */ +#define CACHEAXI_CR1_EVIMEN_Pos (29UL) +#define CACHEAXI_CR1_EVIMEN_Msk (0x1UL << CACHEAXI_CR1_EVIMEN_Pos) /*!< 0x20000000 */ +#define CACHEAXI_CR1_EVIMEN CACHEAXI_CR1_EVIMEN_Msk /*!< Eviction monitor enable */ +#define CACHEAXI_CR1_WTMRST_Pos (30UL) +#define CACHEAXI_CR1_WTMRST_Msk (0x1UL << CACHEAXI_CR1_WTMRST_Pos) /*!< 0x40000000 */ +#define CACHEAXI_CR1_WTMRST CACHEAXI_CR1_WTMRST_Msk /*!< Write-through monitor reset */ +#define CACHEAXI_CR1_EVIMRST_Pos (31UL) +#define CACHEAXI_CR1_EVIMRST_Msk (0x1UL << CACHEAXI_CR1_EVIMRST_Pos) /*!< 0x80000000 */ +#define CACHEAXI_CR1_EVIMRST CACHEAXI_CR1_EVIMRST_Msk /*!< Eviction monitor reset */ + +/****************** Bit definition for CACHEAXI_SR register *******************/ +#define CACHEAXI_SR_BUSYF_Pos (0UL) +#define CACHEAXI_SR_BUSYF_Msk (0x1UL << CACHEAXI_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define CACHEAXI_SR_BUSYF CACHEAXI_SR_BUSYF_Msk /*!< Busy flag */ +#define CACHEAXI_SR_BSYENDF_Pos (1UL) +#define CACHEAXI_SR_BSYENDF_Msk (0x1UL << CACHEAXI_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define CACHEAXI_SR_BSYENDF CACHEAXI_SR_BSYENDF_Msk /*!< Busy end flag */ +#define CACHEAXI_SR_ERRF_Pos (2UL) +#define CACHEAXI_SR_ERRF_Msk (0x1UL << CACHEAXI_SR_ERRF_Pos) /*!< 0x00000004 */ +#define CACHEAXI_SR_ERRF CACHEAXI_SR_ERRF_Msk /*!< Cache error flag */ +#define CACHEAXI_SR_BUSYCMDF_Pos (3UL) +#define CACHEAXI_SR_BUSYCMDF_Msk (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define CACHEAXI_SR_BUSYCMDF CACHEAXI_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define CACHEAXI_SR_CMDENDF_Pos (4UL) +#define CACHEAXI_SR_CMDENDF_Msk (0x1UL << CACHEAXI_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define CACHEAXI_SR_CMDENDF CACHEAXI_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for CACHEAXI_IER register ******************/ +#define CACHEAXI_IER_BSYENDIE_Pos (1UL) +#define CACHEAXI_IER_BSYENDIE_Msk (0x1UL << CACHEAXI_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define CACHEAXI_IER_BSYENDIE CACHEAXI_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define CACHEAXI_IER_ERRIE_Pos (2UL) +#define CACHEAXI_IER_ERRIE_Msk (0x1UL << CACHEAXI_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define CACHEAXI_IER_ERRIE CACHEAXI_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define CACHEAXI_IER_CMDENDIE_Pos (4UL) +#define CACHEAXI_IER_CMDENDIE_Msk (0x1UL << CACHEAXI_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define CACHEAXI_IER_CMDENDIE CACHEAXI_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for CACHEAXI_FCR register ******************/ +#define CACHEAXI_FCR_CBSYENDF_Pos (1UL) +#define CACHEAXI_FCR_CBSYENDF_Msk (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define CACHEAXI_FCR_CBSYENDF CACHEAXI_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define CACHEAXI_FCR_CERRF_Pos (2UL) +#define CACHEAXI_FCR_CERRF_Msk (0x1UL << CACHEAXI_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define CACHEAXI_FCR_CERRF CACHEAXI_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define CACHEAXI_FCR_CCMDENDF_Pos (4UL) +#define CACHEAXI_FCR_CCMDENDF_Msk (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define CACHEAXI_FCR_CCMDENDF CACHEAXI_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for CACHEAXI_RHMONR register ****************/ +#define CACHEAXI_RHMONR_RHITMON_Pos (0UL) +#define CACHEAXI_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RHMONR_RHITMON CACHEAXI_RHMONR_RHITMON_Msk /*!< Cache read hit monitor register */ + +/****************** Bit definition for CACHEAXI_RMMONR register ****************/ +#define CACHEAXI_RMMONR_RMISSMON_Pos (0UL) +#define CACHEAXI_RMMONR_RMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RMMONR_RMISSMON CACHEAXI_RMMONR_RMISSMON_Msk /*!< Cache read miss monitor register */ + +/****************** Bit definition for CACHEAXI_RAMMONR register ****************/ +#define CACHEAXI_RAMMONR_RAMMON_Pos (0UL) +#define CACHEAXI_RAMMONR_RAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RAMMONR_RAMMON CACHEAXI_RAMMONR_RAMMON_Msk /*!< Cache read-allocate miss monitor counter */ + +/****************** Bit definition for CACHEAXI_EVIMONR register ****************/ +#define CACHEAXI_EVIMONR_EVIMON_Pos (0UL) +#define CACHEAXI_EVIMONR_EVIMON_Msk (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_EVIMONR_EVIMON CACHEAXI_EVIMONR_EVIMON_Msk /*!< Cache eviction monitor counter */ + +/****************** Bit definition for CACHEAXI_WHMONR register ****************/ +#define CACHEAXI_WHMONR_WHITMON_Pos (0UL) +#define CACHEAXI_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WHMONR_WHITMON CACHEAXI_WHMONR_WHITMON_Msk /*!< Cache write hit monitor register */ + +/****************** Bit definition for CACHEAXI_WMMONR register ****************/ +#define CACHEAXI_WMMONR_WMISSMON_Pos (0UL) +#define CACHEAXI_WMMONR_WMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WMMONR_WMISSMON CACHEAXI_WMMONR_WMISSMON_Msk /*!< Cache write miss monitor register */ + +/****************** Bit definition for CACHEAXI_WAMMONR register ****************/ +#define CACHEAXI_WAMMONR_WAMMON_Pos (0UL) +#define CACHEAXI_WAMMONR_WAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WAMMONR_WAMMON CACHEAXI_WAMMONR_WAMMON_Msk /*!< Cache write-allocate miss monitor register */ + +/****************** Bit definition for CACHEAXI_WTMONR register ****************/ +#define CACHEAXI_WTMONR_WTMON_Pos (0UL) +#define CACHEAXI_WTMONR_WTMON_Msk (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WTMONR_WTMON CACHEAXI_WTMONR_WTMON_Msk /*!< Cache write-through monitor register */ + +/**************** Bit definition for CACHEAXI_CR2 register ******************/ +#define CACHEAXI_CR2_STARTCMD_Pos (0UL) +#define CACHEAXI_CR2_STARTCMD_Msk (0x1UL << CACHEAXI_CR2_STARTCMD_Pos) /*!< 0x00000001 */ +#define CACHEAXI_CR2_STARTCMD CACHEAXI_CR2_STARTCMD_Msk /*!< Starts maintenance range command */ +#define CACHEAXI_CR2_CACHECMD_Pos (1UL) +#define CACHEAXI_CR2_CACHECMD_Msk (0x3UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000006 */ +#define CACHEAXI_CR2_CACHECMD CACHEAXI_CR2_CACHECMD_Msk /*!< Cache command maintenance operation */ +#define CACHEAXI_CR2_CACHECMD_0 (0x1UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000002 */ +#define CACHEAXI_CR2_CACHECMD_1 (0x2UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000004 */ + +/****************** Bit definition for CACHEAXI_CMDRSADDRR register ****************/ +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos (0UL) +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */ +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for CACHEAXI_CMDREADDRR register ****************/ +#define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos (0UL) +#define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFC0 */ +#define CACHEAXI_CMDREADDRR_CMDENDADDR CACHEAXI_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* (CSI) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CSI_CR register ********************/ +#define CSI_CR_CSIEN_Pos (0UL) +#define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */ +#define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */ +#define CSI_CR_VC0START_Pos (2UL) +#define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */ +#define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */ +#define CSI_CR_VC0STOP_Pos (3UL) +#define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */ +#define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */ +#define CSI_CR_VC1START_Pos (6UL) +#define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */ +#define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */ +#define CSI_CR_VC1STOP_Pos (7UL) +#define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */ +#define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */ +#define CSI_CR_VC2START_Pos (10UL) +#define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */ +#define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */ +#define CSI_CR_VC2STOP_Pos (11UL) +#define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */ +#define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */ +#define CSI_CR_VC3START_Pos (14UL) +#define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */ +#define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */ +#define CSI_CR_VC3STOP_Pos (15UL) +#define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */ +#define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */ + +/******************* Bit definition for CSI_PCR register ********************/ +#define CSI_PCR_PWRDOWN_Pos (0UL) +#define CSI_PCR_PWRDOWN_Msk (0x1UL << CSI_PCR_PWRDOWN_Pos) /*!< 0x00000001 */ +#define CSI_PCR_PWRDOWN CSI_PCR_PWRDOWN_Msk /*!< Virtual channel 3 start */ +#define CSI_PCR_CLEN_Pos (1UL) +#define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */ +#define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */ +#define CSI_PCR_DL0EN_Pos (2UL) +#define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */ +#define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */ +#define CSI_PCR_DL1EN_Pos (3UL) +#define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */ +#define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */ + +/***************** Bit definition for CSI_VC0CFGR1 register *****************/ +#define CSI_VC0CFGR1_ALLDT_Pos (0UL) +#define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC0CFGR1_DT0EN_Pos (1UL) +#define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC0CFGR1_DT1EN_Pos (2UL) +#define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC0CFGR1_DT2EN_Pos (3UL) +#define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC0CFGR1_DT3EN_Pos (4UL) +#define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC0CFGR1_DT4EN_Pos (5UL) +#define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC0CFGR1_DT5EN_Pos (6UL) +#define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC0CFGR1_DT6EN_Pos (7UL) +#define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC0CFGR1_CDTFT_Pos (8UL) +#define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC0CFGR1_DT0_Pos (16UL) +#define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC0CFGR1_DT0FT_Pos (24UL) +#define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC0CFGR2 register *****************/ +#define CSI_VC0CFGR2_DT1_Pos (0UL) +#define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT1FT_Pos (8UL) +#define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC0CFGR2_DT2_Pos (16UL) +#define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT2FT_Pos (24UL) +#define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC0CFGR3 register *****************/ +#define CSI_VC0CFGR3_DT3_Pos (0UL) +#define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT3FT_Pos (8UL) +#define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC0CFGR3_DT4_Pos (16UL) +#define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT4FT_Pos (24UL) +#define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC0CFGR4 register *****************/ +#define CSI_VC0CFGR4_DT5_Pos (0UL) +#define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT5FT_Pos (8UL) +#define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC0CFGR4_DT6_Pos (16UL) +#define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT6FT_Pos (24UL) +#define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC1CFGR1 register *****************/ +#define CSI_VC1CFGR1_ALLDT_Pos (0UL) +#define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC1CFGR1_DT0EN_Pos (1UL) +#define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC1CFGR1_DT1EN_Pos (2UL) +#define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC1CFGR1_DT2EN_Pos (3UL) +#define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC1CFGR1_DT3EN_Pos (4UL) +#define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC1CFGR1_DT4EN_Pos (5UL) +#define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC1CFGR1_DT5EN_Pos (6UL) +#define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC1CFGR1_DT6EN_Pos (7UL) +#define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC1CFGR1_CDTFT_Pos (8UL) +#define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC1CFGR1_DT0_Pos (16UL) +#define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC1CFGR1_DT0FT_Pos (24UL) +#define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC1CFGR2 register *****************/ +#define CSI_VC1CFGR2_DT1_Pos (0UL) +#define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT1FT_Pos (8UL) +#define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC1CFGR2_DT2_Pos (16UL) +#define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT2FT_Pos (24UL) +#define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC1CFGR3 register *****************/ +#define CSI_VC1CFGR3_DT3_Pos (0UL) +#define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT3FT_Pos (8UL) +#define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC1CFGR3_DT4_Pos (16UL) +#define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT4FT_Pos (24UL) +#define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC1CFGR4 register *****************/ +#define CSI_VC1CFGR4_DT5_Pos (0UL) +#define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT5FT_Pos (8UL) +#define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC1CFGR4_DT6_Pos (16UL) +#define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT6FT_Pos (24UL) +#define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC2CFGR1 register *****************/ +#define CSI_VC2CFGR1_ALLDT_Pos (0UL) +#define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC2CFGR1_DT0EN_Pos (1UL) +#define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC2CFGR1_DT1EN_Pos (2UL) +#define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC2CFGR1_DT2EN_Pos (3UL) +#define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC2CFGR1_DT3EN_Pos (4UL) +#define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC2CFGR1_DT4EN_Pos (5UL) +#define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC2CFGR1_DT5EN_Pos (6UL) +#define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC2CFGR1_DT6EN_Pos (7UL) +#define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC2CFGR1_CDTFT_Pos (8UL) +#define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC2CFGR1_DT0_Pos (16UL) +#define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC2CFGR1_DT0FT_Pos (24UL) +#define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC2CFGR2 register *****************/ +#define CSI_VC2CFGR2_DT1_Pos (0UL) +#define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT1FT_Pos (8UL) +#define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC2CFGR2_DT2_Pos (16UL) +#define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT2FT_Pos (24UL) +#define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC2CFGR3 register *****************/ +#define CSI_VC2CFGR3_DT3_Pos (0UL) +#define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT3FT_Pos (8UL) +#define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC2CFGR3_DT4_Pos (16UL) +#define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT4FT_Pos (24UL) +#define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC2CFGR4 register *****************/ +#define CSI_VC2CFGR4_DT5_Pos (0UL) +#define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT5FT_Pos (8UL) +#define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC2CFGR4_DT6_Pos (16UL) +#define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT6FT_Pos (24UL) +#define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC3CFGR1 register *****************/ +#define CSI_VC3CFGR1_ALLDT_Pos (0UL) +#define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC3CFGR1_DT0EN_Pos (1UL) +#define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC3CFGR1_DT1EN_Pos (2UL) +#define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC3CFGR1_DT2EN_Pos (3UL) +#define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC3CFGR1_DT3EN_Pos (4UL) +#define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC3CFGR1_DT4EN_Pos (5UL) +#define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC3CFGR1_DT5EN_Pos (6UL) +#define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC3CFGR1_DT6EN_Pos (7UL) +#define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC3CFGR1_CDTFT_Pos (8UL) +#define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC3CFGR1_DT0_Pos (16UL) +#define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC3CFGR1_DT0FT_Pos (24UL) +#define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC3CFGR2 register *****************/ +#define CSI_VC3CFGR2_DT1_Pos (0UL) +#define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT1FT_Pos (8UL) +#define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC3CFGR2_DT2_Pos (16UL) +#define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT2FT_Pos (24UL) +#define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC3CFGR3 register *****************/ +#define CSI_VC3CFGR3_DT3_Pos (0UL) +#define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT3FT_Pos (8UL) +#define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC3CFGR3_DT4_Pos (16UL) +#define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT4FT_Pos (24UL) +#define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC3CFGR4 register *****************/ +#define CSI_VC3CFGR4_DT5_Pos (0UL) +#define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT5FT_Pos (8UL) +#define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC3CFGR4_DT6_Pos (16UL) +#define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT6FT_Pos (24UL) +#define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_LB0CFGR register ******************/ +#define CSI_LB0CFGR_BYTECNT_Pos (0UL) +#define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB0CFGR_LINECNT_Pos (16UL) +#define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB1CFGR register ******************/ +#define CSI_LB1CFGR_BYTECNT_Pos (0UL) +#define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB1CFGR_LINECNT_Pos (16UL) +#define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB2CFGR register ******************/ +#define CSI_LB2CFGR_BYTECNT_Pos (0UL) +#define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB2CFGR_LINECNT_Pos (16UL) +#define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB3CFGR register ******************/ +#define CSI_LB3CFGR_BYTECNT_Pos (0UL) +#define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB3CFGR_LINECNT_Pos (16UL) +#define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_TIM0CFGR register *****************/ +#define CSI_TIM0CFGR_COUNT_Pos (0UL) +#define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM1CFGR register *****************/ +#define CSI_TIM1CFGR_COUNT_Pos (0UL) +#define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM2CFGR register *****************/ +#define CSI_TIM2CFGR_COUNT_Pos (0UL) +#define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM3CFGR register *****************/ +#define CSI_TIM3CFGR_COUNT_Pos (0UL) +#define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/****************** Bit definition for CSI_LMCFGR register ******************/ +#define CSI_LMCFGR_LANENB_Pos (8UL) +#define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */ +#define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */ +#define CSI_LMCFGR_DL0MAP_Pos (16UL) +#define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */ +#define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */ +#define CSI_LMCFGR_DL1MAP_Pos (20UL) +#define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */ +#define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */ + +/****************** Bit definition for CSI_PRGITR register ******************/ +#define CSI_PRGITR_LB0VC_Pos (0UL) +#define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */ +#define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */ +#define CSI_PRGITR_LB0EN_Pos (3UL) +#define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */ +#define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */ +#define CSI_PRGITR_LB1VC_Pos (4UL) +#define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */ +#define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */ +#define CSI_PRGITR_LB1EN_Pos (7UL) +#define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */ +#define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */ +#define CSI_PRGITR_LB2VC_Pos (8UL) +#define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */ +#define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */ +#define CSI_PRGITR_LB2EN_Pos (11UL) +#define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */ +#define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */ +#define CSI_PRGITR_LB3VC_Pos (12UL) +#define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */ +#define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */ +#define CSI_PRGITR_LB3EN_Pos (15UL) +#define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */ +#define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */ +#define CSI_PRGITR_TIM0VC_Pos (16UL) +#define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */ +#define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM0EOF_Pos (18UL) +#define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */ +#define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */ +#define CSI_PRGITR_TIM0EN_Pos (19UL) +#define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */ +#define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */ +#define CSI_PRGITR_TIM1VC_Pos (20UL) +#define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */ +#define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM1EOF_Pos (22UL) +#define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */ +#define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */ +#define CSI_PRGITR_TIM1EN_Pos (23UL) +#define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */ +#define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */ +#define CSI_PRGITR_TIM2VC_Pos (24UL) +#define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */ +#define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM2EOF_Pos (26UL) +#define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */ +#define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */ +#define CSI_PRGITR_TIM2EN_Pos (27UL) +#define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */ +#define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */ +#define CSI_PRGITR_TIM3VC_Pos (28UL) +#define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */ +#define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM3EOF_Pos (30UL) +#define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */ +#define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */ +#define CSI_PRGITR_TIM3EN_Pos (31UL) +#define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */ +#define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */ + +/******************* Bit definition for CSI_WDR register ********************/ +#define CSI_WDR_CNT_Pos (0UL) +#define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */ +#define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */ + +/******************* Bit definition for CSI_IER0 register *******************/ +#define CSI_IER0_LB0IE_Pos (0UL) +#define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */ +#define CSI_IER0_LB1IE_Pos (1UL) +#define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */ +#define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */ +#define CSI_IER0_LB2IE_Pos (2UL) +#define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */ +#define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */ +#define CSI_IER0_LB3IE_Pos (3UL) +#define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */ +#define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */ +#define CSI_IER0_TIM0IE_Pos (4UL) +#define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */ +#define CSI_IER0_TIM1IE_Pos (5UL) +#define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */ +#define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */ +#define CSI_IER0_TIM2IE_Pos (6UL) +#define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */ +#define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */ +#define CSI_IER0_TIM3IE_Pos (7UL) +#define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */ +#define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */ +#define CSI_IER0_SOF0IE_Pos (8UL) +#define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */ +#define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_SOF1IE_Pos (9UL) +#define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_SOF2IE_Pos (10UL) +#define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */ +#define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_SOF3IE_Pos (11UL) +#define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */ +#define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_EOF0IE_Pos (12UL) +#define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */ +#define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_EOF1IE_Pos (13UL) +#define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */ +#define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_EOF2IE_Pos (14UL) +#define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */ +#define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_EOF3IE_Pos (15UL) +#define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */ +#define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_SPKTIE_Pos (16UL) +#define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */ +#define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */ +#define CSI_IER0_CCFIFOFIE_Pos (21UL) +#define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */ +#define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */ +#define CSI_IER0_CRCERRIE_Pos (24UL) +#define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */ +#define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */ +#define CSI_IER0_ECCERRIE_Pos (25UL) +#define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */ +#define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */ +#define CSI_IER0_CECCERRIE_Pos (26UL) +#define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */ +#define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */ +#define CSI_IER0_IDERRIE_Pos (27UL) +#define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */ +#define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */ +#define CSI_IER0_SPKTERRIE_Pos (28UL) +#define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */ +#define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */ +#define CSI_IER0_WDERRIE_Pos (29UL) +#define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */ +#define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */ +#define CSI_IER0_SYNCERRIE_Pos (30UL) +#define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */ +#define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */ + +/******************* Bit definition for CSI_IER1 register *******************/ +#define CSI_IER1_ESOTDL0IE_Pos (0UL) +#define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */ +#define CSI_IER1_ESOTSYNCDL0IE_Pos (1UL) +#define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */ +#define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */ +#define CSI_IER1_EESCDL0IE_Pos (2UL) +#define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */ +#define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL0IE_Pos (3UL) +#define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */ +#define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL0IE_Pos (4UL) +#define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */ +#define CSI_IER1_ESOTDL1IE_Pos (8UL) +#define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */ +#define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */ +#define CSI_IER1_ESOTSYNCDL1IE_Pos (9UL) +#define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */ +#define CSI_IER1_EESCDL1IE_Pos (10UL) +#define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */ +#define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL1IE_Pos (11UL) +#define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */ +#define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL1IE_Pos (12UL) +#define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */ +#define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */ + +/******************* Bit definition for CSI_SR0 register ********************/ +#define CSI_SR0_LB0F_Pos (0UL) +#define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */ +#define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */ +#define CSI_SR0_LB1F_Pos (1UL) +#define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */ +#define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */ +#define CSI_SR0_LB2F_Pos (2UL) +#define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */ +#define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */ +#define CSI_SR0_LB3F_Pos (3UL) +#define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */ +#define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */ +#define CSI_SR0_TIM0F_Pos (4UL) +#define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */ +#define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */ +#define CSI_SR0_TIM1F_Pos (5UL) +#define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */ +#define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */ +#define CSI_SR0_TIM2F_Pos (6UL) +#define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */ +#define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */ +#define CSI_SR0_TIM3F_Pos (7UL) +#define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */ +#define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */ +#define CSI_SR0_SOF0F_Pos (8UL) +#define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */ +#define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */ +#define CSI_SR0_SOF1F_Pos (9UL) +#define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */ +#define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */ +#define CSI_SR0_SOF2F_Pos (10UL) +#define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */ +#define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */ +#define CSI_SR0_SOF3F_Pos (11UL) +#define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */ +#define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */ +#define CSI_SR0_EOF0F_Pos (12UL) +#define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */ +#define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */ +#define CSI_SR0_EOF1F_Pos (13UL) +#define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */ +#define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */ +#define CSI_SR0_EOF2F_Pos (14UL) +#define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */ +#define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */ +#define CSI_SR0_EOF3F_Pos (15UL) +#define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */ +#define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */ +#define CSI_SR0_SPKTF_Pos (16UL) +#define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */ +#define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */ +#define CSI_SR0_VC0STATEF_Pos (17UL) +#define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */ +#define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */ +#define CSI_SR0_VC1STATEF_Pos (18UL) +#define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */ +#define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */ +#define CSI_SR0_VC2STATEF_Pos (19UL) +#define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */ +#define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */ +#define CSI_SR0_VC3STATEF_Pos (20UL) +#define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */ +#define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */ +#define CSI_SR0_CCFIFOFF_Pos (21UL) +#define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */ +#define CSI_SR0_CRCERRF_Pos (24UL) +#define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */ +#define CSI_SR0_ECCERRF_Pos (25UL) +#define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */ +#define CSI_SR0_CECCERRF_Pos (26UL) +#define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */ +#define CSI_SR0_IDERRF_Pos (27UL) +#define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */ +#define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */ +#define CSI_SR0_SPKTERRF_Pos (28UL) +#define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */ +#define CSI_SR0_WDERRF_Pos (29UL) +#define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */ +#define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */ +#define CSI_SR0_SYNCERRF_Pos (30UL) +#define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */ + +/******************* Bit definition for CSI_SR1 register ********************/ +#define CSI_SR1_ESOTDL0F_Pos (0UL) +#define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */ +#define CSI_SR1_ESOTSYNCDL0F_Pos (1UL) +#define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */ +#define CSI_SR1_EESCDL0F_Pos (2UL) +#define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL0F_Pos (3UL) +#define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL0F_Pos (4UL) +#define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */ +#define CSI_SR1_ESOTDL1F_Pos (8UL) +#define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */ +#define CSI_SR1_ESOTSYNCDL1F_Pos (9UL) +#define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */ +#define CSI_SR1_EESCDL1F_Pos (10UL) +#define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL1F_Pos (11UL) +#define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL1F_Pos (12UL) +#define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */ +#define CSI_SR1_ACTDL0F_Pos (16UL) +#define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */ +#define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */ +#define CSI_SR1_SYNCDL0F_Pos (17UL) +#define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */ +#define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */ +#define CSI_SR1_SKCALDL0F_Pos (18UL) +#define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */ +#define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */ +#define CSI_SR1_STOPDL0F_Pos (19UL) +#define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */ +#define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */ +#define CSI_SR1_ULPNDL0F_Pos (20UL) +#define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */ +#define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */ +#define CSI_SR1_ACTDL1F_Pos (22UL) +#define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */ +#define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */ +#define CSI_SR1_SYNCDL1F_Pos (23UL) +#define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */ +#define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */ +#define CSI_SR1_SKCALDL1F_Pos (24UL) +#define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */ +#define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */ +#define CSI_SR1_STOPDL1F_Pos (25UL) +#define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */ +#define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */ +#define CSI_SR1_ULPNDL1F_Pos (26UL) +#define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */ +#define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */ +#define CSI_SR1_STOPCLF_Pos (28UL) +#define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */ +#define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */ +#define CSI_SR1_ULPNACTF_Pos (29UL) +#define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */ +#define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */ +#define CSI_SR1_ULPNCLF_Pos (30UL) +#define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */ +#define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */ +#define CSI_SR1_ACTCLF_Pos (31UL) +#define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */ +#define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */ + +/******************* Bit definition for CSI_FCR0 register *******************/ +#define CSI_FCR0_CLB0F_Pos (0UL) +#define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */ +#define CSI_FCR0_CLB1F_Pos (1UL) +#define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */ +#define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */ +#define CSI_FCR0_CLB2F_Pos (2UL) +#define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */ +#define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */ +#define CSI_FCR0_CLB3F_Pos (3UL) +#define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */ +#define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */ +#define CSI_FCR0_CTIM0F_Pos (4UL) +#define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */ +#define CSI_FCR0_CTIM1F_Pos (5UL) +#define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */ +#define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */ +#define CSI_FCR0_CTIM2F_Pos (6UL) +#define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */ +#define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */ +#define CSI_FCR0_CTIM3F_Pos (7UL) +#define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */ +#define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */ +#define CSI_FCR0_CSOF0F_Pos (8UL) +#define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */ +#define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */ +#define CSI_FCR0_CSOF1F_Pos (9UL) +#define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */ +#define CSI_FCR0_CSOF2F_Pos (10UL) +#define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */ +#define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */ +#define CSI_FCR0_CSOF3F_Pos (11UL) +#define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */ +#define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */ +#define CSI_FCR0_CEOF0F_Pos (12UL) +#define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */ +#define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */ +#define CSI_FCR0_CEOF1F_Pos (13UL) +#define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */ +#define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */ +#define CSI_FCR0_CEOF2F_Pos (14UL) +#define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */ +#define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */ +#define CSI_FCR0_CEOF3F_Pos (15UL) +#define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */ +#define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */ +#define CSI_FCR0_CSPKTF_Pos (16UL) +#define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */ +#define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */ +#define CSI_FCR0_CCCFIFOFF_Pos (21UL) +#define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */ +#define CSI_FCR0_CCRCERRF_Pos (24UL) +#define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */ +#define CSI_FCR0_CECCERRF_Pos (25UL) +#define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */ +#define CSI_FCR0_CCECCERRF_Pos (26UL) +#define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */ +#define CSI_FCR0_CIDERRF_Pos (27UL) +#define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */ +#define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */ +#define CSI_FCR0_CSPKTERRF_Pos (28UL) +#define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */ +#define CSI_FCR0_CWDERRF_Pos (29UL) +#define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */ +#define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */ +#define CSI_FCR0_CSYNCERRF_Pos (30UL) +#define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */ + +/******************* Bit definition for CSI_FCR1 register *******************/ +#define CSI_FCR1_CESOTDL0F_Pos (0UL) +#define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */ +#define CSI_FCR1_CESOTSYNCDL0F_Pos (1UL) +#define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */ +#define CSI_FCR1_CEESCDL0F_Pos (2UL) +#define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL0F_Pos (3UL) +#define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL0F_Pos (4UL) +#define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */ +#define CSI_FCR1_CESOTDL1F_Pos (8UL) +#define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */ +#define CSI_FCR1_CESOTSYNCDL1F_Pos (9UL) +#define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */ +#define CSI_FCR1_CEESCDL1F_Pos (10UL) +#define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL1F_Pos (11UL) +#define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL1F_Pos (12UL) +#define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */ + +/****************** Bit definition for CSI_SPDFR register *******************/ +#define CSI_SPDFR_DATAFIELD_Pos (0UL) +#define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */ +#define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */ +#define CSI_SPDFR_DATATYPE_Pos (16UL) +#define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */ +#define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */ +#define CSI_SPDFR_VCHANNEL_Pos (22UL) +#define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */ +#define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */ + +/******************* Bit definition for CSI_ERR1 register *******************/ +#define CSI_ERR1_CRCDTERR_Pos (0UL) +#define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */ +#define CSI_ERR1_CRCVCERR_Pos (6UL) +#define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */ +#define CSI_ERR1_CECCDTERR_Pos (8UL) +#define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */ +#define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */ +#define CSI_ERR1_CECCVCERR_Pos (14UL) +#define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */ +#define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */ +#define CSI_ERR1_IDDTERR_Pos (16UL) +#define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */ +#define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */ +#define CSI_ERR1_IDVCERR_Pos (22UL) +#define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */ +#define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */ + +/******************* Bit definition for CSI_ERR2 register *******************/ +#define CSI_ERR2_SPKTDTERR_Pos (0UL) +#define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */ +#define CSI_ERR2_SPKTVCERR_Pos (6UL) +#define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */ +#define CSI_ERR2_WDVCERR_Pos (16UL) +#define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */ +#define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */ +#define CSI_ERR2_SYNCVCERR_Pos (18UL) +#define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */ +#define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */ + +/******************* Bit definition for CSI_PRCR register *******************/ +#define CSI_PRCR_PEN_Pos (1UL) +#define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */ +#define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */ + +/******************* Bit definition for CSI_PMCR register *******************/ +#define CSI_PMCR_FRXMDL0_Pos (0UL) +#define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */ +#define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */ +#define CSI_PMCR_FRXMDL1_Pos (1UL) +#define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */ +#define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */ +#define CSI_PMCR_FTXSMDL0_Pos (2UL) +#define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */ +#define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */ +#define CSI_PMCR_DTDL_Pos (4UL) +#define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */ +#define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */ +#define CSI_PMCR_RTDL0_Pos (8UL) +#define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */ +#define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */ +#define CSI_PMCR_TUESDL0_Pos (12UL) +#define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */ +#define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */ +#define CSI_PMCR_TUEXDL0_Pos (16UL) +#define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */ +#define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */ + +/******************* Bit definition for CSI_PFCR register *******************/ +#define CSI_PFCR_CCFR_Pos (0UL) +#define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */ +#define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */ +#define CSI_PFCR_HSFR_Pos (8UL) +#define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */ +#define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */ +#define CSI_PFCR_DLD_Pos (16UL) +#define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */ +#define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */ + +/****************** Bit definition for CSI_PTCR0 register *******************/ +#define CSI_PTCR0_TCKEN_Pos (0UL) +#define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */ +#define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */ +#define CSI_PTCR0_TRSEN_Pos (1UL) +#define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */ +#define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */ + +/****************** Bit definition for CSI_PTCR1 register *******************/ +#define CSI_PTCR1_TDI_Pos (0UL) +#define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */ +#define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */ +#define CSI_PTCR1_TWM_Pos (16UL) +#define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */ +#define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */ + +/******************* Bit definition for CSI_PTSR register *******************/ +#define CSI_PTSR_TDO_Pos (0UL) +#define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */ +#define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */ + + +/*********************************************************************************/ +/* */ +/* DBGMCU */ +/* */ +/*********************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register ****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */ +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */ + +/******************** Bit definition for DBGMCU_CR register ********************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0UL) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1UL) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2UL) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */ +#define DBGMCU_CR_DBGCLKEN_Pos (20UL) +#define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */ +#define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */ +#define DBGMCU_CR_TRACECLKEN_Pos (21UL) +#define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */ +#define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */ +#define DBGMCU_CR_DBTRGOEN_Pos (28UL) +#define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */ +#define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */ +#define DBGMCU_CR_HLT_TSGEN_EN_Pos (31UL) +#define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */ +#define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */ + +/******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0UL) +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1UL) +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2UL) +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3UL) +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4UL) +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5UL) +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6UL) +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7UL) +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8UL) +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9UL) +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11UL) +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12UL) +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13UL) +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21UL) +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22UL) +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23UL) +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24UL) +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25UL) +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */ + +/******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8UL) +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */ + +/******************** Bit definition for DBGMCU_APB2FZ1 register ***************/ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0UL) +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1UL) +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15UL) +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16UL) +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17UL) +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18UL) +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19UL) +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */ + +/******************** Bit definition for DBGMCU_APB4FZ1 register ***************/ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8UL) +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16UL) +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18UL) +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */ + +/******************** Bit definition for DBGMCU_APB5FZ1 register ***************/ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4UL) +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */ + +/******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */ +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos (16UL) +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk /*!< NPU stop in debug mode */ + +/******************** Bit definition for DBGMCU_SR register ***************/ +#define DBGMCU_SR_AP0_PRESENT_Pos (0UL) +#define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */ +#define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */ +#define DBGMCU_SR_AP1_PRESENT_Pos (1UL) +#define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */ +#define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */ +#define DBGMCU_SR_AP0_ENABLE_Pos (16UL) +#define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */ +#define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */ +#define DBGMCU_SR_AP1_ENABLE_Pos (17UL) +#define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */ +#define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */ + +/******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0UL) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1UL) +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */ + + +/******************************************************************************/ +/* */ +/* DCMI */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DCMI_CR register ******************/ +#define DCMI_CR_CAPTURE_Pos (0UL) +#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ +#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk +#define DCMI_CR_CM_Pos (1UL) +#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ +#define DCMI_CR_CM DCMI_CR_CM_Msk +#define DCMI_CR_CROP_Pos (2UL) +#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ +#define DCMI_CR_CROP DCMI_CR_CROP_Msk +#define DCMI_CR_JPEG_Pos (3UL) +#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ +#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk +#define DCMI_CR_ESS_Pos (4UL) +#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ +#define DCMI_CR_ESS DCMI_CR_ESS_Msk +#define DCMI_CR_PCKPOL_Pos (5UL) +#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk +#define DCMI_CR_HSPOL_Pos (6UL) +#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk +#define DCMI_CR_VSPOL_Pos (7UL) +#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk +#define DCMI_CR_FCRC_Pos (8UL) +#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ +#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ +#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ +#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ +#define DCMI_CR_EDM_Pos (10UL) +#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ +#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ +#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ +#define DCMI_CR_ENABLE_Pos (14UL) +#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk +#define DCMI_CR_BSM_Pos (16UL) +#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ +#define DCMI_CR_BSM DCMI_CR_BSM_Msk +#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ +#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ +#define DCMI_CR_OEBS_Pos (18UL) +#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ +#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk +#define DCMI_CR_LSM_Pos (19UL) +#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ +#define DCMI_CR_LSM DCMI_CR_LSM_Msk +#define DCMI_CR_OELS_Pos (20UL) +#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ +#define DCMI_CR_OELS DCMI_CR_OELS_Msk +#define DCMI_CR_PSDM_Pos (31UL) +#define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */ +#define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ + +/******************** Bits definition for DCMI_SR register ******************/ +#define DCMI_SR_HSYNC_Pos (0UL) +#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ +#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk +#define DCMI_SR_VSYNC_Pos (1UL) +#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ +#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk +#define DCMI_SR_FNE_Pos (2UL) +#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ +#define DCMI_SR_FNE DCMI_SR_FNE_Msk + +/******************** Bits definition for DCMI_RIS register ****************/ +#define DCMI_RIS_FRAME_RIS_Pos (0UL) +#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ +#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk +#define DCMI_RIS_OVR_RIS_Pos (1UL) +#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk +#define DCMI_RIS_ERR_RIS_Pos (2UL) +#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ +#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk +#define DCMI_RIS_VSYNC_RIS_Pos (3UL) +#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ +#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk +#define DCMI_RIS_LINE_RIS_Pos (4UL) +#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ +#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk + +/******************** Bits definition for DCMI_IER register *****************/ +#define DCMI_IER_FRAME_IE_Pos (0UL) +#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ +#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk +#define DCMI_IER_OVR_IE_Pos (1UL) +#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk +#define DCMI_IER_ERR_IE_Pos (2UL) +#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ +#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk +#define DCMI_IER_VSYNC_IE_Pos (3UL) +#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ +#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk +#define DCMI_IER_LINE_IE_Pos (4UL) +#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ +#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk + +/******************** Bits definition for DCMI_MIS register *****************/ +#define DCMI_MIS_FRAME_MIS_Pos (0UL) +#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ +#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk +#define DCMI_MIS_OVR_MIS_Pos (1UL) +#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk +#define DCMI_MIS_ERR_MIS_Pos (2UL) +#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ +#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk +#define DCMI_MIS_VSYNC_MIS_Pos (3UL) +#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ +#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk +#define DCMI_MIS_LINE_MIS_Pos (4UL) +#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ +#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk + +/******************** Bits definition for DCMI_ICR register *****************/ +#define DCMI_ICR_FRAME_ISC_Pos (0UL) +#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ +#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk +#define DCMI_ICR_OVR_ISC_Pos (1UL) +#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk +#define DCMI_ICR_ERR_ISC_Pos (2UL) +#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ +#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk +#define DCMI_ICR_VSYNC_ISC_Pos (3UL) +#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ +#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk +#define DCMI_ICR_LINE_ISC_Pos (4UL) +#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ +#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk + +/******************** Bits definition for DCMI_ESCR register ******************/ +#define DCMI_ESCR_FSC_Pos (0UL) +#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk +#define DCMI_ESCR_LSC_Pos (8UL) +#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk +#define DCMI_ESCR_LEC_Pos (16UL) +#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk +#define DCMI_ESCR_FEC_Pos (24UL) +#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk + +/******************** Bits definition for DCMI_ESUR register ******************/ +#define DCMI_ESUR_FSU_Pos (0UL) +#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk +#define DCMI_ESUR_LSU_Pos (8UL) +#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk +#define DCMI_ESUR_LEU_Pos (16UL) +#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk +#define DCMI_ESUR_FEU_Pos (24UL) +#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk + +/******************** Bits definition for DCMI_CWSTRT register ******************/ +#define DCMI_CWSTRT_HOFFCNT_Pos (0UL) +#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk +#define DCMI_CWSTRT_VST_Pos (16UL) +#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ +#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk + +/******************** Bits definition for DCMI_CWSIZE register ******************/ +#define DCMI_CWSIZE_CAPCNT_Pos (0UL) +#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk +#define DCMI_CWSIZE_VLINE_Pos (16UL) +#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ +#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk + +/******************** Bits definition for DCMI_DR register ******************/ +#define DCMI_DR_BYTE0_Pos (0UL) +#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ +#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk +#define DCMI_DR_BYTE1_Pos (8UL) +#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ +#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk +#define DCMI_DR_BYTE2_Pos (16UL) +#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ +#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk +#define DCMI_DR_BYTE3_Pos (24UL) +#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ +#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk + + +/******************************************************************************/ +/* */ +/* DCMIPP */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DCMIPP_IPGR1 register *****************/ +#define DCMIPP_IPGR1_MEMORYPAGE_Pos (0UL) +#define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */ +#define DCMIPP_IPGR1_QOS_MODE_Pos (24UL) +#define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */ +#define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */ + +/***************** Bit definition for DCMIPP_IPGR2 register *****************/ +#define DCMIPP_IPGR2_PSTART_Pos (0UL) +#define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */ + +/***************** Bit definition for DCMIPP_IPGR3 register *****************/ +#define DCMIPP_IPGR3_IDLE_Pos (0UL) +#define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */ + +/***************** Bit definition for DCMIPP_IPGR8 register *****************/ +#define DCMIPP_IPGR8_DID_Pos (0UL) +#define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */ +#define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */ +#define DCMIPP_IPGR8_REVID_Pos (8UL) +#define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */ +#define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */ +#define DCMIPP_IPGR8_ARCHIID_Pos (16UL) +#define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */ +#define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */ +#define DCMIPP_IPGR8_IPPID_Pos (24UL) +#define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */ +#define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */ + +/**************** Bit definition for DCMIPP_IPC1R1 register *****************/ +#define DCMIPP_IPC1R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC1R1_OTR_Pos (8UL) +#define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC1R2 register *****************/ +#define DCMIPP_IPC1R2_WLRU_Pos (16UL) +#define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC1R3 register *****************/ +#define DCMIPP_IPC1R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC1R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC2R1 register *****************/ +#define DCMIPP_IPC2R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC2R1_OTR_Pos (8UL) +#define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC2R2 register *****************/ +#define DCMIPP_IPC2R2_WLRU_Pos (16UL) +#define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC2R3 register *****************/ +#define DCMIPP_IPC2R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC2R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC3R1 register *****************/ +#define DCMIPP_IPC3R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC3R1_OTR_Pos (8UL) +#define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC3R2 register *****************/ +#define DCMIPP_IPC3R2_WLRU_Pos (16UL) +#define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC3R3 register *****************/ +#define DCMIPP_IPC3R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC3R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC4R1 register *****************/ +#define DCMIPP_IPC4R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC4R1_OTR_Pos (8UL) +#define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC4R2 register *****************/ +#define DCMIPP_IPC4R2_WLRU_Pos (16UL) +#define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC4R3 register *****************/ +#define DCMIPP_IPC4R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC4R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC5R1 register *****************/ +#define DCMIPP_IPC5R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC5R1_OTR_Pos (8UL) +#define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC5R2 register *****************/ +#define DCMIPP_IPC5R2_WLRU_Pos (16UL) +#define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC5R3 register *****************/ +#define DCMIPP_IPC5R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC5R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/*************** Bit definition for DCMIPP_PRHWCFGR register ****************/ + +/***************** Bit definition for DCMIPP_PRCR register ******************/ +#define DCMIPP_PRCR_ESS_Pos (4UL) +#define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */ +#define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */ +#define DCMIPP_PRCR_PCKPOL_Pos (5UL) +#define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */ +#define DCMIPP_PRCR_HSPOL_Pos (6UL) +#define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */ +#define DCMIPP_PRCR_VSPOL_Pos (7UL) +#define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */ +#define DCMIPP_PRCR_EDM_Pos (10UL) +#define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */ +#define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */ +#define DCMIPP_PRCR_ENABLE_Pos (14UL) +#define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */ +#define DCMIPP_PRCR_FORMAT_Pos (16UL) +#define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */ +#define DCMIPP_PRCR_SWAPCYCLES_Pos (25UL) +#define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */ +#define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */ +#define DCMIPP_PRCR_SWAPBITS_Pos (26UL) +#define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */ +#define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */ + +/**************** Bit definition for DCMIPP_PRESCR register *****************/ +#define DCMIPP_PRESCR_FSC_Pos (0UL) +#define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */ +#define DCMIPP_PRESCR_LSC_Pos (8UL) +#define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */ +#define DCMIPP_PRESCR_LEC_Pos (16UL) +#define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */ +#define DCMIPP_PRESCR_FEC_Pos (24UL) +#define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */ + +/**************** Bit definition for DCMIPP_PRESUR register *****************/ +#define DCMIPP_PRESUR_FSU_Pos (0UL) +#define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */ +#define DCMIPP_PRESUR_LSU_Pos (8UL) +#define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */ +#define DCMIPP_PRESUR_LEU_Pos (16UL) +#define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */ +#define DCMIPP_PRESUR_FEU_Pos (24UL) +#define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */ + +/***************** Bit definition for DCMIPP_PRIER register *****************/ +#define DCMIPP_PRIER_ERRIE_Pos (6UL) +#define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */ + +/***************** Bit definition for DCMIPP_PRSR register ******************/ +#define DCMIPP_PRSR_ERRF_Pos (6UL) +#define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */ +#define DCMIPP_PRSR_HSYNC_Pos (16UL) +#define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */ +#define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */ +#define DCMIPP_PRSR_VSYNC_Pos (17UL) +#define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */ +#define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */ + +/***************** Bit definition for DCMIPP_PRFCR register *****************/ +#define DCMIPP_PRFCR_CERRF_Pos (6UL) +#define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */ + +/***************** Bit definition for DCMIPP_CMCR register ******************/ +#define DCMIPP_CMCR_INSEL_Pos (0UL) +#define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */ +#define DCMIPP_CMCR_PSFC_Pos (1UL) +#define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */ +#define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */ +#define DCMIPP_CMCR_CFC_Pos (4UL) +#define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */ +#define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */ +#define DCMIPP_CMCR_SWAPRB_Pos (7UL) +#define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */ +#define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */ + +/**************** Bit definition for DCMIPP_CMFRCR register *****************/ +#define DCMIPP_CMFRCR_FRMCNT_Pos (0UL) +#define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */ + +/***************** Bit definition for DCMIPP_CMIER register *****************/ +#define DCMIPP_CMIER_ATXERRIE_Pos (5UL) +#define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */ +#define DCMIPP_CMIER_PRERRIE_Pos (6UL) +#define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */ +#define DCMIPP_CMIER_P0LINEIE_Pos (8UL) +#define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0FRAMEIE_Pos (9UL) +#define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0VSYNCIE_Pos (10UL) +#define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0LIMITIE_Pos (14UL) +#define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0OVRIE_Pos (15UL) +#define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P1LINEIE_Pos (16UL) +#define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */ +#define DCMIPP_CMIER_P1FRAMEIE_Pos (17UL) +#define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1VSYNCIE_Pos (18UL) +#define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1OVRIE_Pos (23UL) +#define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P2LINEIE_Pos (24UL) +#define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2FRAMEIE_Pos (25UL) +#define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2VSYNCIE_Pos (26UL) +#define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2OVRIE_Pos (31UL) +#define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR1 register *****************/ +#define DCMIPP_CMSR1_PRHSYNC_Pos (0UL) +#define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_PRVSYNC_Pos (1UL) +#define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */ +#define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_P0LSTLINE_Pos (8UL) +#define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0LSTFRM_Pos (9UL) +#define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0CPTACT_Pos (15UL) +#define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */ +#define DCMIPP_CMSR1_P1LSTLINE_Pos (16UL) +#define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1LSTFRM_Pos (17UL) +#define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1CPTACT_Pos (23UL) +#define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */ +#define DCMIPP_CMSR1_P2LSTLINE_Pos (24UL) +#define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2LSTFRM_Pos (25UL) +#define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2CPTACT_Pos (31UL) +#define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR2 register *****************/ +#define DCMIPP_CMSR2_ATXERRF_Pos (5UL) +#define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */ +#define DCMIPP_CMSR2_PRERRF_Pos (6UL) +#define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */ +#define DCMIPP_CMSR2_P0LINEF_Pos (8UL) +#define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0FRAMEF_Pos (9UL) +#define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0VSYNCF_Pos (10UL) +#define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0LIMITF_Pos (14UL) +#define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0OVRF_Pos (15UL) +#define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P1LINEF_Pos (16UL) +#define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1FRAMEF_Pos (17UL) +#define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1VSYNCF_Pos (18UL) +#define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1OVRF_Pos (23UL) +#define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P2LINEF_Pos (24UL) +#define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2FRAMEF_Pos (25UL) +#define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2VSYNCF_Pos (26UL) +#define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2OVRF_Pos (31UL) +#define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMFCR register *****************/ +#define DCMIPP_CMFCR_CATXERRF_Pos (5UL) +#define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */ +#define DCMIPP_CMFCR_CPRERRF_Pos (6UL) +#define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */ +#define DCMIPP_CMFCR_CP0LINEF_Pos (8UL) +#define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0FRAMEF_Pos (9UL) +#define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0VSYNCF_Pos (10UL) +#define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP0LIMITF_Pos (14UL) +#define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_CMFCR_CP0OVRF_Pos (15UL) +#define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP1LINEF_Pos (16UL) +#define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1FRAMEF_Pos (17UL) +#define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1VSYNCF_Pos (18UL) +#define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP1OVRF_Pos (23UL) +#define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP2LINEF_Pos (24UL) +#define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2FRAMEF_Pos (25UL) +#define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2VSYNCF_Pos (26UL) +#define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP2OVRF_Pos (31UL) +#define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0FSCR register *****************/ +#define DCMIPP_P0FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */ +#define DCMIPP_P0FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */ +#define DCMIPP_P0FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_VC_Pos (19UL) +#define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P0FCTCR register ****************/ +#define DCMIPP_P0FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P0SCSTR register ****************/ +#define DCMIPP_P0SCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0SCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P0SCSZR register ****************/ +#define DCMIPP_P0SCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0SCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0SCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */ +#define DCMIPP_P0SCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */ + +/*************** Bit definition for DCMIPP_P0DCCNTR register ****************/ +#define DCMIPP_P0DCCNTR_CNT_Pos (0UL) +#define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */ +#define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */ + +/*************** Bit definition for DCMIPP_P0DCLMTR register ****************/ +#define DCMIPP_P0DCLMTR_LIMIT_Pos (0UL) +#define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */ +#define DCMIPP_P0DCLMTR_ENABLE_Pos (31UL) +#define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P0PPCR register *****************/ +#define DCMIPP_P0PPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0PPCR_PAD_Pos (5UL) +#define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0PPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */ +#define DCMIPP_P0PPCR_BSM_Pos (7UL) +#define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */ +#define DCMIPP_P0PPCR_OEBS_Pos (9UL) +#define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */ +#define DCMIPP_P0PPCR_LSM_Pos (10UL) +#define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */ +#define DCMIPP_P0PPCR_OELS_Pos (11UL) +#define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */ +#define DCMIPP_P0PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0PPCR_DBM_Pos (16UL) +#define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */ + +/*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/ +#define DCMIPP_P0PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/ +#define DCMIPP_P0PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */ + +/***************** Bit definition for DCMIPP_P0IER register *****************/ +#define DCMIPP_P0IER_LINEIE_Pos (0UL) +#define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P0IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P0IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P0IER_LIMITIE_Pos (6UL) +#define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */ +#define DCMIPP_P0IER_OVRIE_Pos (7UL) +#define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P0SR register ******************/ +#define DCMIPP_P0SR_LINEF_Pos (0UL) +#define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P0SR_FRAMEF_Pos (1UL) +#define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P0SR_VSYNCF_Pos (2UL) +#define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P0SR_LIMITF_Pos (6UL) +#define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */ +#define DCMIPP_P0SR_OVRF_Pos (7UL) +#define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P0SR_LSTLINE_Pos (16UL) +#define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_LSTFRM_Pos (17UL) +#define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_CPTACT_Pos (23UL) +#define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P0FCR register *****************/ +#define DCMIPP_P0FCR_CLINEF_Pos (0UL) +#define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P0FCR_CLIMITF_Pos (6UL) +#define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_P0FCR_COVRF_Pos (7UL) +#define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0CFSCR register ****************/ +#define DCMIPP_P0CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */ +#define DCMIPP_P0CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */ +#define DCMIPP_P0CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0CFSCR_VC_Pos (19UL) +#define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P0CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P0CFCTCR register ****************/ +#define DCMIPP_P0CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P0CSCSTR register ****************/ +#define DCMIPP_P0CSCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0CSCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P0CSCSZR register ****************/ +#define DCMIPP_P0CSCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0CSCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0CSCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */ +#define DCMIPP_P0CSCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */ + +/**************** Bit definition for DCMIPP_P0CPPCR register ****************/ +#define DCMIPP_P0CPPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0CPPCR_PAD_Pos (5UL) +#define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0CPPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */ +#define DCMIPP_P0CPPCR_BSM_Pos (7UL) +#define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */ +#define DCMIPP_P0CPPCR_OEBS_Pos (9UL) +#define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */ +#define DCMIPP_P0CPPCR_LSM_Pos (10UL) +#define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */ +#define DCMIPP_P0CPPCR_OELS_Pos (11UL) +#define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */ +#define DCMIPP_P0CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0CPPCR_DBM_Pos (16UL) +#define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */ + +/************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/ +#define DCMIPP_P0CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/**************** Bit definition for DCMIPP_P1FSCR register *****************/ +#define DCMIPP_P1FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */ +#define DCMIPP_P1FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */ +#define DCMIPP_P1FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */ +#define DCMIPP_P1FSCR_VC_Pos (19UL) +#define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_FDTF_Pos (24UL) +#define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P1FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P1FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P1SRCR register *****************/ +#define DCMIPP_P1SRCR_LASTLINE_Pos (0UL) +#define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12UL) +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */ +#define DCMIPP_P1SRCR_CROPEN_Pos (15UL) +#define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */ +#define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */ + +/**************** Bit definition for DCMIPP_P1BPRCR register ****************/ +#define DCMIPP_P1BPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */ +#define DCMIPP_P1BPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */ + +/**************** Bit definition for DCMIPP_P1BPRSR register ****************/ +#define DCMIPP_P1BPRSR_BADCNT_Pos (0UL) +#define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */ + +/**************** Bit definition for DCMIPP_P1DECR register *****************/ +#define DCMIPP_P1DECR_ENABLE_Pos (0UL) +#define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DECR_HDEC_Pos (1UL) +#define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DECR_VDEC_Pos (3UL) +#define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1BLCCR register ****************/ +#define DCMIPP_P1BLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */ +#define DCMIPP_P1BLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */ +#define DCMIPP_P1BLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */ +#define DCMIPP_P1BLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR1 register ****************/ +#define DCMIPP_P1EXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */ +#define DCMIPP_P1EXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */ +#define DCMIPP_P1EXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR2 register ****************/ +#define DCMIPP_P1EXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */ +#define DCMIPP_P1EXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */ +#define DCMIPP_P1EXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */ +#define DCMIPP_P1EXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */ + +/**************** Bit definition for DCMIPP_P1ST1CR register ****************/ +#define DCMIPP_P1ST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST1CR_BINS_Pos (2UL) +#define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST1CR_SRC_Pos (4UL) +#define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST1CR_MODE_Pos (7UL) +#define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST2CR register ****************/ +#define DCMIPP_P1ST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST2CR_BINS_Pos (2UL) +#define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST2CR_SRC_Pos (4UL) +#define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST2CR_MODE_Pos (7UL) +#define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST3CR register ****************/ +#define DCMIPP_P1ST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST3CR_BINS_Pos (2UL) +#define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST3CR_SRC_Pos (4UL) +#define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST3CR_MODE_Pos (7UL) +#define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1STSTR register ****************/ +#define DCMIPP_P1STSTR_HSTART_Pos (0UL) +#define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSTR_VSTART_Pos (16UL) +#define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1STSZR register ****************/ +#define DCMIPP_P1STSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1STSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1ST1SR register ****************/ +#define DCMIPP_P1ST1SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST2SR register ****************/ +#define DCMIPP_P1ST2SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST3SR register ****************/ +#define DCMIPP_P1ST3SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1DMCR register *****************/ +#define DCMIPP_P1DMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DMCR_TYPE_Pos (1UL) +#define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */ +#define DCMIPP_P1DMCR_PEAK_Pos (16UL) +#define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */ +#define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */ +#define DCMIPP_P1DMCR_LINEV_Pos (20UL) +#define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */ +#define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */ +#define DCMIPP_P1DMCR_LINEH_Pos (24UL) +#define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */ +#define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */ +#define DCMIPP_P1DMCR_EDGE_Pos (28UL) +#define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */ + +/**************** Bit definition for DCMIPP_P1CCCR register *****************/ +#define DCMIPP_P1CCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/**************** Bit definition for DCMIPP_P1CCRR1 register ****************/ +#define DCMIPP_P1CCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCRR2 register ****************/ +#define DCMIPP_P1CCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCGR1 register ****************/ +#define DCMIPP_P1CCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCGR2 register ****************/ +#define DCMIPP_P1CCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCBR1 register ****************/ +#define DCMIPP_P1CCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCBR2 register ****************/ +#define DCMIPP_P1CCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CTCR1 register ****************/ +#define DCMIPP_P1CTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */ +#define DCMIPP_P1CTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR2 register ****************/ +#define DCMIPP_P1CTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR3 register ****************/ +#define DCMIPP_P1CTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1FCTCR register ****************/ +#define DCMIPP_P1FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P1CRSTR register ****************/ +#define DCMIPP_P1CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CRSZR register ****************/ +#define DCMIPP_P1CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1DCCR register *****************/ +#define DCMIPP_P1DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1DCCR_HDEC_Pos (1UL) +#define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DCCR_VDEC_Pos (3UL) +#define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1DSCR register *****************/ +#define DCMIPP_P1DSCR_HDIV_Pos (0UL) +#define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_VDIV_Pos (16UL) +#define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */ + +/*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/ +#define DCMIPP_P1DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P1DSSZR register ****************/ +#define DCMIPP_P1DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CMRICR register ***************/ +#define DCMIPP_P1CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P1CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P1CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P1CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P1CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P1CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P1CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P1CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P1CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/ +#define DCMIPP_P1RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P1RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P1RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P1RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P1RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/ +#define DCMIPP_P1RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P1RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P1GMCR register *****************/ +#define DCMIPP_P1GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/ + +/**************** Bit definition for DCMIPP_P1YUVCR register ****************/ +#define DCMIPP_P1YUVCR_ENABLE_Pos (0UL) +#define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1YUVCR_TYPE_Pos (1UL) +#define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */ +#define DCMIPP_P1YUVCR_CLAMP_Pos (2UL) +#define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/ +#define DCMIPP_P1YUVRR1_RR_Pos (0UL) +#define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1YUVRR1_RG_Pos (16UL) +#define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/ +#define DCMIPP_P1YUVRR2_RB_Pos (0UL) +#define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1YUVRR2_RA_Pos (16UL) +#define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/ +#define DCMIPP_P1YUVGR1_GR_Pos (0UL) +#define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1YUVGR1_GG_Pos (16UL) +#define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/ +#define DCMIPP_P1YUVGR2_GB_Pos (0UL) +#define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1YUVGR2_GA_Pos (16UL) +#define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/ +#define DCMIPP_P1YUVBR1_BR_Pos (0UL) +#define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1YUVBR1_BG_Pos (16UL) +#define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/ +#define DCMIPP_P1YUVBR2_BB_Pos (0UL) +#define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1YUVBR2_BA_Pos (16UL) +#define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1PPCR register *****************/ +#define DCMIPP_P1PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P1PPCR_DBM_Pos (16UL) +#define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P1PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P1PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/ +#define DCMIPP_P1PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/ +#define DCMIPP_P1PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */ + +/*************** Bit definition for DCMIPP_P1PPM0PR register ****************/ +#define DCMIPP_P1PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/ +#define DCMIPP_P1PPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/ +#define DCMIPP_P1PPM1AR2_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1PR register ****************/ +#define DCMIPP_P1PPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1STM1AR register ****************/ +#define DCMIPP_P1STM1AR_M1A_Pos (0UL) +#define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */ + +/*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/ +#define DCMIPP_P1PPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/ +#define DCMIPP_P1PPM2AR2_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */ + +/*************** Bit definition for DCMIPP_P1STM2AR register ****************/ +#define DCMIPP_P1STM2AR_M2A_Pos (0UL) +#define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */ + +/***************** Bit definition for DCMIPP_P1IER register *****************/ +#define DCMIPP_P1IER_LINEIE_Pos (0UL) +#define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P1IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P1IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P1IER_OVRIE_Pos (7UL) +#define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P1SR register ******************/ +#define DCMIPP_P1SR_LINEF_Pos (0UL) +#define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P1SR_FRAMEF_Pos (1UL) +#define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P1SR_VSYNCF_Pos (2UL) +#define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P1SR_OVRF_Pos (7UL) +#define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P1SR_LSTLINE_Pos (16UL) +#define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_LSTFRM_Pos (17UL) +#define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_CPTACT_Pos (23UL) +#define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P1FCR register *****************/ +#define DCMIPP_P1FCR_CLINEF_Pos (0UL) +#define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P1FCR_COVRF_Pos (7UL) +#define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P1CFSCR register ****************/ +#define DCMIPP_P1CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */ +#define DCMIPP_P1CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */ +#define DCMIPP_P1CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */ +#define DCMIPP_P1CFSCR_VC_Pos (19UL) +#define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P1CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P1CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P1CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P1CBPRCR register ****************/ +#define DCMIPP_P1CBPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */ +#define DCMIPP_P1CBPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */ + +/*************** Bit definition for DCMIPP_P1CBLCCR register ****************/ +#define DCMIPP_P1CBLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */ +#define DCMIPP_P1CBLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */ +#define DCMIPP_P1CBLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */ +#define DCMIPP_P1CBLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/ +#define DCMIPP_P1CEXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */ +#define DCMIPP_P1CEXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */ +#define DCMIPP_P1CEXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/ +#define DCMIPP_P1CEXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */ +#define DCMIPP_P1CEXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */ +#define DCMIPP_P1CEXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */ +#define DCMIPP_P1CEXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */ + +/*************** Bit definition for DCMIPP_P1CST1CR register ****************/ +#define DCMIPP_P1CST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */ +#define DCMIPP_P1CST1CR_BINS_Pos (2UL) +#define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */ +#define DCMIPP_P1CST1CR_SRC_Pos (4UL) +#define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */ +#define DCMIPP_P1CST1CR_MODE_Pos (7UL) +#define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */ +#define DCMIPP_P1CST1CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST2CR register ****************/ +#define DCMIPP_P1CST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST2CR_BINS_Pos (2UL) +#define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST2CR_SRC_Pos (4UL) +#define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */ +#define DCMIPP_P1CST2CR_MODE_Pos (7UL) +#define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */ +#define DCMIPP_P1CST2CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST3CR register ****************/ +#define DCMIPP_P1CST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST3CR_BINS_Pos (2UL) +#define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST3CR_SRC_Pos (4UL) +#define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1CST3CR_MODE_Pos (7UL) +#define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */ +#define DCMIPP_P1CST3CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CSTSTR register ****************/ +#define DCMIPP_P1CSTSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CSTSZR register ****************/ +#define DCMIPP_P1CSTSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CSTSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */ + +/**************** Bit definition for DCMIPP_P1CCCCR register ****************/ +#define DCMIPP_P1CCCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */ +#define DCMIPP_P1CCCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/ +#define DCMIPP_P1CCCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/ +#define DCMIPP_P1CCCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/ +#define DCMIPP_P1CCCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/ +#define DCMIPP_P1CCCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/ +#define DCMIPP_P1CCCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/ +#define DCMIPP_P1CCCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/ +#define DCMIPP_P1CCTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */ +#define DCMIPP_P1CCTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/ +#define DCMIPP_P1CCTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/ +#define DCMIPP_P1CCTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CFCTCR register ****************/ +#define DCMIPP_P1CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P1CCRSTR register ****************/ +#define DCMIPP_P1CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CCRSZR register ****************/ +#define DCMIPP_P1CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P1CDCCR register *****************/ +#define DCMIPP_P1CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1CDSCR register ****************/ +#define DCMIPP_P1CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/ +#define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P1CDSSZR register ****************/ +#define DCMIPP_P1CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CPPCR register ****************/ +#define DCMIPP_P1CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ + +/************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/ +#define DCMIPP_P1CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/ +#define DCMIPP_P1CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/ +#define DCMIPP_P1CPPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/ +#define DCMIPP_P1CPPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/ +#define DCMIPP_P1CPPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */ + +/**************** Bit definition for DCMIPP_P2FSCR register *****************/ +#define DCMIPP_P2FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */ +#define DCMIPP_P2FSCR_VC_Pos (19UL) +#define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P2FSCR_FDTF_Pos (24UL) +#define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P2FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P2FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P2FCTCR register ****************/ +#define DCMIPP_P2FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P2CRSTR register ****************/ +#define DCMIPP_P2CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CRSZR register ****************/ +#define DCMIPP_P2CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P2DCCR register *****************/ +#define DCMIPP_P2DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2DCCR_HDEC_Pos (1UL) +#define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2DCCR_VDEC_Pos (3UL) +#define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2DSCR register *****************/ +#define DCMIPP_P2DSCR_HDIV_Pos (0UL) +#define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_VDIV_Pos (16UL) +#define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/ +#define DCMIPP_P2DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P2DSSZR register ****************/ +#define DCMIPP_P2DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2GMCR register *****************/ +#define DCMIPP_P2GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2CMRICR register ***************/ +#define DCMIPP_P2CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P2CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P2CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P2CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P2CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P2CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P2CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P2CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P2CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/ +#define DCMIPP_P2RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P2RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P2RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P2RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P2RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/ +#define DCMIPP_P2RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P2RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P2PPCR register *****************/ +#define DCMIPP_P2PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2PPCR_DBM_Pos (16UL) +#define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/ +#define DCMIPP_P2PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */ + +/*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/ +#define DCMIPP_P2PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2STM0AR_Pos (0UL) +#define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */ + +/***************** Bit definition for DCMIPP_P2IER register *****************/ +#define DCMIPP_P2IER_LINEIE_Pos (0UL) +#define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P2IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P2IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P2IER_OVRIE_Pos (7UL) +#define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P2SR register ******************/ +#define DCMIPP_P2SR_LINEF_Pos (0UL) +#define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P2SR_FRAMEF_Pos (1UL) +#define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P2SR_VSYNCF_Pos (2UL) +#define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P2SR_OVRF_Pos (7UL) +#define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P2SR_LSTLINE_Pos (16UL) +#define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_LSTFRM_Pos (17UL) +#define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_CPTACT_Pos (23UL) +#define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P2FCR register *****************/ +#define DCMIPP_P2FCR_CLINEF_Pos (0UL) +#define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P2FCR_COVRF_Pos (7UL) +#define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P2CFSCR register ****************/ +#define DCMIPP_P2CFSCR_DTID_Pos (0UL) +#define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */ +#define DCMIPP_P2CFSCR_VC_Pos (19UL) +#define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P2CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P2CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P2CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P2CFCTCR register ****************/ +#define DCMIPP_P2CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P2CCRSTR register ****************/ +#define DCMIPP_P2CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P2CCRSZR register ****************/ +#define DCMIPP_P2CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P2CDCCR register *****************/ +#define DCMIPP_P2CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2CDSCR register ****************/ +#define DCMIPP_P2CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/ +#define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P2CDSSZR register ****************/ +#define DCMIPP_P2CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CPPCR register ****************/ +#define DCMIPP_P2CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2CPPCR_DBM_Pos (16UL) +#define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2CPPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2CPPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/ +#define DCMIPP_P2CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/ +#define DCMIPP_P2CPPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */ + +/*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/ +#define DCMIPP_P2CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/**************** Bit definition for DCMIPP_HWCFGR2 register ****************/ +#define DCMIPP_HWCFGR2_VPFT_Pos (0UL) +#define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */ +#define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */ +#define DCMIPP_HWCFGR2_DBMFT_Pos (4UL) +#define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */ +#define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */ +#define DCMIPP_HWCFGR2_PROCCLK_Pos (8UL) +#define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */ +#define DCMIPP_HWCFGR2_ADDMOD_Pos (12UL) +#define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */ +#define DCMIPP_HWCFGR2_DEC1_Pos (16UL) +#define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */ +#define DCMIPP_HWCFGR2_DEC2_Pos (17UL) +#define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */ +#define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */ +#define DCMIPP_HWCFGR2_MCU_Pos (20UL) +#define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */ +#define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */ +#define DCMIPP_HWCFGR2_TPG_Pos (24UL) +#define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */ +#define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */ +#define DCMIPP_HWCFGR2_STV_Pos (28UL) +#define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */ +#define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */ + +/**************** Bit definition for DCMIPP_HWCFGR1 register ****************/ +#define DCMIPP_HWCFGR1_CSIFT_Pos (0UL) +#define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */ +#define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */ +#define DCMIPP_HWCFGR1_PIPENB_Pos (4UL) +#define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */ +#define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */ +#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8UL) +#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */ +#define DCMIPP_HWCFGR1_DSP1FT_Pos (12UL) +#define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */ +#define DCMIPP_HWCFGR1_DSP2FT_Pos (13UL) +#define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */ +#define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */ +#define DCMIPP_HWCFGR1_RB2RGB_Pos (16UL) +#define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */ +#define DCMIPP_HWCFGR1_PLANARFT_Pos (20UL) +#define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */ +#define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI1NB_Pos (24UL) +#define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */ +#define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI2NB_Pos (28UL) +#define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */ +#define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */ + +/***************** Bit definition for DCMIPP_VERR register ******************/ +#define DCMIPP_VERR_MINREV_Pos (0UL) +#define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */ +#define DCMIPP_VERR_MAJREV_Pos (4UL) +#define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */ + +/***************** Bit definition for DCMIPP_IPIDR register *****************/ +#define DCMIPP_IPIDR_IDR_Pos (0UL) +#define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */ + +/***************** Bit definition for DCMIPP_SIDR register ******************/ +#define DCMIPP_SIDR_SID_Pos (0UL) +#define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */ + +/******************************************************************************/ +/* */ +/* Delay Block Interface (DLYBSD) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DLYBSD_CFGR register ********************/ +#define DLYB_CFGR_SDMMC_DLL_EN_Pos (0UL) +#define DLYB_CFGR_SDMMC_DLL_EN_Msk (0x1UL << DLYB_CFGR_SDMMC_DLL_EN_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SDMMC_DLL_EN DLYB_CFGR_SDMMC_DLL_EN_Msk /*!= AAW[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWHPCR_WHSPPOS_Pos (16UL) +#define LTDC_LxWHPCR_WHSPPOS_Msk (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos) +#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxWVPCR register */ +#define LTDC_LxWVPCR_WVSTPOS_Pos (0UL) +#define LTDC_LxWVPCR_WVSTPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos) +#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWVPCR_WVSPPOS_Pos (16UL) +#define LTDC_LxWVPCR_WVSPPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos) +#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxCKCR register */ +#define LTDC_LxCKCR_CKBLUE_Pos (0UL) +#define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos) +#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */ +#define LTDC_LxCKCR_CKGREEN_Pos (8UL) +#define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos) +#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */ +#define LTDC_LxCKCR_CKRED_Pos (16UL) +#define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos) +#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */ + +/* Bit fields for LTDC_LxPFCR register */ +#define LTDC_LxPFCR_PF_Pos (0UL) +#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) +#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */ + +/* Bit fields for LTDC_LxCACR register */ +#define LTDC_LxCACR_CONSTA_Pos (0UL) +#define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos) +#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */ + +/* Bit fields for LTDC_LxDCCR register */ +#define LTDC_LxDCCR_DCBLUE_Pos (0UL) +#define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos) +#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */ +#define LTDC_LxDCCR_DCGREEN_Pos (8UL) +#define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos) +#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */ +#define LTDC_LxDCCR_DCRED_Pos (16UL) +#define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos) +#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */ +#define LTDC_LxDCCR_DCALPHA_Pos (24UL) +#define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos) +#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */ + +/* Bit fields for LTDC_LxBFCR register */ +#define LTDC_LxBFCR_BF2_Pos (0UL) +#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) +#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */ +#define LTDC_LxBFCR_BF1_Pos (8UL) +#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) +#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */ +#define LTDC_LxBFCR_BOR_Pos (16UL) +#define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos) +#define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */ + +/* Bit fields for LTDC_LxBLCR register */ +#define LTDC_LxBLCR_BL_Pos (0UL) +#define LTDC_LxBLCR_BL_Msk (0x1fUL << LTDC_LxBLCR_BL_Pos) +#define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */ + +/* Bit fields for LTDC_LxPCR register */ +#define LTDC_LxPCR_YCEN_Pos (3UL) +#define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos) +#define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */ +#define LTDC_LxPCR_YCM_Pos (4UL) +#define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos) +#define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */ +#define LTDC_LxPCR_YF_Pos (6UL) +#define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos) +#define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */ +#define LTDC_LxPCR_CBF_Pos (7UL) +#define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos) +#define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */ +#define LTDC_LxPCR_OF_Pos (8UL) +#define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos) +#define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */ +#define LTDC_LxPCR_YREN_Pos (9UL) +#define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos) +#define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */ + +/* Bit fields for LTDC_LxCFBAR register */ +#define LTDC_LxCFBAR_CFBADD_Pos (0UL) +#define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos) +#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxCFBLR register */ +#define LTDC_LxCFBLR_CFBLL_Pos (0UL) +#define LTDC_LxCFBLR_CFBLL_Msk (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos) +#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_LxCFBLR_CFBP_Pos (16UL) +#define LTDC_LxCFBLR_CFBP_Msk (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos) +#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxCFBLNR register */ +#define LTDC_LxCFBLNR_CFBLNBR_Pos (0UL) +#define LTDC_LxCFBLNR_CFBLNBR_Msk (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos) +#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_L1AFBA0R register */ +#define LTDC_L1AFBA0R_AFBADD0_Pos (0UL) +#define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos) +#define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBA1R register */ +#define LTDC_L1AFBA1R_AFBADD1_Pos (0UL) +#define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos) +#define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBLR register */ +#define LTDC_L1AFBLR_AFBLL_Pos (0UL) +#define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos) +#define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_L1AFBLR_AFBP_Pos (16UL) +#define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos) +#define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxAFBLNR register */ +#define LTDC_L1AFBLNR_AFBLNBR_Pos (0UL) +#define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos) +#define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_LxCLUTWR register */ +#define LTDC_LxCLUTWR_BLUE_Pos (0UL) +#define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos) +#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */ +#define LTDC_LxCLUTWR_GREEN_Pos (8UL) +#define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos) +#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */ +#define LTDC_LxCLUTWR_RED_Pos (16UL) +#define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos) +#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */ +#define LTDC_LxCLUTWR_CLUTADD_Pos (24UL) +#define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos) +#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */ + +/* Bit fields for LTDC_LxCYR0R register */ +#define LTDC_LxCYR0R_CR2R_Pos (0UL) +#define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos) +#define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR0R_CB2B_Pos (16UL) +#define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos) +#define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxCYR1R register */ +#define LTDC_LxCYR1R_CR2G_Pos (0UL) +#define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos) +#define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR1R_CB2G_Pos (16UL) +#define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos) +#define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxFPF0R register */ +#define LTDC_LxFPF0R_APOS_Pos (0UL) +#define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos) +#define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_ALEN_Pos (5UL) +#define LTDC_LxFPF0R_ALEN_Msk (0xfUL << LTDC_LxFPF0R_ALEN_Pos) +#define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF0R_RPOS_Pos (9UL) +#define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos) +#define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_RLEN_Pos (14UL) +#define LTDC_LxFPF0R_RLEN_Msk (0xfUL << LTDC_LxFPF0R_RLEN_Pos) +#define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */ + +/* Bit fields for LTDC_LxFPF1R register */ +#define LTDC_LxFPF1R_GPOS_Pos (0UL) +#define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos) +#define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_GLEN_Pos (5UL) +#define LTDC_LxFPF1R_GLEN_Msk (0xfUL << LTDC_LxFPF1R_GLEN_Pos) +#define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF1R_BPOS_Pos (9UL) +#define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos) +#define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_BLEN_Pos (14UL) +#define LTDC_LxFPF1R_BLEN_Msk (0xfUL << LTDC_LxFPF1R_BLEN_Pos) +#define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */ + +#define LTDC_LxFPF1R_PSIZE_Pos (18UL) +#define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos) +#define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */ + + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ****************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */ +#define MDF_GCR_ILVNB_Pos (4UL) +#define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */ +#define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */ + +/******************* Bit definition for MDF/ADF_CKGCR register ********************/ +#define MDF_CKGCR_CKDEN_Pos (0UL) +#define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */ +#define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5UL) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6UL) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8UL) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10UL) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14UL) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18UL) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29UL) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30UL) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31UL) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2UL) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3UL) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register *******************/ +#define PSSI_RIS_OVR_RIS_Pos (1UL) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register *******************/ +#define PSSI_IER_OVR_IE_Pos (1UL) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register *******************/ +#define PSSI_MIS_OVR_MIS_Pos (1UL) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register *******************/ +#define PSSI_ICR_OVR_ISC_Pos (1UL) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0UL) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************* Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_SDEN_Pos (2UL) +#define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */ +#define PWR_CR1_MODE_PDN_Pos (4UL) +#define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */ +#define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */ +#define PWR_CR1_LPDS08V_Pos (5UL) +#define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */ +#define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */ +#define PWR_CR1_VDD18SMPSVMEN_Pos (8UL) +#define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */ +#define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */ +#define PWR_CR1_VDD18SMPSRDY_Pos (15UL) +#define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */ +#define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */ +#define PWR_CR1_POPL_Pos (16UL) +#define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */ +#define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */ +#define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */ +#define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */ +#define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */ +#define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */ +#define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */ + +/******************* Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDEN_Pos (0UL) +#define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */ +#define PWR_CR2_PVDO_Pos (8UL) +#define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */ +#define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +/******************* Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_VCOREMONEN_Pos (0UL) +#define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */ +#define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */ +#define PWR_CR3_VCORELLS_Pos (4UL) +#define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */ +#define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */ +#define PWR_CR3_VCOREL_Pos (8UL) +#define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */ +#define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */ +#define PWR_CR3_VCOREH_Pos (9UL) +#define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */ +#define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */ + +/******************* Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_TCMRBSEN_Pos (0UL) +#define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */ +#define PWR_CR4_TCMFLXRBSEN_Pos (4UL) +#define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */ +#define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */ + +/****************** Bit definition for PWR_VOSCR register *******************/ +#define PWR_VOSCR_VOS_Pos (0UL) +#define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */ +#define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */ +#define PWR_VOSCR_VOSRDY_Pos (1UL) +#define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSCR_ACTVOS_Pos (16UL) +#define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ +#define PWR_VOSCR_ACTVOSRDY_Pos (17UL) +#define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */ +#define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */ + +/****************** Bit definition for PWR_BDCR1 register *******************/ +#define PWR_BDCR1_MONEN_Pos (0UL) +#define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ +#define PWR_BDCR1_VBATL_Pos (16UL) +#define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */ +#define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */ +#define PWR_BDCR1_VBATH_Pos (17UL) +#define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */ +#define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */ +#define PWR_BDCR1_TEMPL_Pos (18UL) +#define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */ +#define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */ +#define PWR_BDCR1_TEMPH_Pos (19UL) +#define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */ +#define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */ + +/****************** Bit definition for PWR_BDCR2 register *******************/ +#define PWR_BDCR2_BKPRBSEN_Pos (0UL) +#define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */ + +/****************** Bit definition for PWR_DBPCR register *******************/ +#define PWR_DBPCR_DBP_Pos (0UL) +#define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */ + +/****************** Bit definition for PWR_CPUCR register *******************/ +#define PWR_CPUCR_PDDS_Pos (0UL) +#define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */ +#define PWR_CPUCR_CSSF_Pos (1UL) +#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */ +#define PWR_CPUCR_STOPF_Pos (8UL) +#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */ +#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */ +#define PWR_CPUCR_SBF_Pos (9UL) +#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */ +#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */ +#define PWR_CPUCR_SVOS_Pos (16UL) +#define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */ +#define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */ + +/****************** Bit definition for PWR_SVMCR1 register ******************/ +#define PWR_SVMCR1_VDDIO4VMEN_Pos (0UL) +#define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */ +#define PWR_SVMCR1_VDDIO4SV_Pos (8UL) +#define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */ +#define PWR_SVMCR1_VDDIO4RDY_Pos (16UL) +#define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */ +#define PWR_SVMCR1_VDDIO4VRSEL_Pos (24UL) +#define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */ +#define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25UL) +#define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR2 register ******************/ +#define PWR_SVMCR2_VDDIO5VMEN_Pos (0UL) +#define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */ +#define PWR_SVMCR2_VDDIO5SV_Pos (8UL) +#define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */ +#define PWR_SVMCR2_VDDIO5RDY_Pos (16UL) +#define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */ +#define PWR_SVMCR2_VDDIO5VRSEL_Pos (24UL) +#define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */ +#define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25UL) +#define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR3 register ******************/ +#define PWR_SVMCR3_VDDIO2VMEN_Pos (0UL) +#define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */ +#define PWR_SVMCR3_VDDIO3VMEN_Pos (1UL) +#define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */ +#define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */ +#define PWR_SVMCR3_USB33VMEN_Pos (2UL) +#define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */ +#define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */ +#define PWR_SVMCR3_AVMEN_Pos (4UL) +#define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */ +#define PWR_SVMCR3_VDDIO2SV_Pos (8UL) +#define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */ +#define PWR_SVMCR3_VDDIO3SV_Pos (9UL) +#define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */ +#define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */ +#define PWR_SVMCR3_USB33SV_Pos (10UL) +#define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */ +#define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */ +#define PWR_SVMCR3_ASV_Pos (12UL) +#define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */ +#define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */ +#define PWR_SVMCR3_VDDIO2RDY_Pos (16UL) +#define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */ +#define PWR_SVMCR3_VDDIO3RDY_Pos (17UL) +#define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */ +#define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */ +#define PWR_SVMCR3_USB33RDY_Pos (18UL) +#define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */ +#define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */ +#define PWR_SVMCR3_ARDY_Pos (20UL) +#define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */ +#define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */ +#define PWR_SVMCR3_VDDIOVRSEL_Pos (24UL) +#define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */ +#define PWR_SVMCR3_VDDIO2VRSEL_Pos (25UL) +#define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */ +#define PWR_SVMCR3_VDDIO3VRSEL_Pos (26UL) +#define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */ + +/***************** Bit definition for PWR_WKUPCR register *******************/ +#define PWR_WKUPCR_WKUPC1_Pos (0UL) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPCR_WKUPC2_Pos (1UL) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPCR_WKUPC3_Pos (2UL) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPCR_WKUPC4_Pos (3UL) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */ +#define PWR_WKUPCR_WKUPC_Pos (0UL) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */ + +/***************** Bit definition for PWR_WKUPSR register *******************/ +#define PWR_WKUPSR_WKUPF1_Pos (0UL) +#define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPSR_WKUPF2_Pos (1UL) +#define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPSR_WKUPF3_Pos (2UL) +#define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPSR_WKUPF4_Pos (3UL) +#define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */ + +/***************** Bit definition for PWR_WKUPEPR register *******************/ +#define PWR_WKUPEPR_WKUPEN1_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1UL) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2UL) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3UL) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8UL) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPP2_Pos (9UL) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPP3_Pos (10UL) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPP4_Pos (11UL) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPP_Pos (8UL) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16UL) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18UL) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20UL) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22UL) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WKUPEPR_WKUPEN_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ + +/***************** Bit definition for PWR_SECCFGR register ******************/ +#define PWR_SECCFGR_SEC0_Pos (0UL) +#define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */ +#define PWR_SECCFGR_SEC1_Pos (1UL) +#define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */ +#define PWR_SECCFGR_SEC2_Pos (2UL) +#define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */ +#define PWR_SECCFGR_SEC3_Pos (3UL) +#define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */ +#define PWR_SECCFGR_SEC4_Pos (4UL) +#define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */ +#define PWR_SECCFGR_SEC5_Pos (5UL) +#define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */ +#define PWR_SECCFGR_SEC6_Pos (6UL) +#define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */ +#define PWR_SECCFGR_SEC7_Pos (7UL) +#define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */ +#define PWR_SECCFGR_WKUPSEC1_Pos (16UL) +#define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */ +#define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */ +#define PWR_SECCFGR_WKUPSEC2_Pos (17UL) +#define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */ +#define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */ +#define PWR_SECCFGR_WKUPSEC3_Pos (18UL) +#define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */ +#define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */ +#define PWR_SECCFGR_WKUPSEC4_Pos (19UL) +#define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */ +#define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */ + +/***************** Bit definition for PWR_PRIVCFGR register *****************/ +#define PWR_PRIVCFGR_PRIV0_Pos (0UL) +#define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */ +#define PWR_PRIVCFGR_PRIV1_Pos (1UL) +#define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */ +#define PWR_PRIVCFGR_PRIV2_Pos (2UL) +#define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */ +#define PWR_PRIVCFGR_PRIV3_Pos (3UL) +#define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */ +#define PWR_PRIVCFGR_PRIV4_Pos (4UL) +#define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */ +#define PWR_PRIVCFGR_PRIV5_Pos (5UL) +#define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */ +#define PWR_PRIVCFGR_PRIV6_Pos (6UL) +#define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */ +#define PWR_PRIVCFGR_PRIV7_Pos (7UL) +#define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV1_Pos (16UL) +#define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */ +#define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV2_Pos (17UL) +#define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */ +#define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV3_Pos (18UL) +#define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */ +#define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV4_Pos (19UL) +#define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */ +#define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */ + + +/******************************************************************************/ +/* */ +/* RAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_CR register ******************/ +#define RAMCFG_CR_ECCE_Pos (0UL) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */ +#define RAMCFG_CR_ALE_Pos (4UL) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8UL) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_SRAMHWERDIS_Pos (12UL) +#define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */ +#define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */ +#define RAMCFG_CR_ITCMCFG_Pos (16UL) +#define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */ +#define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ +#define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_SRAMSD_Pos (20UL) +#define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */ +#define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */ +#define RAMCFG_CR_DTCMCFG_Pos (24UL) +#define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */ +#define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ + +/******************* Bit definition for RAMCFG_IER register *****************/ +#define RAMCFG_IER_SEIE_Pos (0UL) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */ +#define RAMCFG_IER_DEIE_Pos (1UL) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */ + +/******************* Bit definition for RAMCFG_ISR register *****************/ +#define RAMCFG_ISR_SEDC_Pos (0UL) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */ +#define RAMCFG_ISR_DED_Pos (1UL) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8UL) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */ + +/******************* Bit definition for RAMCFG_ESEAR register ****************/ +#define RAMCFG_ESEAR_ESEA_Pos (0UL) +#define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */ + +/******************* Bit definition for RAMCFG_EDEAR register ****************/ +#define RAMCFG_EDEAR_EDEA_Pos (0UL) +#define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */ + +/******************* Bit definition for RAMCFG_ICR register *****************/ +#define RAMCFG_ICR_CSEDC_Pos (0UL) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */ +#define RAMCFG_ICR_CDED_Pos (1UL) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/ + +/***************** Bit definition for RAMCFG_ECCKEYR register ***************/ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0UL) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */ + +/***************** Bit definition for RAMCFG_ERKEYR register ****************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0UL) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */ + + +/******************************************************************************/ +/* */ +/* (RCC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_LSION_Pos (0UL) +#define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_CR_LSEON_Pos (1UL) +#define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */ +#define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */ +#define RCC_CR_MSION_Pos (2UL) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */ +#define RCC_CR_HSION_Pos (3UL) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */ +#define RCC_CR_HSEON_Pos (4UL) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */ +#define RCC_CR_PLL1ON_Pos (8UL) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */ +#define RCC_CR_PLL2ON_Pos (9UL) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ +#define RCC_CR_PLL3ON_Pos (10UL) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ +#define RCC_CR_PLL4ON_Pos (11UL) +#define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */ +#define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */ + +/******************** Bit definition for RCC_SR register ********************/ +#define RCC_SR_LSIRDY_Pos (0UL) +#define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */ +#define RCC_SR_LSERDY_Pos (1UL) +#define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */ +#define RCC_SR_MSIRDY_Pos (2UL) +#define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */ +#define RCC_SR_HSIRDY_Pos (3UL) +#define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */ +#define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_SR_HSERDY_Pos (4UL) +#define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */ +#define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_SR_PLL1RDY_Pos (8UL) +#define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */ +#define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_SR_PLL2RDY_Pos (9UL) +#define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */ +#define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_SR_PLL3RDY_Pos (10UL) +#define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */ +#define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_SR_PLL4RDY_Pos (11UL) +#define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */ +#define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ + +/****************** Bit definition for RCC_STOPCR register ******************/ +#define RCC_STOPCR_MSISTOPEN_Pos (0UL) +#define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */ +#define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCR_HSISTOPEN_Pos (1UL) +#define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */ +#define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */ + +/****************** Bit definition for RCC_CFGR1 register *******************/ +#define RCC_CFGR1_STOPWUCK_Pos (0UL) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */ +#define RCC_CFGR1_CPUSW_Pos (16UL) +#define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */ +#define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */ +#define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */ +#define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */ +#define RCC_CFGR1_CPUSWS_Pos (20UL) +#define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */ +#define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */ +#define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_SYSSW_Pos (24UL) +#define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */ +#define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */ +#define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_SYSSWS_Pos (28UL) +#define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */ +#define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for RCC_CFGR2 register *******************/ +#define RCC_CFGR2_PPRE1_Pos (0UL) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE2_Pos (4UL) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE4_Pos (12UL) +#define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */ +#define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_PPRE5_Pos (16UL) +#define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */ +#define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */ +#define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */ +#define RCC_CFGR2_HPRE_Pos (20UL) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_TIMPRE_Pos (24UL) +#define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */ +#define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */ +#define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */ +#define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_VSWRST_Pos (31UL) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */ + +/****************** Bit definition for RCC_HWRSR register *******************/ +#define RCC_HWRSR_RMVF_Pos (16UL) +#define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_HWRSR_LCKRSTF_Pos (17UL) +#define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_HWRSR_BORRSTF_Pos (21UL) +#define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_HWRSR_PINRSTF_Pos (22UL) +#define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_HWRSR_PORRSTF_Pos (23UL) +#define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_HWRSR_SFTRSTF_Pos (24UL) +#define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_HWRSR_IWDGRSTF_Pos (26UL) +#define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_HWRSR_WWDGRSTF_Pos (28UL) +#define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_HWRSR_LPWRRSTF_Pos (30UL) +#define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/******************* Bit definition for RCC_RSR register ********************/ +#define RCC_RSR_RMVF_Pos (16UL) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_LCKRSTF_Pos (17UL) +#define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_RSR_BORRSTF_Pos (21UL) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_RSR_PINRSTF_Pos (22UL) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_PORRSTF_Pos (23UL) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (24UL) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_RSR_IWDGRSTF_Pos (26UL) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (28UL) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (30UL) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/***************** Bit definition for RCC_LSECFGR register ******************/ +#define RCC_LSECFGR_LSECSSON_Pos (7UL) +#define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */ +#define RCC_LSECFGR_LSECSSRA_Pos (8UL) +#define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */ +#define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */ +#define RCC_LSECFGR_LSECSSD_Pos (9UL) +#define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */ +#define RCC_LSECFGR_LSEBYP_Pos (15UL) +#define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */ +#define RCC_LSECFGR_LSEEXT_Pos (16UL) +#define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */ +#define RCC_LSECFGR_LSEGFON_Pos (17UL) +#define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */ +#define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */ +#define RCC_LSECFGR_LSEDRV_Pos (18UL) +#define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */ +#define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */ +#define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for RCC_MSICFGR register ******************/ +#define RCC_MSICFGR_MSIFREQSEL_Pos (9UL) +#define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */ +#define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */ +#define RCC_MSICFGR_MSITRIM_Pos (16UL) +#define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */ +#define RCC_MSICFGR_MSICAL_Pos (23UL) +#define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */ +#define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (7UL) +#define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_Pos (16UL) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSICAL_Pos (23UL) +#define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ + +/****************** Bit definition for RCC_HSIMCR register ******************/ +#define RCC_HSIMCR_HSIREF_Pos (0UL) +#define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */ +#define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */ +#define RCC_HSIMCR_HSIDEV_Pos (16UL) +#define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */ +#define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */ +#define RCC_HSIMCR_HSIMONEN_Pos (31UL) +#define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */ +#define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */ + +/****************** Bit definition for RCC_HSIMSR register ******************/ +#define RCC_HSIMSR_HSIVAL_Pos (0UL) +#define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */ +#define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */ + +/***************** Bit definition for RCC_HSECFGR register ******************/ +#define RCC_HSECFGR_HSEDIV2SEL_Pos (6UL) +#define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */ +#define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */ +#define RCC_HSECFGR_HSECSSON_Pos (7UL) +#define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */ +#define RCC_HSECFGR_HSECSSD_Pos (9UL) +#define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */ +#define RCC_HSECFGR_HSECSSBYP_Pos (10UL) +#define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */ +#define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */ +#define RCC_HSECFGR_HSECSSBPRE_Pos (11UL) +#define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */ +#define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */ +#define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */ +#define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */ +#define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */ +#define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */ +#define RCC_HSECFGR_HSEBYP_Pos (15UL) +#define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_HSECFGR_HSEEXT_Pos (16UL) +#define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_PLL1DIVN_Pos (8UL) +#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */ +#define RCC_PLL1CFGR1_PLL1DIVM_Pos (20UL) +#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */ +#define RCC_PLL1CFGR1_PLL1BYP_Pos (27UL) +#define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */ +#define RCC_PLL1CFGR1_PLL1SEL_Pos (28UL) +#define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */ +#define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0UL) +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL1CFGR3 register *****************/ +#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0UL) +#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */ +#define RCC_PLL1CFGR3_PLL1DACEN_Pos (1UL) +#define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2UL) +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */ +#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3UL) +#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4UL) +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */ +#define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8UL) +#define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */ +#define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16UL) +#define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */ +#define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24UL) +#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */ +#define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27UL) +#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30UL) +#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_PLL2DIVN_Pos (8UL) +#define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */ +#define RCC_PLL2CFGR1_PLL2DIVM_Pos (20UL) +#define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */ +#define RCC_PLL2CFGR1_PLL2BYP_Pos (27UL) +#define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */ +#define RCC_PLL2CFGR1_PLL2SEL_Pos (28UL) +#define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */ +#define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0UL) +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL2CFGR3 register *****************/ +#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0UL) +#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */ +#define RCC_PLL2CFGR3_PLL2DACEN_Pos (1UL) +#define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2UL) +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */ +#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3UL) +#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4UL) +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */ +#define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8UL) +#define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */ +#define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16UL) +#define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */ +#define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24UL) +#define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */ +#define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27UL) +#define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30UL) +#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_PLL3DIVN_Pos (8UL) +#define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */ +#define RCC_PLL3CFGR1_PLL3DIVM_Pos (20UL) +#define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */ +#define RCC_PLL3CFGR1_PLL3BYP_Pos (27UL) +#define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */ +#define RCC_PLL3CFGR1_PLL3SEL_Pos (28UL) +#define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */ +#define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0UL) +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL3CFGR3 register *****************/ +#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0UL) +#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */ +#define RCC_PLL3CFGR3_PLL3DACEN_Pos (1UL) +#define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2UL) +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */ +#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3UL) +#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4UL) +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */ +#define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8UL) +#define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */ +#define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16UL) +#define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */ +#define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24UL) +#define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */ +#define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27UL) +#define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30UL) +#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_PLL4DIVN_Pos (8UL) +#define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */ +#define RCC_PLL4CFGR1_PLL4DIVM_Pos (20UL) +#define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */ +#define RCC_PLL4CFGR1_PLL4BYP_Pos (27UL) +#define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */ +#define RCC_PLL4CFGR1_PLL4SEL_Pos (28UL) +#define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */ +#define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0UL) +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL4CFGR3 register *****************/ +#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0UL) +#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */ +#define RCC_PLL4CFGR3_PLL4DACEN_Pos (1UL) +#define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2UL) +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */ +#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3UL) +#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4UL) +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */ +#define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8UL) +#define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */ +#define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16UL) +#define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */ +#define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24UL) +#define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */ +#define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27UL) +#define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30UL) +#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/***************** Bit definition for RCC_IC1CFGR register ******************/ +#define RCC_IC1CFGR_IC1INT_Pos (16UL) +#define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */ +#define RCC_IC1CFGR_IC1SEL_Pos (28UL) +#define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */ +#define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC2CFGR register ******************/ +#define RCC_IC2CFGR_IC2INT_Pos (16UL) +#define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */ +#define RCC_IC2CFGR_IC2SEL_Pos (28UL) +#define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */ +#define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC3CFGR register ******************/ +#define RCC_IC3CFGR_IC3INT_Pos (16UL) +#define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */ +#define RCC_IC3CFGR_IC3SEL_Pos (28UL) +#define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */ +#define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC4CFGR register ******************/ +#define RCC_IC4CFGR_IC4INT_Pos (16UL) +#define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */ +#define RCC_IC4CFGR_IC4SEL_Pos (28UL) +#define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */ +#define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC5CFGR register ******************/ +#define RCC_IC5CFGR_IC5INT_Pos (16UL) +#define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */ +#define RCC_IC5CFGR_IC5SEL_Pos (28UL) +#define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */ +#define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC6CFGR register ******************/ +#define RCC_IC6CFGR_IC6INT_Pos (16UL) +#define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */ +#define RCC_IC6CFGR_IC6SEL_Pos (28UL) +#define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */ +#define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC7CFGR register ******************/ +#define RCC_IC7CFGR_IC7INT_Pos (16UL) +#define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */ +#define RCC_IC7CFGR_IC7SEL_Pos (28UL) +#define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */ +#define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC8CFGR register ******************/ +#define RCC_IC8CFGR_IC8INT_Pos (16UL) +#define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */ +#define RCC_IC8CFGR_IC8SEL_Pos (28UL) +#define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */ +#define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC9CFGR register ******************/ +#define RCC_IC9CFGR_IC9INT_Pos (16UL) +#define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */ +#define RCC_IC9CFGR_IC9SEL_Pos (28UL) +#define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */ +#define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC10CFGR register *****************/ +#define RCC_IC10CFGR_IC10INT_Pos (16UL) +#define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */ +#define RCC_IC10CFGR_IC10SEL_Pos (28UL) +#define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */ +#define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC11CFGR register *****************/ +#define RCC_IC11CFGR_IC11INT_Pos (16UL) +#define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */ +#define RCC_IC11CFGR_IC11SEL_Pos (28UL) +#define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */ +#define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC12CFGR register *****************/ +#define RCC_IC12CFGR_IC12INT_Pos (16UL) +#define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */ +#define RCC_IC12CFGR_IC12SEL_Pos (28UL) +#define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */ +#define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC13CFGR register *****************/ +#define RCC_IC13CFGR_IC13INT_Pos (16UL) +#define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */ +#define RCC_IC13CFGR_IC13SEL_Pos (28UL) +#define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */ +#define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC14CFGR register *****************/ +#define RCC_IC14CFGR_IC14INT_Pos (16UL) +#define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */ +#define RCC_IC14CFGR_IC14SEL_Pos (28UL) +#define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */ +#define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC15CFGR register *****************/ +#define RCC_IC15CFGR_IC15INT_Pos (16UL) +#define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */ +#define RCC_IC15CFGR_IC15SEL_Pos (28UL) +#define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */ +#define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC16CFGR register *****************/ +#define RCC_IC16CFGR_IC16INT_Pos (16UL) +#define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */ +#define RCC_IC16CFGR_IC16SEL_Pos (28UL) +#define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */ +#define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC17CFGR register *****************/ +#define RCC_IC17CFGR_IC17INT_Pos (16UL) +#define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */ +#define RCC_IC17CFGR_IC17SEL_Pos (28UL) +#define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */ +#define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC18CFGR register *****************/ +#define RCC_IC18CFGR_IC18INT_Pos (16UL) +#define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */ +#define RCC_IC18CFGR_IC18SEL_Pos (28UL) +#define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */ +#define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC19CFGR register *****************/ +#define RCC_IC19CFGR_IC19INT_Pos (16UL) +#define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */ +#define RCC_IC19CFGR_IC19SEL_Pos (28UL) +#define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */ +#define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC20CFGR register *****************/ +#define RCC_IC20CFGR_IC20INT_Pos (16UL) +#define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */ +#define RCC_IC20CFGR_IC20SEL_Pos (28UL) +#define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */ +#define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for RCC_CIER register *******************/ +#define RCC_CIER_LSIRDYIE_Pos (0UL) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1UL) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_MSIRDYIE_Pos (2UL) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */ +#define RCC_CIER_HSIRDYIE_Pos (3UL) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (4UL) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ +#define RCC_CIER_PLL1RDYIE_Pos (8UL) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */ +#define RCC_CIER_PLL2RDYIE_Pos (9UL) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */ +#define RCC_CIER_PLL3RDYIE_Pos (10UL) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */ +#define RCC_CIER_PLL4RDYIE_Pos (11UL) +#define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */ +#define RCC_CIER_LSECSSIE_Pos (16UL) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */ +#define RCC_CIER_HSECSSIE_Pos (17UL) +#define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */ +#define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */ +#define RCC_CIER_WKUPIE_Pos (24UL) +#define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */ +#define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */ + +/******************* Bit definition for RCC_CIFR register *******************/ +#define RCC_CIFR_LSIRDYF_Pos (0UL) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1UL) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (2UL) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (3UL) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (4UL) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_PLL1RDYF_Pos (8UL) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */ +#define RCC_CIFR_PLL2RDYF_Pos (9UL) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */ +#define RCC_CIFR_PLL3RDYF_Pos (10UL) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */ +#define RCC_CIFR_PLL4RDYF_Pos (11UL) +#define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (16UL) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (17UL) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_WKUPF_Pos (24UL) +#define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */ +#define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */ + +/******************* Bit definition for RCC_CICR register *******************/ +#define RCC_CICR_LSIRDYC_Pos (0UL) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1UL) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_MSIRDYC_Pos (2UL) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */ +#define RCC_CICR_HSIRDYC_Pos (3UL) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (4UL) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_PLL1RDYC_Pos (8UL) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */ +#define RCC_CICR_PLL2RDYC_Pos (9UL) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */ +#define RCC_CICR_PLL3RDYC_Pos (10UL) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */ +#define RCC_CICR_PLL4RDYC_Pos (11UL) +#define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (16UL) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (17UL) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_WKUPFC_Pos (24UL) +#define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */ +#define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */ + +/****************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_ADF1SEL_Pos (0UL) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */ +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_ADC12SEL_Pos (4UL) +#define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */ +#define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_ADCPRE_Pos (8UL) +#define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */ +#define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */ +#define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_DCMIPPSEL_Pos (20UL) +#define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */ +#define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_ETH1PTPSEL_Pos (0UL) +#define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_ETH1PTPDIV_Pos (4UL) +#define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */ +#define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8UL) +#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1CLKSEL_Pos (12UL) +#define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ETH1SEL_Pos (16UL) +#define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20UL) +#define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24UL) +#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR3 register ******************/ +#define RCC_CCIPR3_FDCANSEL_Pos (0UL) +#define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */ +#define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_FMCSEL_Pos (4UL) +#define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */ +#define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_DFTSEL_Pos (8UL) +#define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */ + +/****************** Bit definition for RCC_CCIPR4 register ******************/ +#define RCC_CCIPR4_I2C1SEL_Pos (0UL) +#define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */ +#define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR4_I2C2SEL_Pos (4UL) +#define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */ +#define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR4_I2C3SEL_Pos (8UL) +#define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */ +#define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR4_I2C4SEL_Pos (12UL) +#define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */ +#define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR4_I3C1SEL_Pos (16UL) +#define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */ +#define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR4_I3C2SEL_Pos (20UL) +#define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */ +#define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR4_LTDCSEL_Pos (24UL) +#define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */ +#define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */ + +/****************** Bit definition for RCC_CCIPR5 register ******************/ +#define RCC_CCIPR5_MCO1SEL_Pos (0UL) +#define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */ +#define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR5_MCO1PRE_Pos (4UL) +#define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */ +#define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR5_MCO2SEL_Pos (8UL) +#define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */ +#define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR5_MCO2PRE_Pos (12UL) +#define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */ +#define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */ +#define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR5_MDF1SEL_Pos (16UL) +#define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */ +#define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for RCC_CCIPR6 register ******************/ +#define RCC_CCIPR6_XSPI1SEL_Pos (0UL) +#define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */ +#define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR6_XSPI2SEL_Pos (4UL) +#define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */ +#define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR6_XSPI3SEL_Pos (8UL) +#define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */ +#define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR6_OTGPHY1SEL_Pos (12UL) +#define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */ +#define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16UL) +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR6_OTGPHY2SEL_Pos (20UL) +#define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */ +#define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24UL) +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR7 register ******************/ +#define RCC_CCIPR7_PERSEL_Pos (0UL) +#define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */ +#define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR7_PSSISEL_Pos (4UL) +#define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */ +#define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR7_RTCSEL_Pos (8UL) +#define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */ +#define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR7_RTCPRE_Pos (12UL) +#define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */ +#define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */ +#define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR7_SAI1SEL_Pos (20UL) +#define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */ +#define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR7_SAI2SEL_Pos (24UL) +#define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */ +#define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */ + +/****************** Bit definition for RCC_CCIPR8 register ******************/ +#define RCC_CCIPR8_SDMMC1SEL_Pos (0UL) +#define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */ +#define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR8_SDMMC2SEL_Pos (4UL) +#define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */ +#define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */ + +/****************** Bit definition for RCC_CCIPR9 register ******************/ +#define RCC_CCIPR9_SPDIFRX1SEL_Pos (0UL) +#define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */ +#define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR9_SPI1SEL_Pos (4UL) +#define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */ +#define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR9_SPI2SEL_Pos (8UL) +#define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */ +#define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR9_SPI3SEL_Pos (12UL) +#define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */ +#define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR9_SPI4SEL_Pos (16UL) +#define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */ +#define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR9_SPI5SEL_Pos (20UL) +#define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */ +#define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR9_SPI6SEL_Pos (24UL) +#define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */ +#define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR12 register ******************/ +#define RCC_CCIPR12_LPTIM1SEL_Pos (8UL) +#define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */ +#define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR12_LPTIM2SEL_Pos (12UL) +#define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */ +#define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR12_LPTIM3SEL_Pos (16UL) +#define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */ +#define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR12_LPTIM4SEL_Pos (20UL) +#define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */ +#define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR12_LPTIM5SEL_Pos (24UL) +#define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */ +#define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR13 register ******************/ +#define RCC_CCIPR13_USART1SEL_Pos (0UL) +#define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */ +#define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR13_USART2SEL_Pos (4UL) +#define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */ +#define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR13_USART3SEL_Pos (8UL) +#define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */ +#define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR13_UART4SEL_Pos (12UL) +#define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */ +#define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR13_UART5SEL_Pos (16UL) +#define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */ +#define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR13_USART6SEL_Pos (20UL) +#define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */ +#define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR13_UART7SEL_Pos (24UL) +#define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */ +#define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR13_UART8SEL_Pos (28UL) +#define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */ +#define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */ +#define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */ + +/***************** Bit definition for RCC_CCIPR14 register ******************/ +#define RCC_CCIPR14_UART9SEL_Pos (0UL) +#define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */ +#define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR14_USART10SEL_Pos (4UL) +#define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */ +#define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR14_LPUART1SEL_Pos (8UL) +#define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */ +#define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */ + +/***************** Bit definition for RCC_MISCRSTR register *****************/ +#define RCC_MISCRSTR_DBGRST_Pos (0UL) +#define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */ +#define RCC_MISCRSTR_XSPIPHY1RST_Pos (4UL) +#define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTR_XSPIPHY2RST_Pos (5UL) +#define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7UL) +#define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8UL) +#define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTR register ******************/ +#define RCC_MEMRSTR_AXISRAM3RST_Pos (0UL) +#define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */ +#define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTR_AXISRAM4RST_Pos (1UL) +#define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */ +#define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTR_AXISRAM5RST_Pos (2UL) +#define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */ +#define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTR_AXISRAM6RST_Pos (3UL) +#define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */ +#define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTR_AHBSRAM1RST_Pos (4UL) +#define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */ +#define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTR_AHBSRAM2RST_Pos (5UL) +#define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */ +#define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTR_AXISRAM1RST_Pos (7UL) +#define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */ +#define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTR_AXISRAM2RST_Pos (8UL) +#define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */ +#define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTR_FLEXRAMRST_Pos (9UL) +#define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTR_CACHEAXIRAMRST_Pos (10UL) +#define RCC_MEMRSTR_CACHEAXIRAMRST_Msk (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTR_CACHEAXIRAMRST RCC_MEMRSTR_CACHEAXIRAMRST_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTR_VENCRAMRST_Pos (11UL) +#define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTR_BOOTROMRST_Pos (12UL) +#define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */ + +/***************** Bit definition for RCC_AHB1RSTR register *****************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4UL) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTR_ADC12RST_Pos (5UL) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */ + +/***************** Bit definition for RCC_AHB2RSTR register *****************/ +#define RCC_AHB2RSTR_RAMCFGRST_Pos (12UL) +#define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTR_MDF1RST_Pos (16UL) +#define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTR_ADF1RST_Pos (17UL) +#define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */ + +/***************** Bit definition for RCC_AHB3RSTR register *****************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0UL) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */ +#define RCC_AHB3RSTR_HASHRST_Pos (1UL) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB3RSTR_PKARST_Pos (8UL) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */ +#define RCC_AHB3RSTR_IACRST_Pos (10UL) +#define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */ + +/***************** Bit definition for RCC_AHB4RSTR register *****************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0UL) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTR_GPIOBRST_Pos (1UL) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTR_GPIOCRST_Pos (2UL) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTR_GPIODRST_Pos (3UL) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTR_GPIOERST_Pos (4UL) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTR_GPIOFRST_Pos (5UL) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTR_GPIOGRST_Pos (6UL) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTR_GPIOHRST_Pos (7UL) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTR_GPIONRST_Pos (13UL) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTR_GPIOORST_Pos (14UL) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTR_GPIOPRST_Pos (15UL) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTR_GPIOQRST_Pos (16UL) +#define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTR_PWRRST_Pos (18UL) +#define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */ +#define RCC_AHB4RSTR_CRCRST_Pos (19UL) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */ + +/***************** Bit definition for RCC_AHB5RSTR register *****************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0UL) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTR_DMA2DRST_Pos (1UL) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTR_JPEGRST_Pos (3UL) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTR_FMCRST_Pos (4UL) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */ +#define RCC_AHB5RSTR_XSPI1RST_Pos (5UL) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTR_PSSIRST_Pos (6UL) +#define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTR_SDMMC2RST_Pos (7UL) +#define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8UL) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTR_XSPI2RST_Pos (12UL) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTR_XSPIMRST_Pos (13UL) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTR_XSPI3RST_Pos (17UL) +#define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTR_GFXMMURST_Pos (19UL) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTR_GPU2DRST_Pos (20UL) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23UL) +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24UL) +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTR_ETH1RST_Pos (25UL) +#define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTR_OTG1RST_Pos (26UL) +#define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTR_OTGPHY1RST_Pos (27UL) +#define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */ +#define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTR_OTGPHY2RST_Pos (28UL) +#define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */ +#define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTR_OTG2RST_Pos (29UL) +#define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTR_CACHEAXIRST_Pos (30UL) +#define RCC_AHB5RSTR_CACHEAXIRST_Msk (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTR_CACHEAXIRST RCC_AHB5RSTR_CACHEAXIRST_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTR_NPURST_Pos (31UL) +#define RCC_AHB5RSTR_NPURST_Msk (0x1UL << RCC_AHB5RSTR_NPURST_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTR_NPURST RCC_AHB5RSTR_NPURST_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTR1 register *****************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0UL) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTR1_TIM3RST_Pos (1UL) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTR1_TIM4RST_Pos (2UL) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTR1_TIM5RST_Pos (3UL) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTR1_TIM6RST_Pos (4UL) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTR1_TIM7RST_Pos (5UL) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTR1_TIM12RST_Pos (6UL) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTR1_TIM13RST_Pos (7UL) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTR1_TIM14RST_Pos (8UL) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9UL) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTR1_WWDGRST_Pos (11UL) +#define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */ +#define RCC_APB1RSTR1_TIM10RST_Pos (12UL) +#define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTR1_TIM11RST_Pos (13UL) +#define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTR1_SPI2RST_Pos (14UL) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTR1_SPI3RST_Pos (15UL) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16UL) +#define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTR1_USART2RST_Pos (17UL) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1RSTR1_USART3RST_Pos (18UL) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1RSTR1_UART4RST_Pos (19UL) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1RSTR1_UART5RST_Pos (20UL) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1RSTR1_I2C1RST_Pos (21UL) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTR1_I2C2RST_Pos (22UL) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTR1_I2C3RST_Pos (23UL) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTR1_I3C1RST_Pos (24UL) +#define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTR1_I3C2RST_Pos (25UL) +#define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTR1_UART7RST_Pos (30UL) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */ +#define RCC_APB1RSTR1_UART8RST_Pos (31UL) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTR2 register *****************/ +#define RCC_APB1RSTR2_MDIOSRST_Pos (5UL) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTR2_FDCANRST_Pos (8UL) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTR2_UCPD1RST_Pos (18UL) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0UL) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (1UL) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (4UL) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_USART6RST_Pos (5UL) +#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ +#define RCC_APB2RSTR_UART9RST_Pos (6UL) +#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */ +#define RCC_APB2RSTR_USART10RST_Pos (7UL) +#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */ +#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12UL) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST_Pos (13UL) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTR_TIM18RST_Pos (15UL) +#define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */ +#define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16UL) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17UL) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18UL) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_TIM9RST_Pos (19UL) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTR_SPI5RST_Pos (20UL) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTR_SAI1RST_Pos (21UL) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST_Pos (22UL) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTR1 register *****************/ +#define RCC_APB4RSTR1_HDPRST_Pos (2UL) +#define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */ +#define RCC_APB4RSTR1_LPUART1RST_Pos (3UL) +#define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTR1_SPI6RST_Pos (5UL) +#define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTR1_I2C4RST_Pos (7UL) +#define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */ +#define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTR1_LPTIM2RST_Pos (9UL) +#define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */ +#define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTR1_LPTIM3RST_Pos (10UL) +#define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */ +#define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTR1_LPTIM4RST_Pos (11UL) +#define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */ +#define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTR1_LPTIM5RST_Pos (12UL) +#define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */ +#define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTR1_VREFBUFRST_Pos (15UL) +#define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTR1_RTCRST_Pos (16UL) +#define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTR2 register *****************/ +#define RCC_APB4RSTR2_SYSCFGRST_Pos (0UL) +#define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */ +#define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTR2_DTSRST_Pos (2UL) +#define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */ + +/***************** Bit definition for RCC_APB5RSTR register *****************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1UL) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2UL) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTR_GFXTIMRST_Pos (4UL) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTR_VENCRST_Pos (5UL) +#define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */ +#define RCC_APB5RSTR_CSIRST_Pos (6UL) +#define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */ + +/****************** Bit definition for RCC_DIVENR register ******************/ +#define RCC_DIVENR_IC1EN_Pos (0UL) +#define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */ +#define RCC_DIVENR_IC2EN_Pos (1UL) +#define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */ +#define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */ +#define RCC_DIVENR_IC3EN_Pos (2UL) +#define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */ +#define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */ +#define RCC_DIVENR_IC4EN_Pos (3UL) +#define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */ +#define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */ +#define RCC_DIVENR_IC5EN_Pos (4UL) +#define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */ +#define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */ +#define RCC_DIVENR_IC6EN_Pos (5UL) +#define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */ +#define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */ +#define RCC_DIVENR_IC7EN_Pos (6UL) +#define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */ +#define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */ +#define RCC_DIVENR_IC8EN_Pos (7UL) +#define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */ +#define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */ +#define RCC_DIVENR_IC9EN_Pos (8UL) +#define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */ +#define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */ +#define RCC_DIVENR_IC10EN_Pos (9UL) +#define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */ +#define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */ +#define RCC_DIVENR_IC11EN_Pos (10UL) +#define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */ +#define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */ +#define RCC_DIVENR_IC12EN_Pos (11UL) +#define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */ +#define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */ +#define RCC_DIVENR_IC13EN_Pos (12UL) +#define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */ +#define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */ +#define RCC_DIVENR_IC14EN_Pos (13UL) +#define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */ +#define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */ +#define RCC_DIVENR_IC15EN_Pos (14UL) +#define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */ +#define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */ +#define RCC_DIVENR_IC16EN_Pos (15UL) +#define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */ +#define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */ +#define RCC_DIVENR_IC17EN_Pos (16UL) +#define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */ +#define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */ +#define RCC_DIVENR_IC18EN_Pos (17UL) +#define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */ +#define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */ +#define RCC_DIVENR_IC19EN_Pos (18UL) +#define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */ +#define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */ +#define RCC_DIVENR_IC20EN_Pos (19UL) +#define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */ +#define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */ + +/****************** Bit definition for RCC_BUSENR register ******************/ +#define RCC_BUSENR_ACLKNEN_Pos (0UL) +#define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */ +#define RCC_BUSENR_ACLKNCEN_Pos (1UL) +#define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */ +#define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */ +#define RCC_BUSENR_AHBMEN_Pos (2UL) +#define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */ +#define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */ +#define RCC_BUSENR_AHB1EN_Pos (3UL) +#define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */ +#define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */ +#define RCC_BUSENR_AHB2EN_Pos (4UL) +#define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */ +#define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */ +#define RCC_BUSENR_AHB3EN_Pos (5UL) +#define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */ +#define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */ +#define RCC_BUSENR_AHB4EN_Pos (6UL) +#define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */ +#define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */ +#define RCC_BUSENR_AHB5EN_Pos (7UL) +#define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */ +#define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */ +#define RCC_BUSENR_APB1EN_Pos (8UL) +#define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */ +#define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */ +#define RCC_BUSENR_APB2EN_Pos (9UL) +#define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */ +#define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */ +#define RCC_BUSENR_APB3EN_Pos (10UL) +#define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */ +#define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */ +#define RCC_BUSENR_APB4EN_Pos (11UL) +#define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */ +#define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */ +#define RCC_BUSENR_APB5EN_Pos (12UL) +#define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */ +#define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENR register ******************/ +#define RCC_MISCENR_DBGEN_Pos (0UL) +#define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */ +#define RCC_MISCENR_MCO1EN_Pos (1UL) +#define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */ +#define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */ +#define RCC_MISCENR_MCO2EN_Pos (2UL) +#define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */ +#define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */ +#define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3UL) +#define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENR_PEREN_Pos (6UL) +#define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */ +#define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */ + +/****************** Bit definition for RCC_MEMENR register ******************/ +#define RCC_MEMENR_AXISRAM3EN_Pos (0UL) +#define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */ +#define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENR_AXISRAM4EN_Pos (1UL) +#define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */ +#define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENR_AXISRAM5EN_Pos (2UL) +#define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */ +#define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENR_AXISRAM6EN_Pos (3UL) +#define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */ +#define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENR_AHBSRAM1EN_Pos (4UL) +#define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */ +#define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENR_AHBSRAM2EN_Pos (5UL) +#define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */ +#define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENR_BKPSRAMEN_Pos (6UL) +#define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENR_AXISRAM1EN_Pos (7UL) +#define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */ +#define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENR_AXISRAM2EN_Pos (8UL) +#define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */ +#define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENR_FLEXRAMEN_Pos (9UL) +#define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENR_CACHEAXIRAMEN_Pos (10UL) +#define RCC_MEMENR_CACHEAXIRAMEN_Msk (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */ +#define RCC_MEMENR_CACHEAXIRAMEN RCC_MEMENR_CACHEAXIRAMEN_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENR_VENCRAMEN_Pos (11UL) +#define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMENR_BOOTROMEN_Pos (12UL) +#define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENR register ******************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4UL) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENR_ADC12EN_Pos (5UL) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENR register ******************/ +#define RCC_AHB2ENR_RAMCFGEN_Pos (12UL) +#define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENR_MDF1EN_Pos (16UL) +#define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENR_ADF1EN_Pos (17UL) +#define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENR register ******************/ +#define RCC_AHB3ENR_RNGEN_Pos (0UL) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */ +#define RCC_AHB3ENR_HASHEN_Pos (1UL) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */ +#define RCC_AHB3ENR_PKAEN_Pos (8UL) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */ +#define RCC_AHB3ENR_RIFSCEN_Pos (9UL) +#define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENR_IACEN_Pos (10UL) +#define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */ +#define RCC_AHB3ENR_RISAFEN_Pos (14UL) +#define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENR register ******************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0UL) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENR_GPIOBEN_Pos (1UL) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENR_GPIOCEN_Pos (2UL) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENR_GPIODEN_Pos (3UL) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENR_GPIOEEN_Pos (4UL) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENR_GPIOFEN_Pos (5UL) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENR_GPIOGEN_Pos (6UL) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENR_GPIOHEN_Pos (7UL) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENR_GPIONEN_Pos (13UL) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENR_GPIOOEN_Pos (14UL) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENR_GPIOPEN_Pos (15UL) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENR_GPIOQEN_Pos (16UL) +#define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENR_PWREN_Pos (18UL) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */ +#define RCC_AHB4ENR_CRCEN_Pos (19UL) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENR register ******************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0UL) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENR_DMA2DEN_Pos (1UL) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENR_JPEGEN_Pos (3UL) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */ +#define RCC_AHB5ENR_FMCEN_Pos (4UL) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */ +#define RCC_AHB5ENR_XSPI1EN_Pos (5UL) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENR_PSSIEN_Pos (6UL) +#define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */ +#define RCC_AHB5ENR_SDMMC2EN_Pos (7UL) +#define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENR_SDMMC1EN_Pos (8UL) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENR_XSPI2EN_Pos (12UL) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENR_XSPIMEN_Pos (13UL) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENR_XSPI3EN_Pos (17UL) +#define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENR_GFXMMUEN_Pos (19UL) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENR_GPU2DEN_Pos (20UL) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENR_ETH1MACEN_Pos (22UL) +#define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENR_ETH1TXEN_Pos (23UL) +#define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENR_ETH1RXEN_Pos (24UL) +#define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENR_ETH1EN_Pos (25UL) +#define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENR_OTG1EN_Pos (26UL) +#define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENR_OTGPHY1EN_Pos (27UL) +#define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENR_OTGPHY2EN_Pos (28UL) +#define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENR_OTG2EN_Pos (29UL) +#define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENR_CACHEAXIEN_Pos (30UL) +#define RCC_AHB5ENR_CACHEAXIEN_Msk (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENR_CACHEAXIEN RCC_AHB5ENR_CACHEAXIEN_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENR_NPUEN_Pos (31UL) +#define RCC_AHB5ENR_NPUEN_Msk (0x1UL << RCC_AHB5ENR_NPUEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENR_NPUEN RCC_AHB5ENR_NPUEN_Msk /*!< NPU enable */ + +/***************** Bit definition for RCC_APB1ENR1 register *****************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0UL) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */ +#define RCC_APB1ENR1_TIM3EN_Pos (1UL) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */ +#define RCC_APB1ENR1_TIM4EN_Pos (2UL) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */ +#define RCC_APB1ENR1_TIM5EN_Pos (3UL) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */ +#define RCC_APB1ENR1_TIM6EN_Pos (4UL) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */ +#define RCC_APB1ENR1_TIM7EN_Pos (5UL) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */ +#define RCC_APB1ENR1_TIM12EN_Pos (6UL) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */ +#define RCC_APB1ENR1_TIM13EN_Pos (7UL) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */ +#define RCC_APB1ENR1_TIM14EN_Pos (8UL) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */ +#define RCC_APB1ENR1_LPTIM1EN_Pos (9UL) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENR1_WWDGEN_Pos (11UL) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */ +#define RCC_APB1ENR1_TIM10EN_Pos (12UL) +#define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */ +#define RCC_APB1ENR1_TIM11EN_Pos (13UL) +#define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */ +#define RCC_APB1ENR1_SPI2EN_Pos (14UL) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */ +#define RCC_APB1ENR1_SPI3EN_Pos (15UL) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */ +#define RCC_APB1ENR1_SPDIFRX1EN_Pos (16UL) +#define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENR1_USART2EN_Pos (17UL) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */ +#define RCC_APB1ENR1_USART3EN_Pos (18UL) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */ +#define RCC_APB1ENR1_UART4EN_Pos (19UL) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */ +#define RCC_APB1ENR1_UART5EN_Pos (20UL) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */ +#define RCC_APB1ENR1_I2C1EN_Pos (21UL) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */ +#define RCC_APB1ENR1_I2C2EN_Pos (22UL) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */ +#define RCC_APB1ENR1_I2C3EN_Pos (23UL) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */ +#define RCC_APB1ENR1_I3C1EN_Pos (24UL) +#define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */ +#define RCC_APB1ENR1_I3C2EN_Pos (25UL) +#define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */ +#define RCC_APB1ENR1_UART7EN_Pos (30UL) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */ +#define RCC_APB1ENR1_UART8EN_Pos (31UL) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */ + +/***************** Bit definition for RCC_APB1ENR2 register *****************/ +#define RCC_APB1ENR2_MDIOSEN_Pos (5UL) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */ +#define RCC_APB1ENR2_FDCANEN_Pos (8UL) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */ +#define RCC_APB1ENR2_UCPD1EN_Pos (18UL) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENR register ******************/ +#define RCC_APB2ENR_TIM1EN_Pos (0UL) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */ +#define RCC_APB2ENR_TIM8EN_Pos (1UL) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */ +#define RCC_APB2ENR_USART1EN_Pos (4UL) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */ +#define RCC_APB2ENR_USART6EN_Pos (5UL) +#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */ +#define RCC_APB2ENR_UART9EN_Pos (6UL) +#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */ +#define RCC_APB2ENR_USART10EN_Pos (7UL) +#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12UL) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */ +#define RCC_APB2ENR_SPI4EN_Pos (13UL) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */ +#define RCC_APB2ENR_TIM18EN_Pos (15UL) +#define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16UL) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17UL) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18UL) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */ +#define RCC_APB2ENR_TIM9EN_Pos (19UL) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */ +#define RCC_APB2ENR_SPI5EN_Pos (20UL) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */ +#define RCC_APB2ENR_SAI1EN_Pos (21UL) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */ +#define RCC_APB2ENR_SAI2EN_Pos (22UL) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENR register ******************/ +#define RCC_APB3ENR_DFTEN_Pos (2UL) +#define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */ + +/***************** Bit definition for RCC_APB4ENR1 register *****************/ +#define RCC_APB4ENR1_HDPEN_Pos (2UL) +#define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */ +#define RCC_APB4ENR1_LPUART1EN_Pos (3UL) +#define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENR1_SPI6EN_Pos (5UL) +#define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */ +#define RCC_APB4ENR1_I2C4EN_Pos (7UL) +#define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */ +#define RCC_APB4ENR1_LPTIM2EN_Pos (9UL) +#define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENR1_LPTIM3EN_Pos (10UL) +#define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENR1_LPTIM4EN_Pos (11UL) +#define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENR1_LPTIM5EN_Pos (12UL) +#define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENR1_VREFBUFEN_Pos (15UL) +#define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENR1_RTCEN_Pos (16UL) +#define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */ +#define RCC_APB4ENR1_RTCAPBEN_Pos (17UL) +#define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */ + +/***************** Bit definition for RCC_APB4ENR2 register *****************/ +#define RCC_APB4ENR2_SYSCFGEN_Pos (0UL) +#define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENR2_BSECEN_Pos (1UL) +#define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */ +#define RCC_APB4ENR2_DTSEN_Pos (2UL) +#define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENR register ******************/ +#define RCC_APB5ENR_LTDCEN_Pos (1UL) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */ +#define RCC_APB5ENR_DCMIPPEN_Pos (2UL) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENR_GFXTIMEN_Pos (4UL) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENR_VENCEN_Pos (5UL) +#define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */ +#define RCC_APB5ENR_CSIEN_Pos (6UL) +#define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */ + +/***************** Bit definition for RCC_BUSLPENR register *****************/ +#define RCC_BUSLPENR_ACLKNLPEN_Pos (0UL) +#define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENR_ACLKNCLPEN_Pos (1UL) +#define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */ +#define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENR register *****************/ +#define RCC_MISCLPENR_DBGLPEN_Pos (0UL) +#define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3UL) +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENR_PERLPEN_Pos (6UL) +#define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMLPENR register *****************/ +#define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0UL) +#define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1UL) +#define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2UL) +#define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3UL) +#define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4UL) +#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5UL) +#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6UL) +#define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7UL) +#define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8UL) +#define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9UL) +#define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos (10UL) +#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENR_CACHEAXIRAMLPEN RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMLPENR_VENCRAMLPEN_Pos (11UL) +#define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENR_BOOTROMLPEN_Pos (12UL) +#define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENR register *****************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4UL) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5UL) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENR register *****************/ +#define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12UL) +#define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENR_MDF1LPEN_Pos (16UL) +#define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENR_ADF1LPEN_Pos (17UL) +#define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENR register *****************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0UL) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */ +#define RCC_AHB3LPENR_HASHLPEN_Pos (1UL) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */ +#define RCC_AHB3LPENR_PKALPEN_Pos (8UL) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */ +#define RCC_AHB3LPENR_RIFSCLPEN_Pos (9UL) +#define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */ +#define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENR_IACLPEN_Pos (10UL) +#define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */ +#define RCC_AHB3LPENR_RISAFLPEN_Pos (14UL) +#define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENR register *****************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0UL) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1UL) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2UL) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3UL) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4UL) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5UL) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6UL) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7UL) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13UL) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14UL) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15UL) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENR_GPIOQLPEN_Pos (16UL) +#define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */ +#define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENR_PWRLPEN_Pos (18UL) +#define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */ +#define RCC_AHB4LPENR_CRCLPEN_Pos (19UL) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENR register *****************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0UL) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1UL) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3UL) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENR_FMCLPEN_Pos (4UL) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */ +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5UL) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENR_PSSILPEN_Pos (6UL) +#define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7UL) +#define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8UL) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12UL) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (13UL) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENR_XSPI3LPEN_Pos (17UL) +#define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19UL) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20UL) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22UL) +#define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23UL) +#define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24UL) +#define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENR_ETH1LPEN_Pos (25UL) +#define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENR_OTG1LPEN_Pos (26UL) +#define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27UL) +#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28UL) +#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENR_OTG2LPEN_Pos (29UL) +#define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */ +#define RCC_AHB5LPENR_CACHEAXILPEN_Pos (30UL) +#define RCC_AHB5LPENR_CACHEAXILPEN_Msk (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_CACHEAXILPEN RCC_AHB5LPENR_CACHEAXILPEN_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5LPENR_NPULPEN_Pos (31UL) +#define RCC_AHB5LPENR_NPULPEN_Msk (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_NPULPEN RCC_AHB5LPENR_NPULPEN_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1LPENR1 register ****************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0UL) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1UL) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2UL) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3UL) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4UL) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5UL) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6UL) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7UL) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8UL) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9UL) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11UL) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */ +#define RCC_APB1LPENR1_TIM10LPEN_Pos (12UL) +#define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENR1_TIM11LPEN_Pos (13UL) +#define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14UL) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15UL) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16UL) +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENR1_USART2LPEN_Pos (17UL) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */ +#define RCC_APB1LPENR1_USART3LPEN_Pos (18UL) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */ +#define RCC_APB1LPENR1_UART4LPEN_Pos (19UL) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */ +#define RCC_APB1LPENR1_UART5LPEN_Pos (20UL) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */ +#define RCC_APB1LPENR1_I2C1LPEN_Pos (21UL) +#define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22UL) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23UL) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENR1_I3C1LPEN_Pos (24UL) +#define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */ +#define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENR1_I3C2LPEN_Pos (25UL) +#define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */ +#define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENR1_UART7LPEN_Pos (30UL) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */ +#define RCC_APB1LPENR1_UART8LPEN_Pos (31UL) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1LPENR2 register ****************/ +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5UL) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */ +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8UL) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */ +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (18UL) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */ + +/**************** Bit definition for RCC_APB2LPENR register *****************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0UL) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (1UL) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENR_USART1LPEN_Pos (4UL) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */ +#define RCC_APB2LPENR_USART6LPEN_Pos (5UL) +#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */ +#define RCC_APB2LPENR_UART9LPEN_Pos (6UL) +#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */ +#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */ +#define RCC_APB2LPENR_USART10LPEN_Pos (7UL) +#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12UL) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENR_SPI4LPEN_Pos (13UL) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENR_TIM18LPEN_Pos (15UL) +#define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16UL) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17UL) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18UL) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENR_TIM9LPEN_Pos (19UL) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENR_SPI5LPEN_Pos (20UL) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENR_SAI1LPEN_Pos (21UL) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENR_SAI2LPEN_Pos (22UL) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENR register *****************/ +#define RCC_APB3LPENR_DFTLPEN_Pos (2UL) +#define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4LPENR1 register ****************/ +#define RCC_APB4LPENR1_HDPLPEN_Pos (2UL) +#define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */ +#define RCC_APB4LPENR1_LPUART1LPEN_Pos (3UL) +#define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENR1_SPI6LPEN_Pos (5UL) +#define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENR1_I2C4LPEN_Pos (7UL) +#define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */ +#define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9UL) +#define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10UL) +#define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11UL) +#define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12UL) +#define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15UL) +#define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENR1_RTCLPEN_Pos (16UL) +#define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */ +#define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17UL) +#define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4LPENR2 register ****************/ +#define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0UL) +#define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENR2_BSECLPEN_Pos (1UL) +#define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */ +#define RCC_APB4LPENR2_DTSLPEN_Pos (2UL) +#define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENR register *****************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1UL) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2UL) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4UL) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENR_VENCLPEN_Pos (5UL) +#define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */ +#define RCC_APB5LPENR_CSILPEN_Pos (6UL) +#define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */ + +/******************* Bit definition for RCC_RDCR register *******************/ +#define RCC_RDCR_MRD_Pos (16UL) +#define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */ + +/***************** Bit definition for RCC_SECCFGR0 register *****************/ +#define RCC_SECCFGR0_LSISEC_Pos (0UL) +#define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */ +#define RCC_SECCFGR0_LSESEC_Pos (1UL) +#define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */ +#define RCC_SECCFGR0_MSISEC_Pos (2UL) +#define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSISEC_Pos (3UL) +#define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSESEC_Pos (4UL) +#define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR0 register *****************/ +#define RCC_PRIVCFGR0_LSIPRIV_Pos (0UL) +#define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_LSEPRIV_Pos (1UL) +#define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */ +#define RCC_PRIVCFGR0_MSIPRIV_Pos (2UL) +#define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSIPRIV_Pos (3UL) +#define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSEPRIV_Pos (4UL) +#define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR0 register *****************/ +#define RCC_LOCKCFGR0_LSILOCK_Pos (0UL) +#define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_LSELOCK_Pos (1UL) +#define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */ +#define RCC_LOCKCFGR0_MSILOCK_Pos (2UL) +#define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSILOCK_Pos (3UL) +#define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSELOCK_Pos (4UL) +#define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR0 register *****************/ +#define RCC_PUBCFGR0_LSIPUB_Pos (0UL) +#define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */ +#define RCC_PUBCFGR0_LSEPUB_Pos (1UL) +#define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */ +#define RCC_PUBCFGR0_MSIPUB_Pos (2UL) +#define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSIPUB_Pos (3UL) +#define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSEPUB_Pos (4UL) +#define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_SECCFGR1 register *****************/ +#define RCC_SECCFGR1_PLL1SEC_Pos (0UL) +#define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */ +#define RCC_SECCFGR1_PLL2SEC_Pos (1UL) +#define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */ +#define RCC_SECCFGR1_PLL3SEC_Pos (2UL) +#define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */ +#define RCC_SECCFGR1_PLL4SEC_Pos (3UL) +#define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR1 register *****************/ +#define RCC_PRIVCFGR1_PLL1PRIV_Pos (0UL) +#define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */ +#define RCC_PRIVCFGR1_PLL2PRIV_Pos (1UL) +#define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */ +#define RCC_PRIVCFGR1_PLL3PRIV_Pos (2UL) +#define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */ +#define RCC_PRIVCFGR1_PLL4PRIV_Pos (3UL) +#define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR1 register *****************/ +#define RCC_LOCKCFGR1_PLL1LOCK_Pos (0UL) +#define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */ +#define RCC_LOCKCFGR1_PLL2LOCK_Pos (1UL) +#define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */ +#define RCC_LOCKCFGR1_PLL3LOCK_Pos (2UL) +#define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */ +#define RCC_LOCKCFGR1_PLL4LOCK_Pos (3UL) +#define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR1 register *****************/ +#define RCC_PUBCFGR1_PLL1PUB_Pos (0UL) +#define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */ +#define RCC_PUBCFGR1_PLL2PUB_Pos (1UL) +#define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */ +#define RCC_PUBCFGR1_PLL3PUB_Pos (2UL) +#define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */ +#define RCC_PUBCFGR1_PLL4PUB_Pos (3UL) +#define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_SECCFGR2 register *****************/ +#define RCC_SECCFGR2_IC1SEC_Pos (0UL) +#define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */ +#define RCC_SECCFGR2_IC2SEC_Pos (1UL) +#define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */ +#define RCC_SECCFGR2_IC3SEC_Pos (2UL) +#define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */ +#define RCC_SECCFGR2_IC4SEC_Pos (3UL) +#define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */ +#define RCC_SECCFGR2_IC5SEC_Pos (4UL) +#define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */ +#define RCC_SECCFGR2_IC6SEC_Pos (5UL) +#define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */ +#define RCC_SECCFGR2_IC7SEC_Pos (6UL) +#define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */ +#define RCC_SECCFGR2_IC8SEC_Pos (7UL) +#define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */ +#define RCC_SECCFGR2_IC9SEC_Pos (8UL) +#define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */ +#define RCC_SECCFGR2_IC10SEC_Pos (9UL) +#define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */ +#define RCC_SECCFGR2_IC11SEC_Pos (10UL) +#define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */ +#define RCC_SECCFGR2_IC12SEC_Pos (11UL) +#define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */ +#define RCC_SECCFGR2_IC13SEC_Pos (12UL) +#define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */ +#define RCC_SECCFGR2_IC14SEC_Pos (13UL) +#define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */ +#define RCC_SECCFGR2_IC15SEC_Pos (14UL) +#define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */ +#define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */ +#define RCC_SECCFGR2_IC16SEC_Pos (15UL) +#define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */ +#define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */ +#define RCC_SECCFGR2_IC17SEC_Pos (16UL) +#define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */ +#define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */ +#define RCC_SECCFGR2_IC18SEC_Pos (17UL) +#define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */ +#define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */ +#define RCC_SECCFGR2_IC19SEC_Pos (18UL) +#define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */ +#define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */ +#define RCC_SECCFGR2_IC20SEC_Pos (19UL) +#define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */ +#define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR2 register *****************/ +#define RCC_PRIVCFGR2_IC1PRIV_Pos (0UL) +#define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */ +#define RCC_PRIVCFGR2_IC2PRIV_Pos (1UL) +#define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */ +#define RCC_PRIVCFGR2_IC3PRIV_Pos (2UL) +#define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */ +#define RCC_PRIVCFGR2_IC4PRIV_Pos (3UL) +#define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */ +#define RCC_PRIVCFGR2_IC5PRIV_Pos (4UL) +#define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */ +#define RCC_PRIVCFGR2_IC6PRIV_Pos (5UL) +#define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */ +#define RCC_PRIVCFGR2_IC7PRIV_Pos (6UL) +#define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */ +#define RCC_PRIVCFGR2_IC8PRIV_Pos (7UL) +#define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */ +#define RCC_PRIVCFGR2_IC9PRIV_Pos (8UL) +#define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */ +#define RCC_PRIVCFGR2_IC10PRIV_Pos (9UL) +#define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */ +#define RCC_PRIVCFGR2_IC11PRIV_Pos (10UL) +#define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */ +#define RCC_PRIVCFGR2_IC12PRIV_Pos (11UL) +#define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */ +#define RCC_PRIVCFGR2_IC13PRIV_Pos (12UL) +#define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */ +#define RCC_PRIVCFGR2_IC14PRIV_Pos (13UL) +#define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */ +#define RCC_PRIVCFGR2_IC15PRIV_Pos (14UL) +#define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */ +#define RCC_PRIVCFGR2_IC16PRIV_Pos (15UL) +#define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */ +#define RCC_PRIVCFGR2_IC17PRIV_Pos (16UL) +#define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */ +#define RCC_PRIVCFGR2_IC18PRIV_Pos (17UL) +#define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */ +#define RCC_PRIVCFGR2_IC19PRIV_Pos (18UL) +#define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */ +#define RCC_PRIVCFGR2_IC20PRIV_Pos (19UL) +#define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR2 register *****************/ +#define RCC_LOCKCFGR2_IC1LOCK_Pos (0UL) +#define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */ +#define RCC_LOCKCFGR2_IC2LOCK_Pos (1UL) +#define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */ +#define RCC_LOCKCFGR2_IC3LOCK_Pos (2UL) +#define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */ +#define RCC_LOCKCFGR2_IC4LOCK_Pos (3UL) +#define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */ +#define RCC_LOCKCFGR2_IC5LOCK_Pos (4UL) +#define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */ +#define RCC_LOCKCFGR2_IC6LOCK_Pos (5UL) +#define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */ +#define RCC_LOCKCFGR2_IC7LOCK_Pos (6UL) +#define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */ +#define RCC_LOCKCFGR2_IC8LOCK_Pos (7UL) +#define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */ +#define RCC_LOCKCFGR2_IC9LOCK_Pos (8UL) +#define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */ +#define RCC_LOCKCFGR2_IC10LOCK_Pos (9UL) +#define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */ +#define RCC_LOCKCFGR2_IC11LOCK_Pos (10UL) +#define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */ +#define RCC_LOCKCFGR2_IC12LOCK_Pos (11UL) +#define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */ +#define RCC_LOCKCFGR2_IC13LOCK_Pos (12UL) +#define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */ +#define RCC_LOCKCFGR2_IC14LOCK_Pos (13UL) +#define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */ +#define RCC_LOCKCFGR2_IC15LOCK_Pos (14UL) +#define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */ +#define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */ +#define RCC_LOCKCFGR2_IC16LOCK_Pos (15UL) +#define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */ +#define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */ +#define RCC_LOCKCFGR2_IC17LOCK_Pos (16UL) +#define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */ +#define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */ +#define RCC_LOCKCFGR2_IC18LOCK_Pos (17UL) +#define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */ +#define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */ +#define RCC_LOCKCFGR2_IC19LOCK_Pos (18UL) +#define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */ +#define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */ +#define RCC_LOCKCFGR2_IC20LOCK_Pos (19UL) +#define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */ +#define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR2 register *****************/ +#define RCC_PUBCFGR2_IC1PUB_Pos (0UL) +#define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */ +#define RCC_PUBCFGR2_IC2PUB_Pos (1UL) +#define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */ +#define RCC_PUBCFGR2_IC3PUB_Pos (2UL) +#define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */ +#define RCC_PUBCFGR2_IC4PUB_Pos (3UL) +#define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */ +#define RCC_PUBCFGR2_IC5PUB_Pos (4UL) +#define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */ +#define RCC_PUBCFGR2_IC6PUB_Pos (5UL) +#define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */ +#define RCC_PUBCFGR2_IC7PUB_Pos (6UL) +#define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */ +#define RCC_PUBCFGR2_IC8PUB_Pos (7UL) +#define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */ +#define RCC_PUBCFGR2_IC9PUB_Pos (8UL) +#define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */ +#define RCC_PUBCFGR2_IC10PUB_Pos (9UL) +#define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */ +#define RCC_PUBCFGR2_IC11PUB_Pos (10UL) +#define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */ +#define RCC_PUBCFGR2_IC12PUB_Pos (11UL) +#define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */ +#define RCC_PUBCFGR2_IC13PUB_Pos (12UL) +#define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */ +#define RCC_PUBCFGR2_IC14PUB_Pos (13UL) +#define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */ +#define RCC_PUBCFGR2_IC15PUB_Pos (14UL) +#define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */ +#define RCC_PUBCFGR2_IC16PUB_Pos (15UL) +#define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */ +#define RCC_PUBCFGR2_IC17PUB_Pos (16UL) +#define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */ +#define RCC_PUBCFGR2_IC18PUB_Pos (17UL) +#define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */ +#define RCC_PUBCFGR2_IC19PUB_Pos (18UL) +#define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */ +#define RCC_PUBCFGR2_IC20PUB_Pos (19UL) +#define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_SECCFGR3 register *****************/ +#define RCC_SECCFGR3_MODSEC_Pos (0UL) +#define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */ +#define RCC_SECCFGR3_SYSSEC_Pos (1UL) +#define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */ +#define RCC_SECCFGR3_BUSSEC_Pos (2UL) +#define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */ +#define RCC_SECCFGR3_PERSEC_Pos (3UL) +#define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */ +#define RCC_SECCFGR3_INTSEC_Pos (4UL) +#define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */ +#define RCC_SECCFGR3_RSTSEC_Pos (5UL) +#define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR3 register *****************/ +#define RCC_PRIVCFGR3_MODPRIV_Pos (0UL) +#define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */ +#define RCC_PRIVCFGR3_SYSPRIV_Pos (1UL) +#define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */ +#define RCC_PRIVCFGR3_BUSPRIV_Pos (2UL) +#define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */ +#define RCC_PRIVCFGR3_PERPRIV_Pos (3UL) +#define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */ +#define RCC_PRIVCFGR3_INTPRIV_Pos (4UL) +#define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */ +#define RCC_PRIVCFGR3_RSTPRIV_Pos (5UL) +#define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR3 register *****************/ +#define RCC_LOCKCFGR3_MODLOCK_Pos (0UL) +#define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */ +#define RCC_LOCKCFGR3_SYSLOCK_Pos (1UL) +#define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */ +#define RCC_LOCKCFGR3_BUSLOCK_Pos (2UL) +#define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */ +#define RCC_LOCKCFGR3_PERLOCK_Pos (3UL) +#define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */ +#define RCC_LOCKCFGR3_INTLOCK_Pos (4UL) +#define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */ +#define RCC_LOCKCFGR3_RSTLOCK_Pos (5UL) +#define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR3 register *****************/ +#define RCC_PUBCFGR3_MODPUB_Pos (0UL) +#define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */ +#define RCC_PUBCFGR3_SYSPUB_Pos (1UL) +#define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */ +#define RCC_PUBCFGR3_BUSPUB_Pos (2UL) +#define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */ +#define RCC_PUBCFGR3_PERPUB_Pos (3UL) +#define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */ +#define RCC_PUBCFGR3_INTPUB_Pos (4UL) +#define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */ +#define RCC_PUBCFGR3_RSTPUB_Pos (5UL) +#define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */ + +/***************** Bit definition for RCC_SECCFGR4 register *****************/ +#define RCC_SECCFGR4_ACLKNSEC_Pos (0UL) +#define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */ +#define RCC_SECCFGR4_ACLKNCSEC_Pos (1UL) +#define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */ +#define RCC_SECCFGR4_AHBMSEC_Pos (2UL) +#define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */ +#define RCC_SECCFGR4_AHB1SEC_Pos (3UL) +#define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */ +#define RCC_SECCFGR4_AHB2SEC_Pos (4UL) +#define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */ +#define RCC_SECCFGR4_AHB3SEC_Pos (5UL) +#define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */ +#define RCC_SECCFGR4_AHB4SEC_Pos (6UL) +#define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */ +#define RCC_SECCFGR4_AHB5SEC_Pos (7UL) +#define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */ +#define RCC_SECCFGR4_APB1SEC_Pos (8UL) +#define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */ +#define RCC_SECCFGR4_APB2SEC_Pos (9UL) +#define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */ +#define RCC_SECCFGR4_APB3SEC_Pos (10UL) +#define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */ +#define RCC_SECCFGR4_APB4SEC_Pos (11UL) +#define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */ +#define RCC_SECCFGR4_APB5SEC_Pos (12UL) +#define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */ +#define RCC_SECCFGR4_NOCSEC_Pos (13UL) +#define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR4 register *****************/ +#define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0UL) +#define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */ +#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1UL) +#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */ +#define RCC_PRIVCFGR4_AHBMPRIV_Pos (2UL) +#define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */ +#define RCC_PRIVCFGR4_AHB1PRIV_Pos (3UL) +#define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB2PRIV_Pos (4UL) +#define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB3PRIV_Pos (5UL) +#define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB4PRIV_Pos (6UL) +#define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB5PRIV_Pos (7UL) +#define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */ +#define RCC_PRIVCFGR4_APB1PRIV_Pos (8UL) +#define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */ +#define RCC_PRIVCFGR4_APB2PRIV_Pos (9UL) +#define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */ +#define RCC_PRIVCFGR4_APB3PRIV_Pos (10UL) +#define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */ +#define RCC_PRIVCFGR4_APB4PRIV_Pos (11UL) +#define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */ +#define RCC_PRIVCFGR4_APB5PRIV_Pos (12UL) +#define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */ +#define RCC_PRIVCFGR4_NOCPRIV_Pos (13UL) +#define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR4 register *****************/ +#define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0UL) +#define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */ +#define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */ +#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1UL) +#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */ +#define RCC_LOCKCFGR4_AHBMLOCK_Pos (2UL) +#define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */ +#define RCC_LOCKCFGR4_AHB1LOCK_Pos (3UL) +#define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB2LOCK_Pos (4UL) +#define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB3LOCK_Pos (5UL) +#define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB4LOCK_Pos (6UL) +#define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB5LOCK_Pos (7UL) +#define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */ +#define RCC_LOCKCFGR4_APB1LOCK_Pos (8UL) +#define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */ +#define RCC_LOCKCFGR4_APB2LOCK_Pos (9UL) +#define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */ +#define RCC_LOCKCFGR4_APB3LOCK_Pos (10UL) +#define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */ +#define RCC_LOCKCFGR4_APB4LOCK_Pos (11UL) +#define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */ +#define RCC_LOCKCFGR4_APB5LOCK_Pos (12UL) +#define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */ +#define RCC_LOCKCFGR4_NOCLOCK_Pos (13UL) +#define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR4 register *****************/ +#define RCC_PUBCFGR4_ACLKNPUB_Pos (0UL) +#define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */ +#define RCC_PUBCFGR4_ACLKNCPUB_Pos (1UL) +#define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */ +#define RCC_PUBCFGR4_AHBMPUB_Pos (2UL) +#define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */ +#define RCC_PUBCFGR4_AHB1PUB_Pos (3UL) +#define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */ +#define RCC_PUBCFGR4_AHB2PUB_Pos (4UL) +#define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */ +#define RCC_PUBCFGR4_AHB3PUB_Pos (5UL) +#define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */ +#define RCC_PUBCFGR4_AHB4PUB_Pos (6UL) +#define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */ +#define RCC_PUBCFGR4_AHB5PUB_Pos (7UL) +#define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */ +#define RCC_PUBCFGR4_APB1PUB_Pos (8UL) +#define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */ +#define RCC_PUBCFGR4_APB2PUB_Pos (9UL) +#define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */ +#define RCC_PUBCFGR4_APB3PUB_Pos (10UL) +#define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */ +#define RCC_PUBCFGR4_APB4PUB_Pos (11UL) +#define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */ +#define RCC_PUBCFGR4_APB5PUB_Pos (12UL) +#define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */ +#define RCC_PUBCFGR4_NOCPUB_Pos (13UL) +#define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR5 register *****************/ +#define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0UL) +#define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1UL) +#define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2UL) +#define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3UL) +#define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4UL) +#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5UL) +#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6UL) +#define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */ +#define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7UL) +#define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8UL) +#define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9UL) +#define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */ +#define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */ +#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos (10UL) +#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR5_CACHEAXIRAMPUB RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk /*!< Public protection of CACHEAXIRAM bus configuration bits */ +#define RCC_PUBCFGR5_VENCRAMPUB_Pos (11UL) +#define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */ +#define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSIONS_Pos (0UL) +#define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */ +#define RCC_CSR_LSEONS_Pos (1UL) +#define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */ +#define RCC_CSR_MSIONS_Pos (2UL) +#define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */ +#define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */ +#define RCC_CSR_HSIONS_Pos (3UL) +#define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */ +#define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */ +#define RCC_CSR_HSEONS_Pos (4UL) +#define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */ +#define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */ +#define RCC_CSR_PLL1ONS_Pos (8UL) +#define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */ +#define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */ +#define RCC_CSR_PLL2ONS_Pos (9UL) +#define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */ +#define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */ +#define RCC_CSR_PLL3ONS_Pos (10UL) +#define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */ +#define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */ +#define RCC_CSR_PLL4ONS_Pos (11UL) +#define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */ +#define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCSR register ******************/ +#define RCC_STOPCSR_MSISTOPENS_Pos (0UL) +#define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */ +#define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCSR_HSISTOPENS_Pos (1UL) +#define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */ +#define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTSR register *****************/ +#define RCC_MISCRSTSR_DBGRSTS_Pos (0UL) +#define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4UL) +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5UL) +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7UL) +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8UL) +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTSR register *****************/ +#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0UL) +#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1UL) +#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2UL) +#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3UL) +#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4UL) +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5UL) +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7UL) +#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8UL) +#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9UL) +#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos (10UL) +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11UL) +#define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12UL) +#define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTSR register *****************/ +#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4UL) +#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTSR_ADC12RSTS_Pos (5UL) +#define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTSR register *****************/ +#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12UL) +#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTSR_MDF1RSTS_Pos (16UL) +#define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTSR_ADF1RSTS_Pos (17UL) +#define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTSR register *****************/ +#define RCC_AHB3RSTSR_RNGRSTS_Pos (0UL) +#define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */ +#define RCC_AHB3RSTSR_HASHRSTS_Pos (1UL) +#define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */ +#define RCC_AHB3RSTSR_PKARSTS_Pos (8UL) +#define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */ +#define RCC_AHB3RSTSR_IACRSTS_Pos (10UL) +#define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTSR register *****************/ +#define RCC_AHB4RSTSR_GPIOARSTS_Pos (0UL) +#define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1UL) +#define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2UL) +#define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTSR_GPIODRSTS_Pos (3UL) +#define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTSR_GPIOERSTS_Pos (4UL) +#define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5UL) +#define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6UL) +#define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7UL) +#define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTSR_GPIONRSTS_Pos (13UL) +#define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTSR_GPIOORSTS_Pos (14UL) +#define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15UL) +#define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16UL) +#define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTSR_PWRRSTS_Pos (18UL) +#define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */ +#define RCC_AHB4RSTSR_CRCRSTS_Pos (19UL) +#define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTSR register *****************/ +#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0UL) +#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1UL) +#define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTSR_JPEGRSTS_Pos (3UL) +#define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTSR_FMCRSTS_Pos (4UL) +#define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */ +#define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5UL) +#define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTSR_PSSIRSTS_Pos (6UL) +#define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7UL) +#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8UL) +#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12UL) +#define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13UL) +#define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17UL) +#define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19UL) +#define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20UL) +#define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23UL) +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24UL) +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTSR_ETH1RSTS_Pos (25UL) +#define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTSR_OTG1RSTS_Pos (26UL) +#define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27UL) +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28UL) +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTSR_OTG2RSTS_Pos (29UL) +#define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos (30UL) +#define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTSR_CACHEAXIRSTS RCC_AHB5RSTSR_CACHEAXIRSTS_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTSR_NPURSTS_Pos (31UL) +#define RCC_AHB5RSTSR_NPURSTS_Msk (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTSR_NPURSTS RCC_AHB5RSTSR_NPURSTS_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTSR1 register ****************/ +#define RCC_APB1RSTSR1_TIM2RSTS_Pos (0UL) +#define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTSR1_TIM3RSTS_Pos (1UL) +#define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTSR1_TIM4RSTS_Pos (2UL) +#define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTSR1_TIM5RSTS_Pos (3UL) +#define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTSR1_TIM6RSTS_Pos (4UL) +#define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTSR1_TIM7RSTS_Pos (5UL) +#define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTSR1_TIM12RSTS_Pos (6UL) +#define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTSR1_TIM13RSTS_Pos (7UL) +#define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTSR1_TIM14RSTS_Pos (8UL) +#define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9UL) +#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTSR1_WWDGRSTS_Pos (11UL) +#define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */ +#define RCC_APB1RSTSR1_TIM10RSTS_Pos (12UL) +#define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTSR1_TIM11RSTS_Pos (13UL) +#define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTSR1_SPI2RSTS_Pos (14UL) +#define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTSR1_SPI3RSTS_Pos (15UL) +#define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16UL) +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTSR1_USART2RSTS_Pos (17UL) +#define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */ +#define RCC_APB1RSTSR1_USART3RSTS_Pos (18UL) +#define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */ +#define RCC_APB1RSTSR1_UART4RSTS_Pos (19UL) +#define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */ +#define RCC_APB1RSTSR1_UART5RSTS_Pos (20UL) +#define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */ +#define RCC_APB1RSTSR1_I2C1RSTS_Pos (21UL) +#define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTSR1_I2C2RSTS_Pos (22UL) +#define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTSR1_I2C3RSTS_Pos (23UL) +#define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTSR1_I3C1RSTS_Pos (24UL) +#define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTSR1_I3C2RSTS_Pos (25UL) +#define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTSR1_UART7RSTS_Pos (30UL) +#define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */ +#define RCC_APB1RSTSR1_UART8RSTS_Pos (31UL) +#define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTSR2 register ****************/ +#define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5UL) +#define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTSR2_FDCANRSTS_Pos (8UL) +#define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18UL) +#define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTSR register *****************/ +#define RCC_APB2RSTSR_TIM1RSTS_Pos (0UL) +#define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTSR_TIM8RSTS_Pos (1UL) +#define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTSR_USART1RSTS_Pos (4UL) +#define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */ +#define RCC_APB2RSTSR_USART6RSTS_Pos (5UL) +#define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */ +#define RCC_APB2RSTSR_UART9RSTS_Pos (6UL) +#define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */ +#define RCC_APB2RSTSR_USART10RSTS_Pos (7UL) +#define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */ +#define RCC_APB2RSTSR_SPI1RSTS_Pos (12UL) +#define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTSR_SPI4RSTS_Pos (13UL) +#define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTSR_TIM18RSTS_Pos (15UL) +#define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTSR_TIM15RSTS_Pos (16UL) +#define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTSR_TIM16RSTS_Pos (17UL) +#define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTSR_TIM17RSTS_Pos (18UL) +#define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTSR_TIM9RSTS_Pos (19UL) +#define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTSR_SPI5RSTS_Pos (20UL) +#define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTSR_SAI1RSTS_Pos (21UL) +#define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTSR_SAI2RSTS_Pos (22UL) +#define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTSR1 register ****************/ +#define RCC_APB4RSTSR1_HDPRSTS_Pos (2UL) +#define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */ +#define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3UL) +#define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTSR1_SPI6RSTS_Pos (5UL) +#define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTSR1_I2C4RSTS_Pos (7UL) +#define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9UL) +#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10UL) +#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11UL) +#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12UL) +#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15UL) +#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTSR1_RTCRSTS_Pos (16UL) +#define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTSR2 register ****************/ +#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0UL) +#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTSR2_DTSRSTS_Pos (2UL) +#define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTSR register *****************/ +#define RCC_APB5RSTSR_LTDCRSTS_Pos (1UL) +#define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */ +#define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2UL) +#define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4UL) +#define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTSR_VENCRSTS_Pos (5UL) +#define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */ +#define RCC_APB5RSTSR_CSIRSTS_Pos (6UL) +#define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENSR register ******************/ +#define RCC_DIVENSR_IC1ENS_Pos (0UL) +#define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */ +#define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */ +#define RCC_DIVENSR_IC2ENS_Pos (1UL) +#define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */ +#define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */ +#define RCC_DIVENSR_IC3ENS_Pos (2UL) +#define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */ +#define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */ +#define RCC_DIVENSR_IC4ENS_Pos (3UL) +#define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */ +#define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */ +#define RCC_DIVENSR_IC5ENS_Pos (4UL) +#define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */ +#define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */ +#define RCC_DIVENSR_IC6ENS_Pos (5UL) +#define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */ +#define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */ +#define RCC_DIVENSR_IC7ENS_Pos (6UL) +#define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */ +#define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */ +#define RCC_DIVENSR_IC8ENS_Pos (7UL) +#define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */ +#define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */ +#define RCC_DIVENSR_IC9ENS_Pos (8UL) +#define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */ +#define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */ +#define RCC_DIVENSR_IC10ENS_Pos (9UL) +#define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */ +#define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */ +#define RCC_DIVENSR_IC11ENS_Pos (10UL) +#define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */ +#define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */ +#define RCC_DIVENSR_IC12ENS_Pos (11UL) +#define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */ +#define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */ +#define RCC_DIVENSR_IC13ENS_Pos (12UL) +#define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */ +#define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */ +#define RCC_DIVENSR_IC14ENS_Pos (13UL) +#define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */ +#define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */ +#define RCC_DIVENSR_IC15ENS_Pos (14UL) +#define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */ +#define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */ +#define RCC_DIVENSR_IC16ENS_Pos (15UL) +#define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */ +#define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */ +#define RCC_DIVENSR_IC17ENS_Pos (16UL) +#define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */ +#define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */ +#define RCC_DIVENSR_IC18ENS_Pos (17UL) +#define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */ +#define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */ +#define RCC_DIVENSR_IC19ENS_Pos (18UL) +#define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */ +#define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */ +#define RCC_DIVENSR_IC20ENS_Pos (19UL) +#define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */ +#define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENSR register ******************/ +#define RCC_BUSENSR_ACLKNENS_Pos (0UL) +#define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */ +#define RCC_BUSENSR_ACLKNCENS_Pos (1UL) +#define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */ +#define RCC_BUSENSR_AHBMENS_Pos (2UL) +#define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */ +#define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */ +#define RCC_BUSENSR_AHB1ENS_Pos (3UL) +#define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */ +#define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */ +#define RCC_BUSENSR_AHB2ENS_Pos (4UL) +#define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */ +#define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */ +#define RCC_BUSENSR_AHB3ENS_Pos (5UL) +#define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */ +#define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */ +#define RCC_BUSENSR_AHB4ENS_Pos (6UL) +#define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */ +#define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */ +#define RCC_BUSENSR_AHB5ENS_Pos (7UL) +#define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */ +#define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */ +#define RCC_BUSENSR_APB1ENS_Pos (8UL) +#define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */ +#define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */ +#define RCC_BUSENSR_APB2ENS_Pos (9UL) +#define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */ +#define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */ +#define RCC_BUSENSR_APB3ENS_Pos (10UL) +#define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */ +#define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */ +#define RCC_BUSENSR_APB4ENS_Pos (11UL) +#define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */ +#define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */ +#define RCC_BUSENSR_APB5ENS_Pos (12UL) +#define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */ +#define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENSR register *****************/ +#define RCC_MISCENSR_DBGENS_Pos (0UL) +#define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */ +#define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */ +#define RCC_MISCENSR_MCO1ENS_Pos (1UL) +#define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */ +#define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */ +#define RCC_MISCENSR_MCO2ENS_Pos (2UL) +#define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */ +#define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */ +#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3UL) +#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENSR_PERENS_Pos (6UL) +#define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */ +#define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENSR register ******************/ +#define RCC_MEMENSR_AXISRAM3ENS_Pos (0UL) +#define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */ +#define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENSR_AXISRAM4ENS_Pos (1UL) +#define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */ +#define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENSR_AXISRAM5ENS_Pos (2UL) +#define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */ +#define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENSR_AXISRAM6ENS_Pos (3UL) +#define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */ +#define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENSR_AHBSRAM1ENS_Pos (4UL) +#define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */ +#define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENSR_AHBSRAM2ENS_Pos (5UL) +#define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */ +#define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENSR_BKPSRAMENS_Pos (6UL) +#define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENSR_AXISRAM1ENS_Pos (7UL) +#define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */ +#define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENSR_AXISRAM2ENS_Pos (8UL) +#define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */ +#define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENSR_FLEXRAMENS_Pos (9UL) +#define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENSR_CACHEAXIRAMENS_Pos (10UL) +#define RCC_MEMENSR_CACHEAXIRAMENS_Msk (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos) /*!< 0x00000400 */ +#define RCC_MEMENSR_CACHEAXIRAMENS RCC_MEMENSR_CACHEAXIRAMENS_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENSR_VENCRAMENS_Pos (11UL) +#define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMENSR_BOOTROMENS_Pos (12UL) +#define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENSR register *****************/ +#define RCC_AHB1ENSR_GPDMA1ENS_Pos (4UL) +#define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENSR_ADC12ENS_Pos (5UL) +#define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENSR register *****************/ +#define RCC_AHB2ENSR_RAMCFGENS_Pos (12UL) +#define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENSR_MDF1ENS_Pos (16UL) +#define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENSR_ADF1ENS_Pos (17UL) +#define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENSR register *****************/ +#define RCC_AHB3ENSR_RNGENS_Pos (0UL) +#define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */ +#define RCC_AHB3ENSR_HASHENS_Pos (1UL) +#define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */ +#define RCC_AHB3ENSR_PKAENS_Pos (8UL) +#define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */ +#define RCC_AHB3ENSR_RIFSCENS_Pos (9UL) +#define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENSR_IACENS_Pos (10UL) +#define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */ +#define RCC_AHB3ENSR_RISAFENS_Pos (14UL) +#define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENSR register *****************/ +#define RCC_AHB4ENSR_GPIOAENS_Pos (0UL) +#define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENSR_GPIOBENS_Pos (1UL) +#define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENSR_GPIOCENS_Pos (2UL) +#define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENSR_GPIODENS_Pos (3UL) +#define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENSR_GPIOEENS_Pos (4UL) +#define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENSR_GPIOFENS_Pos (5UL) +#define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENSR_GPIOGENS_Pos (6UL) +#define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENSR_GPIOHENS_Pos (7UL) +#define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENSR_GPIONENS_Pos (13UL) +#define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENSR_GPIOOENS_Pos (14UL) +#define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENSR_GPIOPENS_Pos (15UL) +#define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENSR_GPIOQENS_Pos (16UL) +#define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENSR_PWRENS_Pos (18UL) +#define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */ +#define RCC_AHB4ENSR_CRCENS_Pos (19UL) +#define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENSR register *****************/ +#define RCC_AHB5ENSR_HPDMA1ENS_Pos (0UL) +#define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENSR_DMA2DENS_Pos (1UL) +#define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENSR_JPEGENS_Pos (3UL) +#define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */ +#define RCC_AHB5ENSR_FMCENS_Pos (4UL) +#define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */ +#define RCC_AHB5ENSR_XSPI1ENS_Pos (5UL) +#define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENSR_PSSIENS_Pos (6UL) +#define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */ +#define RCC_AHB5ENSR_SDMMC2ENS_Pos (7UL) +#define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENSR_SDMMC1ENS_Pos (8UL) +#define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENSR_XSPI2ENS_Pos (12UL) +#define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENSR_XSPIMENS_Pos (13UL) +#define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENSR_XSPI3ENS_Pos (17UL) +#define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENSR_GFXMMUENS_Pos (19UL) +#define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENSR_GPU2DENS_Pos (20UL) +#define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENSR_ETH1MACENS_Pos (22UL) +#define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENSR_ETH1TXENS_Pos (23UL) +#define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENSR_ETH1RXENS_Pos (24UL) +#define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENSR_ETH1ENS_Pos (25UL) +#define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENSR_OTG1ENS_Pos (26UL) +#define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27UL) +#define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28UL) +#define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENSR_OTG2ENS_Pos (29UL) +#define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENSR_CACHEAXIENS_Pos (30UL) +#define RCC_AHB5ENSR_CACHEAXIENS_Msk (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENSR_CACHEAXIENS RCC_AHB5ENSR_CACHEAXIENS_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENSR_NPUENS_Pos (31UL) +#define RCC_AHB5ENSR_NPUENS_Msk (0x1UL << RCC_AHB5ENSR_NPUENS_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENSR_NPUENS RCC_AHB5ENSR_NPUENS_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1ENSR1 register *****************/ +#define RCC_APB1ENSR1_TIM2ENS_Pos (0UL) +#define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */ +#define RCC_APB1ENSR1_TIM3ENS_Pos (1UL) +#define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */ +#define RCC_APB1ENSR1_TIM4ENS_Pos (2UL) +#define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */ +#define RCC_APB1ENSR1_TIM5ENS_Pos (3UL) +#define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */ +#define RCC_APB1ENSR1_TIM6ENS_Pos (4UL) +#define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */ +#define RCC_APB1ENSR1_TIM7ENS_Pos (5UL) +#define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */ +#define RCC_APB1ENSR1_TIM12ENS_Pos (6UL) +#define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */ +#define RCC_APB1ENSR1_TIM13ENS_Pos (7UL) +#define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */ +#define RCC_APB1ENSR1_TIM14ENS_Pos (8UL) +#define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */ +#define RCC_APB1ENSR1_LPTIM1ENS_Pos (9UL) +#define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENSR1_WWDGENS_Pos (11UL) +#define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */ +#define RCC_APB1ENSR1_TIM10ENS_Pos (12UL) +#define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */ +#define RCC_APB1ENSR1_TIM11ENS_Pos (13UL) +#define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */ +#define RCC_APB1ENSR1_SPI2ENS_Pos (14UL) +#define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */ +#define RCC_APB1ENSR1_SPI3ENS_Pos (15UL) +#define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */ +#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16UL) +#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENSR1_USART2ENS_Pos (17UL) +#define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */ +#define RCC_APB1ENSR1_USART3ENS_Pos (18UL) +#define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */ +#define RCC_APB1ENSR1_UART4ENS_Pos (19UL) +#define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */ +#define RCC_APB1ENSR1_UART5ENS_Pos (20UL) +#define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */ +#define RCC_APB1ENSR1_I2C1ENS_Pos (21UL) +#define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */ +#define RCC_APB1ENSR1_I2C2ENS_Pos (22UL) +#define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */ +#define RCC_APB1ENSR1_I2C3ENS_Pos (23UL) +#define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */ +#define RCC_APB1ENSR1_I3C1ENS_Pos (24UL) +#define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */ +#define RCC_APB1ENSR1_I3C2ENS_Pos (25UL) +#define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */ +#define RCC_APB1ENSR1_UART7ENS_Pos (30UL) +#define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */ +#define RCC_APB1ENSR1_UART8ENS_Pos (31UL) +#define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENSR2 register *****************/ +#define RCC_APB1ENSR2_MDIOSENS_Pos (5UL) +#define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */ +#define RCC_APB1ENSR2_FDCANENS_Pos (8UL) +#define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */ +#define RCC_APB1ENSR2_UCPD1ENS_Pos (18UL) +#define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENSR register *****************/ +#define RCC_APB2ENSR_TIM1ENS_Pos (0UL) +#define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */ +#define RCC_APB2ENSR_TIM8ENS_Pos (1UL) +#define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */ +#define RCC_APB2ENSR_USART1ENS_Pos (4UL) +#define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */ +#define RCC_APB2ENSR_USART6ENS_Pos (5UL) +#define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */ +#define RCC_APB2ENSR_UART9ENS_Pos (6UL) +#define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */ +#define RCC_APB2ENSR_USART10ENS_Pos (7UL) +#define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */ +#define RCC_APB2ENSR_SPI1ENS_Pos (12UL) +#define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */ +#define RCC_APB2ENSR_SPI4ENS_Pos (13UL) +#define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */ +#define RCC_APB2ENSR_TIM18ENS_Pos (15UL) +#define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */ +#define RCC_APB2ENSR_TIM15ENS_Pos (16UL) +#define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */ +#define RCC_APB2ENSR_TIM16ENS_Pos (17UL) +#define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */ +#define RCC_APB2ENSR_TIM17ENS_Pos (18UL) +#define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */ +#define RCC_APB2ENSR_TIM9ENS_Pos (19UL) +#define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */ +#define RCC_APB2ENSR_SPI5ENS_Pos (20UL) +#define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */ +#define RCC_APB2ENSR_SAI1ENS_Pos (21UL) +#define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */ +#define RCC_APB2ENSR_SAI2ENS_Pos (22UL) +#define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENSR register *****************/ +#define RCC_APB3ENSR_DFTENS_Pos (2UL) +#define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENSR1 register *****************/ +#define RCC_APB4ENSR1_HDPENS_Pos (2UL) +#define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */ +#define RCC_APB4ENSR1_LPUART1ENS_Pos (3UL) +#define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENSR1_SPI6ENS_Pos (5UL) +#define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */ +#define RCC_APB4ENSR1_I2C4ENS_Pos (7UL) +#define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */ +#define RCC_APB4ENSR1_LPTIM2ENS_Pos (9UL) +#define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENSR1_LPTIM3ENS_Pos (10UL) +#define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENSR1_LPTIM4ENS_Pos (11UL) +#define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENSR1_LPTIM5ENS_Pos (12UL) +#define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENSR1_VREFBUFENS_Pos (15UL) +#define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENSR1_RTCENS_Pos (16UL) +#define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */ +#define RCC_APB4ENSR1_RTCAPBENS_Pos (17UL) +#define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENSR2 register *****************/ +#define RCC_APB4ENSR2_SYSCFGENS_Pos (0UL) +#define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENSR2_BSECENS_Pos (1UL) +#define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */ +#define RCC_APB4ENSR2_DTSENS_Pos (2UL) +#define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENSR register *****************/ +#define RCC_APB5ENSR_LTDCENS_Pos (1UL) +#define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */ +#define RCC_APB5ENSR_DCMIPPENS_Pos (2UL) +#define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENSR_GFXTIMENS_Pos (4UL) +#define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENSR_VENCENS_Pos (5UL) +#define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */ +#define RCC_APB5ENSR_CSIENS_Pos (6UL) +#define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENSR register *****************/ +#define RCC_BUSLPENSR_ACLKNLPENS_Pos (0UL) +#define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1UL) +#define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENSR register ****************/ +#define RCC_MISCLPENSR_DBGLPENS_Pos (0UL) +#define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3UL) +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENSR_PERLPENS_Pos (6UL) +#define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */ + +/**************** Bit definition for RCC_MEMLPENSR register *****************/ +#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0UL) +#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1UL) +#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2UL) +#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3UL) +#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4UL) +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5UL) +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6UL) +#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7UL) +#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8UL) +#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9UL) +#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos (10UL) +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11UL) +#define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12UL) +#define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENSR register ****************/ +#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4UL) +#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENSR_ADC12LPENS_Pos (5UL) +#define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENSR register ****************/ +#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12UL) +#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENSR_MDF1LPENS_Pos (16UL) +#define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENSR_ADF1LPENS_Pos (17UL) +#define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENSR register ****************/ +#define RCC_AHB3LPENSR_RNGLPENS_Pos (0UL) +#define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */ +#define RCC_AHB3LPENSR_HASHLPENS_Pos (1UL) +#define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */ +#define RCC_AHB3LPENSR_PKALPENS_Pos (8UL) +#define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */ +#define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9UL) +#define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENSR_IACLPENS_Pos (10UL) +#define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENSR_RISAFLPENS_Pos (14UL) +#define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENSR register ****************/ +#define RCC_AHB4LPENSR_GPIOALPENS_Pos (0UL) +#define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1UL) +#define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2UL) +#define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENSR_GPIODLPENS_Pos (3UL) +#define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENSR_GPIOELPENS_Pos (4UL) +#define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5UL) +#define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6UL) +#define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7UL) +#define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENSR_GPIONLPENS_Pos (13UL) +#define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14UL) +#define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15UL) +#define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16UL) +#define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENSR_PWRLPENS_Pos (18UL) +#define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */ +#define RCC_AHB4LPENSR_CRCLPENS_Pos (19UL) +#define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENSR register ****************/ +#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0UL) +#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1UL) +#define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENSR_JPEGLPENS_Pos (3UL) +#define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENSR_FMCLPENS_Pos (4UL) +#define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */ +#define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5UL) +#define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENSR_PSSILPENS_Pos (6UL) +#define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7UL) +#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8UL) +#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12UL) +#define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13UL) +#define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17UL) +#define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19UL) +#define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20UL) +#define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22UL) +#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23UL) +#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24UL) +#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENSR_ETH1LPENS_Pos (25UL) +#define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENSR_OTG1LPENS_Pos (26UL) +#define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27UL) +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28UL) +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENSR_OTG2LPENS_Pos (29UL) +#define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */ +#define RCC_AHB5LPENSR_CACHEAXILPENS_Pos (30UL) +#define RCC_AHB5LPENSR_CACHEAXILPENS_Msk (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENSR_CACHEAXILPENS RCC_AHB5LPENSR_CACHEAXILPENS_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5LPENSR_NPULPENS_Pos (31UL) +#define RCC_AHB5LPENSR_NPULPENS_Msk (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */ +#define RCC_AHB5LPENSR_NPULPENS RCC_AHB5LPENSR_NPULPENS_Msk /*!< NPU enable */ + +/*************** Bit definition for RCC_APB1LPENSR1 register ****************/ +#define RCC_APB1LPENSR1_TIM2LPENS_Pos (0UL) +#define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENSR1_TIM3LPENS_Pos (1UL) +#define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENSR1_TIM4LPENS_Pos (2UL) +#define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENSR1_TIM5LPENS_Pos (3UL) +#define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENSR1_TIM6LPENS_Pos (4UL) +#define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENSR1_TIM7LPENS_Pos (5UL) +#define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENSR1_TIM12LPENS_Pos (6UL) +#define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENSR1_TIM13LPENS_Pos (7UL) +#define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENSR1_TIM14LPENS_Pos (8UL) +#define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9UL) +#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENSR1_WWDGLPENS_Pos (11UL) +#define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */ +#define RCC_APB1LPENSR1_TIM10LPENS_Pos (12UL) +#define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENSR1_TIM11LPENS_Pos (13UL) +#define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENSR1_SPI2LPENS_Pos (14UL) +#define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENSR1_SPI3LPENS_Pos (15UL) +#define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16UL) +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENSR1_USART2LPENS_Pos (17UL) +#define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */ +#define RCC_APB1LPENSR1_USART3LPENS_Pos (18UL) +#define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */ +#define RCC_APB1LPENSR1_UART4LPENS_Pos (19UL) +#define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */ +#define RCC_APB1LPENSR1_UART5LPENS_Pos (20UL) +#define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */ +#define RCC_APB1LPENSR1_I2C1LPENS_Pos (21UL) +#define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENSR1_I2C2LPENS_Pos (22UL) +#define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENSR1_I2C3LPENS_Pos (23UL) +#define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENSR1_I3C1LPENS_Pos (24UL) +#define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENSR1_I3C2LPENS_Pos (25UL) +#define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENSR1_UART7LPENS_Pos (30UL) +#define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */ +#define RCC_APB1LPENSR1_UART8LPENS_Pos (31UL) +#define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENSR2 register ****************/ +#define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5UL) +#define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENSR2_FDCANLPENS_Pos (8UL) +#define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18UL) +#define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENSR register ****************/ +#define RCC_APB2LPENSR_TIM1LPENS_Pos (0UL) +#define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENSR_TIM8LPENS_Pos (1UL) +#define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENSR_USART1LPENS_Pos (4UL) +#define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */ +#define RCC_APB2LPENSR_USART6LPENS_Pos (5UL) +#define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */ +#define RCC_APB2LPENSR_UART9LPENS_Pos (6UL) +#define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */ +#define RCC_APB2LPENSR_USART10LPENS_Pos (7UL) +#define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */ +#define RCC_APB2LPENSR_SPI1LPENS_Pos (12UL) +#define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENSR_SPI4LPENS_Pos (13UL) +#define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENSR_TIM18LPENS_Pos (15UL) +#define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENSR_TIM15LPENS_Pos (16UL) +#define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENSR_TIM16LPENS_Pos (17UL) +#define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENSR_TIM17LPENS_Pos (18UL) +#define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENSR_TIM9LPENS_Pos (19UL) +#define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENSR_SPI5LPENS_Pos (20UL) +#define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENSR_SAI1LPENS_Pos (21UL) +#define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENSR_SAI2LPENS_Pos (22UL) +#define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENSR register ****************/ +#define RCC_APB3LPENSR_DFTLPENS_Pos (2UL) +#define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENSR1 register ****************/ +#define RCC_APB4LPENSR1_HDPLPENS_Pos (2UL) +#define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */ +#define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3UL) +#define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENSR1_SPI6LPENS_Pos (5UL) +#define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENSR1_I2C4LPENS_Pos (7UL) +#define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9UL) +#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10UL) +#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11UL) +#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12UL) +#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15UL) +#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENSR1_RTCLPENS_Pos (16UL) +#define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */ +#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17UL) +#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENSR2 register ****************/ +#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0UL) +#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENSR2_BSECLPENS_Pos (1UL) +#define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */ +#define RCC_APB4LPENSR2_DTSLPENS_Pos (2UL) +#define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENSR register ****************/ +#define RCC_APB5LPENSR_LTDCLPENS_Pos (1UL) +#define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */ +#define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2UL) +#define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4UL) +#define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENSR_VENCLPENS_Pos (5UL) +#define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */ +#define RCC_APB5LPENSR_CSILPENS_Pos (6UL) +#define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_PRIVCFGSR0 register ****************/ +#define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR0 register *****************/ +#define RCC_PUBCFGSR0_LSIPUBS_Pos (0UL) +#define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_LSEPUBS_Pos (1UL) +#define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_MSIPUBS_Pos (2UL) +#define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSIPUBS_Pos (3UL) +#define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSEPUBS_Pos (4UL) +#define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR1 register ****************/ +#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR1 register *****************/ +#define RCC_PUBCFGSR1_PLL1PUBS_Pos (0UL) +#define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL2PUBS_Pos (1UL) +#define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL3PUBS_Pos (2UL) +#define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL4PUBS_Pos (3UL) +#define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR2 register ****************/ +#define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13UL) +#define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14UL) +#define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15UL) +#define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16UL) +#define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17UL) +#define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18UL) +#define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19UL) +#define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR2 register *****************/ +#define RCC_PUBCFGSR2_IC1PUBS_Pos (0UL) +#define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC2PUBS_Pos (1UL) +#define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC3PUBS_Pos (2UL) +#define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC4PUBS_Pos (3UL) +#define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC5PUBS_Pos (4UL) +#define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC6PUBS_Pos (5UL) +#define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC7PUBS_Pos (6UL) +#define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC8PUBS_Pos (7UL) +#define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC9PUBS_Pos (8UL) +#define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC10PUBS_Pos (9UL) +#define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC11PUBS_Pos (10UL) +#define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC12PUBS_Pos (11UL) +#define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC13PUBS_Pos (12UL) +#define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC14PUBS_Pos (13UL) +#define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC15PUBS_Pos (14UL) +#define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC16PUBS_Pos (15UL) +#define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */ +#define RCC_PUBCFGSR2_IC17PUBS_Pos (16UL) +#define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC18PUBS_Pos (17UL) +#define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC19PUBS_Pos (18UL) +#define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC20PUBS_Pos (19UL) +#define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR3 register ****************/ +#define RCC_PRIVCFGSR3_MODPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_PERPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_INTPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5UL) +#define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR3 register *****************/ +#define RCC_PUBCFGSR3_MODPUBS_Pos (0UL) +#define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_SYSPUBS_Pos (1UL) +#define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_BUSPUBS_Pos (2UL) +#define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_PERPUBS_Pos (3UL) +#define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_INTPUBS_Pos (4UL) +#define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_RSTPUBS_Pos (5UL) +#define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR4 register ****************/ +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13UL) +#define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR4 register *****************/ +#define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0UL) +#define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1UL) +#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHBMPUBS_Pos (2UL) +#define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB1PUBS_Pos (3UL) +#define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB2PUBS_Pos (4UL) +#define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB3PUBS_Pos (5UL) +#define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB4PUBS_Pos (6UL) +#define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB5PUBS_Pos (7UL) +#define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB1PUBS_Pos (8UL) +#define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB2PUBS_Pos (9UL) +#define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB3PUBS_Pos (10UL) +#define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB4PUBS_Pos (11UL) +#define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB5PUBS_Pos (12UL) +#define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_NOCPUBS_Pos (13UL) +#define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR5 register *****************/ +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0UL) +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1UL) +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2UL) +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3UL) +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4UL) +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5UL) +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6UL) +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7UL) +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8UL) +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9UL) +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos (10UL) +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11UL) +#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + +/******************* Bit definition for RCC_CCR register ********************/ +#define RCC_CCR_LSIONC_Pos (0UL) +#define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */ +#define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */ +#define RCC_CCR_LSEONC_Pos (1UL) +#define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */ +#define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */ +#define RCC_CCR_MSIONC_Pos (2UL) +#define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */ +#define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */ +#define RCC_CCR_HSIONC_Pos (3UL) +#define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */ +#define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */ +#define RCC_CCR_HSEONC_Pos (4UL) +#define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */ +#define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */ +#define RCC_CCR_PLL1ONC_Pos (8UL) +#define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */ +#define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */ +#define RCC_CCR_PLL2ONC_Pos (9UL) +#define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */ +#define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */ +#define RCC_CCR_PLL3ONC_Pos (10UL) +#define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */ +#define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */ +#define RCC_CCR_PLL4ONC_Pos (11UL) +#define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */ +#define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCCR register ******************/ +#define RCC_STOPCCR_MSISTOPENC_Pos (0UL) +#define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */ +#define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCCR_HSISTOPENC_Pos (1UL) +#define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */ +#define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTCR register *****************/ +#define RCC_MISCRSTCR_DBGRSTC_Pos (0UL) +#define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4UL) +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5UL) +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7UL) +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8UL) +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTCR register *****************/ +#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0UL) +#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1UL) +#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2UL) +#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3UL) +#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4UL) +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5UL) +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7UL) +#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8UL) +#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9UL) +#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos (10UL) +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11UL) +#define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12UL) +#define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTCR register *****************/ +#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4UL) +#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTCR_ADC12RSTC_Pos (5UL) +#define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTCR register *****************/ +#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12UL) +#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTCR_MDF1RSTC_Pos (16UL) +#define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTCR_ADF1RSTC_Pos (17UL) +#define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTCR register *****************/ +#define RCC_AHB3RSTCR_RNGRSTC_Pos (0UL) +#define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */ +#define RCC_AHB3RSTCR_HASHRSTC_Pos (1UL) +#define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */ +#define RCC_AHB3RSTCR_PKARSTC_Pos (8UL) +#define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */ +#define RCC_AHB3RSTCR_IACRSTC_Pos (10UL) +#define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTCR register *****************/ +#define RCC_AHB4RSTCR_GPIOARSTC_Pos (0UL) +#define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1UL) +#define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2UL) +#define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTCR_GPIODRSTC_Pos (3UL) +#define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTCR_GPIOERSTC_Pos (4UL) +#define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5UL) +#define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6UL) +#define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7UL) +#define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTCR_GPIONRSTC_Pos (13UL) +#define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTCR_GPIOORSTC_Pos (14UL) +#define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15UL) +#define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16UL) +#define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTCR_PWRRSTC_Pos (18UL) +#define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */ +#define RCC_AHB4RSTCR_CRCRSTC_Pos (19UL) +#define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTCR register *****************/ +#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0UL) +#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1UL) +#define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTCR_JPEGRSTC_Pos (3UL) +#define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTCR_FMCRSTC_Pos (4UL) +#define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */ +#define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5UL) +#define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTCR_PSSIRSTC_Pos (6UL) +#define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7UL) +#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8UL) +#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12UL) +#define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13UL) +#define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17UL) +#define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19UL) +#define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20UL) +#define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23UL) +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24UL) +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTCR_ETH1RSTC_Pos (25UL) +#define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTCR_OTG1RSTC_Pos (26UL) +#define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27UL) +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28UL) +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTCR_OTG2RSTC_Pos (29UL) +#define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos (30UL) +#define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTCR_CACHEAXIRSTC RCC_AHB5RSTCR_CACHEAXIRSTC_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTCR_NPURSTC_Pos (31UL) +#define RCC_AHB5RSTCR_NPURSTC_Msk (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTCR_NPURSTC RCC_AHB5RSTCR_NPURSTC_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTCR1 register ****************/ +#define RCC_APB1RSTCR1_TIM2RSTC_Pos (0UL) +#define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTCR1_TIM3RSTC_Pos (1UL) +#define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTCR1_TIM4RSTC_Pos (2UL) +#define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTCR1_TIM5RSTC_Pos (3UL) +#define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTCR1_TIM6RSTC_Pos (4UL) +#define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTCR1_TIM7RSTC_Pos (5UL) +#define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTCR1_TIM12RSTC_Pos (6UL) +#define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTCR1_TIM13RSTC_Pos (7UL) +#define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTCR1_TIM14RSTC_Pos (8UL) +#define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9UL) +#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTCR1_WWDGRSTC_Pos (11UL) +#define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */ +#define RCC_APB1RSTCR1_TIM10RSTC_Pos (12UL) +#define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTCR1_TIM11RSTC_Pos (13UL) +#define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTCR1_SPI2RSTC_Pos (14UL) +#define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTCR1_SPI3RSTC_Pos (15UL) +#define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16UL) +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTCR1_USART2RSTC_Pos (17UL) +#define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */ +#define RCC_APB1RSTCR1_USART3RSTC_Pos (18UL) +#define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */ +#define RCC_APB1RSTCR1_UART4RSTC_Pos (19UL) +#define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */ +#define RCC_APB1RSTCR1_UART5RSTC_Pos (20UL) +#define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */ +#define RCC_APB1RSTCR1_I2C1RSTC_Pos (21UL) +#define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTCR1_I2C2RSTC_Pos (22UL) +#define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTCR1_I2C3RSTC_Pos (23UL) +#define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTCR1_I3C1RSTC_Pos (24UL) +#define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTCR1_I3C2RSTC_Pos (25UL) +#define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTCR1_UART7RSTC_Pos (30UL) +#define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */ +#define RCC_APB1RSTCR1_UART8RSTC_Pos (31UL) +#define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTCR2 register ****************/ +#define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5UL) +#define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTCR2_FDCANRSTC_Pos (8UL) +#define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18UL) +#define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTCR register *****************/ +#define RCC_APB2RSTCR_TIM1RSTC_Pos (0UL) +#define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTCR_TIM8RSTC_Pos (1UL) +#define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTCR_USART1RSTC_Pos (4UL) +#define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */ +#define RCC_APB2RSTCR_USART6RSTC_Pos (5UL) +#define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */ +#define RCC_APB2RSTCR_UART9RSTC_Pos (6UL) +#define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */ +#define RCC_APB2RSTCR_USART10RSTC_Pos (7UL) +#define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */ +#define RCC_APB2RSTCR_SPI1RSTC_Pos (12UL) +#define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTCR_SPI4RSTC_Pos (13UL) +#define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTCR_TIM18RSTC_Pos (15UL) +#define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTCR_TIM15RSTC_Pos (16UL) +#define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTCR_TIM16RSTC_Pos (17UL) +#define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTCR_TIM17RSTC_Pos (18UL) +#define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTCR_TIM9RSTC_Pos (19UL) +#define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTCR_SPI5RSTC_Pos (20UL) +#define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTCR_SAI1RSTC_Pos (21UL) +#define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTCR_SAI2RSTC_Pos (22UL) +#define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTCR1 register ****************/ +#define RCC_APB4RSTCR1_HDPRSTC_Pos (2UL) +#define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */ +#define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3UL) +#define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTCR1_SPI6RSTC_Pos (5UL) +#define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTCR1_I2C4RSTC_Pos (7UL) +#define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9UL) +#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10UL) +#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11UL) +#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12UL) +#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15UL) +#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTCR1_RTCRSTC_Pos (16UL) +#define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTCR2 register ****************/ +#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0UL) +#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTCR2_DTSRSTC_Pos (2UL) +#define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTCR register *****************/ +#define RCC_APB5RSTCR_LTDCRSTC_Pos (1UL) +#define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */ +#define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2UL) +#define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4UL) +#define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTCR_VENCRSTC_Pos (5UL) +#define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */ +#define RCC_APB5RSTCR_CSIRSTC_Pos (6UL) +#define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENCR register ******************/ +#define RCC_DIVENCR_IC1ENC_Pos (0UL) +#define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */ +#define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */ +#define RCC_DIVENCR_IC2ENC_Pos (1UL) +#define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */ +#define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */ +#define RCC_DIVENCR_IC3ENC_Pos (2UL) +#define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */ +#define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */ +#define RCC_DIVENCR_IC4ENC_Pos (3UL) +#define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */ +#define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */ +#define RCC_DIVENCR_IC5ENC_Pos (4UL) +#define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */ +#define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */ +#define RCC_DIVENCR_IC6ENC_Pos (5UL) +#define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */ +#define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */ +#define RCC_DIVENCR_IC7ENC_Pos (6UL) +#define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */ +#define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */ +#define RCC_DIVENCR_IC8ENC_Pos (7UL) +#define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */ +#define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */ +#define RCC_DIVENCR_IC9ENC_Pos (8UL) +#define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */ +#define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */ +#define RCC_DIVENCR_IC10ENC_Pos (9UL) +#define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */ +#define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */ +#define RCC_DIVENCR_IC11ENC_Pos (10UL) +#define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */ +#define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */ +#define RCC_DIVENCR_IC12ENC_Pos (11UL) +#define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */ +#define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */ +#define RCC_DIVENCR_IC13ENC_Pos (12UL) +#define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */ +#define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */ +#define RCC_DIVENCR_IC14ENC_Pos (13UL) +#define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */ +#define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */ +#define RCC_DIVENCR_IC15ENC_Pos (14UL) +#define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */ +#define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */ +#define RCC_DIVENCR_IC16ENC_Pos (15UL) +#define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */ +#define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */ +#define RCC_DIVENCR_IC17ENC_Pos (16UL) +#define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */ +#define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */ +#define RCC_DIVENCR_IC18ENC_Pos (17UL) +#define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */ +#define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */ +#define RCC_DIVENCR_IC19ENC_Pos (18UL) +#define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */ +#define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */ +#define RCC_DIVENCR_IC20ENC_Pos (19UL) +#define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */ +#define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENCR register ******************/ +#define RCC_BUSENCR_ACLKNENC_Pos (0UL) +#define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */ +#define RCC_BUSENCR_ACLKNCENC_Pos (1UL) +#define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */ +#define RCC_BUSENCR_AHBMENC_Pos (2UL) +#define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */ +#define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */ +#define RCC_BUSENCR_AHB1ENC_Pos (3UL) +#define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */ +#define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */ +#define RCC_BUSENCR_AHB2ENC_Pos (4UL) +#define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */ +#define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */ +#define RCC_BUSENCR_AHB3ENC_Pos (5UL) +#define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */ +#define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */ +#define RCC_BUSENCR_AHB4ENC_Pos (6UL) +#define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */ +#define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */ +#define RCC_BUSENCR_AHB5ENC_Pos (7UL) +#define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */ +#define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */ +#define RCC_BUSENCR_APB1ENC_Pos (8UL) +#define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */ +#define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */ +#define RCC_BUSENCR_APB2ENC_Pos (9UL) +#define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */ +#define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */ +#define RCC_BUSENCR_APB3ENC_Pos (10UL) +#define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */ +#define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */ +#define RCC_BUSENCR_APB4ENC_Pos (11UL) +#define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */ +#define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */ +#define RCC_BUSENCR_APB5ENC_Pos (12UL) +#define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */ +#define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENCR register *****************/ +#define RCC_MISCENCR_DBGENC_Pos (0UL) +#define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */ +#define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */ +#define RCC_MISCENCR_MCO1ENC_Pos (1UL) +#define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */ +#define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */ +#define RCC_MISCENCR_MCO2ENC_Pos (2UL) +#define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */ +#define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */ +#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3UL) +#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENCR_PERENC_Pos (6UL) +#define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */ +#define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENCR register ******************/ +#define RCC_MEMENCR_AXISRAM3ENC_Pos (0UL) +#define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */ +#define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENCR_AXISRAM4ENC_Pos (1UL) +#define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */ +#define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENCR_AXISRAM5ENC_Pos (2UL) +#define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */ +#define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENCR_AXISRAM6ENC_Pos (3UL) +#define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */ +#define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENCR_AHBSRAM1ENC_Pos (4UL) +#define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */ +#define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENCR_AHBSRAM2ENC_Pos (5UL) +#define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */ +#define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENCR_BKPSRAMENC_Pos (6UL) +#define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENCR_AXISRAM1ENC_Pos (7UL) +#define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */ +#define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENCR_AXISRAM2ENC_Pos (8UL) +#define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */ +#define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENCR_FLEXRAMENC_Pos (9UL) +#define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENCR_CACHEAXIRAMENC_Pos (10UL) +#define RCC_MEMENCR_CACHEAXIRAMENC_Msk (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos) /*!< 0x00000400 */ +#define RCC_MEMENCR_CACHEAXIRAMENC RCC_MEMENCR_CACHEAXIRAMENC_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENCR_VENCRAMENC_Pos (11UL) +#define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */ +#define RCC_MEMENCR_BOOTROMENC_Pos (12UL) +#define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENCR register *****************/ +#define RCC_AHB1ENCR_GPDMA1ENC_Pos (4UL) +#define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENCR_ADC12ENC_Pos (5UL) +#define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENCR register *****************/ +#define RCC_AHB2ENCR_RAMCFGENC_Pos (12UL) +#define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENCR_MDF1ENC_Pos (16UL) +#define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENCR_ADF1ENC_Pos (17UL) +#define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENCR register *****************/ +#define RCC_AHB3ENCR_RNGENC_Pos (0UL) +#define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */ +#define RCC_AHB3ENCR_HASHENC_Pos (1UL) +#define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */ +#define RCC_AHB3ENCR_PKAENC_Pos (8UL) +#define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */ +#define RCC_AHB3ENCR_RIFSCENC_Pos (9UL) +#define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENCR_IACENC_Pos (10UL) +#define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */ +#define RCC_AHB3ENCR_RISAFENC_Pos (14UL) +#define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENCR register *****************/ +#define RCC_AHB4ENCR_GPIOAENC_Pos (0UL) +#define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENCR_GPIOBENC_Pos (1UL) +#define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENCR_GPIOCENC_Pos (2UL) +#define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENCR_GPIODENC_Pos (3UL) +#define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENCR_GPIOEENC_Pos (4UL) +#define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENCR_GPIOFENC_Pos (5UL) +#define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENCR_GPIOGENC_Pos (6UL) +#define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENCR_GPIOHENC_Pos (7UL) +#define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENCR_GPIONENC_Pos (13UL) +#define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENCR_GPIOOENC_Pos (14UL) +#define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENCR_GPIOPENC_Pos (15UL) +#define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENCR_GPIOQENC_Pos (16UL) +#define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENCR_PWRENC_Pos (18UL) +#define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */ +#define RCC_AHB4ENCR_CRCENC_Pos (19UL) +#define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENCR register *****************/ +#define RCC_AHB5ENCR_HPDMA1ENC_Pos (0UL) +#define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENCR_DMA2DENC_Pos (1UL) +#define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENCR_JPEGENC_Pos (3UL) +#define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */ +#define RCC_AHB5ENCR_FMCENC_Pos (4UL) +#define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */ +#define RCC_AHB5ENCR_XSPI1ENC_Pos (5UL) +#define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENCR_PSSIENC_Pos (6UL) +#define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */ +#define RCC_AHB5ENCR_SDMMC2ENC_Pos (7UL) +#define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENCR_SDMMC1ENC_Pos (8UL) +#define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENCR_XSPI2ENC_Pos (12UL) +#define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENCR_XSPIMENC_Pos (13UL) +#define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENCR_XSPI3ENC_Pos (17UL) +#define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENCR_GFXMMUENC_Pos (19UL) +#define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENCR_GPU2DENC_Pos (20UL) +#define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENCR_ETH1MACENC_Pos (22UL) +#define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENCR_ETH1TXENC_Pos (23UL) +#define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENCR_ETH1RXENC_Pos (24UL) +#define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENCR_ETH1ENC_Pos (25UL) +#define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENCR_OTG1ENC_Pos (26UL) +#define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27UL) +#define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28UL) +#define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENCR_OTG2ENC_Pos (29UL) +#define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENCR_CACHEAXIENC_Pos (30UL) +#define RCC_AHB5ENCR_CACHEAXIENC_Msk (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENCR_CACHEAXIENC RCC_AHB5ENCR_CACHEAXIENC_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENCR_NPUENC_Pos (31UL) +#define RCC_AHB5ENCR_NPUENC_Msk (0x1UL << RCC_AHB5ENCR_NPUENC_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENCR_NPUENC RCC_AHB5ENCR_NPUENC_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1ENCR1 register *****************/ +#define RCC_APB1ENCR1_TIM2ENC_Pos (0UL) +#define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */ +#define RCC_APB1ENCR1_TIM3ENC_Pos (1UL) +#define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */ +#define RCC_APB1ENCR1_TIM4ENC_Pos (2UL) +#define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */ +#define RCC_APB1ENCR1_TIM5ENC_Pos (3UL) +#define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */ +#define RCC_APB1ENCR1_TIM6ENC_Pos (4UL) +#define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */ +#define RCC_APB1ENCR1_TIM7ENC_Pos (5UL) +#define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */ +#define RCC_APB1ENCR1_TIM12ENC_Pos (6UL) +#define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */ +#define RCC_APB1ENCR1_TIM13ENC_Pos (7UL) +#define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */ +#define RCC_APB1ENCR1_TIM14ENC_Pos (8UL) +#define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */ +#define RCC_APB1ENCR1_LPTIM1ENC_Pos (9UL) +#define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENCR1_TIM10ENC_Pos (12UL) +#define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */ +#define RCC_APB1ENCR1_TIM11ENC_Pos (13UL) +#define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */ +#define RCC_APB1ENCR1_SPI2ENC_Pos (14UL) +#define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */ +#define RCC_APB1ENCR1_SPI3ENC_Pos (15UL) +#define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */ +#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16UL) +#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENCR1_USART2ENC_Pos (17UL) +#define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */ +#define RCC_APB1ENCR1_USART3ENC_Pos (18UL) +#define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */ +#define RCC_APB1ENCR1_UART4ENC_Pos (19UL) +#define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */ +#define RCC_APB1ENCR1_UART5ENC_Pos (20UL) +#define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */ +#define RCC_APB1ENCR1_I2C1ENC_Pos (21UL) +#define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */ +#define RCC_APB1ENCR1_I2C2ENC_Pos (22UL) +#define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */ +#define RCC_APB1ENCR1_I2C3ENC_Pos (23UL) +#define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */ +#define RCC_APB1ENCR1_I3C1ENC_Pos (24UL) +#define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */ +#define RCC_APB1ENCR1_I3C2ENC_Pos (25UL) +#define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */ +#define RCC_APB1ENCR1_UART7ENC_Pos (30UL) +#define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */ +#define RCC_APB1ENCR1_UART8ENC_Pos (31UL) +#define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENCR2 register *****************/ +#define RCC_APB1ENCR2_MDIOSENC_Pos (5UL) +#define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */ +#define RCC_APB1ENCR2_FDCANENC_Pos (8UL) +#define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */ +#define RCC_APB1ENCR2_UCPD1ENC_Pos (18UL) +#define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENCR register *****************/ +#define RCC_APB2ENCR_TIM1ENC_Pos (0UL) +#define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */ +#define RCC_APB2ENCR_TIM8ENC_Pos (1UL) +#define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */ +#define RCC_APB2ENCR_USART1ENC_Pos (4UL) +#define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */ +#define RCC_APB2ENCR_USART6ENC_Pos (5UL) +#define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */ +#define RCC_APB2ENCR_UART9ENC_Pos (6UL) +#define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */ +#define RCC_APB2ENCR_USART10ENC_Pos (7UL) +#define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */ +#define RCC_APB2ENCR_SPI1ENC_Pos (12UL) +#define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */ +#define RCC_APB2ENCR_SPI4ENC_Pos (13UL) +#define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */ +#define RCC_APB2ENCR_TIM18ENC_Pos (15UL) +#define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */ +#define RCC_APB2ENCR_TIM15ENC_Pos (16UL) +#define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */ +#define RCC_APB2ENCR_TIM16ENC_Pos (17UL) +#define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */ +#define RCC_APB2ENCR_TIM17ENC_Pos (18UL) +#define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */ +#define RCC_APB2ENCR_TIM9ENC_Pos (19UL) +#define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */ +#define RCC_APB2ENCR_SPI5ENC_Pos (20UL) +#define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */ +#define RCC_APB2ENCR_SAI1ENC_Pos (21UL) +#define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */ +#define RCC_APB2ENCR_SAI2ENC_Pos (22UL) +#define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENCR register *****************/ +#define RCC_APB3ENCR_DFTENC_Pos (2UL) +#define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENCR1 register *****************/ +#define RCC_APB4ENCR1_HDPENC_Pos (2UL) +#define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */ +#define RCC_APB4ENCR1_LPUART1ENC_Pos (3UL) +#define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENCR1_SPI6ENC_Pos (5UL) +#define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */ +#define RCC_APB4ENCR1_I2C4ENC_Pos (7UL) +#define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */ +#define RCC_APB4ENCR1_LPTIM2ENC_Pos (9UL) +#define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENCR1_LPTIM3ENC_Pos (10UL) +#define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENCR1_LPTIM4ENC_Pos (11UL) +#define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENCR1_LPTIM5ENC_Pos (12UL) +#define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENCR1_VREFBUFENC_Pos (15UL) +#define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENCR1_RTCENC_Pos (16UL) +#define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */ +#define RCC_APB4ENCR1_RTCAPBENC_Pos (17UL) +#define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENCR2 register *****************/ +#define RCC_APB4ENCR2_SYSCFGENC_Pos (0UL) +#define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENCR2_BSECENC_Pos (1UL) +#define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */ +#define RCC_APB4ENCR2_DTSENC_Pos (2UL) +#define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENCR register *****************/ +#define RCC_APB5ENCR_LTDCENC_Pos (1UL) +#define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */ +#define RCC_APB5ENCR_DCMIPPENC_Pos (2UL) +#define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENCR_GFXTIMENC_Pos (4UL) +#define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENCR_VENCENC_Pos (5UL) +#define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */ +#define RCC_APB5ENCR_CSIENC_Pos (6UL) +#define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENCR register *****************/ +#define RCC_BUSLPENCR_ACLKNLPENC_Pos (0UL) +#define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */ +#define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1UL) +#define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */ + +/**************** Bit definition for RCC_MISCLPENCR register ****************/ +#define RCC_MISCLPENCR_DBGLPENC_Pos (0UL) +#define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3UL) +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */ +#define RCC_MISCLPENCR_PERLPENC_Pos (6UL) +#define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */ + +/**************** Bit definition for RCC_MEMLPENCR register *****************/ +#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0UL) +#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1UL) +#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2UL) +#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3UL) +#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4UL) +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5UL) +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6UL) +#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7UL) +#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8UL) +#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9UL) +#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos (10UL) +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk /*!< CACHEAXIRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11UL) +#define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12UL) +#define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB1LPENCR register ****************/ +#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4UL) +#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */ +#define RCC_AHB1LPENCR_ADC12LPENC_Pos (5UL) +#define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB2LPENCR register ****************/ +#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12UL) +#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */ +#define RCC_AHB2LPENCR_MDF1LPENC_Pos (16UL) +#define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */ +#define RCC_AHB2LPENCR_ADF1LPENC_Pos (17UL) +#define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB3LPENCR register ****************/ +#define RCC_AHB3LPENCR_RNGLPENC_Pos (0UL) +#define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */ +#define RCC_AHB3LPENCR_HASHLPENC_Pos (1UL) +#define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */ +#define RCC_AHB3LPENCR_PKALPENC_Pos (8UL) +#define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */ +#define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9UL) +#define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */ +#define RCC_AHB3LPENCR_IACLPENC_Pos (10UL) +#define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENCR_RISAFLPENC_Pos (14UL) +#define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB4LPENCR register ****************/ +#define RCC_AHB4LPENCR_GPIOALPENC_Pos (0UL) +#define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1UL) +#define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2UL) +#define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIODLPENC_Pos (3UL) +#define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOELPENC_Pos (4UL) +#define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5UL) +#define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6UL) +#define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7UL) +#define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIONLPENC_Pos (13UL) +#define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14UL) +#define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15UL) +#define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16UL) +#define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */ +#define RCC_AHB4LPENCR_PWRLPENC_Pos (18UL) +#define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */ +#define RCC_AHB4LPENCR_CRCLPENC_Pos (19UL) +#define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB5LPENCR register ****************/ +#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0UL) +#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1UL) +#define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_JPEGLPENC_Pos (3UL) +#define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */ +#define RCC_AHB5LPENCR_FMCLPENC_Pos (4UL) +#define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5UL) +#define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_PSSILPENC_Pos (6UL) +#define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7UL) +#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8UL) +#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12UL) +#define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13UL) +#define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17UL) +#define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19UL) +#define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */ +#define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20UL) +#define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22UL) +#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23UL) +#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24UL) +#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1LPENC_Pos (25UL) +#define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG1LPENC_Pos (26UL) +#define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27UL) +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28UL) +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG2LPENC_Pos (29UL) +#define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_CACHEAXILPENC_Pos (30UL) +#define RCC_AHB5LPENCR_CACHEAXILPENC_Msk (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENCR_CACHEAXILPENC RCC_AHB5LPENCR_CACHEAXILPENC_Msk /*!< CACHEAXI enable in Sleep mode */ +#define RCC_AHB5LPENCR_NPULPENC_Pos (31UL) +#define RCC_AHB5LPENCR_NPULPENC_Msk (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */ +#define RCC_AHB5LPENCR_NPULPENC RCC_AHB5LPENCR_NPULPENC_Msk /*!< NPU enable in Sleep mode */ + +/*************** Bit definition for RCC_APB1LPENCR1 register ****************/ +#define RCC_APB1LPENCR1_TIM2LPENC_Pos (0UL) +#define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENCR1_TIM3LPENC_Pos (1UL) +#define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENCR1_TIM4LPENC_Pos (2UL) +#define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENCR1_TIM5LPENC_Pos (3UL) +#define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENCR1_TIM6LPENC_Pos (4UL) +#define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENCR1_TIM7LPENC_Pos (5UL) +#define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENCR1_TIM12LPENC_Pos (6UL) +#define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENCR1_TIM13LPENC_Pos (7UL) +#define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENCR1_TIM14LPENC_Pos (8UL) +#define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9UL) +#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENCR1_WWDGLPENC_Pos (11UL) +#define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */ +#define RCC_APB1LPENCR1_TIM10LPENC_Pos (12UL) +#define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENCR1_TIM11LPENC_Pos (13UL) +#define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENCR1_SPI2LPENC_Pos (14UL) +#define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENCR1_SPI3LPENC_Pos (15UL) +#define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16UL) +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENCR1_USART2LPENC_Pos (17UL) +#define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */ +#define RCC_APB1LPENCR1_USART3LPENC_Pos (18UL) +#define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */ +#define RCC_APB1LPENCR1_UART4LPENC_Pos (19UL) +#define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */ +#define RCC_APB1LPENCR1_UART5LPENC_Pos (20UL) +#define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */ +#define RCC_APB1LPENCR1_I2C1LPENC_Pos (21UL) +#define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENCR1_I2C2LPENC_Pos (22UL) +#define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENCR1_I2C3LPENC_Pos (23UL) +#define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENCR1_I3C1LPENC_Pos (24UL) +#define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENCR1_I3C2LPENC_Pos (25UL) +#define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENCR1_UART7LPENC_Pos (30UL) +#define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */ +#define RCC_APB1LPENCR1_UART8LPENC_Pos (31UL) +#define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENCR2 register ****************/ +#define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5UL) +#define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENCR2_FDCANLPENC_Pos (8UL) +#define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18UL) +#define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENCR register ****************/ +#define RCC_APB2LPENCR_TIM1LPENC_Pos (0UL) +#define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENCR_TIM8LPENC_Pos (1UL) +#define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENCR_USART1LPENC_Pos (4UL) +#define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */ +#define RCC_APB2LPENCR_USART6LPENC_Pos (5UL) +#define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */ +#define RCC_APB2LPENCR_UART9LPENC_Pos (6UL) +#define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */ +#define RCC_APB2LPENCR_USART10LPENC_Pos (7UL) +#define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */ +#define RCC_APB2LPENCR_SPI1LPENC_Pos (12UL) +#define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENCR_SPI4LPENC_Pos (13UL) +#define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENCR_TIM18LPENC_Pos (15UL) +#define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENCR_TIM15LPENC_Pos (16UL) +#define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENCR_TIM16LPENC_Pos (17UL) +#define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENCR_TIM17LPENC_Pos (18UL) +#define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENCR_TIM9LPENC_Pos (19UL) +#define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENCR_SPI5LPENC_Pos (20UL) +#define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENCR_SAI1LPENC_Pos (21UL) +#define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENCR_SAI2LPENC_Pos (22UL) +#define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENCR register ****************/ +#define RCC_APB3LPENCR_DFTLPENC_Pos (2UL) +#define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENCR1 register ****************/ +#define RCC_APB4LPENCR1_HDPLPENC_Pos (2UL) +#define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */ +#define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3UL) +#define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENCR1_SPI6LPENC_Pos (5UL) +#define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENCR1_I2C4LPENC_Pos (7UL) +#define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9UL) +#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10UL) +#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11UL) +#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12UL) +#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15UL) +#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENCR1_RTCLPENC_Pos (16UL) +#define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */ +#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17UL) +#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENCR2 register ****************/ +#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0UL) +#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENCR2_BSECLPENC_Pos (1UL) +#define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */ +#define RCC_APB4LPENCR2_DTSLPENC_Pos (2UL) +#define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENCR register ****************/ +#define RCC_APB5LPENCR_LTDCLPENC_Pos (1UL) +#define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */ +#define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2UL) +#define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */ +#define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4UL) +#define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */ +#define RCC_APB5LPENCR_VENCLPENC_Pos (5UL) +#define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */ +#define RCC_APB5LPENCR_CSILPENC_Pos (6UL) +#define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */ + +/**************** Bit definition for RCC_PRIVCFGCR0 register ****************/ +#define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR0 register *****************/ +#define RCC_PUBCFGCR0_LSIPUBC_Pos (0UL) +#define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_LSEPUBC_Pos (1UL) +#define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_MSIPUBC_Pos (2UL) +#define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSIPUBC_Pos (3UL) +#define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSEPUBC_Pos (4UL) +#define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR1 register ****************/ +#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR1 register *****************/ +#define RCC_PUBCFGCR1_PLL1PUBC_Pos (0UL) +#define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL2PUBC_Pos (1UL) +#define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL3PUBC_Pos (2UL) +#define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL4PUBC_Pos (3UL) +#define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR2 register ****************/ +#define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13UL) +#define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14UL) +#define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15UL) +#define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16UL) +#define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17UL) +#define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18UL) +#define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19UL) +#define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR2 register *****************/ +#define RCC_PUBCFGCR2_IC1PUBC_Pos (0UL) +#define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC2PUBC_Pos (1UL) +#define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC3PUBC_Pos (2UL) +#define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC4PUBC_Pos (3UL) +#define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC5PUBC_Pos (4UL) +#define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC6PUBC_Pos (5UL) +#define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC7PUBC_Pos (6UL) +#define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC8PUBC_Pos (7UL) +#define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC9PUBC_Pos (8UL) +#define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC10PUBC_Pos (9UL) +#define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC11PUBC_Pos (10UL) +#define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC12PUBC_Pos (11UL) +#define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC13PUBC_Pos (12UL) +#define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC14PUBC_Pos (13UL) +#define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC15PUBC_Pos (14UL) +#define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC16PUBC_Pos (15UL) +#define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC17PUBC_Pos (16UL) +#define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC18PUBC_Pos (17UL) +#define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC19PUBC_Pos (18UL) +#define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC20PUBC_Pos (19UL) +#define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR3 register ****************/ +#define RCC_PRIVCFGCR3_MODPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_PERPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_INTPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5UL) +#define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR3 register *****************/ +#define RCC_PUBCFGCR3_MODPUBC_Pos (0UL) +#define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_SYSPUBC_Pos (1UL) +#define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_BUSPUBC_Pos (2UL) +#define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_PERPUBC_Pos (3UL) +#define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_INTPUBC_Pos (4UL) +#define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_RSTPUBC_Pos (5UL) +#define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR4 register ****************/ +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13UL) +#define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR4 register *****************/ +#define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0UL) +#define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1UL) +#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHBMPUBC_Pos (2UL) +#define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB1PUBC_Pos (3UL) +#define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB2PUBC_Pos (4UL) +#define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB3PUBC_Pos (5UL) +#define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB4PUBC_Pos (6UL) +#define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB5PUBC_Pos (7UL) +#define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB1PUBC_Pos (8UL) +#define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB2PUBC_Pos (9UL) +#define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB3PUBC_Pos (10UL) +#define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB4PUBC_Pos (11UL) +#define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB5PUBC_Pos (12UL) +#define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_NOCPUBC_Pos (13UL) +#define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR5 register *****************/ +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0UL) +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1UL) +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2UL) +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3UL) +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4UL) +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5UL) +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6UL) +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7UL) +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8UL) +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9UL) +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos (10UL) +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk /*!< Public protection of CACHEAXIRAM configuration bits */ +#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11UL) +#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + + +/******************************************************************************/ +/* */ +/* Resource Isolation Framework Security Controller (RIFSC) */ +/* */ +/******************************************************************************/ +/**************** Bit definition for RIFSC_RISC_CR register *****************/ +#define RIFSC_RISC_CR_GLOCK_Pos (0UL) +#define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */ + +/************* Bit definition for RIFSC_RISC_SECCFGRx register **************/ +#define RIFSC_RISC_SECCFGRx_SEC0_Pos (0UL) +#define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */ +#define RIFSC_RISC_SECCFGRx_SEC1_Pos (1UL) +#define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */ +#define RIFSC_RISC_SECCFGRx_SEC2_Pos (2UL) +#define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */ +#define RIFSC_RISC_SECCFGRx_SEC3_Pos (3UL) +#define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */ +#define RIFSC_RISC_SECCFGRx_SEC4_Pos (4UL) +#define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */ +#define RIFSC_RISC_SECCFGRx_SEC5_Pos (5UL) +#define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */ +#define RIFSC_RISC_SECCFGRx_SEC6_Pos (6UL) +#define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */ +#define RIFSC_RISC_SECCFGRx_SEC7_Pos (7UL) +#define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */ +#define RIFSC_RISC_SECCFGRx_SEC8_Pos (8UL) +#define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */ +#define RIFSC_RISC_SECCFGRx_SEC9_Pos (9UL) +#define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */ +#define RIFSC_RISC_SECCFGRx_SEC10_Pos (10UL) +#define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */ +#define RIFSC_RISC_SECCFGRx_SEC11_Pos (11UL) +#define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */ +#define RIFSC_RISC_SECCFGRx_SEC12_Pos (12UL) +#define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */ +#define RIFSC_RISC_SECCFGRx_SEC13_Pos (13UL) +#define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */ +#define RIFSC_RISC_SECCFGRx_SEC14_Pos (14UL) +#define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */ +#define RIFSC_RISC_SECCFGRx_SEC15_Pos (15UL) +#define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */ +#define RIFSC_RISC_SECCFGRx_SEC16_Pos (16UL) +#define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */ +#define RIFSC_RISC_SECCFGRx_SEC17_Pos (17UL) +#define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */ +#define RIFSC_RISC_SECCFGRx_SEC18_Pos (18UL) +#define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */ +#define RIFSC_RISC_SECCFGRx_SEC19_Pos (19UL) +#define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */ +#define RIFSC_RISC_SECCFGRx_SEC20_Pos (20UL) +#define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */ +#define RIFSC_RISC_SECCFGRx_SEC21_Pos (21UL) +#define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */ +#define RIFSC_RISC_SECCFGRx_SEC22_Pos (22UL) +#define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */ +#define RIFSC_RISC_SECCFGRx_SEC23_Pos (23UL) +#define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */ +#define RIFSC_RISC_SECCFGRx_SEC24_Pos (24UL) +#define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */ +#define RIFSC_RISC_SECCFGRx_SEC25_Pos (25UL) +#define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */ +#define RIFSC_RISC_SECCFGRx_SEC26_Pos (26UL) +#define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */ +#define RIFSC_RISC_SECCFGRx_SEC27_Pos (27UL) +#define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */ +#define RIFSC_RISC_SECCFGRx_SEC28_Pos (28UL) +#define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */ +#define RIFSC_RISC_SECCFGRx_SEC29_Pos (29UL) +#define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */ +#define RIFSC_RISC_SECCFGRx_SEC30_Pos (30UL) +#define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */ +#define RIFSC_RISC_SECCFGRx_SEC31_Pos (31UL) +#define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/ +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */ + +/**************** Bit definition for RIFSC_RIMC_CR register *****************/ +#define RIFSC_RIMC_CR_GLOCK_Pos (0UL) +#define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */ +#define RIFSC_RIMC_CR_DAPCID_Pos (8UL) +#define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */ +#define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */ +#define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */ + +/*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/ +#define RIFSC_RIMC_ATTRx_MCID_Pos (4UL) +#define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */ +#define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */ +#define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */ +#define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */ +#define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */ +#define RIFSC_RIMC_ATTRx_MSEC_Pos (8UL) +#define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */ +#define RIFSC_RIMC_ATTRx_MPRIV_Pos (9UL) +#define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */ + +/******************************************************************************/ +/* */ +/* Resource Isolation Slave unit for Address space protection (RISAF) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RISAF_CR register *******************/ +#define RISAF_CR_GLOCK_Pos (0UL) +#define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */ + +/****************** Bit definition for RISAF_IASR register ******************/ +#define RISAF_IASR_CAEF_Pos (0UL) +#define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IASR_IAEF_Pos (1UL) +#define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */ + +/****************** Bit definition for RISAF_IACR register ******************/ +#define RISAF_IACR_CAEF_Pos (0UL) +#define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IACR_IAEF_Pos (1UL) +#define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */ + +/***************** Bit definition for RISAF_IAESR register *****************/ +#define RISAF_IAESR_IACID_Pos (0UL) +#define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */ +#define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */ +#define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */ +#define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */ +#define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */ +#define RISAF_IAESR_IAPRIV_Pos (4UL) +#define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */ +#define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */ +#define RISAF_IAESR_IASEC_Pos (5UL) +#define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */ +#define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */ +#define RISAF_IAESR_IANRW_Pos (7UL) +#define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */ +#define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */ + +/***************** Bit definition for RISAF_IADDR register *****************/ +#define RISAF_IADDR_IADD_Pos (0UL) +#define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */ +#define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */ +#define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */ +#define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */ +#define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */ +#define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */ +#define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */ +#define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */ +#define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */ +#define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */ +#define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */ +#define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */ +#define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */ +#define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */ +#define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */ +#define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */ +#define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */ +#define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */ +#define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */ +#define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */ +#define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */ +#define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */ +#define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */ +#define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */ +#define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */ +#define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */ +#define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */ +#define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */ +#define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */ +#define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */ +#define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */ +#define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */ +#define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_CFGR register ****************/ +#define RISAF_REGx_CFGR_BREN_Pos (0UL) +#define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */ +#define RISAF_REGx_CFGR_SEC_Pos (8UL) +#define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */ +#define RISAF_REGx_CFGR_PRIVC0_Pos (16UL) +#define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */ +#define RISAF_REGx_CFGR_PRIVC1_Pos (17UL) +#define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */ +#define RISAF_REGx_CFGR_PRIVC2_Pos (18UL) +#define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */ +#define RISAF_REGx_CFGR_PRIVC3_Pos (19UL) +#define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */ +#define RISAF_REGx_CFGR_PRIVC4_Pos (20UL) +#define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */ +#define RISAF_REGx_CFGR_PRIVC5_Pos (21UL) +#define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */ +#define RISAF_REGx_CFGR_PRIVC6_Pos (22UL) +#define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */ +#define RISAF_REGx_CFGR_PRIVC7_Pos (23UL) +#define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */ + +/************** Bit definition for RISAF_REGx_STARTR register ***************/ +#define RISAF_REGx_STARTR_BADDSTART_Pos (0UL) +#define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */ +#define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_ENDR register ****************/ +#define RISAF_REGx_ENDR_BADDEND_Pos (0UL) +#define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */ +#define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_CIDCFGR register **************/ +#define RISAF_REGx_CIDCFGR_RDENC0_Pos (0UL) +#define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_RDENC1_Pos (1UL) +#define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_RDENC2_Pos (2UL) +#define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_RDENC3_Pos (3UL) +#define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_RDENC4_Pos (4UL) +#define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_RDENC5_Pos (5UL) +#define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_RDENC6_Pos (6UL) +#define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_RDENC7_Pos (7UL) +#define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */ +#define RISAF_REGx_CIDCFGR_WRENC0_Pos (16UL) +#define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_WRENC1_Pos (17UL) +#define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_WRENC2_Pos (18UL) +#define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_WRENC3_Pos (19UL) +#define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_WRENC4_Pos (20UL) +#define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_WRENC5_Pos (21UL) +#define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_WRENC6_Pos (22UL) +#define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_WRENC7_Pos (23UL) +#define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */ + +/*************** Bit definition for RISAF_REGx_zCFGR register ***************/ +#define RISAF_REGx_zCFGR_SREN_Pos (0UL) +#define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */ +#define RISAF_REGx_zCFGR_RLOCK_Pos (1UL) +#define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */ +#define RISAF_REGx_zCFGR_SRCID_Pos (4UL) +#define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */ +#define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zCFGR_SEC_Pos (8UL) +#define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */ +#define RISAF_REGx_zCFGR_PRIV_Pos (9UL) +#define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */ +#define RISAF_REGx_zCFGR_RDEN_Pos (12UL) +#define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */ +#define RISAF_REGx_zCFGR_WREN_Pos (13UL) +#define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */ + +/************** Bit definition for RISAF_REGx_zSTARTR register **************/ +#define RISAF_REGx_zSTARTR_SADDSTART_Pos (0UL) +#define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */ +#define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_zENDR register ***************/ +#define RISAF_REGx_zENDR_SADDEND_Pos (0UL) +#define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */ +#define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_zNESTR register ***************/ +#define RISAF_REGx_zNESTR_DCEN_Pos (2UL) +#define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */ +#define RISAF_REGx_zNESTR_DCCID_Pos (4UL) +#define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */ +#define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */ + +/******************************************************************************/ +/* */ +/* (IAC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IAC_IER0 register *******************/ +#define IAC_IERx_IAIE0_Pos (0UL) +#define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */ +#define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_IERx_IAIE1_Pos (1UL) +#define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */ +#define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_IERx_IAIE2_Pos (2UL) +#define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */ +#define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_IERx_IAIE3_Pos (3UL) +#define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */ +#define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_IERx_IAIE4_Pos (4UL) +#define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */ +#define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_IERx_IAIE5_Pos (5UL) +#define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */ +#define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_IERx_IAIE6_Pos (6UL) +#define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */ +#define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_IERx_IAIE7_Pos (7UL) +#define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */ +#define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_IERx_IAIE8_Pos (8UL) +#define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */ +#define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_IERx_IAIE9_Pos (9UL) +#define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */ +#define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_IERx_IAIE10_Pos (10UL) +#define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */ +#define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_IERx_IAIE11_Pos (11UL) +#define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */ +#define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_IERx_IAIE12_Pos (12UL) +#define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */ +#define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_IERx_IAIE13_Pos (13UL) +#define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */ +#define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_IERx_IAIE14_Pos (14UL) +#define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */ +#define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_IERx_IAIE15_Pos (15UL) +#define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */ +#define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_IERx_IAIE16_Pos (16UL) +#define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */ +#define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_IERx_IAIE17_Pos (17UL) +#define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */ +#define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_IERx_IAIE18_Pos (18UL) +#define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */ +#define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_IERx_IAIE19_Pos (19UL) +#define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */ +#define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_IERx_IAIE20_Pos (20UL) +#define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */ +#define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_IERx_IAIE21_Pos (21UL) +#define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */ +#define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_IERx_IAIE22_Pos (22UL) +#define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */ +#define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_IERx_IAIE23_Pos (23UL) +#define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */ +#define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_IERx_IAIE24_Pos (24UL) +#define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */ +#define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_IERx_IAIE25_Pos (25UL) +#define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */ +#define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_IERx_IAIE26_Pos (26UL) +#define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */ +#define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_IERx_IAIE27_Pos (27UL) +#define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */ +#define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_IERx_IAIE28_Pos (28UL) +#define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */ +#define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_IERx_IAIE29_Pos (29UL) +#define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */ +#define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_IERx_IAIE30_Pos (30UL) +#define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */ +#define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_IERx_IAIE31_Pos (31UL) +#define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */ +#define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ISRx register *******************/ +#define IAC_ISRx_IAF0_Pos (0UL) +#define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_ISRx_IAF1_Pos (1UL) +#define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_ISRx_IAF2_Pos (2UL) +#define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_ISRx_IAF3_Pos (3UL) +#define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_ISRx_IAF4_Pos (4UL) +#define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_ISRx_IAF5_Pos (5UL) +#define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_ISRx_IAF6_Pos (6UL) +#define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_ISRx_IAF7_Pos (7UL) +#define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_ISRx_IAF8_Pos (8UL) +#define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_ISRx_IAF9_Pos (9UL) +#define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_ISRx_IAF10_Pos (10UL) +#define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_ISRx_IAF11_Pos (11UL) +#define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_ISRx_IAF12_Pos (12UL) +#define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_ISRx_IAF13_Pos (13UL) +#define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_ISRx_IAF14_Pos (14UL) +#define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_ISRx_IAF15_Pos (15UL) +#define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_ISRx_IAF16_Pos (16UL) +#define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_ISRx_IAF17_Pos (17UL) +#define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_ISRx_IAF18_Pos (18UL) +#define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_ISRx_IAF19_Pos (19UL) +#define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_ISRx_IAF20_Pos (20UL) +#define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_ISRx_IAF21_Pos (21UL) +#define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_ISRx_IAF22_Pos (22UL) +#define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_ISRx_IAF23_Pos (23UL) +#define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_ISRx_IAF24_Pos (24UL) +#define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_ISRx_IAF25_Pos (25UL) +#define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_ISRx_IAF26_Pos (26UL) +#define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_ISRx_IAF27_Pos (27UL) +#define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_ISRx_IAF28_Pos (28UL) +#define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_ISRx_IAF29_Pos (29UL) +#define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_ISRx_IAF30_Pos (30UL) +#define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_ISRx_IAF31_Pos (31UL) +#define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ICRx register *******************/ +#define IAC_ICRx_IAF0_Pos (0UL) +#define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */ +#define IAC_ICRx_IAF1_Pos (1UL) +#define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */ +#define IAC_ICRx_IAF2_Pos (2UL) +#define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */ +#define IAC_ICRx_IAF3_Pos (3UL) +#define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */ +#define IAC_ICRx_IAF4_Pos (4UL) +#define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */ +#define IAC_ICRx_IAF5_Pos (5UL) +#define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */ +#define IAC_ICRx_IAF6_Pos (6UL) +#define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */ +#define IAC_ICRx_IAF7_Pos (7UL) +#define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */ +#define IAC_ICRx_IAF8_Pos (8UL) +#define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */ +#define IAC_ICRx_IAF9_Pos (9UL) +#define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */ +#define IAC_ICRx_IAF10_Pos (10UL) +#define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */ +#define IAC_ICRx_IAF11_Pos (11UL) +#define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */ +#define IAC_ICRx_IAF12_Pos (12UL) +#define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */ +#define IAC_ICRx_IAF13_Pos (13UL) +#define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */ +#define IAC_ICRx_IAF14_Pos (14UL) +#define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */ +#define IAC_ICRx_IAF15_Pos (15UL) +#define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */ +#define IAC_ICRx_IAF16_Pos (16UL) +#define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */ +#define IAC_ICRx_IAF17_Pos (17UL) +#define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */ +#define IAC_ICRx_IAF18_Pos (18UL) +#define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */ +#define IAC_ICRx_IAF19_Pos (19UL) +#define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */ +#define IAC_ICRx_IAF20_Pos (20UL) +#define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */ +#define IAC_ICRx_IAF21_Pos (21UL) +#define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */ +#define IAC_ICRx_IAF22_Pos (22UL) +#define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */ +#define IAC_ICRx_IAF23_Pos (23UL) +#define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */ +#define IAC_ICRx_IAF24_Pos (24UL) +#define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */ +#define IAC_ICRx_IAF25_Pos (25UL) +#define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */ +#define IAC_ICRx_IAF26_Pos (26UL) +#define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */ +#define IAC_ICRx_IAF27_Pos (27UL) +#define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */ +#define IAC_ICRx_IAF28_Pos (28UL) +#define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */ +#define IAC_ICRx_IAF29_Pos (29UL) +#define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */ +#define IAC_ICRx_IAF30_Pos (30UL) +#define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */ +#define IAC_ICRx_IAF31_Pos (31UL) +#define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */ + +/****************** Bit definition for IAC_IISRx register *******************/ +#define IAC_IISRx_ILACIN0_Pos (0UL) +#define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */ +#define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN1_Pos (1UL) +#define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */ +#define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN2_Pos (2UL) +#define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */ +#define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN3_Pos (3UL) +#define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */ +#define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN4_Pos (4UL) +#define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */ +#define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN5_Pos (5UL) +#define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */ +#define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN6_Pos (6UL) +#define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */ +#define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN7_Pos (7UL) +#define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */ +#define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN8_Pos (8UL) +#define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */ +#define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN9_Pos (9UL) +#define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */ +#define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN10_Pos (10UL) +#define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */ +#define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN11_Pos (11UL) +#define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */ +#define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN12_Pos (12UL) +#define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */ +#define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN13_Pos (13UL) +#define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */ +#define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN14_Pos (14UL) +#define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */ +#define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN15_Pos (15UL) +#define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */ +#define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN16_Pos (16UL) +#define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */ +#define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN17_Pos (17UL) +#define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */ +#define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN18_Pos (18UL) +#define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */ +#define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN19_Pos (19UL) +#define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */ +#define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN20_Pos (20UL) +#define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */ +#define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN21_Pos (21UL) +#define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */ +#define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN22_Pos (22UL) +#define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */ +#define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN23_Pos (23UL) +#define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */ +#define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN24_Pos (24UL) +#define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */ +#define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN25_Pos (25UL) +#define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */ +#define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN26_Pos (26UL) +#define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */ +#define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN27_Pos (27UL) +#define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */ +#define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN28_Pos (28UL) +#define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */ +#define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN29_Pos (29UL) +#define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */ +#define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN30_Pos (30UL) +#define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */ +#define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN31_Pos (31UL) +#define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */ +#define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0UL) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4UL) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8UL) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12UL) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16UL) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20UL) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22UL) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0UL) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4UL) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8UL) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12UL) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13UL) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16UL) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20UL) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0UL) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2UL) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3UL) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4UL) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5UL) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6UL) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7UL) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8UL) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10UL) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16UL) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0UL) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16UL) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0UL) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16UL) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0UL) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3UL) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4UL) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5UL) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6UL) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7UL) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8UL) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9UL) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10UL) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11UL) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12UL) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13UL) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14UL) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15UL) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16UL) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17UL) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18UL) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19UL) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20UL) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21UL) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23UL) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24UL) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0UL) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief RAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */ + __IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */ + __IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */ + __IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */ + uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */ + __IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */ + __IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */ + __IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */ + __IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */ + __IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */ + __IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */ + __IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */ + __IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */ + __IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */ + __IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */ + __IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */ + __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */ + __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */ + __IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */ + __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */ + __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */ + __IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */ + __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */ + __IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */ + __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */ + __IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */ + __IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */ + __IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */ + __IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */ + __IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */ + __IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */ + __IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */ + __IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */ + __IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */ + __IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */ + __IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */ + __IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */ + __IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */ + __IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */ + __IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */ + __IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */ + __IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */ + __IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */ + __IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */ + __IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */ + __IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */ + uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */ + __IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */ + __IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */ + __IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */ + __IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */ + __IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */ + __IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */ + __IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */ + __IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */ + __IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */ + __IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */ + __IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */ + __IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */ + uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */ + __IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */ + __IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */ + __IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */ + uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */ + __IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */ + __IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */ + __IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */ + __IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */ + __IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */ + __IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */ + __IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */ + __IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */ + __IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */ + __IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */ + __IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */ + __IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */ + __IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */ + __IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */ + __IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */ + __IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */ + uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */ + __IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */ + uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */ + __IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */ + __IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */ + __IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */ + __IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */ + __IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */ + __IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */ + __IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */ + __IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */ + __IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */ + __IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */ + __IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */ + __IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */ + __IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */ + __IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */ + __IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */ + __IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */ + __IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */ + __IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */ + __IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */ + __IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */ + __IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */ + uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */ + __IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */ + __IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */ + uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */ + __IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */ + __IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */ + __IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */ + __IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */ + __IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */ + __IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */ + __IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */ + __IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */ + __IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */ + __IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */ + __IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */ + __IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */ + __IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */ + __IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */ + __IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */ + __IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */ + __IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */ + __IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */ + __IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */ + __IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */ + __IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */ + __IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */ + __IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */ + __IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */ + __IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */ + __IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */ + __IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */ + __IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */ + __IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */ + __IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */ + __IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */ + __IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */ + __IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */ + __IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */ + __IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */ + __IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */ + __IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */ + __IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */ + __IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */ + __IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */ + __IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */ + __IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */ + __IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */ + __IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */ + uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */ + __IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */ + __IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */ + __IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */ + uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */ + __IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */ + __IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */ + uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */ + __IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */ + __IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */ + uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */ + __IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */ + uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */ + __IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */ + __IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */ + __IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */ + uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */ + __IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */ + uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */ + __IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */ + uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */ + __IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */ + __IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */ + __IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */ + __IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */ + __IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */ + __IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */ + __IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */ + __IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */ + __IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */ + __IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */ + __IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */ + __IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */ + __IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */ + __IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */ + __IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */ + __IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */ + __IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */ + __IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */ + __IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */ + __IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */ + __IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */ + __IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */ + __IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */ + __IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */ + __IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */ + __IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */ + __IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */ + __IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */ + __IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */ + __IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */ + __IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */ + __IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */ + __IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */ + __IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */ + __IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */ + __IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */ + __IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */ + __IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */ + __IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */ + __IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */ + __IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */ + __IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */ + __IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */ + __IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */ + uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */ + __IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */ + uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */ + __IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */ + __IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */ + __IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */ + __IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */ + __IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */ + __IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */ + __IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */ + __IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */ + __IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */ + __IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */ +} RCC_TypeDef; + +/* + * @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1) + */ +typedef struct +{ + __IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */ + __IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */ + __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */ + uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */ + __IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */ + __IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */ + uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */ + __IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */ + uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */ +} RIFSC_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) + */ +typedef struct +{ + __IO uint32_t CFGR; /*!< RISAF Region X configuration register */ + __IO uint32_t STARTR; /*!< RISAF Region X start address register */ + __IO uint32_t ENDR; /*!< RISAF Region X end address register */ + __IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */ + __IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */ + __IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */ + __IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */ + __IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */ + __IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */ + __IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */ + __IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */ + __IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */ + uint32_t RESERVED0[4]; /*!< Reserved */ +} RISAF_Region_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t IAESR; /*!< RISAF Illegal access error status register */ + __IO uint32_t IADDR; /*!< RISAF Illegal address register, */ +} RISAF_Illegal_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */ + RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */ + RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */ +} RISAF_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 7U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ +__IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x004 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x008 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x00C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x010 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x014 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x018 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x01C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x020 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x024 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x028 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x02C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x030 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x034 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x038 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x03C */ + uint32_t RESERVED1[48]; /*!< Reserved, Address offset: 0x040 -- 0x0FC */ + __IO uint32_t DPACFGR; /*!< SAES DPA configuration register, Address offset: 0x100 */ + uint32_t RESERVED2[127]; /*!< Reserved, Address offset: 0x104 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + __IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */ +} USB_PHY_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + __IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + __IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + __IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + __IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + __IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */ +} USB_HS_PHYC_GlobalTypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */ + __IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */ + __IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */ + __IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */ + __IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */ + __IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */ + __IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */ + __IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */ + __IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */ + __IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */ + __IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */ + __IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x44 */ + __IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x48 */ + __IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x4C */ + __IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x50 */ + __IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x54 */ + __IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x58 */ + __IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x5C */ + __IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x60 */ + __IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */ + __IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */ + __IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */ + __IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */ + uint32_t RESERVED3[34]; /*!< Reserved, Address offset: 0x78-0xFC */ + __IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */ + __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */ + uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */ + __IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */ + uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */ + __IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Extended-SPI Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** @} */ /* End of group STM32N6xx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal RAMs sizes */ +#define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */ +#define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */ +#define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */ +#define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */ +#define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */ +#define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */ +#define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */ +#define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */ +#define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */ +#define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */ +#define SRAM7_AXI_SIZE 0x40000UL /*!< SRAM7_AXI = 256 Kbytes */ +#define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */ + + +#define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */ +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK5_1 FMC_BANK5 +#define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL) +#define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL) +#define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL) +#define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK6_1 FMC_BANK6 +#define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL) +#define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL) +#define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL) +#define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */ +#define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */ +#define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */ + +/**************************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */ +/* */ +/**************************************************************************/ + +#define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define SRAM7_AXI_BASE_NS 0x243C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */ +#define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL) +#define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL) +#define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL) +#define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL) +#define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL) +#define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL) +#define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL) +#define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL) +#define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL) +#define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL) +#define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) +#define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL) +#define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL) +#define CRYP_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define SAES_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL) +#define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL) +#define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL) +#define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL) +#define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL) +#define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL) +#define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL) +#define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL) +#define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL) +#define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL) +#define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL) +#define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL) +#define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL) +#define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL) +#define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL) +#define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL) +#define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL) +#define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL) +#define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL) +#define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL) +#define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL) +#define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL) +#define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL) +#define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL) +#define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL) +#define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL) +#define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL) +#define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL) +#define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL) +#define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL) +#define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL) +#define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL) +#define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL) +#define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL) +#define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL) +#define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL) +#define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL) +#define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL) +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL) +#define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL) +#define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL) +#define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL) +#define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL) +#define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL) +#define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL) +#define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL) +#define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL) +#define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL) +#define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL) +#define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL) +#define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL) +#define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL) +#define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL) +#define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL) +#define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL) +#define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL) +#define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL) +#define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL) +#define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL) +#define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL) +#define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL) +#define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL) +#define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL) +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) +#define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL) +#define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL) +#define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL) +#define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL) +#define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL) +#define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL) +#define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL) +#define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL) +#define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL) +#define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL) +#define MCE1_BASE_NS (AHB5PERIPH_BASE_NS + 0xB800UL) +#define MCE1_REGION1_BASE_NS (MCE1_BASE_NS + 0x040UL) +#define MCE1_REGION2_BASE_NS (MCE1_BASE_NS + 0x050UL) +#define MCE1_REGION3_BASE_NS (MCE1_BASE_NS + 0x060UL) +#define MCE1_REGION4_BASE_NS (MCE1_BASE_NS + 0x070UL) +#define MCE1_CONTEXT1_BASE_NS (MCE1_BASE_NS + 0x240UL) +#define MCE1_CONTEXT2_BASE_NS (MCE1_BASE_NS + 0x270UL) +#define MCE2_BASE_NS (AHB5PERIPH_BASE_NS + 0xBC00UL) +#define MCE2_REGION1_BASE_NS (MCE2_BASE_NS + 0x040UL) +#define MCE2_REGION2_BASE_NS (MCE2_BASE_NS + 0x050UL) +#define MCE2_REGION3_BASE_NS (MCE2_BASE_NS + 0x060UL) +#define MCE2_REGION4_BASE_NS (MCE2_BASE_NS + 0x070UL) +#define MCE2_CONTEXT1_BASE_NS (MCE2_BASE_NS + 0x240UL) +#define MCE2_CONTEXT2_BASE_NS (MCE2_BASE_NS + 0x270UL) +#define MCE3_BASE_NS (AHB5PERIPH_BASE_NS + 0xC000UL) +#define MCE3_REGION1_BASE_NS (MCE3_BASE_NS + 0x040UL) +#define MCE3_REGION2_BASE_NS (MCE3_BASE_NS + 0x050UL) +#define MCE3_REGION3_BASE_NS (MCE3_BASE_NS + 0x060UL) +#define MCE3_REGION4_BASE_NS (MCE3_BASE_NS + 0x070UL) +#define MCE3_CONTEXT1_BASE_NS (MCE3_BASE_NS + 0x240UL) +#define MCE3_CONTEXT2_BASE_NS (MCE3_BASE_NS + 0x270UL) +#define MCE4_BASE_NS (AHB5PERIPH_BASE_NS + 0xE000UL) +#define MCE4_REGION1_BASE_NS (MCE4_BASE_NS + 0x040UL) +#define MCE4_REGION2_BASE_NS (MCE4_BASE_NS + 0x050UL) +#define MCE4_REGION3_BASE_NS (MCE4_BASE_NS + 0x060UL) +#define MCE4_REGION4_BASE_NS (MCE4_BASE_NS + 0x070UL) +#define MCE4_CONTEXT1_BASE_NS (MCE4_BASE_NS + 0x240UL) +#define MCE4_CONTEXT2_BASE_NS (MCE4_BASE_NS + 0x270UL) +#define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL) +#define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL) +#define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL) +#define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL) +#define ETH1_MAC_BASE_NS (ETH1_BASE_NS) +#define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL) +#define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL) +#define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_NS (0x46009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_NS (BOOTROM_BASE_NS + 0x001004UL) + + +#if defined (CPU_IN_SECURE_STATE) +/*********************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */ +/* */ +/*********************************************************************/ +#define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define SRAM7_AXI_BASE_S 0x343C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */ +#define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL) +#define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL) +#define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL) +#define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL) +#define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL) +#define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL) +#define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL) +#define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL) +#define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL) +#define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL) +#define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) +#define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL) +#define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL) +#define CRYP_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define SAES_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL) +#define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL) +#define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL) +#define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL) +#define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL) +#define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL) +#define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL) +#define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL) +#define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL) +#define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL) +#define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL) +#define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL) +#define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL) +#define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL) +#define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL) +#define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL) +#define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL) +#define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL) +#define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL) +#define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL) +#define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL) +#define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL) +#define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL) +#define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL) +#define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL) + +#define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL) +#define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL) +#define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL) +#define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL) +#define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL) +#define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL) +#define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL) +#define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL) +#define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL) +#define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL) +#define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL) +#define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL) +#define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL) +#define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL) +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL) +#define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL) +#define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL) +#define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL) +#define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL) +#define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL) +#define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL) +#define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL) +#define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL) +#define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL) +#define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL) +#define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL) +#define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL) +#define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL) +#define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL) +#define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL) +#define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL) +#define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL) +#define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL) +#define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL) +#define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL) +#define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL) +#define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL) +#define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL) +#define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) +#define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL) +#define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL) +#define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL) +#define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL) +#define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL) +#define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL) +#define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL) +#define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL) +#define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL) +#define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL) +#define MCE1_BASE_S (AHB5PERIPH_BASE_S + 0xB800UL) +#define MCE1_REGION1_BASE_S (MCE1_BASE_S + 0x040UL) +#define MCE1_REGION2_BASE_S (MCE1_BASE_S + 0x050UL) +#define MCE1_REGION3_BASE_S (MCE1_BASE_S + 0x060UL) +#define MCE1_REGION4_BASE_S (MCE1_BASE_S + 0x070UL) +#define MCE1_CONTEXT1_BASE_S (MCE1_BASE_S + 0x240UL) +#define MCE1_CONTEXT2_BASE_S (MCE1_BASE_S + 0x270UL) +#define MCE2_BASE_S (AHB5PERIPH_BASE_S + 0xBC00UL) +#define MCE2_REGION1_BASE_S (MCE2_BASE_S + 0x040UL) +#define MCE2_REGION2_BASE_S (MCE2_BASE_S + 0x050UL) +#define MCE2_REGION3_BASE_S (MCE2_BASE_S + 0x060UL) +#define MCE2_REGION4_BASE_S (MCE2_BASE_S + 0x070UL) +#define MCE2_CONTEXT1_BASE_S (MCE2_BASE_S + 0x240UL) +#define MCE2_CONTEXT2_BASE_S (MCE2_BASE_S + 0x270UL) +#define MCE3_BASE_S (AHB5PERIPH_BASE_S + 0xC000UL) +#define MCE3_REGION1_BASE_S (MCE3_BASE_S + 0x040UL) +#define MCE3_REGION2_BASE_S (MCE3_BASE_S + 0x050UL) +#define MCE3_REGION3_BASE_S (MCE3_BASE_S + 0x060UL) +#define MCE3_REGION4_BASE_S (MCE3_BASE_S + 0x070UL) +#define MCE3_CONTEXT1_BASE_S (MCE3_BASE_S + 0x240UL) +#define MCE3_CONTEXT2_BASE_S (MCE3_BASE_S + 0x270UL) +#define MCE4_BASE_S (AHB5PERIPH_BASE_S + 0xE000UL) +#define MCE4_REGION1_BASE_S (MCE4_BASE_S + 0x040UL) +#define MCE4_REGION2_BASE_S (MCE4_BASE_S + 0x050UL) +#define MCE4_REGION3_BASE_S (MCE4_BASE_S + 0x060UL) +#define MCE4_REGION4_BASE_S (MCE4_BASE_S + 0x070UL) +#define MCE4_CONTEXT1_BASE_S (MCE4_BASE_S + 0x240UL) +#define MCE4_CONTEXT2_BASE_S (MCE4_BASE_S + 0x270UL) +#define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL) +#define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL) +#define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL) +#define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL) +#define ETH1_MAC_BASE_S (ETH1_BASE_S) +#define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL) +#define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL) +#define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_S (0x56009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_S (BOOTROM_BASE_S + 0x001004UL) + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS) +#define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CRYP_NS ((CRYP_TypeDef *) CRYP_BASE_NS) +#define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS) +#define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS) +#define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS) +#define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS) +#define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS) +#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS) +#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) +#define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS) +#define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS) +#define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS) +#define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS) +#define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS) +#define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS) +#define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS) +#define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS) +#define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS) +#define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS) +#define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS) +#define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS) +#define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS) +#define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS) +#define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS) +#define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS) +#define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS) +#define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS) +#define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS) +#define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS) +#define MCE1_NS ((MCE_TypeDef *) MCE1_BASE_NS) +#define MCE1_REGION1_NS ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS) +#define MCE1_REGION2_NS ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS) +#define MCE1_REGION3_NS ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS) +#define MCE1_REGION4_NS ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS) +#define MCE1_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS) +#define MCE1_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS) +#define MCE2_NS ((MCE_TypeDef *) MCE2_BASE_NS) +#define MCE2_REGION1_NS ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS) +#define MCE2_REGION2_NS ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS) +#define MCE2_REGION3_NS ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS) +#define MCE2_REGION4_NS ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS) +#define MCE2_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS) +#define MCE2_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS) +#define MCE3_NS ((MCE_TypeDef *) MCE3_BASE_NS) +#define MCE3_REGION1_NS ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS) +#define MCE3_REGION2_NS ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS) +#define MCE3_REGION3_NS ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS) +#define MCE3_REGION4_NS ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS) +#define MCE3_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS) +#define MCE3_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS) +#define MCE4_NS ((MCE_TypeDef *) MCE4_BASE_NS) +#define MCE4_REGION1_NS ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS) +#define MCE4_REGION2_NS ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS) +#define MCE4_REGION3_NS ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS) +#define MCE4_REGION4_NS ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS) +#define MCE4_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS) +#define MCE4_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS) +#define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS) +#define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS) +#define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS) +#define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS) +#define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS) +#define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS) +#define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS) +#define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS) +#define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS) +#define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS) +#define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS) +#define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS) +#define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS) +#define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS) +#define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS) +#define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS) +#define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS) +#define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS) +#define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS) +#define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS) +#define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS) +#define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS) +#define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS) +#define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS) +#define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((SAES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS) +#define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS) +#define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define UART7_NS ((USART_TypeDef *) UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *) UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *) UART9_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *) USART10_BASE_NS) +#define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS) +#define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS) +#define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS) +#define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS) +#define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS) +#define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS) +#define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS) +#define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S) +#define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CRYP_S ((CRYP_TypeDef *) CRYP_BASE_S) +#define CSI_S ((CSI_TypeDef *) CSI_BASE_S) +#define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define DTS_S ((DTS_TypeDef *) DTS_BASE_S) +#define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S) +#define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S) +#define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S) +#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S) +#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) +#define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPION_S ((GPIO_TypeDef *) GPION_BASE_S) +#define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S) +#define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S) +#define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S) +#define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S) +#define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S) +#define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S) +#define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S) +#define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S) +#define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S) +#define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S) +#define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S) +#define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S) +#define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S) +#define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S) +#define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S) +#define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S) +#define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S) +#define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S) +#define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define IAC_S ((IAC_TypeDef *) IAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S) +#define MCE1_S ((MCE_TypeDef *) MCE1_BASE_S) +#define MCE1_REGION1_S ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S) +#define MCE1_REGION2_S ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S) +#define MCE1_REGION3_S ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S) +#define MCE1_REGION4_S ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S) +#define MCE1_CONTEXT1_S ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S) +#define MCE1_CONTEXT2_S ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S) +#define MCE2_S ((MCE_TypeDef *) MCE2_BASE_S) +#define MCE2_REGION1_S ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S) +#define MCE2_REGION2_S ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S) +#define MCE2_REGION3_S ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S) +#define MCE2_REGION4_S ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S) +#define MCE2_CONTEXT1_S ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S) +#define MCE2_CONTEXT2_S ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S) +#define MCE3_S ((MCE_TypeDef *) MCE3_BASE_S) +#define MCE3_REGION1_S ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S) +#define MCE3_REGION2_S ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S) +#define MCE3_REGION3_S ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S) +#define MCE3_REGION4_S ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S) +#define MCE3_CONTEXT1_S ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S) +#define MCE3_CONTEXT2_S ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S) +#define MCE4_S ((MCE_TypeDef *) MCE4_BASE_S) +#define MCE4_REGION1_S ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S) +#define MCE4_REGION2_S ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S) +#define MCE4_REGION3_S ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S) +#define MCE4_REGION4_S ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S) +#define MCE4_CONTEXT1_S ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S) +#define MCE4_CONTEXT2_S ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S) +#define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S) +#define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S) +#define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S) +#define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S) +#define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S) +#define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S) +#define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S) +#define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S) +#define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S) +#define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S) +#define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S) +#define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S) +#define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S) +#define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S) +#define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S) +#define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S) +#define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S) +#define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S) +#define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S) +#define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S) +#define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S) +#define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S) +#define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S) +#define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S) +#define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((SAES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S) +#define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S) +#define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define UART7_S ((USART_TypeDef *) UART7_BASE_S) +#define UART8_S ((USART_TypeDef *) UART8_BASE_S) +#define UART9_S ((USART_TypeDef *) UART9_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define USART10_S ((USART_TypeDef *) USART10_BASE_S) +#define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S) +#define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S) +#define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S) +#define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S) +#define VENC_S ((VENC_TypeDef *) VENC_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S) +#define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S) +#define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S) +#define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S) +#endif + +/*!< Peripheral Instance aliases for Non-Secure/Secure execution */ +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define BSEC BSEC_S +#define BSEC_BASE BSEC_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define CRYP CRYP_S +#define CRYP_BASE CRYP_BASE_S + +#define CSI CSI_S +#define CSI_BASE CSI_BASE_S + +#define DBGMCU DBGMCU_S +#define DBGMCU_BASE DBGMCU_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define DCMIPP DCMIPP_S +#define DCMIPP_BASE DCMIPP_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define DTS_Sensor0 DTS_Sensor0_S +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_S + +#define DTS_Sensor1 DTS_Sensor1_S +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_S + +#define ETH1 ETH1_S +#define ETH1_BASE ETH1_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define FDCAN3 FDCAN3_S +#define FDCAN3_BASE FDCAN3_BASE_S + +#define FDCAN_CCU FDCAN_CCU_S +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S + +#define FMC_R_BASE FMC_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define FMC_Common_R FMC_Common_R_S +#define FMC_Common_R_BASE FMC_Common_R_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPION GPION_S +#define GPION_BASE GPION_BASE_S + +#define GPIOO GPIOO_S +#define GPIOO_BASE GPIOO_BASE_S + +#define GPIOP GPIOP_S +#define GPIOP_BASE GPIOP_BASE_S + +#define GPIOQ GPIOQ_S +#define GPIOQ_BASE GPIOQ_BASE_S + +#define GPU2D GPU2D_BASE_S +#define GPU2D_BASE GPU2D_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define HPDMA1 HPDMA1_S +#define HPDMA1_BASE HPDMA1_BASE_S + +#define HPDMA1_Channel0 HPDMA1_Channel0_S +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S + +#define HPDMA1_Channel1 HPDMA1_Channel1_S +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S + +#define HPDMA1_Channel2 HPDMA1_Channel2_S +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S + +#define HPDMA1_Channel3 HPDMA1_Channel3_S +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S + +#define HPDMA1_Channel4 HPDMA1_Channel4_S +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S + +#define HPDMA1_Channel5 HPDMA1_Channel5_S +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S + +#define HPDMA1_Channel6 HPDMA1_Channel6_S +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S + +#define HPDMA1_Channel7 HPDMA1_Channel7_S +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S + +#define HPDMA1_Channel8 HPDMA1_Channel8_S +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S + +#define HPDMA1_Channel9 HPDMA1_Channel9_S +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S + +#define HPDMA1_Channel10 HPDMA1_Channel10_S +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S + +#define HPDMA1_Channel11 HPDMA1_Channel11_S +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S + +#define HPDMA1_Channel12 HPDMA1_Channel12_S +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S + +#define HPDMA1_Channel13 HPDMA1_Channel13_S +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S + +#define HPDMA1_Channel14 HPDMA1_Channel14_S +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S + +#define HPDMA1_Channel15 HPDMA1_Channel15_S +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define IAC IAC_S +#define IAC_BASE IAC_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1 LTDC_Layer1_S +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S + +#define LTDC_Layer2 LTDC_Layer2_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define MCE1 MCE1_S +#define MCE1_BASE MCE1_BASE_S + +#define MCE1_REGION1 MCE1_REGION1_S +#define MCE1_REGION1_BASE MCE1_REGION1_BASE_S + +#define MCE1_REGION2 MCE1_REGION2_S +#define MCE1_REGION2_BASE MCE1_REGION2_BASE_S + +#define MCE1_REGION3 MCE1_REGION3_S +#define MCE1_REGION3_BASE MCE1_REGION3_BASE_S + +#define MCE1_REGION4 MCE1_REGION4_S +#define MCE1_REGION4_BASE MCE1_REGION4_BASE_S + +#define MCE1_CONTEXT1 MCE1_CONTEXT1_S +#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_S + +#define MCE1_CONTEXT2 MCE1_CONTEXT2_S +#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_S + +#define MCE2 MCE2_S +#define MCE2_BASE MCE2_BASE_S + +#define MCE2_REGION1 MCE2_REGION1_S +#define MCE2_REGION1_BASE MCE2_REGION1_BASE_S + +#define MCE2_REGION2 MCE2_REGION2_S +#define MCE2_REGION2_BASE MCE2_REGION2_BASE_S + +#define MCE2_REGION3 MCE2_REGION3_S +#define MCE2_REGION3_BASE MCE2_REGION3_BASE_S + +#define MCE2_REGION4 MCE2_REGION4_S +#define MCE2_REGION4_BASE MCE2_REGION4_BASE_S + +#define MCE2_CONTEXT1 MCE2_CONTEXT1_S +#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_S + +#define MCE2_CONTEXT2 MCE2_CONTEXT2_S +#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_S + +#define MCE3 MCE3_S +#define MCE3_BASE MCE3_BASE_S + +#define MCE3_REGION1 MCE3_REGION1_S +#define MCE3_REGION1_BASE MCE3_REGION1_BASE_S + +#define MCE3_REGION2 MCE3_REGION2_S +#define MCE3_REGION2_BASE MCE3_REGION2_BASE_S + +#define MCE3_REGION3 MCE3_REGION3_S +#define MCE3_REGION3_BASE MCE3_REGION3_BASE_S + +#define MCE3_REGION4 MCE3_REGION4_S +#define MCE3_REGION4_BASE MCE3_REGION4_BASE_S + +#define MCE3_CONTEXT1 MCE3_CONTEXT1_S +#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_S + +#define MCE3_CONTEXT2 MCE3_CONTEXT2_S +#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_S + +#define MCE4 MCE4_S +#define MCE4_BASE MCE4_BASE_S + +#define MCE4_REGION1 MCE4_REGION1_S +#define MCE4_REGION1_BASE MCE4_REGION1_BASE_S + +#define MCE4_REGION2 MCE4_REGION2_S +#define MCE4_REGION2_BASE MCE4_REGION2_BASE_S + +#define MCE4_REGION3 MCE4_REGION3_S +#define MCE4_REGION3_BASE MCE4_REGION3_BASE_S + +#define MCE4_REGION4 MCE4_REGION4_S +#define MCE4_REGION4_BASE MCE4_REGION4_BASE_S + +#define MCE4_CONTEXT1 MCE4_CONTEXT1_S +#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_S + +#define MCE4_CONTEXT2 MCE4_CONTEXT2_S +#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define MDIOS MDIOS_S +#define MDIOS_BASE MDIOS_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG RAMCFG_S +#define RAMCFG_BASE RAMCFG_BASE_S + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define RIFSC RIFSC_S +#define RIFSC_BASE RIFSC_BASE_S + +#define RISAF1 RISAF1_S +#define RISAF1_BASE RISAF1_BASE_S + +#define RISAF2 RISAF2_S +#define RISAF2_BASE RISAF2_BASE_S + +#define RISAF3 RISAF3_S +#define RISAF3_BASE RISAF3_BASE_S + +#define RISAF6 RISAF6_S +#define RISAF6_BASE RISAF6_BASE_S + +#define RISAF7 RISAF7_S +#define RISAF7_BASE RISAF7_BASE_S + +#define RISAF8 RISAF8_S +#define RISAF8_BASE RISAF8_BASE_S + +#define RISAF9 RISAF9_S +#define RISAF9_BASE RISAF9_BASE_S + +#define RISAF11 RISAF11_S +#define RISAF11_BASE RISAF11_BASE_S + +#define RISAF12 RISAF12_S +#define RISAF12_BASE RISAF12_BASE_S + +#define RISAF13 RISAF13_S +#define RISAF13_BASE RISAF13_BASE_S + +#define RISAF14 RISAF14_S +#define RISAF14_BASE RISAF14_BASE_S + +#define RISAF21 RISAF21_S +#define RISAF21_BASE RISAF21_BASE_S + +#define RISAF22 RISAF22_S +#define RISAF22_BASE RISAF22_BASE_S + +#define RISAF23 RISAF23_S +#define RISAF23_BASE RISAF23_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define SPDIFRX SPDIFRX_S +#define SPDIFRX_BASE SPDIFRX_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM9 TIM9_S +#define TIM9_BASE TIM9_BASE_S + +#define TIM10 TIM10_S +#define TIM10_BASE TIM10_BASE_S + +#define TIM11 TIM11_S +#define TIM11_BASE TIM11_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define TIM18 TIM18_S +#define TIM18_BASE TIM18_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USB1_OTG_HS USB1_OTG_HS_S +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S + +#define USB2_OTG_HS USB2_OTG_HS_S +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S + +#define USB1_HS_PHYC USB1_HS_PHYC_S +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S + +#define USB2_HS_PHYC USB2_HS_PHYC_S +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S + +#define VENC VENC_S +#define VENC_BASE VENC_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define XSPI1 XSPI1_S + +#define XSPI2 XSPI2_S + +#define XSPI3 XSPI3_S + +#define XSPIM XSPIM_S +#define XSPIM_BASE XSPIM_BASE_S + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_S + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_S + +#else + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS + +#define BSEC BSEC_NS +#define BSEC_BASE BSEC_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define CRYP CRYP_NS +#define CRYP_BASE CRYP_BASE_NS + +#define CSI CSI_NS +#define CSI_BASE CSI_BASE_NS + +#define DBGMCU DBGMCU_NS +#define DBGMCU_BASE DBGMCU_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define DCMIPP DCMIPP_NS +#define DCMIPP_BASE DCMIPP_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define DTS_Sensor0 DTS_Sensor0_NS +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS + +#define DTS_Sensor1 DTS_Sensor1_NS +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS + +#define ETH1 ETH1_NS +#define ETH1_BASE ETH1_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define FDCAN3 FDCAN3_NS +#define FDCAN3_BASE FDCAN3_BASE_NS + +#define FDCAN_CCU FDCAN_CCU_NS +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS + +#define FMC_R_BASE FMC_R_BASE_NS +#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define FMC_Common_R FMC_Common_R_NS +#define FMC_Common_R_BASE FMC_Common_R_BASE_NS + +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPION GPION_NS +#define GPION_BASE GPION_BASE_NS + +#define GPIOO GPIOO_NS +#define GPIOO_BASE GPIOO_BASE_NS + +#define GPIOP GPIOP_NS +#define GPIOP_BASE GPIOP_BASE_NS + +#define GPIOQ GPIOQ_NS +#define GPIOQ_BASE GPIOQ_BASE_NS + +#define GPU2D GPU2D_BASE_NS +#define GPU2D_BASE GPU2D_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define HPDMA1 HPDMA1_NS +#define HPDMA1_BASE HPDMA1_BASE_NS + +#define HPDMA1_Channel0 HPDMA1_Channel0_NS +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS + +#define HPDMA1_Channel1 HPDMA1_Channel1_NS +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS + +#define HPDMA1_Channel2 HPDMA1_Channel2_NS +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS + +#define HPDMA1_Channel3 HPDMA1_Channel3_NS +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS + +#define HPDMA1_Channel4 HPDMA1_Channel4_NS +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS + +#define HPDMA1_Channel5 HPDMA1_Channel5_NS +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS + +#define HPDMA1_Channel6 HPDMA1_Channel6_NS +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS + +#define HPDMA1_Channel7 HPDMA1_Channel7_NS +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS + +#define HPDMA1_Channel8 HPDMA1_Channel8_NS +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS + +#define HPDMA1_Channel9 HPDMA1_Channel9_NS +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS + +#define HPDMA1_Channel10 HPDMA1_Channel10_NS +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS + +#define HPDMA1_Channel11 HPDMA1_Channel11_NS +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS + +#define HPDMA1_Channel12 HPDMA1_Channel12_NS +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS + +#define HPDMA1_Channel13 HPDMA1_Channel13_NS +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS + +#define HPDMA1_Channel14 HPDMA1_Channel14_NS +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS + +#define HPDMA1_Channel15 HPDMA1_Channel15_NS +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define MCE1 MCE1_NS +#define MCE1_BASE MCE1_BASE_NS + +#define MCE1_REGION1 MCE1_REGION1_NS +#define MCE1_REGION1_BASE MCE1_REGION1_BASE_NS + +#define MCE1_REGION2 MCE1_REGION2_NS +#define MCE1_REGION2_BASE MCE1_REGION2_BASE_NS + +#define MCE1_REGION3 MCE1_REGION3_NS +#define MCE1_REGION3_BASE MCE1_REGION3_BASE_NS + +#define MCE1_REGION4 MCE1_REGION4_NS +#define MCE1_REGION4_BASE MCE1_REGION4_BASE_NS + +#define MCE1_CONTEXT1 MCE1_CONTEXT1_NS +#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_NS + +#define MCE1_CONTEXT2 MCE1_CONTEXT2_NS +#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_NS + +#define MCE2 MCE2_NS +#define MCE2_BASE MCE2_BASE_NS + +#define MCE2_REGION1 MCE2_REGION1_NS +#define MCE2_REGION1_BASE MCE2_REGION1_BASE_NS + +#define MCE2_REGION2 MCE2_REGION2_NS +#define MCE2_REGION2_BASE MCE2_REGION2_BASE_NS + +#define MCE2_REGION3 MCE2_REGION3_NS +#define MCE2_REGION3_BASE MCE2_REGION3_BASE_NS + +#define MCE2_REGION4 MCE2_REGION4_NS +#define MCE2_REGION4_BASE MCE2_REGION4_BASE_NS + +#define MCE2_CONTEXT1 MCE2_CONTEXT1_NS +#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_NS + +#define MCE2_CONTEXT2 MCE2_CONTEXT2_NS +#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_NS + +#define MCE3 MCE3_NS +#define MCE3_BASE MCE3_BASE_NS + +#define MCE3_REGION1 MCE3_REGION1_NS +#define MCE3_REGION1_BASE MCE3_REGION1_BASE_NS + +#define MCE3_REGION2 MCE3_REGION2_NS +#define MCE3_REGION2_BASE MCE3_REGION2_BASE_NS + +#define MCE3_REGION3 MCE3_REGION3_NS +#define MCE3_REGION3_BASE MCE3_REGION3_BASE_NS + +#define MCE3_REGION4 MCE3_REGION4_NS +#define MCE3_REGION4_BASE MCE3_REGION4_BASE_NS + +#define MCE3_CONTEXT1 MCE3_CONTEXT1_NS +#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_NS + +#define MCE3_CONTEXT2 MCE3_CONTEXT2_NS +#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_NS + +#define MCE4 MCE4_NS +#define MCE4_BASE MCE4_BASE_NS + +#define MCE4_REGION1 MCE4_REGION1_NS +#define MCE4_REGION1_BASE MCE4_REGION1_BASE_NS + +#define MCE4_REGION2 MCE4_REGION2_NS +#define MCE4_REGION2_BASE MCE4_REGION2_BASE_NS + +#define MCE4_REGION3 MCE4_REGION3_NS +#define MCE4_REGION3_BASE MCE4_REGION3_BASE_NS + +#define MCE4_REGION4 MCE4_REGION4_NS +#define MCE4_REGION4_BASE MCE4_REGION4_BASE_NS + +#define MCE4_CONTEXT1 MCE4_CONTEXT1_NS +#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_NS + +#define MCE4_CONTEXT2 MCE4_CONTEXT2_NS +#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define MDIOS MDIOS_NS +#define MDIOS_BASE MDIOS_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG RAMCFG_NS +#define RAMCFG_BASE RAMCFG_BASE_NS + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define RIFSC RIFSC_NS +#define RIFSC_BASE RIFSC_BASE_NS + +#define RISAF1 RISAF1_NS +#define RISAF1_BASE RISAF1_BASE_NS + +#define RISAF2 RISAF2_NS +#define RISAF2_BASE RISAF2_BASE_NS + +#define RISAF3 RISAF3_NS +#define RISAF3_BASE RISAF3_BASE_NS + +#define RISAF6 RISAF6_NS +#define RISAF6_BASE RISAF6_BASE_NS + +#define RISAF7 RISAF7_NS +#define RISAF7_BASE RISAF7_BASE_NS + +#define RISAF8 RISAF8_NS +#define RISAF8_BASE RISAF8_BASE_NS + +#define RISAF9 RISAF9_NS +#define RISAF9_BASE RISAF9_BASE_NS + +#define RISAF11 RISAF11_NS +#define RISAF11_BASE RISAF11_BASE_NS + +#define RISAF12 RISAF12_NS +#define RISAF12_BASE RISAF12_BASE_NS + +#define RISAF13 RISAF13_NS +#define RISAF13_BASE RISAF13_BASE_NS + +#define RISAF14 RISAF14_NS +#define RISAF14_BASE RISAF14_BASE_NS + +#define RISAF21 RISAF21_NS +#define RISAF21_BASE RISAF21_BASE_NS + +#define RISAF22 RISAF22_NS +#define RISAF22_BASE RISAF22_BASE_NS + +#define RISAF23 RISAF23_NS +#define RISAF23_BASE RISAF23_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define SPDIFRX SPDIFRX_NS +#define SPDIFRX_BASE SPDIFRX_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM9 TIM9_NS +#define TIM9_BASE TIM9_BASE_NS + +#define TIM10 TIM10_NS +#define TIM10_BASE TIM10_BASE_NS + +#define TIM11 TIM11_NS +#define TIM11_BASE TIM11_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define TIM18 TIM18_NS +#define TIM18_BASE TIM18_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USB1_OTG_HS USB1_OTG_HS_NS +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS + +#define USB2_OTG_HS USB2_OTG_HS_NS +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS + +#define USB1_HS_PHYC USB1_HS_PHYC_NS +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS + +#define USB2_HS_PHYC USB2_HS_PHYC_NS +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS + +#define VENC VENC_NS +#define VENC_BASE VENC_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define XSPI1 XSPI1_NS + +#define XSPI2 XSPI2_NS + +#define XSPI3 XSPI3_NS + +#define XSPIM XSPIM_NS +#define XSPIM_BASE XSPIM_BASE_NS + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_NS + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_NS + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_declaration */ + +/** @addtogroup STM32N6xx_Peripheral_Timing_Definition + * @{ + */ + +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ + +/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30UL) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0UL) +#define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16UL) +#define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ + +#define ADC_CALFACT_CALADDOS_Pos (31UL) +#define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */ +#define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */ + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_OP0_Pos (0UL) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */ + +#define ADC_OR_OP1_Pos (1UL) +#define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */ + +#define ADC_OR_OP2_Pos (2UL) +#define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */ +#define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */ + + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* BSEC unit (Boot and Security) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for BSEC_FVRw register *******************/ +#define BSEC_FVRw_FV_Pos (0UL) +#define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */ + +/***************** Bit definition for BSEC_SPLOCKx register *****************/ +#define BSEC_SPLOCKx_SPLOCK0_Pos (0UL) +#define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */ +#define BSEC_SPLOCKx_SPLOCK1_Pos (1UL) +#define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */ +#define BSEC_SPLOCKx_SPLOCK2_Pos (2UL) +#define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */ +#define BSEC_SPLOCKx_SPLOCK3_Pos (3UL) +#define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */ +#define BSEC_SPLOCKx_SPLOCK4_Pos (4UL) +#define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */ +#define BSEC_SPLOCKx_SPLOCK5_Pos (5UL) +#define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */ +#define BSEC_SPLOCKx_SPLOCK6_Pos (6UL) +#define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */ +#define BSEC_SPLOCKx_SPLOCK7_Pos (7UL) +#define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */ +#define BSEC_SPLOCKx_SPLOCK8_Pos (8UL) +#define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */ +#define BSEC_SPLOCKx_SPLOCK9_Pos (9UL) +#define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */ +#define BSEC_SPLOCKx_SPLOCK10_Pos (10UL) +#define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */ +#define BSEC_SPLOCKx_SPLOCK11_Pos (11UL) +#define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */ +#define BSEC_SPLOCKx_SPLOCK12_Pos (12UL) +#define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */ +#define BSEC_SPLOCKx_SPLOCK13_Pos (13UL) +#define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */ +#define BSEC_SPLOCKx_SPLOCK14_Pos (14UL) +#define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */ +#define BSEC_SPLOCKx_SPLOCK15_Pos (15UL) +#define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */ +#define BSEC_SPLOCKx_SPLOCK16_Pos (16UL) +#define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */ +#define BSEC_SPLOCKx_SPLOCK17_Pos (17UL) +#define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */ +#define BSEC_SPLOCKx_SPLOCK18_Pos (18UL) +#define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */ +#define BSEC_SPLOCKx_SPLOCK19_Pos (19UL) +#define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */ +#define BSEC_SPLOCKx_SPLOCK20_Pos (20UL) +#define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */ +#define BSEC_SPLOCKx_SPLOCK21_Pos (21UL) +#define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */ +#define BSEC_SPLOCKx_SPLOCK22_Pos (22UL) +#define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */ +#define BSEC_SPLOCKx_SPLOCK23_Pos (23UL) +#define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */ +#define BSEC_SPLOCKx_SPLOCK24_Pos (24UL) +#define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */ +#define BSEC_SPLOCKx_SPLOCK25_Pos (25UL) +#define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */ +#define BSEC_SPLOCKx_SPLOCK26_Pos (26UL) +#define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */ +#define BSEC_SPLOCKx_SPLOCK27_Pos (27UL) +#define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */ +#define BSEC_SPLOCKx_SPLOCK28_Pos (28UL) +#define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */ +#define BSEC_SPLOCKx_SPLOCK29_Pos (29UL) +#define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */ +#define BSEC_SPLOCKx_SPLOCK30_Pos (30UL) +#define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */ +#define BSEC_SPLOCKx_SPLOCK31_Pos (31UL) +#define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */ + +/***************** Bit definition for BSEC_SWLOCKx register *****************/ +#define BSEC_SWLOCKx_SWLOCK0_Pos (0UL) +#define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */ +#define BSEC_SWLOCKx_SWLOCK1_Pos (1UL) +#define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */ +#define BSEC_SWLOCKx_SWLOCK2_Pos (2UL) +#define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */ +#define BSEC_SWLOCKx_SWLOCK3_Pos (3UL) +#define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */ +#define BSEC_SWLOCKx_SWLOCK4_Pos (4UL) +#define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */ +#define BSEC_SWLOCKx_SWLOCK5_Pos (5UL) +#define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */ +#define BSEC_SWLOCKx_SWLOCK6_Pos (6UL) +#define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */ +#define BSEC_SWLOCKx_SWLOCK7_Pos (7UL) +#define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */ +#define BSEC_SWLOCKx_SWLOCK8_Pos (8UL) +#define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */ +#define BSEC_SWLOCKx_SWLOCK9_Pos (9UL) +#define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */ +#define BSEC_SWLOCKx_SWLOCK10_Pos (10UL) +#define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */ +#define BSEC_SWLOCKx_SWLOCK11_Pos (11UL) +#define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */ +#define BSEC_SWLOCKx_SWLOCK12_Pos (12UL) +#define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */ +#define BSEC_SWLOCKx_SWLOCK13_Pos (13UL) +#define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */ +#define BSEC_SWLOCKx_SWLOCK14_Pos (14UL) +#define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */ +#define BSEC_SWLOCKx_SWLOCK15_Pos (15UL) +#define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */ +#define BSEC_SWLOCKx_SWLOCK16_Pos (16UL) +#define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */ +#define BSEC_SWLOCKx_SWLOCK17_Pos (17UL) +#define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */ +#define BSEC_SWLOCKx_SWLOCK18_Pos (18UL) +#define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */ +#define BSEC_SWLOCKx_SWLOCK19_Pos (19UL) +#define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */ +#define BSEC_SWLOCKx_SWLOCK20_Pos (20UL) +#define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */ +#define BSEC_SWLOCKx_SWLOCK21_Pos (21UL) +#define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */ +#define BSEC_SWLOCKx_SWLOCK22_Pos (22UL) +#define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */ +#define BSEC_SWLOCKx_SWLOCK23_Pos (23UL) +#define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */ +#define BSEC_SWLOCKx_SWLOCK24_Pos (24UL) +#define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */ +#define BSEC_SWLOCKx_SWLOCK25_Pos (25UL) +#define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */ +#define BSEC_SWLOCKx_SWLOCK26_Pos (26UL) +#define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */ +#define BSEC_SWLOCKx_SWLOCK27_Pos (27UL) +#define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */ +#define BSEC_SWLOCKx_SWLOCK28_Pos (28UL) +#define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */ +#define BSEC_SWLOCKx_SWLOCK29_Pos (29UL) +#define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */ +#define BSEC_SWLOCKx_SWLOCK30_Pos (30UL) +#define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */ +#define BSEC_SWLOCKx_SWLOCK31_Pos (31UL) +#define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */ + +/***************** Bit definition for BSEC_SRLOCKx register *****************/ +#define BSEC_SRLOCKx_SRLOCK0_Pos (0UL) +#define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */ +#define BSEC_SRLOCKx_SRLOCK1_Pos (1UL) +#define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */ +#define BSEC_SRLOCKx_SRLOCK2_Pos (2UL) +#define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */ +#define BSEC_SRLOCKx_SRLOCK3_Pos (3UL) +#define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */ +#define BSEC_SRLOCKx_SRLOCK4_Pos (4UL) +#define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */ +#define BSEC_SRLOCKx_SRLOCK5_Pos (5UL) +#define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */ +#define BSEC_SRLOCKx_SRLOCK6_Pos (6UL) +#define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */ +#define BSEC_SRLOCKx_SRLOCK7_Pos (7UL) +#define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */ +#define BSEC_SRLOCKx_SRLOCK8_Pos (8UL) +#define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */ +#define BSEC_SRLOCKx_SRLOCK9_Pos (9UL) +#define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */ +#define BSEC_SRLOCKx_SRLOCK10_Pos (10UL) +#define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */ +#define BSEC_SRLOCKx_SRLOCK11_Pos (11UL) +#define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */ +#define BSEC_SRLOCKx_SRLOCK12_Pos (12UL) +#define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */ +#define BSEC_SRLOCKx_SRLOCK13_Pos (13UL) +#define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */ +#define BSEC_SRLOCKx_SRLOCK14_Pos (14UL) +#define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */ +#define BSEC_SRLOCKx_SRLOCK15_Pos (15UL) +#define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */ +#define BSEC_SRLOCKx_SRLOCK16_Pos (16UL) +#define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */ +#define BSEC_SRLOCKx_SRLOCK17_Pos (17UL) +#define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */ +#define BSEC_SRLOCKx_SRLOCK18_Pos (18UL) +#define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */ +#define BSEC_SRLOCKx_SRLOCK19_Pos (19UL) +#define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */ +#define BSEC_SRLOCKx_SRLOCK20_Pos (20UL) +#define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */ +#define BSEC_SRLOCKx_SRLOCK21_Pos (21UL) +#define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */ +#define BSEC_SRLOCKx_SRLOCK22_Pos (22UL) +#define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */ +#define BSEC_SRLOCKx_SRLOCK23_Pos (23UL) +#define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */ +#define BSEC_SRLOCKx_SRLOCK24_Pos (24UL) +#define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */ +#define BSEC_SRLOCKx_SRLOCK25_Pos (25UL) +#define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */ +#define BSEC_SRLOCKx_SRLOCK26_Pos (26UL) +#define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */ +#define BSEC_SRLOCKx_SRLOCK27_Pos (27UL) +#define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */ +#define BSEC_SRLOCKx_SRLOCK28_Pos (28UL) +#define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */ +#define BSEC_SRLOCKx_SRLOCK29_Pos (29UL) +#define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */ +#define BSEC_SRLOCKx_SRLOCK30_Pos (30UL) +#define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */ +#define BSEC_SRLOCKx_SRLOCK31_Pos (31UL) +#define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */ + +/**************** Bit definition for BSEC_OTPVLDRx register *****************/ +#define BSEC_OTPVLDRx_VLDF0_Pos (0UL) +#define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */ +#define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */ +#define BSEC_OTPVLDRx_VLDF1_Pos (1UL) +#define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */ +#define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */ +#define BSEC_OTPVLDRx_VLDF2_Pos (2UL) +#define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */ +#define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */ +#define BSEC_OTPVLDRx_VLDF3_Pos (3UL) +#define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */ +#define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */ +#define BSEC_OTPVLDRx_VLDF4_Pos (4UL) +#define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */ +#define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */ +#define BSEC_OTPVLDRx_VLDF5_Pos (5UL) +#define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */ +#define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */ +#define BSEC_OTPVLDRx_VLDF6_Pos (6UL) +#define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */ +#define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */ +#define BSEC_OTPVLDRx_VLDF7_Pos (7UL) +#define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */ +#define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */ +#define BSEC_OTPVLDRx_VLDF8_Pos (8UL) +#define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */ +#define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */ +#define BSEC_OTPVLDRx_VLDF9_Pos (9UL) +#define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */ +#define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */ +#define BSEC_OTPVLDRx_VLDF10_Pos (10UL) +#define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */ +#define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */ +#define BSEC_OTPVLDRx_VLDF11_Pos (11UL) +#define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */ +#define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */ +#define BSEC_OTPVLDRx_VLDF12_Pos (12UL) +#define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */ +#define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */ +#define BSEC_OTPVLDRx_VLDF13_Pos (13UL) +#define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */ +#define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */ +#define BSEC_OTPVLDRx_VLDF14_Pos (14UL) +#define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */ +#define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */ +#define BSEC_OTPVLDRx_VLDF15_Pos (15UL) +#define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */ +#define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */ +#define BSEC_OTPVLDRx_VLDF16_Pos (16UL) +#define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */ +#define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */ +#define BSEC_OTPVLDRx_VLDF17_Pos (17UL) +#define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */ +#define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */ +#define BSEC_OTPVLDRx_VLDF18_Pos (18UL) +#define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */ +#define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */ +#define BSEC_OTPVLDRx_VLDF19_Pos (19UL) +#define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */ +#define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */ +#define BSEC_OTPVLDRx_VLDF20_Pos (20UL) +#define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */ +#define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */ +#define BSEC_OTPVLDRx_VLDF21_Pos (21UL) +#define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */ +#define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */ +#define BSEC_OTPVLDRx_VLDF22_Pos (22UL) +#define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */ +#define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */ +#define BSEC_OTPVLDRx_VLDF23_Pos (23UL) +#define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */ +#define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */ +#define BSEC_OTPVLDRx_VLDF24_Pos (24UL) +#define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */ +#define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */ +#define BSEC_OTPVLDRx_VLDF25_Pos (25UL) +#define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */ +#define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */ +#define BSEC_OTPVLDRx_VLDF26_Pos (26UL) +#define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */ +#define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */ +#define BSEC_OTPVLDRx_VLDF27_Pos (27UL) +#define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */ +#define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */ +#define BSEC_OTPVLDRx_VLDF28_Pos (28UL) +#define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */ +#define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */ +#define BSEC_OTPVLDRx_VLDF29_Pos (29UL) +#define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */ +#define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */ +#define BSEC_OTPVLDRx_VLDF30_Pos (30UL) +#define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */ +#define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */ +#define BSEC_OTPVLDRx_VLDF31_Pos (31UL) +#define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */ +#define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */ + +/****************** Bit definition for BSEC_SFSRx register ******************/ +#define BSEC_SFSRx_SFW0_Pos (0UL) +#define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */ +#define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */ +#define BSEC_SFSRx_SFW1_Pos (1UL) +#define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */ +#define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */ +#define BSEC_SFSRx_SFW2_Pos (2UL) +#define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */ +#define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */ +#define BSEC_SFSRx_SFW3_Pos (3UL) +#define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */ +#define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */ +#define BSEC_SFSRx_SFW4_Pos (4UL) +#define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */ +#define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */ +#define BSEC_SFSRx_SFW5_Pos (5UL) +#define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */ +#define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */ +#define BSEC_SFSRx_SFW6_Pos (6UL) +#define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */ +#define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */ +#define BSEC_SFSRx_SFW7_Pos (7UL) +#define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */ +#define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */ +#define BSEC_SFSRx_SFW8_Pos (8UL) +#define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */ +#define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */ +#define BSEC_SFSRx_SFW9_Pos (9UL) +#define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */ +#define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */ +#define BSEC_SFSRx_SFW10_Pos (10UL) +#define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */ +#define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */ +#define BSEC_SFSRx_SFW11_Pos (11UL) +#define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */ +#define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */ +#define BSEC_SFSRx_SFW12_Pos (12UL) +#define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */ +#define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */ +#define BSEC_SFSRx_SFW13_Pos (13UL) +#define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */ +#define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */ +#define BSEC_SFSRx_SFW14_Pos (14UL) +#define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */ +#define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */ +#define BSEC_SFSRx_SFW15_Pos (15UL) +#define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */ +#define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */ +#define BSEC_SFSRx_SFW16_Pos (16UL) +#define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */ +#define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */ +#define BSEC_SFSRx_SFW17_Pos (17UL) +#define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */ +#define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */ +#define BSEC_SFSRx_SFW18_Pos (18UL) +#define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */ +#define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */ +#define BSEC_SFSRx_SFW19_Pos (19UL) +#define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */ +#define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */ +#define BSEC_SFSRx_SFW20_Pos (20UL) +#define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */ +#define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */ +#define BSEC_SFSRx_SFW21_Pos (21UL) +#define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */ +#define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */ +#define BSEC_SFSRx_SFW22_Pos (22UL) +#define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */ +#define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */ +#define BSEC_SFSRx_SFW23_Pos (23UL) +#define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */ +#define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */ +#define BSEC_SFSRx_SFW24_Pos (24UL) +#define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */ +#define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */ +#define BSEC_SFSRx_SFW25_Pos (25UL) +#define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */ +#define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */ +#define BSEC_SFSRx_SFW26_Pos (26UL) +#define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */ +#define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */ +#define BSEC_SFSRx_SFW27_Pos (27UL) +#define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */ +#define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */ +#define BSEC_SFSRx_SFW28_Pos (28UL) +#define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */ +#define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */ +#define BSEC_SFSRx_SFW29_Pos (29UL) +#define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */ +#define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */ +#define BSEC_SFSRx_SFW30_Pos (30UL) +#define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */ +#define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */ +#define BSEC_SFSRx_SFW31_Pos (31UL) +#define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */ +#define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */ + +/****************** Bit definition for BSEC_OTPCR register ******************/ +#define BSEC_OTPCR_ADDR_Pos (0UL) +#define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */ +#define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */ +#define BSEC_OTPCR_PROG_Pos (13UL) +#define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */ +#define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */ +#define BSEC_OTPCR_PPLOCK_Pos (14UL) +#define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */ +#define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */ +#define BSEC_OTPCR_LASTCID_Pos (19UL) +#define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */ +#define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */ + +/******************* Bit definition for BSEC_WDR register *******************/ +#define BSEC_WDR_WRDATA_Pos (0UL) +#define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */ + +/**************** Bit definition for BSEC_SCRATCHRx register ****************/ +#define BSEC_SCRATCHRx_SDATA_Pos (0UL) +#define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */ + +/****************** Bit definition for BSEC_LOCKR register ******************/ +#define BSEC_LOCKR_GWLOCK_Pos (0UL) +#define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */ +#define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */ +#define BSEC_LOCKR_HKLOCK_Pos (2UL) +#define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */ +#define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */ + +/***************** Bit definition for BSEC_JTAGINR register *****************/ +#define BSEC_JTAGINR_JDATAIN_Pos (0UL) +#define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */ + +/**************** Bit definition for BSEC_JTAGOUTR register *****************/ +#define BSEC_JTAGOUTR_JDATAOUT_Pos (0UL) +#define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */ + +/***************** Bit definition for BSEC_UNMAPR register ******************/ +#define BSEC_UNMAPR_UNMAP_Pos (0UL) +#define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */ + +/******************* Bit definition for BSEC_SR register ********************/ +#define BSEC_SR_HVALID_Pos (1UL) +#define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */ +#define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */ +#define BSEC_SR_DBGREQ_Pos (16UL) +#define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */ +#define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */ +#define BSEC_SR_NVSTATE_Pos (26UL) +#define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */ +#define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */ + +/****************** Bit definition for BSEC_OTPSR register ******************/ +#define BSEC_OTPSR_BUSY_Pos (0UL) +#define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */ +#define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */ +#define BSEC_OTPSR_INIT_DONE_Pos (1UL) +#define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */ +#define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */ +#define BSEC_OTPSR_HIDEUP_Pos (2UL) +#define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */ +#define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */ +#define BSEC_OTPSR_OTPNVIR_Pos (4UL) +#define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */ +#define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */ +#define BSEC_OTPSR_OTPERR_Pos (5UL) +#define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */ +#define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */ +#define BSEC_OTPSR_OTPSEC_Pos (6UL) +#define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */ +#define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */ +#define BSEC_OTPSR_PROGFAIL_Pos (16UL) +#define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */ +#define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */ +#define BSEC_OTPSR_DISTURBF_Pos (17UL) +#define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */ +#define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */ +#define BSEC_OTPSR_DEDF_Pos (18UL) +#define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */ +#define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */ +#define BSEC_OTPSR_SECF_Pos (19UL) +#define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */ +#define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */ +#define BSEC_OTPSR_PPLF_Pos (20UL) +#define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */ +#define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */ +#define BSEC_OTPSR_PPLMF_Pos (21UL) +#define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */ +#define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */ +#define BSEC_OTPSR_AMEF_Pos (22UL) +#define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */ +#define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */ + +/***************** Bit definition for BSEC_EPOCHRx register *****************/ +#define BSEC_EPOCHRx_EPOCH_Pos (0UL) +#define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */ + +/**************** Bit definition for BSEC_EPOCHSELR register ****************/ +#define BSEC_EPOCHSELR_EPSEL_Pos (0UL) +#define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */ +#define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */ + +/****************** Bit definition for BSEC_DBGCR register ******************/ +#define BSEC_DBGCR_UNLOCK_Pos (8UL) +#define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */ +#define BSEC_DBGCR_AUTH_HDPL_Pos (16UL) +#define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */ +#define BSEC_DBGCR_AUTH_SEC_Pos (24UL) +#define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */ + +/*************** Bit definition for BSEC_AP_UNLOCK register *****************/ +#define BSEC_AP_UNLOCK_UNLOCK_Pos (0UL) +#define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */ +#define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */ + +/***************** Bit definition for BSEC_HDPLSR register ******************/ +#define BSEC_HDPLSR_HDPL_Pos (0UL) +#define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */ + +/***************** Bit definition for BSEC_HDPLCR register ******************/ +#define BSEC_HDPLCR_INCR_HDPL_Pos (0UL) +#define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */ + +/***************** Bit definition for BSEC_NEXTLR register ******************/ +#define BSEC_NEXTLR_INCR_Pos (0UL) +#define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */ +#define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */ + +/***************** Bit definition for BSEC_WOSCRx register ******************/ +#define BSEC_WOSCRx_WOSDATA_Pos (0UL) +#define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */ + +/****************** Bit definition for BSEC_HRCR register *******************/ +#define BSEC_HRCR_HRC_Pos (0UL) +#define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */ + +/****************** Bit definition for BSEC_WRCR register *******************/ +#define BSEC_WRCR_WRC_Pos (0UL) +#define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Cryp Processor */ +/* */ +/******************************************************************************/ +/******************* Bits definition for CRYP_CR register ********************/ +#define CRYP_CR_ALGODIR_Pos (2UL) +#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */ +#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk /*!< Algorithm direction (Encrypt/Decrypt) */ + +#define CRYP_CR_ALGOMODE_Pos (3UL) +#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */ +#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk /*!< Algorithm mode */ +#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ +#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ +#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ +#define CRYP_CR_ALGOMODE_3 (0x10000UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080000 */ +#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5UL) +#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */ +#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk +#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */ +#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk +#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4UL) +#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */ +#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk +#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */ +#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk +#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19UL) +#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */ +#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk +#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */ +#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk + +#define CRYP_CR_DATATYPE_Pos (6UL) +#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */ +#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk /*!< Data Type selection */ +#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */ +#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */ +#define CRYP_CR_KEYSIZE_Pos (8UL) +#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */ +#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk /*!< Key Size selection */ +#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */ +#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */ +#define CRYP_CR_FFLUSH_Pos (14UL) +#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */ +#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk /*!< CRYP FIFO Flush */ +#define CRYP_CR_CRYPEN_Pos (15UL) +#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */ +#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk /*!< CRYP processor enable */ + +#define CRYP_CR_GCM_CCMPH_Pos (16UL) +#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */ +#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk /*!< GCM or CCM Phase selection */ +#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ +#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ + +#define CRYP_CR_NPBLB_Pos (20UL) +#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk /*!< Number of Padding Bytes in Last Block of payload */ + +#define CRYP_CR_KMOD_Pos (24UL) +#define CRYP_CR_KMOD_Msk (0x3UL << CRYP_CR_KMOD_Pos) /*!< 0x03000000 */ +#define CRYP_CR_KMOD CRYP_CR_KMOD_Msk /*!< Key mode selection */ +#define CRYP_CR_KMOD_0 (0x1UL << CRYP_CR_KMOD_Pos) /*!< 0x01000000 */ +#define CRYP_CR_KMOD_1 (0x2UL << CRYP_CR_KMOD_Pos) /*!< 0x02000000 */ + +#define CRYP_CR_IPRST_Pos (31UL) +#define CRYP_CR_IPRST_Msk (0x1UL << CRYP_CR_IPRST_Pos) /*!< 0x80000000 */ +#define CRYP_CR_IPRST CRYP_CR_IPRST_Msk /*!< CRYP peripheral software reset */ + +/****************** Bits definition for CRYP_SR register *********************/ +#define CRYP_SR_IFEM_Pos (0UL) +#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */ +#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk /*!< Input FIFO empty flag */ +#define CRYP_SR_IFNF_Pos (1UL) +#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */ +#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk /*!< Input FIFO not full flag */ +#define CRYP_SR_OFNE_Pos (2UL) +#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */ +#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk /*!< Output FIFO not empty flag */ +#define CRYP_SR_OFFU_Pos (3UL) +#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */ +#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk /*!< Output FIFO full flag */ +#define CRYP_SR_BUSY_Pos (4UL) +#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */ +#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk /*!< Busy bit */ +#define CRYP_SR_KERF_Pos (6UL) +#define CRYP_SR_KERF_Msk (0x1UL << CRYP_SR_KERF_Pos) /*!< 0x00000040 */ +#define CRYP_SR_KERF CRYP_SR_KERF_Msk /*!< Key error flag */ +#define CRYP_SR_KEYVALID_Pos (7UL) +#define CRYP_SR_KEYVALID_Msk (0x1UL << CRYP_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define CRYP_SR_KEYVALID CRYP_SR_KEYVALID_Msk /*!< Key valid flag */ + +/******************* Bit definition for CRYP_DIN register *******************/ +#define CRYP_DIN_DATAIN_Pos (0UL) +#define CRYP_DIN_DATAIN_Msk (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_DIN_DATAIN CRYP_DIN_DATAIN_Msk /*!< CRYP Data Input */ + +/******************* Bit definition for CRYP_DIN register *******************/ +#define CRYP_DOUT_DATAOUT_Pos (0UL) +#define CRYP_DOUT_DATAOUT_Msk (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_DOUT_DATAOUT CRYP_DOUT_DATAOUT_Msk /*!< CRYP Data Output */ + +/****************** Bits definition for CRYP_DMACR register ******************/ +#define CRYP_DMACR_DIEN_Pos (0UL) +#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */ +#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk /*!< DMA Input Enable */ +#define CRYP_DMACR_DOEN_Pos (1UL) +#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */ +#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk /*!< DMA Output Enable */ + +/***************** Bits definition for CRYP_IMSCR register ******************/ +#define CRYP_IMSCR_INIM_Pos (0UL) +#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */ +#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk /*!< Input FIFO service interrupt mask */ +#define CRYP_IMSCR_OUTIM_Pos (1UL) +#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */ +#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk /*!< Output FIFO service interrupt mask */ + +/****************** Bits definition for CRYP_RISR register *******************/ +#define CRYP_RISR_INRIS_Pos (0UL) +#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */ +#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk /*!< Input FIFO service raw interrupt status */ +#define CRYP_RISR_OUTRIS_Pos (1UL) +#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */ +#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk /*!< Output FIFO service raw interrupt mask */ + +/****************** Bits definition for CRYP_MISR register *******************/ +#define CRYP_MISR_INMIS_Pos (0UL) +#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */ +#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk /*!< Input FIFO service masked interrupt status */ +#define CRYP_MISR_OUTMIS_Pos (1UL) +#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */ +#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk /*!< Output FIFO service masked interrupt status */ + +/******************* Bit definition for CRYP_K0LR register ******************/ +#define CRYP_K0LR_K_Pos (0UL) +#define CRYP_K0LR_K_Msk (0xFFFFFFFFUL << CRYP_K0LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K0LR_K CRYP_K0LR_K_Msk /*!< AES key bit x (x= 224 to 255) */ + +/******************* Bit definition for CRYP_K0RR register ******************/ +#define CRYP_K0RR_K_Pos (0UL) +#define CRYP_K0RR_K_Msk (0xFFFFFFFFUL << CRYP_K0RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K0RR_K CRYP_K0RR_K_Msk /*!< AES key bit x (x= 192 to 223) */ + +/******************* Bit definition for CRYP_IV1LR register ******************/ +#define CRYP_IV1LR_K_Pos (0UL) +#define CRYP_IV1LR_K_Msk (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1LR_K CRYP_IV1LR_K_Msk /*!< AES key bit x (x= 160 to 291) */ + +/******************* Bit definition for CRYP_IV1RR register ******************/ +#define CRYP_IV1RR_K_Pos (0UL) +#define CRYP_IV1RR_K_Msk (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1RR_K CRYP_IV1RR_K_Msk /*!< AES key bit x (x= 128 to 159) */ + +/******************* Bit definition for CRYP_K2LR register ******************/ +#define CRYP_K2LR_K_Pos (0UL) +#define CRYP_K2LR_K_Msk (0xFFFFFFFFUL << CRYP_K2LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K2LR_K CRYP_K2LR_K_Msk /*!< AES key bit x (x= 96 to 127) */ + +/******************* Bit definition for CRYP_K2RR register ******************/ +#define CRYP_K2RR_K_Pos (0UL) +#define CRYP_K2RR_K_Msk (0xFFFFFFFFUL << CRYP_K2RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K2RR_K CRYP_K2RR_K_Msk /*!< AES key bit x (x= 64 to 95) */ + +/******************* Bit definition for CRYP_K3LR register ******************/ +#define CRYP_K3LR_K_Pos (0UL) +#define CRYP_K3LR_K_Msk (0xFFFFFFFFUL << CRYP_K3LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K3LR_K CRYP_K3LR_K_Msk /*!< AES key bit x (x= 32 to 63) */ + +/******************* Bit definition for CRYP_K3RR register ******************/ +#define CRYP_K3RR_K_Pos (0UL) +#define CRYP_K3RR_K_Msk (0xFFFFFFFFUL << CRYP_K3RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K3RR_K CRYP_K3RR_K_Msk /*!< AES key bit x (x= 0 to 31) */ + +/******************* Bit definition for CRYP_IV0LR register ******************/ +#define CRYP_IV0LR_IV_Pos (0UL) +#define CRYP_IV0LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV0LR_IV CRYP_IV0LR_IV_Msk /*!< Initialization vector bit x (x= 0 to 31) */ + +/******************* Bit definition for CRYP_IV0RR register ******************/ +#define CRYP_IV0RR_IV_Pos (0UL) +#define CRYP_IV0RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV0RR_IV CRYP_IV0RR_IV_Msk /*!< Initialization vector bit x (x= 32 to 63) */ + +/******************* Bit definition for CRYP_IV1LR register ******************/ +#define CRYP_IV1LR_IV_Pos (0UL) +#define CRYP_IV1LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1LR_IV CRYP_IV1LR_IV_Msk /*!< Initialization vector bit x (x= 64 to 95) */ + +/******************* Bit definition for CRYP_IV1RR register ******************/ +#define CRYP_IV1RR_IV_Pos (0UL) +#define CRYP_IV1RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1RR_IV CRYP_IV1RR_IV_Msk /*!< Initialization vector bit x (x= 96 to 127) */ + +/******************* Bit definition for CRYP_CSGCMCCM0R register ******************/ +#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos (0UL) +#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM0R_CSGCMCCM0 CRYP_CSGCMCCM0R_CSGCMCCM0_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM1R register ******************/ +#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos (0UL) +#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM1R_CSGCMCCM1 CRYP_CSGCMCCM1R_CSGCMCCM1_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM2R register ******************/ +#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos (0UL) +#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM2R_CSGCMCCM2 CRYP_CSGCMCCM2R_CSGCMCCM2_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM3R register ******************/ +#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos (0UL) +#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM3R_CSGCMCCM3 CRYP_CSGCMCCM3R_CSGCMCCM3_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM4R register ******************/ +#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos (0UL) +#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM4R_CSGCMCCM4 CRYP_CSGCMCCM4R_CSGCMCCM4_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM5R register ******************/ +#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos (0UL) +#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM5R_CSGCMCCM5 CRYP_CSGCMCCM5R_CSGCMCCM5_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM6R register ******************/ +#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos (0UL) +#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM6R_CSGCMCCM6 CRYP_CSGCMCCM6R_CSGCMCCM6_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM7R register ******************/ +#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos (0UL) +#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM7R_CSGCMCCM7 CRYP_CSGCMCCM7R_CSGCMCCM7_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCM0R register ******************/ +#define CRYP_CSGCM0R_CSGCM0_Pos (0UL) +#define CRYP_CSGCM0R_CSGCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM0R_CSGCM0 CRYP_CSGCM0R_CSGCM0_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM1R register ******************/ +#define CRYP_CSGCM1R_CSGCM1_Pos (0UL) +#define CRYP_CSGCM1R_CSGCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM1R_CSGCM1 CRYP_CSGCM1R_CSGCM1_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM2R register ******************/ +#define CRYP_CSGCM2R_CSGCM2_Pos (0UL) +#define CRYP_CSGCM2R_CSGCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM2R_CSGCM2 CRYP_CSGCM2R_CSGCM2_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM3R register ******************/ +#define CRYP_CSGCM3R_CSGCM3_Pos (0UL) +#define CRYP_CSGCM3R_CSGCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM3R_CSGCM3 CRYP_CSGCM3R_CSGCM3_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM4R register ******************/ +#define CRYP_CSGCM4R_CSGCM4_Pos (0UL) +#define CRYP_CSGCM4R_CSGCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM4R_CSGCM4 CRYP_CSGCM4R_CSGCM4_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM5R register ******************/ +#define CRYP_CSGCM5R_CSGCM5_Pos (0UL) +#define CRYP_CSGCM5R_CSGCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM5R_CSGCM5 CRYP_CSGCM5R_CSGCM5_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM6R register ******************/ +#define CRYP_CSGCM6R_CSGCM6_Pos (0UL) +#define CRYP_CSGCM6R_CSGCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM6R_CSGCM6 CRYP_CSGCM6R_CSGCM6_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM7R register ******************/ +#define CRYP_CSGCM7R_CSGCM7_Pos (0UL) +#define CRYP_CSGCM7R_CSGCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM7R_CSGCM7 CRYP_CSGCM7R_CSGCM7_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + + +/******************************************************************************/ +/* */ +/* (CSI) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CSI_CR register ********************/ +#define CSI_CR_CSIEN_Pos (0UL) +#define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */ +#define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */ +#define CSI_CR_VC0START_Pos (2UL) +#define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */ +#define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */ +#define CSI_CR_VC0STOP_Pos (3UL) +#define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */ +#define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */ +#define CSI_CR_VC1START_Pos (6UL) +#define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */ +#define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */ +#define CSI_CR_VC1STOP_Pos (7UL) +#define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */ +#define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */ +#define CSI_CR_VC2START_Pos (10UL) +#define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */ +#define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */ +#define CSI_CR_VC2STOP_Pos (11UL) +#define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */ +#define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */ +#define CSI_CR_VC3START_Pos (14UL) +#define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */ +#define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */ +#define CSI_CR_VC3STOP_Pos (15UL) +#define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */ +#define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */ + +/******************* Bit definition for CSI_PCR register ********************/ +#define CSI_PCR_PWRDOWN_Pos (0UL) +#define CSI_PCR_PWRDOWN_Msk (0x1UL << CSI_PCR_PWRDOWN_Pos) /*!< 0x00000001 */ +#define CSI_PCR_PWRDOWN CSI_PCR_PWRDOWN_Msk /*!< Virtual channel 3 start */ +#define CSI_PCR_CLEN_Pos (1UL) +#define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */ +#define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */ +#define CSI_PCR_DL0EN_Pos (2UL) +#define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */ +#define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */ +#define CSI_PCR_DL1EN_Pos (3UL) +#define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */ +#define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */ + +/***************** Bit definition for CSI_VC0CFGR1 register *****************/ +#define CSI_VC0CFGR1_ALLDT_Pos (0UL) +#define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC0CFGR1_DT0EN_Pos (1UL) +#define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC0CFGR1_DT1EN_Pos (2UL) +#define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC0CFGR1_DT2EN_Pos (3UL) +#define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC0CFGR1_DT3EN_Pos (4UL) +#define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC0CFGR1_DT4EN_Pos (5UL) +#define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC0CFGR1_DT5EN_Pos (6UL) +#define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC0CFGR1_DT6EN_Pos (7UL) +#define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC0CFGR1_CDTFT_Pos (8UL) +#define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC0CFGR1_DT0_Pos (16UL) +#define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC0CFGR1_DT0FT_Pos (24UL) +#define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC0CFGR2 register *****************/ +#define CSI_VC0CFGR2_DT1_Pos (0UL) +#define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT1FT_Pos (8UL) +#define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC0CFGR2_DT2_Pos (16UL) +#define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT2FT_Pos (24UL) +#define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC0CFGR3 register *****************/ +#define CSI_VC0CFGR3_DT3_Pos (0UL) +#define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT3FT_Pos (8UL) +#define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC0CFGR3_DT4_Pos (16UL) +#define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT4FT_Pos (24UL) +#define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC0CFGR4 register *****************/ +#define CSI_VC0CFGR4_DT5_Pos (0UL) +#define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT5FT_Pos (8UL) +#define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC0CFGR4_DT6_Pos (16UL) +#define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT6FT_Pos (24UL) +#define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC1CFGR1 register *****************/ +#define CSI_VC1CFGR1_ALLDT_Pos (0UL) +#define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC1CFGR1_DT0EN_Pos (1UL) +#define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC1CFGR1_DT1EN_Pos (2UL) +#define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC1CFGR1_DT2EN_Pos (3UL) +#define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC1CFGR1_DT3EN_Pos (4UL) +#define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC1CFGR1_DT4EN_Pos (5UL) +#define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC1CFGR1_DT5EN_Pos (6UL) +#define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC1CFGR1_DT6EN_Pos (7UL) +#define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC1CFGR1_CDTFT_Pos (8UL) +#define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC1CFGR1_DT0_Pos (16UL) +#define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC1CFGR1_DT0FT_Pos (24UL) +#define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC1CFGR2 register *****************/ +#define CSI_VC1CFGR2_DT1_Pos (0UL) +#define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT1FT_Pos (8UL) +#define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC1CFGR2_DT2_Pos (16UL) +#define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT2FT_Pos (24UL) +#define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC1CFGR3 register *****************/ +#define CSI_VC1CFGR3_DT3_Pos (0UL) +#define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT3FT_Pos (8UL) +#define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC1CFGR3_DT4_Pos (16UL) +#define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT4FT_Pos (24UL) +#define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC1CFGR4 register *****************/ +#define CSI_VC1CFGR4_DT5_Pos (0UL) +#define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT5FT_Pos (8UL) +#define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC1CFGR4_DT6_Pos (16UL) +#define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT6FT_Pos (24UL) +#define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC2CFGR1 register *****************/ +#define CSI_VC2CFGR1_ALLDT_Pos (0UL) +#define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC2CFGR1_DT0EN_Pos (1UL) +#define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC2CFGR1_DT1EN_Pos (2UL) +#define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC2CFGR1_DT2EN_Pos (3UL) +#define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC2CFGR1_DT3EN_Pos (4UL) +#define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC2CFGR1_DT4EN_Pos (5UL) +#define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC2CFGR1_DT5EN_Pos (6UL) +#define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC2CFGR1_DT6EN_Pos (7UL) +#define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC2CFGR1_CDTFT_Pos (8UL) +#define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC2CFGR1_DT0_Pos (16UL) +#define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC2CFGR1_DT0FT_Pos (24UL) +#define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC2CFGR2 register *****************/ +#define CSI_VC2CFGR2_DT1_Pos (0UL) +#define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT1FT_Pos (8UL) +#define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC2CFGR2_DT2_Pos (16UL) +#define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT2FT_Pos (24UL) +#define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC2CFGR3 register *****************/ +#define CSI_VC2CFGR3_DT3_Pos (0UL) +#define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT3FT_Pos (8UL) +#define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC2CFGR3_DT4_Pos (16UL) +#define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT4FT_Pos (24UL) +#define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC2CFGR4 register *****************/ +#define CSI_VC2CFGR4_DT5_Pos (0UL) +#define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT5FT_Pos (8UL) +#define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC2CFGR4_DT6_Pos (16UL) +#define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT6FT_Pos (24UL) +#define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC3CFGR1 register *****************/ +#define CSI_VC3CFGR1_ALLDT_Pos (0UL) +#define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC3CFGR1_DT0EN_Pos (1UL) +#define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC3CFGR1_DT1EN_Pos (2UL) +#define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC3CFGR1_DT2EN_Pos (3UL) +#define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC3CFGR1_DT3EN_Pos (4UL) +#define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC3CFGR1_DT4EN_Pos (5UL) +#define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC3CFGR1_DT5EN_Pos (6UL) +#define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC3CFGR1_DT6EN_Pos (7UL) +#define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC3CFGR1_CDTFT_Pos (8UL) +#define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC3CFGR1_DT0_Pos (16UL) +#define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC3CFGR1_DT0FT_Pos (24UL) +#define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC3CFGR2 register *****************/ +#define CSI_VC3CFGR2_DT1_Pos (0UL) +#define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT1FT_Pos (8UL) +#define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC3CFGR2_DT2_Pos (16UL) +#define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT2FT_Pos (24UL) +#define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC3CFGR3 register *****************/ +#define CSI_VC3CFGR3_DT3_Pos (0UL) +#define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT3FT_Pos (8UL) +#define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC3CFGR3_DT4_Pos (16UL) +#define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT4FT_Pos (24UL) +#define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC3CFGR4 register *****************/ +#define CSI_VC3CFGR4_DT5_Pos (0UL) +#define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT5FT_Pos (8UL) +#define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC3CFGR4_DT6_Pos (16UL) +#define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT6FT_Pos (24UL) +#define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_LB0CFGR register ******************/ +#define CSI_LB0CFGR_BYTECNT_Pos (0UL) +#define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB0CFGR_LINECNT_Pos (16UL) +#define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB1CFGR register ******************/ +#define CSI_LB1CFGR_BYTECNT_Pos (0UL) +#define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB1CFGR_LINECNT_Pos (16UL) +#define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB2CFGR register ******************/ +#define CSI_LB2CFGR_BYTECNT_Pos (0UL) +#define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB2CFGR_LINECNT_Pos (16UL) +#define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB3CFGR register ******************/ +#define CSI_LB3CFGR_BYTECNT_Pos (0UL) +#define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB3CFGR_LINECNT_Pos (16UL) +#define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_TIM0CFGR register *****************/ +#define CSI_TIM0CFGR_COUNT_Pos (0UL) +#define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM1CFGR register *****************/ +#define CSI_TIM1CFGR_COUNT_Pos (0UL) +#define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM2CFGR register *****************/ +#define CSI_TIM2CFGR_COUNT_Pos (0UL) +#define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM3CFGR register *****************/ +#define CSI_TIM3CFGR_COUNT_Pos (0UL) +#define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/****************** Bit definition for CSI_LMCFGR register ******************/ +#define CSI_LMCFGR_LANENB_Pos (8UL) +#define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */ +#define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */ +#define CSI_LMCFGR_DL0MAP_Pos (16UL) +#define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */ +#define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */ +#define CSI_LMCFGR_DL1MAP_Pos (20UL) +#define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */ +#define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */ + +/****************** Bit definition for CSI_PRGITR register ******************/ +#define CSI_PRGITR_LB0VC_Pos (0UL) +#define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */ +#define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */ +#define CSI_PRGITR_LB0EN_Pos (3UL) +#define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */ +#define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */ +#define CSI_PRGITR_LB1VC_Pos (4UL) +#define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */ +#define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */ +#define CSI_PRGITR_LB1EN_Pos (7UL) +#define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */ +#define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */ +#define CSI_PRGITR_LB2VC_Pos (8UL) +#define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */ +#define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */ +#define CSI_PRGITR_LB2EN_Pos (11UL) +#define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */ +#define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */ +#define CSI_PRGITR_LB3VC_Pos (12UL) +#define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */ +#define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */ +#define CSI_PRGITR_LB3EN_Pos (15UL) +#define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */ +#define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */ +#define CSI_PRGITR_TIM0VC_Pos (16UL) +#define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */ +#define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM0EOF_Pos (18UL) +#define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */ +#define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */ +#define CSI_PRGITR_TIM0EN_Pos (19UL) +#define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */ +#define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */ +#define CSI_PRGITR_TIM1VC_Pos (20UL) +#define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */ +#define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM1EOF_Pos (22UL) +#define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */ +#define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */ +#define CSI_PRGITR_TIM1EN_Pos (23UL) +#define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */ +#define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */ +#define CSI_PRGITR_TIM2VC_Pos (24UL) +#define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */ +#define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM2EOF_Pos (26UL) +#define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */ +#define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */ +#define CSI_PRGITR_TIM2EN_Pos (27UL) +#define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */ +#define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */ +#define CSI_PRGITR_TIM3VC_Pos (28UL) +#define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */ +#define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM3EOF_Pos (30UL) +#define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */ +#define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */ +#define CSI_PRGITR_TIM3EN_Pos (31UL) +#define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */ +#define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */ + +/******************* Bit definition for CSI_WDR register ********************/ +#define CSI_WDR_CNT_Pos (0UL) +#define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */ +#define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */ + +/******************* Bit definition for CSI_IER0 register *******************/ +#define CSI_IER0_LB0IE_Pos (0UL) +#define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */ +#define CSI_IER0_LB1IE_Pos (1UL) +#define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */ +#define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */ +#define CSI_IER0_LB2IE_Pos (2UL) +#define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */ +#define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */ +#define CSI_IER0_LB3IE_Pos (3UL) +#define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */ +#define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */ +#define CSI_IER0_TIM0IE_Pos (4UL) +#define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */ +#define CSI_IER0_TIM1IE_Pos (5UL) +#define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */ +#define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */ +#define CSI_IER0_TIM2IE_Pos (6UL) +#define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */ +#define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */ +#define CSI_IER0_TIM3IE_Pos (7UL) +#define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */ +#define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */ +#define CSI_IER0_SOF0IE_Pos (8UL) +#define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */ +#define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_SOF1IE_Pos (9UL) +#define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_SOF2IE_Pos (10UL) +#define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */ +#define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_SOF3IE_Pos (11UL) +#define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */ +#define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_EOF0IE_Pos (12UL) +#define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */ +#define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_EOF1IE_Pos (13UL) +#define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */ +#define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_EOF2IE_Pos (14UL) +#define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */ +#define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_EOF3IE_Pos (15UL) +#define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */ +#define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_SPKTIE_Pos (16UL) +#define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */ +#define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */ +#define CSI_IER0_CCFIFOFIE_Pos (21UL) +#define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */ +#define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */ +#define CSI_IER0_CRCERRIE_Pos (24UL) +#define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */ +#define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */ +#define CSI_IER0_ECCERRIE_Pos (25UL) +#define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */ +#define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */ +#define CSI_IER0_CECCERRIE_Pos (26UL) +#define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */ +#define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */ +#define CSI_IER0_IDERRIE_Pos (27UL) +#define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */ +#define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */ +#define CSI_IER0_SPKTERRIE_Pos (28UL) +#define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */ +#define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */ +#define CSI_IER0_WDERRIE_Pos (29UL) +#define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */ +#define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */ +#define CSI_IER0_SYNCERRIE_Pos (30UL) +#define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */ +#define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */ + +/******************* Bit definition for CSI_IER1 register *******************/ +#define CSI_IER1_ESOTDL0IE_Pos (0UL) +#define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */ +#define CSI_IER1_ESOTSYNCDL0IE_Pos (1UL) +#define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */ +#define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */ +#define CSI_IER1_EESCDL0IE_Pos (2UL) +#define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */ +#define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL0IE_Pos (3UL) +#define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */ +#define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL0IE_Pos (4UL) +#define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */ +#define CSI_IER1_ESOTDL1IE_Pos (8UL) +#define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */ +#define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */ +#define CSI_IER1_ESOTSYNCDL1IE_Pos (9UL) +#define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */ +#define CSI_IER1_EESCDL1IE_Pos (10UL) +#define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */ +#define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL1IE_Pos (11UL) +#define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */ +#define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL1IE_Pos (12UL) +#define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */ +#define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */ + +/******************* Bit definition for CSI_SR0 register ********************/ +#define CSI_SR0_LB0F_Pos (0UL) +#define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */ +#define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */ +#define CSI_SR0_LB1F_Pos (1UL) +#define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */ +#define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */ +#define CSI_SR0_LB2F_Pos (2UL) +#define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */ +#define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */ +#define CSI_SR0_LB3F_Pos (3UL) +#define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */ +#define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */ +#define CSI_SR0_TIM0F_Pos (4UL) +#define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */ +#define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */ +#define CSI_SR0_TIM1F_Pos (5UL) +#define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */ +#define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */ +#define CSI_SR0_TIM2F_Pos (6UL) +#define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */ +#define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */ +#define CSI_SR0_TIM3F_Pos (7UL) +#define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */ +#define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */ +#define CSI_SR0_SOF0F_Pos (8UL) +#define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */ +#define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */ +#define CSI_SR0_SOF1F_Pos (9UL) +#define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */ +#define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */ +#define CSI_SR0_SOF2F_Pos (10UL) +#define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */ +#define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */ +#define CSI_SR0_SOF3F_Pos (11UL) +#define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */ +#define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */ +#define CSI_SR0_EOF0F_Pos (12UL) +#define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */ +#define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */ +#define CSI_SR0_EOF1F_Pos (13UL) +#define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */ +#define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */ +#define CSI_SR0_EOF2F_Pos (14UL) +#define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */ +#define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */ +#define CSI_SR0_EOF3F_Pos (15UL) +#define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */ +#define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */ +#define CSI_SR0_SPKTF_Pos (16UL) +#define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */ +#define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */ +#define CSI_SR0_VC0STATEF_Pos (17UL) +#define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */ +#define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */ +#define CSI_SR0_VC1STATEF_Pos (18UL) +#define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */ +#define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */ +#define CSI_SR0_VC2STATEF_Pos (19UL) +#define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */ +#define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */ +#define CSI_SR0_VC3STATEF_Pos (20UL) +#define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */ +#define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */ +#define CSI_SR0_CCFIFOFF_Pos (21UL) +#define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */ +#define CSI_SR0_CRCERRF_Pos (24UL) +#define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */ +#define CSI_SR0_ECCERRF_Pos (25UL) +#define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */ +#define CSI_SR0_CECCERRF_Pos (26UL) +#define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */ +#define CSI_SR0_IDERRF_Pos (27UL) +#define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */ +#define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */ +#define CSI_SR0_SPKTERRF_Pos (28UL) +#define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */ +#define CSI_SR0_WDERRF_Pos (29UL) +#define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */ +#define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */ +#define CSI_SR0_SYNCERRF_Pos (30UL) +#define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */ + +/******************* Bit definition for CSI_SR1 register ********************/ +#define CSI_SR1_ESOTDL0F_Pos (0UL) +#define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */ +#define CSI_SR1_ESOTSYNCDL0F_Pos (1UL) +#define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */ +#define CSI_SR1_EESCDL0F_Pos (2UL) +#define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL0F_Pos (3UL) +#define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL0F_Pos (4UL) +#define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */ +#define CSI_SR1_ESOTDL1F_Pos (8UL) +#define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */ +#define CSI_SR1_ESOTSYNCDL1F_Pos (9UL) +#define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */ +#define CSI_SR1_EESCDL1F_Pos (10UL) +#define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL1F_Pos (11UL) +#define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL1F_Pos (12UL) +#define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */ +#define CSI_SR1_ACTDL0F_Pos (16UL) +#define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */ +#define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */ +#define CSI_SR1_SYNCDL0F_Pos (17UL) +#define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */ +#define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */ +#define CSI_SR1_SKCALDL0F_Pos (18UL) +#define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */ +#define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */ +#define CSI_SR1_STOPDL0F_Pos (19UL) +#define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */ +#define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */ +#define CSI_SR1_ULPNDL0F_Pos (20UL) +#define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */ +#define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */ +#define CSI_SR1_ACTDL1F_Pos (22UL) +#define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */ +#define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */ +#define CSI_SR1_SYNCDL1F_Pos (23UL) +#define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */ +#define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */ +#define CSI_SR1_SKCALDL1F_Pos (24UL) +#define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */ +#define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */ +#define CSI_SR1_STOPDL1F_Pos (25UL) +#define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */ +#define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */ +#define CSI_SR1_ULPNDL1F_Pos (26UL) +#define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */ +#define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */ +#define CSI_SR1_STOPCLF_Pos (28UL) +#define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */ +#define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */ +#define CSI_SR1_ULPNACTF_Pos (29UL) +#define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */ +#define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */ +#define CSI_SR1_ULPNCLF_Pos (30UL) +#define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */ +#define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */ +#define CSI_SR1_ACTCLF_Pos (31UL) +#define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */ +#define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */ + +/******************* Bit definition for CSI_FCR0 register *******************/ +#define CSI_FCR0_CLB0F_Pos (0UL) +#define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */ +#define CSI_FCR0_CLB1F_Pos (1UL) +#define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */ +#define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */ +#define CSI_FCR0_CLB2F_Pos (2UL) +#define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */ +#define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */ +#define CSI_FCR0_CLB3F_Pos (3UL) +#define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */ +#define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */ +#define CSI_FCR0_CTIM0F_Pos (4UL) +#define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */ +#define CSI_FCR0_CTIM1F_Pos (5UL) +#define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */ +#define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */ +#define CSI_FCR0_CTIM2F_Pos (6UL) +#define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */ +#define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */ +#define CSI_FCR0_CTIM3F_Pos (7UL) +#define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */ +#define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */ +#define CSI_FCR0_CSOF0F_Pos (8UL) +#define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */ +#define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */ +#define CSI_FCR0_CSOF1F_Pos (9UL) +#define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */ +#define CSI_FCR0_CSOF2F_Pos (10UL) +#define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */ +#define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */ +#define CSI_FCR0_CSOF3F_Pos (11UL) +#define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */ +#define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */ +#define CSI_FCR0_CEOF0F_Pos (12UL) +#define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */ +#define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */ +#define CSI_FCR0_CEOF1F_Pos (13UL) +#define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */ +#define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */ +#define CSI_FCR0_CEOF2F_Pos (14UL) +#define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */ +#define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */ +#define CSI_FCR0_CEOF3F_Pos (15UL) +#define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */ +#define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */ +#define CSI_FCR0_CSPKTF_Pos (16UL) +#define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */ +#define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */ +#define CSI_FCR0_CCCFIFOFF_Pos (21UL) +#define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */ +#define CSI_FCR0_CCRCERRF_Pos (24UL) +#define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */ +#define CSI_FCR0_CECCERRF_Pos (25UL) +#define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */ +#define CSI_FCR0_CCECCERRF_Pos (26UL) +#define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */ +#define CSI_FCR0_CIDERRF_Pos (27UL) +#define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */ +#define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */ +#define CSI_FCR0_CSPKTERRF_Pos (28UL) +#define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */ +#define CSI_FCR0_CWDERRF_Pos (29UL) +#define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */ +#define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */ +#define CSI_FCR0_CSYNCERRF_Pos (30UL) +#define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */ + +/******************* Bit definition for CSI_FCR1 register *******************/ +#define CSI_FCR1_CESOTDL0F_Pos (0UL) +#define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */ +#define CSI_FCR1_CESOTSYNCDL0F_Pos (1UL) +#define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */ +#define CSI_FCR1_CEESCDL0F_Pos (2UL) +#define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL0F_Pos (3UL) +#define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL0F_Pos (4UL) +#define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */ +#define CSI_FCR1_CESOTDL1F_Pos (8UL) +#define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */ +#define CSI_FCR1_CESOTSYNCDL1F_Pos (9UL) +#define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */ +#define CSI_FCR1_CEESCDL1F_Pos (10UL) +#define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL1F_Pos (11UL) +#define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL1F_Pos (12UL) +#define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */ + +/****************** Bit definition for CSI_SPDFR register *******************/ +#define CSI_SPDFR_DATAFIELD_Pos (0UL) +#define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */ +#define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */ +#define CSI_SPDFR_DATATYPE_Pos (16UL) +#define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */ +#define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */ +#define CSI_SPDFR_VCHANNEL_Pos (22UL) +#define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */ +#define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */ + +/******************* Bit definition for CSI_ERR1 register *******************/ +#define CSI_ERR1_CRCDTERR_Pos (0UL) +#define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */ +#define CSI_ERR1_CRCVCERR_Pos (6UL) +#define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */ +#define CSI_ERR1_CECCDTERR_Pos (8UL) +#define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */ +#define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */ +#define CSI_ERR1_CECCVCERR_Pos (14UL) +#define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */ +#define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */ +#define CSI_ERR1_IDDTERR_Pos (16UL) +#define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */ +#define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */ +#define CSI_ERR1_IDVCERR_Pos (22UL) +#define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */ +#define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */ + +/******************* Bit definition for CSI_ERR2 register *******************/ +#define CSI_ERR2_SPKTDTERR_Pos (0UL) +#define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */ +#define CSI_ERR2_SPKTVCERR_Pos (6UL) +#define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */ +#define CSI_ERR2_WDVCERR_Pos (16UL) +#define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */ +#define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */ +#define CSI_ERR2_SYNCVCERR_Pos (18UL) +#define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */ +#define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */ + +/******************* Bit definition for CSI_PRCR register *******************/ +#define CSI_PRCR_PEN_Pos (1UL) +#define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */ +#define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */ + +/******************* Bit definition for CSI_PMCR register *******************/ +#define CSI_PMCR_FRXMDL0_Pos (0UL) +#define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */ +#define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */ +#define CSI_PMCR_FRXMDL1_Pos (1UL) +#define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */ +#define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */ +#define CSI_PMCR_FTXSMDL0_Pos (2UL) +#define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */ +#define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */ +#define CSI_PMCR_DTDL_Pos (4UL) +#define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */ +#define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */ +#define CSI_PMCR_RTDL0_Pos (8UL) +#define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */ +#define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */ +#define CSI_PMCR_TUESDL0_Pos (12UL) +#define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */ +#define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */ +#define CSI_PMCR_TUEXDL0_Pos (16UL) +#define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */ +#define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */ + +/******************* Bit definition for CSI_PFCR register *******************/ +#define CSI_PFCR_CCFR_Pos (0UL) +#define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */ +#define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */ +#define CSI_PFCR_HSFR_Pos (8UL) +#define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */ +#define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */ +#define CSI_PFCR_DLD_Pos (16UL) +#define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */ +#define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */ + +/****************** Bit definition for CSI_PTCR0 register *******************/ +#define CSI_PTCR0_TCKEN_Pos (0UL) +#define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */ +#define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */ +#define CSI_PTCR0_TRSEN_Pos (1UL) +#define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */ +#define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */ + +/****************** Bit definition for CSI_PTCR1 register *******************/ +#define CSI_PTCR1_TDI_Pos (0UL) +#define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */ +#define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */ +#define CSI_PTCR1_TWM_Pos (16UL) +#define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */ +#define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */ + +/******************* Bit definition for CSI_PTSR register *******************/ +#define CSI_PTSR_TDO_Pos (0UL) +#define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */ +#define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */ + + +/*********************************************************************************/ +/* */ +/* DBGMCU */ +/* */ +/*********************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register ****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */ +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */ + +/******************** Bit definition for DBGMCU_CR register ********************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0UL) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1UL) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2UL) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */ +#define DBGMCU_CR_DBGCLKEN_Pos (20UL) +#define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */ +#define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */ +#define DBGMCU_CR_TRACECLKEN_Pos (21UL) +#define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */ +#define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */ +#define DBGMCU_CR_DBTRGOEN_Pos (28UL) +#define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */ +#define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */ +#define DBGMCU_CR_HLT_TSGEN_EN_Pos (31UL) +#define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */ +#define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */ + +/******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0UL) +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1UL) +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2UL) +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3UL) +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4UL) +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5UL) +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6UL) +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7UL) +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8UL) +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9UL) +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11UL) +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12UL) +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13UL) +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21UL) +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22UL) +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23UL) +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24UL) +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25UL) +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */ + +/******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8UL) +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */ + +/******************** Bit definition for DBGMCU_APB2FZ1 register ***************/ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0UL) +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1UL) +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15UL) +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16UL) +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17UL) +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18UL) +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19UL) +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */ + +/******************** Bit definition for DBGMCU_APB4FZ1 register ***************/ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8UL) +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16UL) +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18UL) +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */ + +/******************** Bit definition for DBGMCU_APB5FZ1 register ***************/ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4UL) +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */ + +/******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_SR register ***************/ +#define DBGMCU_SR_AP0_PRESENT_Pos (0UL) +#define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */ +#define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */ +#define DBGMCU_SR_AP1_PRESENT_Pos (1UL) +#define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */ +#define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */ +#define DBGMCU_SR_AP0_ENABLE_Pos (16UL) +#define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */ +#define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */ +#define DBGMCU_SR_AP1_ENABLE_Pos (17UL) +#define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */ +#define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */ + +/******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0UL) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1UL) +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */ + + +/******************************************************************************/ +/* */ +/* DCMI */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DCMI_CR register ******************/ +#define DCMI_CR_CAPTURE_Pos (0UL) +#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ +#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk +#define DCMI_CR_CM_Pos (1UL) +#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ +#define DCMI_CR_CM DCMI_CR_CM_Msk +#define DCMI_CR_CROP_Pos (2UL) +#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ +#define DCMI_CR_CROP DCMI_CR_CROP_Msk +#define DCMI_CR_JPEG_Pos (3UL) +#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ +#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk +#define DCMI_CR_ESS_Pos (4UL) +#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ +#define DCMI_CR_ESS DCMI_CR_ESS_Msk +#define DCMI_CR_PCKPOL_Pos (5UL) +#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk +#define DCMI_CR_HSPOL_Pos (6UL) +#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk +#define DCMI_CR_VSPOL_Pos (7UL) +#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk +#define DCMI_CR_FCRC_Pos (8UL) +#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ +#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ +#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ +#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ +#define DCMI_CR_EDM_Pos (10UL) +#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ +#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ +#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ +#define DCMI_CR_ENABLE_Pos (14UL) +#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk +#define DCMI_CR_BSM_Pos (16UL) +#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ +#define DCMI_CR_BSM DCMI_CR_BSM_Msk +#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ +#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ +#define DCMI_CR_OEBS_Pos (18UL) +#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ +#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk +#define DCMI_CR_LSM_Pos (19UL) +#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ +#define DCMI_CR_LSM DCMI_CR_LSM_Msk +#define DCMI_CR_OELS_Pos (20UL) +#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ +#define DCMI_CR_OELS DCMI_CR_OELS_Msk +#define DCMI_CR_PSDM_Pos (31UL) +#define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */ +#define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ + +/******************** Bits definition for DCMI_SR register ******************/ +#define DCMI_SR_HSYNC_Pos (0UL) +#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ +#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk +#define DCMI_SR_VSYNC_Pos (1UL) +#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ +#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk +#define DCMI_SR_FNE_Pos (2UL) +#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ +#define DCMI_SR_FNE DCMI_SR_FNE_Msk + +/******************** Bits definition for DCMI_RIS register ****************/ +#define DCMI_RIS_FRAME_RIS_Pos (0UL) +#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ +#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk +#define DCMI_RIS_OVR_RIS_Pos (1UL) +#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk +#define DCMI_RIS_ERR_RIS_Pos (2UL) +#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ +#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk +#define DCMI_RIS_VSYNC_RIS_Pos (3UL) +#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ +#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk +#define DCMI_RIS_LINE_RIS_Pos (4UL) +#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ +#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk + +/******************** Bits definition for DCMI_IER register *****************/ +#define DCMI_IER_FRAME_IE_Pos (0UL) +#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ +#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk +#define DCMI_IER_OVR_IE_Pos (1UL) +#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk +#define DCMI_IER_ERR_IE_Pos (2UL) +#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ +#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk +#define DCMI_IER_VSYNC_IE_Pos (3UL) +#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ +#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk +#define DCMI_IER_LINE_IE_Pos (4UL) +#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ +#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk + +/******************** Bits definition for DCMI_MIS register *****************/ +#define DCMI_MIS_FRAME_MIS_Pos (0UL) +#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ +#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk +#define DCMI_MIS_OVR_MIS_Pos (1UL) +#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk +#define DCMI_MIS_ERR_MIS_Pos (2UL) +#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ +#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk +#define DCMI_MIS_VSYNC_MIS_Pos (3UL) +#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ +#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk +#define DCMI_MIS_LINE_MIS_Pos (4UL) +#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ +#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk + +/******************** Bits definition for DCMI_ICR register *****************/ +#define DCMI_ICR_FRAME_ISC_Pos (0UL) +#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ +#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk +#define DCMI_ICR_OVR_ISC_Pos (1UL) +#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk +#define DCMI_ICR_ERR_ISC_Pos (2UL) +#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ +#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk +#define DCMI_ICR_VSYNC_ISC_Pos (3UL) +#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ +#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk +#define DCMI_ICR_LINE_ISC_Pos (4UL) +#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ +#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk + +/******************** Bits definition for DCMI_ESCR register ******************/ +#define DCMI_ESCR_FSC_Pos (0UL) +#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk +#define DCMI_ESCR_LSC_Pos (8UL) +#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk +#define DCMI_ESCR_LEC_Pos (16UL) +#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk +#define DCMI_ESCR_FEC_Pos (24UL) +#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk + +/******************** Bits definition for DCMI_ESUR register ******************/ +#define DCMI_ESUR_FSU_Pos (0UL) +#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk +#define DCMI_ESUR_LSU_Pos (8UL) +#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk +#define DCMI_ESUR_LEU_Pos (16UL) +#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk +#define DCMI_ESUR_FEU_Pos (24UL) +#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk + +/******************** Bits definition for DCMI_CWSTRT register ******************/ +#define DCMI_CWSTRT_HOFFCNT_Pos (0UL) +#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk +#define DCMI_CWSTRT_VST_Pos (16UL) +#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ +#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk + +/******************** Bits definition for DCMI_CWSIZE register ******************/ +#define DCMI_CWSIZE_CAPCNT_Pos (0UL) +#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk +#define DCMI_CWSIZE_VLINE_Pos (16UL) +#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ +#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk + +/******************** Bits definition for DCMI_DR register ******************/ +#define DCMI_DR_BYTE0_Pos (0UL) +#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ +#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk +#define DCMI_DR_BYTE1_Pos (8UL) +#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ +#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk +#define DCMI_DR_BYTE2_Pos (16UL) +#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ +#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk +#define DCMI_DR_BYTE3_Pos (24UL) +#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ +#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk + + +/******************************************************************************/ +/* */ +/* DCMIPP */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DCMIPP_IPGR1 register *****************/ +#define DCMIPP_IPGR1_MEMORYPAGE_Pos (0UL) +#define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */ +#define DCMIPP_IPGR1_QOS_MODE_Pos (24UL) +#define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */ +#define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */ + +/***************** Bit definition for DCMIPP_IPGR2 register *****************/ +#define DCMIPP_IPGR2_PSTART_Pos (0UL) +#define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */ + +/***************** Bit definition for DCMIPP_IPGR3 register *****************/ +#define DCMIPP_IPGR3_IDLE_Pos (0UL) +#define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */ + +/***************** Bit definition for DCMIPP_IPGR8 register *****************/ +#define DCMIPP_IPGR8_DID_Pos (0UL) +#define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */ +#define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */ +#define DCMIPP_IPGR8_REVID_Pos (8UL) +#define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */ +#define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */ +#define DCMIPP_IPGR8_ARCHIID_Pos (16UL) +#define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */ +#define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */ +#define DCMIPP_IPGR8_IPPID_Pos (24UL) +#define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */ +#define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */ + +/**************** Bit definition for DCMIPP_IPC1R1 register *****************/ +#define DCMIPP_IPC1R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC1R1_OTR_Pos (8UL) +#define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC1R2 register *****************/ +#define DCMIPP_IPC1R2_WLRU_Pos (16UL) +#define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC1R3 register *****************/ +#define DCMIPP_IPC1R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC1R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC2R1 register *****************/ +#define DCMIPP_IPC2R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC2R1_OTR_Pos (8UL) +#define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC2R2 register *****************/ +#define DCMIPP_IPC2R2_WLRU_Pos (16UL) +#define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC2R3 register *****************/ +#define DCMIPP_IPC2R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC2R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC3R1 register *****************/ +#define DCMIPP_IPC3R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC3R1_OTR_Pos (8UL) +#define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC3R2 register *****************/ +#define DCMIPP_IPC3R2_WLRU_Pos (16UL) +#define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC3R3 register *****************/ +#define DCMIPP_IPC3R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC3R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC4R1 register *****************/ +#define DCMIPP_IPC4R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC4R1_OTR_Pos (8UL) +#define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC4R2 register *****************/ +#define DCMIPP_IPC4R2_WLRU_Pos (16UL) +#define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC4R3 register *****************/ +#define DCMIPP_IPC4R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC4R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC5R1 register *****************/ +#define DCMIPP_IPC5R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC5R1_OTR_Pos (8UL) +#define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC5R2 register *****************/ +#define DCMIPP_IPC5R2_WLRU_Pos (16UL) +#define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC5R3 register *****************/ +#define DCMIPP_IPC5R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC5R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/*************** Bit definition for DCMIPP_PRHWCFGR register ****************/ + +/***************** Bit definition for DCMIPP_PRCR register ******************/ +#define DCMIPP_PRCR_ESS_Pos (4UL) +#define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */ +#define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */ +#define DCMIPP_PRCR_PCKPOL_Pos (5UL) +#define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */ +#define DCMIPP_PRCR_HSPOL_Pos (6UL) +#define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */ +#define DCMIPP_PRCR_VSPOL_Pos (7UL) +#define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */ +#define DCMIPP_PRCR_EDM_Pos (10UL) +#define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */ +#define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */ +#define DCMIPP_PRCR_ENABLE_Pos (14UL) +#define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */ +#define DCMIPP_PRCR_FORMAT_Pos (16UL) +#define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */ +#define DCMIPP_PRCR_SWAPCYCLES_Pos (25UL) +#define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */ +#define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */ +#define DCMIPP_PRCR_SWAPBITS_Pos (26UL) +#define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */ +#define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */ + +/**************** Bit definition for DCMIPP_PRESCR register *****************/ +#define DCMIPP_PRESCR_FSC_Pos (0UL) +#define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */ +#define DCMIPP_PRESCR_LSC_Pos (8UL) +#define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */ +#define DCMIPP_PRESCR_LEC_Pos (16UL) +#define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */ +#define DCMIPP_PRESCR_FEC_Pos (24UL) +#define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */ + +/**************** Bit definition for DCMIPP_PRESUR register *****************/ +#define DCMIPP_PRESUR_FSU_Pos (0UL) +#define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */ +#define DCMIPP_PRESUR_LSU_Pos (8UL) +#define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */ +#define DCMIPP_PRESUR_LEU_Pos (16UL) +#define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */ +#define DCMIPP_PRESUR_FEU_Pos (24UL) +#define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */ + +/***************** Bit definition for DCMIPP_PRIER register *****************/ +#define DCMIPP_PRIER_ERRIE_Pos (6UL) +#define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */ + +/***************** Bit definition for DCMIPP_PRSR register ******************/ +#define DCMIPP_PRSR_ERRF_Pos (6UL) +#define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */ +#define DCMIPP_PRSR_HSYNC_Pos (16UL) +#define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */ +#define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */ +#define DCMIPP_PRSR_VSYNC_Pos (17UL) +#define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */ +#define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */ + +/***************** Bit definition for DCMIPP_PRFCR register *****************/ +#define DCMIPP_PRFCR_CERRF_Pos (6UL) +#define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */ + +/***************** Bit definition for DCMIPP_CMCR register ******************/ +#define DCMIPP_CMCR_INSEL_Pos (0UL) +#define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */ +#define DCMIPP_CMCR_PSFC_Pos (1UL) +#define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */ +#define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */ +#define DCMIPP_CMCR_CFC_Pos (4UL) +#define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */ +#define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */ +#define DCMIPP_CMCR_SWAPRB_Pos (7UL) +#define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */ +#define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */ + +/**************** Bit definition for DCMIPP_CMFRCR register *****************/ +#define DCMIPP_CMFRCR_FRMCNT_Pos (0UL) +#define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */ + +/***************** Bit definition for DCMIPP_CMIER register *****************/ +#define DCMIPP_CMIER_ATXERRIE_Pos (5UL) +#define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */ +#define DCMIPP_CMIER_PRERRIE_Pos (6UL) +#define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */ +#define DCMIPP_CMIER_P0LINEIE_Pos (8UL) +#define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0FRAMEIE_Pos (9UL) +#define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0VSYNCIE_Pos (10UL) +#define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0LIMITIE_Pos (14UL) +#define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0OVRIE_Pos (15UL) +#define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P1LINEIE_Pos (16UL) +#define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */ +#define DCMIPP_CMIER_P1FRAMEIE_Pos (17UL) +#define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1VSYNCIE_Pos (18UL) +#define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1OVRIE_Pos (23UL) +#define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P2LINEIE_Pos (24UL) +#define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2FRAMEIE_Pos (25UL) +#define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2VSYNCIE_Pos (26UL) +#define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2OVRIE_Pos (31UL) +#define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR1 register *****************/ +#define DCMIPP_CMSR1_PRHSYNC_Pos (0UL) +#define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_PRVSYNC_Pos (1UL) +#define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */ +#define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_P0LSTLINE_Pos (8UL) +#define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0LSTFRM_Pos (9UL) +#define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0CPTACT_Pos (15UL) +#define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */ +#define DCMIPP_CMSR1_P1LSTLINE_Pos (16UL) +#define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1LSTFRM_Pos (17UL) +#define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1CPTACT_Pos (23UL) +#define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */ +#define DCMIPP_CMSR1_P2LSTLINE_Pos (24UL) +#define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2LSTFRM_Pos (25UL) +#define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2CPTACT_Pos (31UL) +#define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR2 register *****************/ +#define DCMIPP_CMSR2_ATXERRF_Pos (5UL) +#define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */ +#define DCMIPP_CMSR2_PRERRF_Pos (6UL) +#define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */ +#define DCMIPP_CMSR2_P0LINEF_Pos (8UL) +#define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0FRAMEF_Pos (9UL) +#define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0VSYNCF_Pos (10UL) +#define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0LIMITF_Pos (14UL) +#define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0OVRF_Pos (15UL) +#define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P1LINEF_Pos (16UL) +#define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1FRAMEF_Pos (17UL) +#define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1VSYNCF_Pos (18UL) +#define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1OVRF_Pos (23UL) +#define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P2LINEF_Pos (24UL) +#define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2FRAMEF_Pos (25UL) +#define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2VSYNCF_Pos (26UL) +#define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2OVRF_Pos (31UL) +#define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMFCR register *****************/ +#define DCMIPP_CMFCR_CATXERRF_Pos (5UL) +#define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */ +#define DCMIPP_CMFCR_CPRERRF_Pos (6UL) +#define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */ +#define DCMIPP_CMFCR_CP0LINEF_Pos (8UL) +#define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0FRAMEF_Pos (9UL) +#define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0VSYNCF_Pos (10UL) +#define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP0LIMITF_Pos (14UL) +#define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_CMFCR_CP0OVRF_Pos (15UL) +#define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP1LINEF_Pos (16UL) +#define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1FRAMEF_Pos (17UL) +#define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1VSYNCF_Pos (18UL) +#define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP1OVRF_Pos (23UL) +#define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP2LINEF_Pos (24UL) +#define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2FRAMEF_Pos (25UL) +#define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2VSYNCF_Pos (26UL) +#define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP2OVRF_Pos (31UL) +#define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0FSCR register *****************/ +#define DCMIPP_P0FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */ +#define DCMIPP_P0FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */ +#define DCMIPP_P0FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_VC_Pos (19UL) +#define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P0FCTCR register ****************/ +#define DCMIPP_P0FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P0SCSTR register ****************/ +#define DCMIPP_P0SCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0SCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P0SCSZR register ****************/ +#define DCMIPP_P0SCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0SCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0SCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */ +#define DCMIPP_P0SCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */ + +/*************** Bit definition for DCMIPP_P0DCCNTR register ****************/ +#define DCMIPP_P0DCCNTR_CNT_Pos (0UL) +#define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */ +#define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */ + +/*************** Bit definition for DCMIPP_P0DCLMTR register ****************/ +#define DCMIPP_P0DCLMTR_LIMIT_Pos (0UL) +#define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */ +#define DCMIPP_P0DCLMTR_ENABLE_Pos (31UL) +#define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P0PPCR register *****************/ +#define DCMIPP_P0PPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0PPCR_PAD_Pos (5UL) +#define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0PPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */ +#define DCMIPP_P0PPCR_BSM_Pos (7UL) +#define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */ +#define DCMIPP_P0PPCR_OEBS_Pos (9UL) +#define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */ +#define DCMIPP_P0PPCR_LSM_Pos (10UL) +#define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */ +#define DCMIPP_P0PPCR_OELS_Pos (11UL) +#define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */ +#define DCMIPP_P0PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0PPCR_DBM_Pos (16UL) +#define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */ + +/*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/ +#define DCMIPP_P0PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/ +#define DCMIPP_P0PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */ + +/***************** Bit definition for DCMIPP_P0IER register *****************/ +#define DCMIPP_P0IER_LINEIE_Pos (0UL) +#define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P0IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P0IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P0IER_LIMITIE_Pos (6UL) +#define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */ +#define DCMIPP_P0IER_OVRIE_Pos (7UL) +#define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P0SR register ******************/ +#define DCMIPP_P0SR_LINEF_Pos (0UL) +#define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P0SR_FRAMEF_Pos (1UL) +#define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P0SR_VSYNCF_Pos (2UL) +#define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P0SR_LIMITF_Pos (6UL) +#define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */ +#define DCMIPP_P0SR_OVRF_Pos (7UL) +#define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P0SR_LSTLINE_Pos (16UL) +#define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_LSTFRM_Pos (17UL) +#define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_CPTACT_Pos (23UL) +#define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P0FCR register *****************/ +#define DCMIPP_P0FCR_CLINEF_Pos (0UL) +#define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P0FCR_CLIMITF_Pos (6UL) +#define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_P0FCR_COVRF_Pos (7UL) +#define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0CFSCR register ****************/ +#define DCMIPP_P0CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */ +#define DCMIPP_P0CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */ +#define DCMIPP_P0CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0CFSCR_VC_Pos (19UL) +#define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P0CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P0CFCTCR register ****************/ +#define DCMIPP_P0CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P0CSCSTR register ****************/ +#define DCMIPP_P0CSCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0CSCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P0CSCSZR register ****************/ +#define DCMIPP_P0CSCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0CSCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0CSCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */ +#define DCMIPP_P0CSCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */ + +/**************** Bit definition for DCMIPP_P0CPPCR register ****************/ +#define DCMIPP_P0CPPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0CPPCR_PAD_Pos (5UL) +#define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0CPPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */ +#define DCMIPP_P0CPPCR_BSM_Pos (7UL) +#define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */ +#define DCMIPP_P0CPPCR_OEBS_Pos (9UL) +#define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */ +#define DCMIPP_P0CPPCR_LSM_Pos (10UL) +#define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */ +#define DCMIPP_P0CPPCR_OELS_Pos (11UL) +#define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */ +#define DCMIPP_P0CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0CPPCR_DBM_Pos (16UL) +#define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */ + +/************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/ +#define DCMIPP_P0CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/**************** Bit definition for DCMIPP_P1FSCR register *****************/ +#define DCMIPP_P1FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */ +#define DCMIPP_P1FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */ +#define DCMIPP_P1FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */ +#define DCMIPP_P1FSCR_VC_Pos (19UL) +#define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_FDTF_Pos (24UL) +#define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P1FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P1FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P1SRCR register *****************/ +#define DCMIPP_P1SRCR_LASTLINE_Pos (0UL) +#define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12UL) +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */ +#define DCMIPP_P1SRCR_CROPEN_Pos (15UL) +#define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */ +#define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */ + +/**************** Bit definition for DCMIPP_P1BPRCR register ****************/ +#define DCMIPP_P1BPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */ +#define DCMIPP_P1BPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */ + +/**************** Bit definition for DCMIPP_P1BPRSR register ****************/ +#define DCMIPP_P1BPRSR_BADCNT_Pos (0UL) +#define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */ + +/**************** Bit definition for DCMIPP_P1DECR register *****************/ +#define DCMIPP_P1DECR_ENABLE_Pos (0UL) +#define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DECR_HDEC_Pos (1UL) +#define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DECR_VDEC_Pos (3UL) +#define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1BLCCR register ****************/ +#define DCMIPP_P1BLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */ +#define DCMIPP_P1BLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */ +#define DCMIPP_P1BLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */ +#define DCMIPP_P1BLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR1 register ****************/ +#define DCMIPP_P1EXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */ +#define DCMIPP_P1EXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */ +#define DCMIPP_P1EXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR2 register ****************/ +#define DCMIPP_P1EXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */ +#define DCMIPP_P1EXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */ +#define DCMIPP_P1EXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */ +#define DCMIPP_P1EXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */ + +/**************** Bit definition for DCMIPP_P1ST1CR register ****************/ +#define DCMIPP_P1ST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST1CR_BINS_Pos (2UL) +#define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST1CR_SRC_Pos (4UL) +#define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST1CR_MODE_Pos (7UL) +#define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST2CR register ****************/ +#define DCMIPP_P1ST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST2CR_BINS_Pos (2UL) +#define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST2CR_SRC_Pos (4UL) +#define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST2CR_MODE_Pos (7UL) +#define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST3CR register ****************/ +#define DCMIPP_P1ST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST3CR_BINS_Pos (2UL) +#define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST3CR_SRC_Pos (4UL) +#define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST3CR_MODE_Pos (7UL) +#define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1STSTR register ****************/ +#define DCMIPP_P1STSTR_HSTART_Pos (0UL) +#define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSTR_VSTART_Pos (16UL) +#define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1STSZR register ****************/ +#define DCMIPP_P1STSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1STSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1ST1SR register ****************/ +#define DCMIPP_P1ST1SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST2SR register ****************/ +#define DCMIPP_P1ST2SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST3SR register ****************/ +#define DCMIPP_P1ST3SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1DMCR register *****************/ +#define DCMIPP_P1DMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DMCR_TYPE_Pos (1UL) +#define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */ +#define DCMIPP_P1DMCR_PEAK_Pos (16UL) +#define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */ +#define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */ +#define DCMIPP_P1DMCR_LINEV_Pos (20UL) +#define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */ +#define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */ +#define DCMIPP_P1DMCR_LINEH_Pos (24UL) +#define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */ +#define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */ +#define DCMIPP_P1DMCR_EDGE_Pos (28UL) +#define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */ + +/**************** Bit definition for DCMIPP_P1CCCR register *****************/ +#define DCMIPP_P1CCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/**************** Bit definition for DCMIPP_P1CCRR1 register ****************/ +#define DCMIPP_P1CCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCRR2 register ****************/ +#define DCMIPP_P1CCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCGR1 register ****************/ +#define DCMIPP_P1CCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCGR2 register ****************/ +#define DCMIPP_P1CCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCBR1 register ****************/ +#define DCMIPP_P1CCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCBR2 register ****************/ +#define DCMIPP_P1CCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CTCR1 register ****************/ +#define DCMIPP_P1CTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */ +#define DCMIPP_P1CTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR2 register ****************/ +#define DCMIPP_P1CTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR3 register ****************/ +#define DCMIPP_P1CTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1FCTCR register ****************/ +#define DCMIPP_P1FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P1CRSTR register ****************/ +#define DCMIPP_P1CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CRSZR register ****************/ +#define DCMIPP_P1CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1DCCR register *****************/ +#define DCMIPP_P1DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1DCCR_HDEC_Pos (1UL) +#define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DCCR_VDEC_Pos (3UL) +#define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1DSCR register *****************/ +#define DCMIPP_P1DSCR_HDIV_Pos (0UL) +#define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_VDIV_Pos (16UL) +#define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */ + +/*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/ +#define DCMIPP_P1DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P1DSSZR register ****************/ +#define DCMIPP_P1DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CMRICR register ***************/ +#define DCMIPP_P1CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P1CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P1CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P1CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P1CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P1CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P1CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P1CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P1CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/ +#define DCMIPP_P1RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P1RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P1RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P1RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P1RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/ +#define DCMIPP_P1RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P1RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P1GMCR register *****************/ +#define DCMIPP_P1GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/ + +/**************** Bit definition for DCMIPP_P1YUVCR register ****************/ +#define DCMIPP_P1YUVCR_ENABLE_Pos (0UL) +#define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1YUVCR_TYPE_Pos (1UL) +#define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */ +#define DCMIPP_P1YUVCR_CLAMP_Pos (2UL) +#define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/ +#define DCMIPP_P1YUVRR1_RR_Pos (0UL) +#define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1YUVRR1_RG_Pos (16UL) +#define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/ +#define DCMIPP_P1YUVRR2_RB_Pos (0UL) +#define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1YUVRR2_RA_Pos (16UL) +#define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/ +#define DCMIPP_P1YUVGR1_GR_Pos (0UL) +#define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1YUVGR1_GG_Pos (16UL) +#define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/ +#define DCMIPP_P1YUVGR2_GB_Pos (0UL) +#define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1YUVGR2_GA_Pos (16UL) +#define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/ +#define DCMIPP_P1YUVBR1_BR_Pos (0UL) +#define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1YUVBR1_BG_Pos (16UL) +#define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/ +#define DCMIPP_P1YUVBR2_BB_Pos (0UL) +#define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1YUVBR2_BA_Pos (16UL) +#define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1PPCR register *****************/ +#define DCMIPP_P1PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P1PPCR_DBM_Pos (16UL) +#define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P1PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P1PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/ +#define DCMIPP_P1PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/ +#define DCMIPP_P1PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */ + +/*************** Bit definition for DCMIPP_P1PPM0PR register ****************/ +#define DCMIPP_P1PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/ +#define DCMIPP_P1PPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/ +#define DCMIPP_P1PPM1AR2_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1PR register ****************/ +#define DCMIPP_P1PPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1STM1AR register ****************/ +#define DCMIPP_P1STM1AR_M1A_Pos (0UL) +#define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */ + +/*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/ +#define DCMIPP_P1PPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/ +#define DCMIPP_P1PPM2AR2_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */ + +/*************** Bit definition for DCMIPP_P1STM2AR register ****************/ +#define DCMIPP_P1STM2AR_M2A_Pos (0UL) +#define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */ + +/***************** Bit definition for DCMIPP_P1IER register *****************/ +#define DCMIPP_P1IER_LINEIE_Pos (0UL) +#define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P1IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P1IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P1IER_OVRIE_Pos (7UL) +#define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P1SR register ******************/ +#define DCMIPP_P1SR_LINEF_Pos (0UL) +#define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P1SR_FRAMEF_Pos (1UL) +#define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P1SR_VSYNCF_Pos (2UL) +#define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P1SR_OVRF_Pos (7UL) +#define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P1SR_LSTLINE_Pos (16UL) +#define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_LSTFRM_Pos (17UL) +#define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_CPTACT_Pos (23UL) +#define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P1FCR register *****************/ +#define DCMIPP_P1FCR_CLINEF_Pos (0UL) +#define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P1FCR_COVRF_Pos (7UL) +#define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P1CFSCR register ****************/ +#define DCMIPP_P1CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */ +#define DCMIPP_P1CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */ +#define DCMIPP_P1CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */ +#define DCMIPP_P1CFSCR_VC_Pos (19UL) +#define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P1CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P1CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P1CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P1CBPRCR register ****************/ +#define DCMIPP_P1CBPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */ +#define DCMIPP_P1CBPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */ + +/*************** Bit definition for DCMIPP_P1CBLCCR register ****************/ +#define DCMIPP_P1CBLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */ +#define DCMIPP_P1CBLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */ +#define DCMIPP_P1CBLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */ +#define DCMIPP_P1CBLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/ +#define DCMIPP_P1CEXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */ +#define DCMIPP_P1CEXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */ +#define DCMIPP_P1CEXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/ +#define DCMIPP_P1CEXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */ +#define DCMIPP_P1CEXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */ +#define DCMIPP_P1CEXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */ +#define DCMIPP_P1CEXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */ + +/*************** Bit definition for DCMIPP_P1CST1CR register ****************/ +#define DCMIPP_P1CST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */ +#define DCMIPP_P1CST1CR_BINS_Pos (2UL) +#define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */ +#define DCMIPP_P1CST1CR_SRC_Pos (4UL) +#define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */ +#define DCMIPP_P1CST1CR_MODE_Pos (7UL) +#define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */ +#define DCMIPP_P1CST1CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST2CR register ****************/ +#define DCMIPP_P1CST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST2CR_BINS_Pos (2UL) +#define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST2CR_SRC_Pos (4UL) +#define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */ +#define DCMIPP_P1CST2CR_MODE_Pos (7UL) +#define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */ +#define DCMIPP_P1CST2CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST3CR register ****************/ +#define DCMIPP_P1CST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST3CR_BINS_Pos (2UL) +#define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST3CR_SRC_Pos (4UL) +#define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1CST3CR_MODE_Pos (7UL) +#define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */ +#define DCMIPP_P1CST3CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CSTSTR register ****************/ +#define DCMIPP_P1CSTSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CSTSZR register ****************/ +#define DCMIPP_P1CSTSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CSTSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */ + +/**************** Bit definition for DCMIPP_P1CCCCR register ****************/ +#define DCMIPP_P1CCCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */ +#define DCMIPP_P1CCCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/ +#define DCMIPP_P1CCCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/ +#define DCMIPP_P1CCCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/ +#define DCMIPP_P1CCCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/ +#define DCMIPP_P1CCCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/ +#define DCMIPP_P1CCCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/ +#define DCMIPP_P1CCCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/ +#define DCMIPP_P1CCTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */ +#define DCMIPP_P1CCTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/ +#define DCMIPP_P1CCTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/ +#define DCMIPP_P1CCTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CFCTCR register ****************/ +#define DCMIPP_P1CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P1CCRSTR register ****************/ +#define DCMIPP_P1CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CCRSZR register ****************/ +#define DCMIPP_P1CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P1CDCCR register *****************/ +#define DCMIPP_P1CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1CDSCR register ****************/ +#define DCMIPP_P1CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/ +#define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P1CDSSZR register ****************/ +#define DCMIPP_P1CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CPPCR register ****************/ +#define DCMIPP_P1CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ + +/************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/ +#define DCMIPP_P1CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/ +#define DCMIPP_P1CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/ +#define DCMIPP_P1CPPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/ +#define DCMIPP_P1CPPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/ +#define DCMIPP_P1CPPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */ + +/**************** Bit definition for DCMIPP_P2FSCR register *****************/ +#define DCMIPP_P2FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */ +#define DCMIPP_P2FSCR_VC_Pos (19UL) +#define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P2FSCR_FDTF_Pos (24UL) +#define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P2FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P2FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P2FCTCR register ****************/ +#define DCMIPP_P2FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P2CRSTR register ****************/ +#define DCMIPP_P2CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CRSZR register ****************/ +#define DCMIPP_P2CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P2DCCR register *****************/ +#define DCMIPP_P2DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2DCCR_HDEC_Pos (1UL) +#define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2DCCR_VDEC_Pos (3UL) +#define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2DSCR register *****************/ +#define DCMIPP_P2DSCR_HDIV_Pos (0UL) +#define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_VDIV_Pos (16UL) +#define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/ +#define DCMIPP_P2DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P2DSSZR register ****************/ +#define DCMIPP_P2DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2GMCR register *****************/ +#define DCMIPP_P2GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2CMRICR register ***************/ +#define DCMIPP_P2CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P2CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P2CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P2CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P2CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P2CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P2CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P2CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P2CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/ +#define DCMIPP_P2RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P2RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P2RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P2RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P2RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/ +#define DCMIPP_P2RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P2RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P2PPCR register *****************/ +#define DCMIPP_P2PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2PPCR_DBM_Pos (16UL) +#define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/ +#define DCMIPP_P2PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */ + +/*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/ +#define DCMIPP_P2PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2STM0AR_Pos (0UL) +#define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */ + +/***************** Bit definition for DCMIPP_P2IER register *****************/ +#define DCMIPP_P2IER_LINEIE_Pos (0UL) +#define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P2IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P2IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P2IER_OVRIE_Pos (7UL) +#define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P2SR register ******************/ +#define DCMIPP_P2SR_LINEF_Pos (0UL) +#define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P2SR_FRAMEF_Pos (1UL) +#define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P2SR_VSYNCF_Pos (2UL) +#define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P2SR_OVRF_Pos (7UL) +#define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P2SR_LSTLINE_Pos (16UL) +#define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_LSTFRM_Pos (17UL) +#define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_CPTACT_Pos (23UL) +#define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P2FCR register *****************/ +#define DCMIPP_P2FCR_CLINEF_Pos (0UL) +#define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P2FCR_COVRF_Pos (7UL) +#define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P2CFSCR register ****************/ +#define DCMIPP_P2CFSCR_DTID_Pos (0UL) +#define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */ +#define DCMIPP_P2CFSCR_VC_Pos (19UL) +#define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P2CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P2CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P2CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P2CFCTCR register ****************/ +#define DCMIPP_P2CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P2CCRSTR register ****************/ +#define DCMIPP_P2CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P2CCRSZR register ****************/ +#define DCMIPP_P2CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P2CDCCR register *****************/ +#define DCMIPP_P2CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2CDSCR register ****************/ +#define DCMIPP_P2CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/ +#define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P2CDSSZR register ****************/ +#define DCMIPP_P2CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CPPCR register ****************/ +#define DCMIPP_P2CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2CPPCR_DBM_Pos (16UL) +#define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2CPPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2CPPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/ +#define DCMIPP_P2CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/ +#define DCMIPP_P2CPPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */ + +/*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/ +#define DCMIPP_P2CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/**************** Bit definition for DCMIPP_HWCFGR2 register ****************/ +#define DCMIPP_HWCFGR2_VPFT_Pos (0UL) +#define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */ +#define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */ +#define DCMIPP_HWCFGR2_DBMFT_Pos (4UL) +#define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */ +#define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */ +#define DCMIPP_HWCFGR2_PROCCLK_Pos (8UL) +#define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */ +#define DCMIPP_HWCFGR2_ADDMOD_Pos (12UL) +#define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */ +#define DCMIPP_HWCFGR2_DEC1_Pos (16UL) +#define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */ +#define DCMIPP_HWCFGR2_DEC2_Pos (17UL) +#define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */ +#define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */ +#define DCMIPP_HWCFGR2_MCU_Pos (20UL) +#define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */ +#define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */ +#define DCMIPP_HWCFGR2_TPG_Pos (24UL) +#define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */ +#define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */ +#define DCMIPP_HWCFGR2_STV_Pos (28UL) +#define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */ +#define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */ + +/**************** Bit definition for DCMIPP_HWCFGR1 register ****************/ +#define DCMIPP_HWCFGR1_CSIFT_Pos (0UL) +#define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */ +#define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */ +#define DCMIPP_HWCFGR1_PIPENB_Pos (4UL) +#define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */ +#define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */ +#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8UL) +#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */ +#define DCMIPP_HWCFGR1_DSP1FT_Pos (12UL) +#define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */ +#define DCMIPP_HWCFGR1_DSP2FT_Pos (13UL) +#define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */ +#define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */ +#define DCMIPP_HWCFGR1_RB2RGB_Pos (16UL) +#define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */ +#define DCMIPP_HWCFGR1_PLANARFT_Pos (20UL) +#define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */ +#define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI1NB_Pos (24UL) +#define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */ +#define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI2NB_Pos (28UL) +#define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */ +#define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */ + +/***************** Bit definition for DCMIPP_VERR register ******************/ +#define DCMIPP_VERR_MINREV_Pos (0UL) +#define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */ +#define DCMIPP_VERR_MAJREV_Pos (4UL) +#define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */ + +/***************** Bit definition for DCMIPP_IPIDR register *****************/ +#define DCMIPP_IPIDR_IDR_Pos (0UL) +#define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */ + +/***************** Bit definition for DCMIPP_SIDR register ******************/ +#define DCMIPP_SIDR_SID_Pos (0UL) +#define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */ + +/******************************************************************************/ +/* */ +/* Delay Block Interface (DLYBSD) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DLYBSD_CFGR register ********************/ +#define DLYB_CFGR_SDMMC_DLL_EN_Pos (0UL) +#define DLYB_CFGR_SDMMC_DLL_EN_Msk (0x1UL << DLYB_CFGR_SDMMC_DLL_EN_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SDMMC_DLL_EN DLYB_CFGR_SDMMC_DLL_EN_Msk /*!= AAW[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWHPCR_WHSPPOS_Pos (16UL) +#define LTDC_LxWHPCR_WHSPPOS_Msk (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos) +#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxWVPCR register */ +#define LTDC_LxWVPCR_WVSTPOS_Pos (0UL) +#define LTDC_LxWVPCR_WVSTPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos) +#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWVPCR_WVSPPOS_Pos (16UL) +#define LTDC_LxWVPCR_WVSPPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos) +#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxCKCR register */ +#define LTDC_LxCKCR_CKBLUE_Pos (0UL) +#define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos) +#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */ +#define LTDC_LxCKCR_CKGREEN_Pos (8UL) +#define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos) +#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */ +#define LTDC_LxCKCR_CKRED_Pos (16UL) +#define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos) +#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */ + +/* Bit fields for LTDC_LxPFCR register */ +#define LTDC_LxPFCR_PF_Pos (0UL) +#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) +#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */ + +/* Bit fields for LTDC_LxCACR register */ +#define LTDC_LxCACR_CONSTA_Pos (0UL) +#define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos) +#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */ + +/* Bit fields for LTDC_LxDCCR register */ +#define LTDC_LxDCCR_DCBLUE_Pos (0UL) +#define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos) +#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */ +#define LTDC_LxDCCR_DCGREEN_Pos (8UL) +#define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos) +#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */ +#define LTDC_LxDCCR_DCRED_Pos (16UL) +#define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos) +#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */ +#define LTDC_LxDCCR_DCALPHA_Pos (24UL) +#define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos) +#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */ + +/* Bit fields for LTDC_LxBFCR register */ +#define LTDC_LxBFCR_BF2_Pos (0UL) +#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) +#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */ +#define LTDC_LxBFCR_BF1_Pos (8UL) +#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) +#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */ +#define LTDC_LxBFCR_BOR_Pos (16UL) +#define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos) +#define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */ + +/* Bit fields for LTDC_LxBLCR register */ +#define LTDC_LxBLCR_BL_Pos (0UL) +#define LTDC_LxBLCR_BL_Msk (0x1fUL << LTDC_LxBLCR_BL_Pos) +#define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */ + +/* Bit fields for LTDC_LxPCR register */ +#define LTDC_LxPCR_YCEN_Pos (3UL) +#define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos) +#define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */ +#define LTDC_LxPCR_YCM_Pos (4UL) +#define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos) +#define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */ +#define LTDC_LxPCR_YF_Pos (6UL) +#define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos) +#define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */ +#define LTDC_LxPCR_CBF_Pos (7UL) +#define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos) +#define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */ +#define LTDC_LxPCR_OF_Pos (8UL) +#define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos) +#define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */ +#define LTDC_LxPCR_YREN_Pos (9UL) +#define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos) +#define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */ + +/* Bit fields for LTDC_LxCFBAR register */ +#define LTDC_LxCFBAR_CFBADD_Pos (0UL) +#define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos) +#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxCFBLR register */ +#define LTDC_LxCFBLR_CFBLL_Pos (0UL) +#define LTDC_LxCFBLR_CFBLL_Msk (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos) +#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_LxCFBLR_CFBP_Pos (16UL) +#define LTDC_LxCFBLR_CFBP_Msk (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos) +#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxCFBLNR register */ +#define LTDC_LxCFBLNR_CFBLNBR_Pos (0UL) +#define LTDC_LxCFBLNR_CFBLNBR_Msk (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos) +#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_L1AFBA0R register */ +#define LTDC_L1AFBA0R_AFBADD0_Pos (0UL) +#define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos) +#define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBA1R register */ +#define LTDC_L1AFBA1R_AFBADD1_Pos (0UL) +#define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos) +#define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBLR register */ +#define LTDC_L1AFBLR_AFBLL_Pos (0UL) +#define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos) +#define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_L1AFBLR_AFBP_Pos (16UL) +#define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos) +#define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxAFBLNR register */ +#define LTDC_L1AFBLNR_AFBLNBR_Pos (0UL) +#define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos) +#define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_LxCLUTWR register */ +#define LTDC_LxCLUTWR_BLUE_Pos (0UL) +#define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos) +#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */ +#define LTDC_LxCLUTWR_GREEN_Pos (8UL) +#define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos) +#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */ +#define LTDC_LxCLUTWR_RED_Pos (16UL) +#define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos) +#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */ +#define LTDC_LxCLUTWR_CLUTADD_Pos (24UL) +#define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos) +#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */ + +/* Bit fields for LTDC_LxCYR0R register */ +#define LTDC_LxCYR0R_CR2R_Pos (0UL) +#define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos) +#define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR0R_CB2B_Pos (16UL) +#define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos) +#define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxCYR1R register */ +#define LTDC_LxCYR1R_CR2G_Pos (0UL) +#define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos) +#define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR1R_CB2G_Pos (16UL) +#define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos) +#define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxFPF0R register */ +#define LTDC_LxFPF0R_APOS_Pos (0UL) +#define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos) +#define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_ALEN_Pos (5UL) +#define LTDC_LxFPF0R_ALEN_Msk (0xfUL << LTDC_LxFPF0R_ALEN_Pos) +#define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF0R_RPOS_Pos (9UL) +#define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos) +#define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_RLEN_Pos (14UL) +#define LTDC_LxFPF0R_RLEN_Msk (0xfUL << LTDC_LxFPF0R_RLEN_Pos) +#define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */ + +/* Bit fields for LTDC_LxFPF1R register */ +#define LTDC_LxFPF1R_GPOS_Pos (0UL) +#define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos) +#define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_GLEN_Pos (5UL) +#define LTDC_LxFPF1R_GLEN_Msk (0xfUL << LTDC_LxFPF1R_GLEN_Pos) +#define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF1R_BPOS_Pos (9UL) +#define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos) +#define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_BLEN_Pos (14UL) +#define LTDC_LxFPF1R_BLEN_Msk (0xfUL << LTDC_LxFPF1R_BLEN_Pos) +#define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */ + +#define LTDC_LxFPF1R_PSIZE_Pos (18UL) +#define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos) +#define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */ + + +/******************************************************************************/ +/* */ +/* Memory Cipher Engine (MCE) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for MCE_CR register ********************/ +#define MCE_CR_GLOCK_Pos (0UL) +#define MCE_CR_GLOCK_Msk (0x1UL << MCE_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define MCE_CR_GLOCK MCE_CR_GLOCK_Msk /*!< MCE global lock */ +#define MCE_CR_MKLOCK_Pos (1UL) +#define MCE_CR_MKLOCK_Msk (0x1UL << MCE_CR_MKLOCK_Pos) /*!< 0x00000002 */ +#define MCE_CR_MKLOCK MCE_CR_MKLOCK_Msk /*!< MCE master and fast master keys lock */ +#define MCE_CR_CIPHERSEL_Pos (4UL) +#define MCE_CR_CIPHERSEL_Msk (0x3UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000030 */ +#define MCE_CR_CIPHERSEL MCE_CR_CIPHERSEL_Msk /*!< MCE Cipher selection */ +#define MCE_CR_CIPHERSEL_0 (0x1UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000010 */ +#define MCE_CR_CIPHERSEL_1 (0x2UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000020 */ + +/******************** Bit definition for MCE_SR register ********************/ +#define MCE_SR_MKVALID_Pos (0UL) +#define MCE_SR_MKVALID_Msk (0x1UL << MCE_SR_MKVALID_Pos) /*!< 0x00000001 */ +#define MCE_SR_MKVALID MCE_SR_MKVALID_Msk /*!< MCE master key valid flag */ +#define MCE_SR_FMKVALID_Pos (2UL) +#define MCE_SR_FMKVALID_Msk (0x1UL << MCE_SR_FMKVALID_Pos) /*!< 0x00000004 */ +#define MCE_SR_FMKVALID MCE_SR_FMKVALID_Msk /*!< MCE fast master key valid flag */ +#define MCE_SR_ENCDIS_Pos (4UL) +#define MCE_SR_ENCDIS_Msk (0x1UL << MCE_SR_ENCDIS_Pos) /*!< 0x00000010 */ +#define MCE_SR_ENCDIS MCE_SR_ENCDIS_Msk /*!< MCE encryption disabled flag */ + +/******************** Bit definition for MCE_IASR register ******************/ +#define MCE_IASR_IAEF_Pos (1UL) +#define MCE_IASR_IAEF_Msk (0x1UL << MCE_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define MCE_IASR_IAEF MCE_IASR_IAEF_Msk /*!< MCE illegal access error flag */ + +/******************** Bit definition for MCE_IACR register ******************/ +#define MCE_IACR_IAEF_Pos (1UL) +#define MCE_IACR_IAEF_Msk (0x1UL << MCE_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define MCE_IACR_IAEF MCE_IACR_IAEF_Msk /*!< MCE illegal access error clear bit */ + +/******************** Bit definition for MCE_IAIER register *****************/ +#define MCE_IAIER_IAEIE_Pos (1UL) +#define MCE_IAIER_IAEIE_Msk (0x1UL << MCE_IAIER_IAEIE_Pos) /*!< 0x00000002 */ +#define MCE_IAIER_IAEIE MCE_IAIER_IAEIE_Msk /*!< MCE illegal access error interrupt enable */ + +/******************** Bit definition for MCE_IADDR register *****************/ +#define MCE_IADDR_IADD_Pos (0UL) +#define MCE_IADDR_IADD_Msk (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define MCE_IADDR_IADD MCE_IADDR_IADD_Msk /*!< MCE illegal access */ + +/******************** Bit definition for MCE_REGCR register *****************/ +#define MCE_REGCR_BREN_Pos (0UL) +#define MCE_REGCR_BREN_Msk (0x1UL << MCE_REGCR_BREN_Pos) /*!< 0x00000001 */ +#define MCE_REGCR_BREN MCE_REGCR_BREN_Msk /*!< MCE base region enable */ +#define MCE_REGCR_CTXID_Pos (9UL) +#define MCE_REGCR_CTXID_Msk (0x3UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000600 */ +#define MCE_REGCR_CTXID MCE_REGCR_CTXID_Msk /*!< MCE context ID */ +#define MCE_REGCR_CTXID_0 (0x1UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000200 */ +#define MCE_REGCR_CTXID_1 (0x2UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000400 */ +#define MCE_REGCR_ENC_Pos (14UL) +#define MCE_REGCR_ENC_Msk (0x3UL << MCE_REGCR_ENC_Pos) /*!< 0x0000C000 */ +#define MCE_REGCR_ENC MCE_REGCR_ENC_Msk /*!< MCE encrypted region */ +#define MCE_REGCR_ENC_0 (0x1UL << MCE_REGCR_ENC_Pos) /*!< 0x00004000 */ +#define MCE_REGCR_ENC_1 (0x2UL << MCE_REGCR_ENC_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for MCE_SADDR register *****************/ +#define MCE_SADDR_BADDSTART_Pos (12UL) +#define MCE_SADDR_BADDSTART_Msk (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos) /*!< 0xFFFFF000 */ +#define MCE_SADDR_BADDSTART MCE_SADDR_BADDSTART_Msk /*!< MCE region address start */ + +/******************** Bit definition for MCE_EADDR register *****************/ +#define MCE_EADDR_BADDEND_Pos (12UL) +#define MCE_EADDR_BADDEND_Msk (0xFFFFFUL << MCE_EADDR_BADDEND_Pos) /*!< 0xFFFFF000 */ +#define MCE_EADDR_BADDEND MCE_EADDR_BADDEND_Msk /*!< MCE region address end */ + +/******************** Bit definition for MCE_MKEYR0 register ****************/ +#define MCE_MKEYR0_MKEY_Pos (0UL) +#define MCE_MKEYR0_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR0_MKEY MCE_MKEYR0_MKEY_Msk /*!< MCE master key, bits [31:0] */ + +/******************** Bit definition for MCE_MKEYR1 register ****************/ +#define MCE_MKEYR1_MKEY_Pos (0UL) +#define MCE_MKEYR1_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR1_MKEY MCE_MKEYR1_MKEY_Msk /*!< MCE master key, bits [63:32] */ + +/******************** Bit definition for MCE_MKEYR2 register ****************/ +#define MCE_MKEYR2_MKEY_Pos (0UL) +#define MCE_MKEYR2_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR2_MKEY MCE_MKEYR2_MKEY_Msk /*!< MCE master key, bits [95:64] */ + +/******************** Bit definition for MCE_MKEYR3 register ****************/ +#define MCE_MKEYR3_MKEY_Pos (0UL) +#define MCE_MKEYR3_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR3_MKEY MCE_MKEYR3_MKEY_Msk /*!< MCE master key, bits [127:96] */ + +/******************** Bit definition for MCE_MKEYR4 register ****************/ +#define MCE_MKEYR4_MKEY_Pos (0UL) +#define MCE_MKEYR4_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR4_MKEY MCE_MKEYR4_MKEY_Msk /*!< MCE master key, bits [159:128] */ + +/******************** Bit definition for MCE_MKEYR5 register ****************/ +#define MCE_MKEYR5_MKEY_Pos (0UL) +#define MCE_MKEYR5_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR5_MKEY MCE_MKEYR5_MKEY_Msk /*!< MCE master key, bits [191:160] */ + +/******************** Bit definition for MCE_MKEYR6 register ****************/ +#define MCE_MKEYR6_MKEY_Pos (0UL) +#define MCE_MKEYR6_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR6_MKEY MCE_MKEYR6_MKEY_Msk /*!< MCE master key, bits [223:192] */ + +/******************** Bit definition for MCE_MKEYR7 register ****************/ +#define MCE_MKEYR7_MKEY_Pos (0UL) +#define MCE_MKEYR7_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR7_MKEY MCE_MKEYR7_MKEY_Msk /*!< MCE master key, bits [255:224] */ + +/******************** Bit definition for MCE_FMKEYR0 register ***************/ +#define MCE_FMKEYR0_FMKEY_Pos (0UL) +#define MCE_FMKEYR0_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR0_FMKEY MCE_FMKEYR0_FMKEY_Msk /*!< MCE fast master key, bits [31:0] */ + +/******************** Bit definition for MCE_FMKEYR1 register ***************/ +#define MCE_FMKEYR1_FMKEY_Pos (0UL) +#define MCE_FMKEYR1_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR1_FMKEY MCE_FMKEYR1_FMKEY_Msk /*!< MCE fast master key, bits [63:32] */ + +/******************** Bit definition for MCE_FMKEYR2 register ***************/ +#define MCE_FMKEYR2_FMKEY_Pos (0UL) +#define MCE_FMKEYR2_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR2_FMKEY MCE_FMKEYR2_FMKEY_Msk /*!< MCE fast master key, bits [95:64] */ + +/******************** Bit definition for MCE_FMKEYR3 register ***************/ +#define MCE_FMKEYR3_FMKEY_Pos (0UL) +#define MCE_FMKEYR3_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR3_FMKEY MCE_FMKEYR3_FMKEY_Msk /*!< MCE fast master key, bits [127:96] */ + +/******************** Bit definition for MCE_FMKEYR4 register ****************/ +#define MCE_FMKEYR4_FMKEY_Pos (0UL) +#define MCE_FMKEYR4_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR4_FMKEY MCE_FMKEYR4_FMKEY_Msk /*!< MCE fast master key, bits [159:128] */ + +/******************** Bit definition for MCE_FMKEYR5 register ****************/ +#define MCE_FMKEYR5_FMKEY_Pos (0UL) +#define MCE_FMKEYR5_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR5_FMKEY MCE_FMKEYR5_FMKEY_Msk /*!< MCE fast master key, bits [191:160] */ + +/******************** Bit definition for MCE_FMKEYR6 register ****************/ +#define MCE_FMKEYR6_FMKEY_Pos (0UL) +#define MCE_FMKEYR6_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR6_FMKEY MCE_FMKEYR6_FMKEY_Msk /*!< MCE fast master key, bits [223:192] */ + +/******************** Bit definition for MCE_FMKEYR7 register ****************/ +#define MCE_FMKEYR7_FMKEY_Pos (0UL) +#define MCE_FMKEYR7_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR7_FMKEY MCE_FMKEYR7_FMKEY_Msk /*!< MCE fast master key, bits [255:224] */ + +/******************** Bit definition for MCE_CCCFGR register ****************/ +#define MCE_CCCFGR_CCEN_Pos (0UL) +#define MCE_CCCFGR_CCEN_Msk (0x1UL << MCE_CCCFGR_CCEN_Pos) /*!< 0x00000001 */ +#define MCE_CCCFGR_CCEN MCE_CCCFGR_CCEN_Msk /*!< MCE cipher context enable */ +#define MCE_CCCFGR_CCLOCK_Pos (1UL) +#define MCE_CCCFGR_CCLOCK_Msk (0x1UL << MCE_CCCFGR_CCLOCK_Pos) /*!< 0x00000002 */ +#define MCE_CCCFGR_CCLOCK MCE_CCCFGR_CCLOCK_Msk /*!< MCE cipher context lock */ +#define MCE_CCCFGR_KEYLOCK_Pos (2UL) +#define MCE_CCCFGR_KEYLOCK_Msk (0x1UL << MCE_CCCFGR_KEYLOCK_Pos) /*!< 0x00000004 */ +#define MCE_CCCFGR_KEYLOCK MCE_CCCFGR_KEYLOCK_Msk /*!< MCE cipher context key lock */ +#define MCE_CCCFGR_MODE_Pos (4UL) +#define MCE_CCCFGR_MODE_Msk (0x3UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000030 */ +#define MCE_CCCFGR_MODE MCE_CCCFGR_MODE_Msk /*!< MCE authorized cipher mode */ +#define MCE_CCCFGR_MODE_0 (0x1UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000010 */ +#define MCE_CCCFGR_MODE_1 (0x2UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000020 */ +#define MCE_CCCFGR_KEYCRC_Pos (8UL) +#define MCE_CCCFGR_KEYCRC_Msk (0xFFUL << MCE_CCCFGR_KEYCRC_Pos) /*!< 0x0000FF00 */ +#define MCE_CCCFGR_KEYCRC MCE_CCCFGR_KEYCRC_Msk /*!< MCE cipher context key CRC */ +#define MCE_CCCFGR_VERSION_Pos (16UL) +#define MCE_CCCFGR_VERSION_Msk (0xFFFFUL << MCE_CCCFGR_VERSION_Pos) /*!< 0xFFFF0000 */ +#define MCE_CCCFGR_VERSION MCE_CCCFGR_VERSION_Msk /*!< MCE cipher context version */ + +/******************** Bit definition for MCE_CCNR0 register *****************/ +#define MCE_CCNR0_SCNONCE_Pos (0UL) +#define MCE_CCNR0_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCNR0_SCNONCE MCE_CCNR0_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [31:0] */ + +/******************** Bit definition for MCE_CCNR1 register ****************/ +#define MCE_CCNR1_SCNONCE_Pos (0UL) +#define MCE_CCNR1_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCNR1_SCNONCE MCE_CCNR1_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [63:32] */ + +/******************** Bit definition for MCE_CCKEYR0 register ***************/ +#define MCE_CCKEYR0_KEY_Pos (0UL) +#define MCE_CCKEYR0_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR0_KEY MCE_CCKEYR0_KEY_Msk /*!< MCE cipher context key, bits [31:0] */ + +/******************** Bit definition for MCE_CCKEYR1 register ***************/ +#define MCE_CCKEYR1_KEY_Pos (0UL) +#define MCE_CCKEYR1_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR1_KEY MCE_CCKEYR1_KEY_Msk /*!< MCE fast master key, bits [63:32] */ + +/******************** Bit definition for MCE_CCKEYR2 register ***************/ +#define MCE_CCKEYR2_KEY_Pos (0UL) +#define MCE_CCKEYR2_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR2_KEY MCE_CCKEYR2_KEY_Msk /*!< MCE fast master key, bits [95:64] */ + +/******************** Bit definition for MCE_CCKEYR3 register ***************/ +#define MCE_CCKEYR3_KEY_Pos (0UL) +#define MCE_CCKEYR3_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR3_KEY MCE_CCKEYR3_KEY_Msk /*!< MCE fast master key, bits [127:96] */ + + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ****************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */ +#define MDF_GCR_ILVNB_Pos (4UL) +#define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */ +#define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */ + +/******************* Bit definition for MDF/ADF_CKGCR register ********************/ +#define MDF_CKGCR_CKDEN_Pos (0UL) +#define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */ +#define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5UL) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6UL) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8UL) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10UL) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14UL) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18UL) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29UL) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30UL) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31UL) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2UL) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3UL) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register *******************/ +#define PSSI_RIS_OVR_RIS_Pos (1UL) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register *******************/ +#define PSSI_IER_OVR_IE_Pos (1UL) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register *******************/ +#define PSSI_MIS_OVR_MIS_Pos (1UL) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register *******************/ +#define PSSI_ICR_OVR_ISC_Pos (1UL) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0UL) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************* Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_SDEN_Pos (2UL) +#define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */ +#define PWR_CR1_MODE_PDN_Pos (4UL) +#define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */ +#define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */ +#define PWR_CR1_LPDS08V_Pos (5UL) +#define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */ +#define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */ +#define PWR_CR1_VDD18SMPSVMEN_Pos (8UL) +#define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */ +#define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */ +#define PWR_CR1_VDD18SMPSRDY_Pos (15UL) +#define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */ +#define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */ +#define PWR_CR1_POPL_Pos (16UL) +#define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */ +#define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */ +#define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */ +#define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */ +#define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */ +#define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */ +#define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */ + +/******************* Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDEN_Pos (0UL) +#define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */ +#define PWR_CR2_PVDO_Pos (8UL) +#define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */ +#define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +/******************* Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_VCOREMONEN_Pos (0UL) +#define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */ +#define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */ +#define PWR_CR3_VCORELLS_Pos (4UL) +#define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */ +#define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */ +#define PWR_CR3_VCOREL_Pos (8UL) +#define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */ +#define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */ +#define PWR_CR3_VCOREH_Pos (9UL) +#define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */ +#define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */ + +/******************* Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_TCMRBSEN_Pos (0UL) +#define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */ +#define PWR_CR4_TCMFLXRBSEN_Pos (4UL) +#define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */ +#define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */ + +/****************** Bit definition for PWR_VOSCR register *******************/ +#define PWR_VOSCR_VOS_Pos (0UL) +#define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */ +#define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */ +#define PWR_VOSCR_VOSRDY_Pos (1UL) +#define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSCR_ACTVOS_Pos (16UL) +#define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ +#define PWR_VOSCR_ACTVOSRDY_Pos (17UL) +#define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */ +#define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */ + +/****************** Bit definition for PWR_BDCR1 register *******************/ +#define PWR_BDCR1_MONEN_Pos (0UL) +#define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ +#define PWR_BDCR1_VBATL_Pos (16UL) +#define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */ +#define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */ +#define PWR_BDCR1_VBATH_Pos (17UL) +#define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */ +#define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */ +#define PWR_BDCR1_TEMPL_Pos (18UL) +#define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */ +#define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */ +#define PWR_BDCR1_TEMPH_Pos (19UL) +#define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */ +#define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */ + +/****************** Bit definition for PWR_BDCR2 register *******************/ +#define PWR_BDCR2_BKPRBSEN_Pos (0UL) +#define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */ + +/****************** Bit definition for PWR_DBPCR register *******************/ +#define PWR_DBPCR_DBP_Pos (0UL) +#define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */ + +/****************** Bit definition for PWR_CPUCR register *******************/ +#define PWR_CPUCR_PDDS_Pos (0UL) +#define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */ +#define PWR_CPUCR_CSSF_Pos (1UL) +#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */ +#define PWR_CPUCR_STOPF_Pos (8UL) +#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */ +#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */ +#define PWR_CPUCR_SBF_Pos (9UL) +#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */ +#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */ +#define PWR_CPUCR_SVOS_Pos (16UL) +#define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */ +#define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */ + +/****************** Bit definition for PWR_SVMCR1 register ******************/ +#define PWR_SVMCR1_VDDIO4VMEN_Pos (0UL) +#define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */ +#define PWR_SVMCR1_VDDIO4SV_Pos (8UL) +#define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */ +#define PWR_SVMCR1_VDDIO4RDY_Pos (16UL) +#define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */ +#define PWR_SVMCR1_VDDIO4VRSEL_Pos (24UL) +#define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */ +#define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25UL) +#define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR2 register ******************/ +#define PWR_SVMCR2_VDDIO5VMEN_Pos (0UL) +#define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */ +#define PWR_SVMCR2_VDDIO5SV_Pos (8UL) +#define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */ +#define PWR_SVMCR2_VDDIO5RDY_Pos (16UL) +#define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */ +#define PWR_SVMCR2_VDDIO5VRSEL_Pos (24UL) +#define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */ +#define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25UL) +#define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR3 register ******************/ +#define PWR_SVMCR3_VDDIO2VMEN_Pos (0UL) +#define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */ +#define PWR_SVMCR3_VDDIO3VMEN_Pos (1UL) +#define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */ +#define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */ +#define PWR_SVMCR3_USB33VMEN_Pos (2UL) +#define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */ +#define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */ +#define PWR_SVMCR3_AVMEN_Pos (4UL) +#define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */ +#define PWR_SVMCR3_VDDIO2SV_Pos (8UL) +#define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */ +#define PWR_SVMCR3_VDDIO3SV_Pos (9UL) +#define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */ +#define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */ +#define PWR_SVMCR3_USB33SV_Pos (10UL) +#define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */ +#define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */ +#define PWR_SVMCR3_ASV_Pos (12UL) +#define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */ +#define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */ +#define PWR_SVMCR3_VDDIO2RDY_Pos (16UL) +#define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */ +#define PWR_SVMCR3_VDDIO3RDY_Pos (17UL) +#define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */ +#define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */ +#define PWR_SVMCR3_USB33RDY_Pos (18UL) +#define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */ +#define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */ +#define PWR_SVMCR3_ARDY_Pos (20UL) +#define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */ +#define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */ +#define PWR_SVMCR3_VDDIOVRSEL_Pos (24UL) +#define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */ +#define PWR_SVMCR3_VDDIO2VRSEL_Pos (25UL) +#define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */ +#define PWR_SVMCR3_VDDIO3VRSEL_Pos (26UL) +#define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */ + +/***************** Bit definition for PWR_WKUPCR register *******************/ +#define PWR_WKUPCR_WKUPC1_Pos (0UL) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPCR_WKUPC2_Pos (1UL) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPCR_WKUPC3_Pos (2UL) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPCR_WKUPC4_Pos (3UL) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */ +#define PWR_WKUPCR_WKUPC_Pos (0UL) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */ + +/***************** Bit definition for PWR_WKUPSR register *******************/ +#define PWR_WKUPSR_WKUPF1_Pos (0UL) +#define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPSR_WKUPF2_Pos (1UL) +#define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPSR_WKUPF3_Pos (2UL) +#define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPSR_WKUPF4_Pos (3UL) +#define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */ + +/***************** Bit definition for PWR_WKUPEPR register *******************/ +#define PWR_WKUPEPR_WKUPEN1_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1UL) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2UL) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3UL) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8UL) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPP2_Pos (9UL) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPP3_Pos (10UL) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPP4_Pos (11UL) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPP_Pos (8UL) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16UL) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18UL) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20UL) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22UL) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WKUPEPR_WKUPEN_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ + +/***************** Bit definition for PWR_SECCFGR register ******************/ +#define PWR_SECCFGR_SEC0_Pos (0UL) +#define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */ +#define PWR_SECCFGR_SEC1_Pos (1UL) +#define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */ +#define PWR_SECCFGR_SEC2_Pos (2UL) +#define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */ +#define PWR_SECCFGR_SEC3_Pos (3UL) +#define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */ +#define PWR_SECCFGR_SEC4_Pos (4UL) +#define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */ +#define PWR_SECCFGR_SEC5_Pos (5UL) +#define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */ +#define PWR_SECCFGR_SEC6_Pos (6UL) +#define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */ +#define PWR_SECCFGR_SEC7_Pos (7UL) +#define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */ +#define PWR_SECCFGR_WKUPSEC1_Pos (16UL) +#define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */ +#define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */ +#define PWR_SECCFGR_WKUPSEC2_Pos (17UL) +#define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */ +#define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */ +#define PWR_SECCFGR_WKUPSEC3_Pos (18UL) +#define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */ +#define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */ +#define PWR_SECCFGR_WKUPSEC4_Pos (19UL) +#define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */ +#define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */ + +/***************** Bit definition for PWR_PRIVCFGR register *****************/ +#define PWR_PRIVCFGR_PRIV0_Pos (0UL) +#define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */ +#define PWR_PRIVCFGR_PRIV1_Pos (1UL) +#define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */ +#define PWR_PRIVCFGR_PRIV2_Pos (2UL) +#define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */ +#define PWR_PRIVCFGR_PRIV3_Pos (3UL) +#define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */ +#define PWR_PRIVCFGR_PRIV4_Pos (4UL) +#define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */ +#define PWR_PRIVCFGR_PRIV5_Pos (5UL) +#define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */ +#define PWR_PRIVCFGR_PRIV6_Pos (6UL) +#define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */ +#define PWR_PRIVCFGR_PRIV7_Pos (7UL) +#define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV1_Pos (16UL) +#define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */ +#define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV2_Pos (17UL) +#define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */ +#define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV3_Pos (18UL) +#define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */ +#define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV4_Pos (19UL) +#define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */ +#define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */ + + +/******************************************************************************/ +/* */ +/* RAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_CR register ******************/ +#define RAMCFG_CR_ECCE_Pos (0UL) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */ +#define RAMCFG_CR_ALE_Pos (4UL) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8UL) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_SRAMHWERDIS_Pos (12UL) +#define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */ +#define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */ +#define RAMCFG_CR_ITCMCFG_Pos (16UL) +#define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */ +#define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ +#define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_SRAMSD_Pos (20UL) +#define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */ +#define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */ +#define RAMCFG_CR_DTCMCFG_Pos (24UL) +#define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */ +#define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ + +/******************* Bit definition for RAMCFG_IER register *****************/ +#define RAMCFG_IER_SEIE_Pos (0UL) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */ +#define RAMCFG_IER_DEIE_Pos (1UL) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */ + +/******************* Bit definition for RAMCFG_ISR register *****************/ +#define RAMCFG_ISR_SEDC_Pos (0UL) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */ +#define RAMCFG_ISR_DED_Pos (1UL) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8UL) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */ + +/******************* Bit definition for RAMCFG_ESEAR register ****************/ +#define RAMCFG_ESEAR_ESEA_Pos (0UL) +#define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */ + +/******************* Bit definition for RAMCFG_EDEAR register ****************/ +#define RAMCFG_EDEAR_EDEA_Pos (0UL) +#define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */ + +/******************* Bit definition for RAMCFG_ICR register *****************/ +#define RAMCFG_ICR_CSEDC_Pos (0UL) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */ +#define RAMCFG_ICR_CDED_Pos (1UL) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/ + +/***************** Bit definition for RAMCFG_ECCKEYR register ***************/ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0UL) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */ + +/***************** Bit definition for RAMCFG_ERKEYR register ****************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0UL) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */ + + +/******************************************************************************/ +/* */ +/* (RCC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_LSION_Pos (0UL) +#define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_CR_LSEON_Pos (1UL) +#define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */ +#define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */ +#define RCC_CR_MSION_Pos (2UL) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */ +#define RCC_CR_HSION_Pos (3UL) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */ +#define RCC_CR_HSEON_Pos (4UL) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */ +#define RCC_CR_PLL1ON_Pos (8UL) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */ +#define RCC_CR_PLL2ON_Pos (9UL) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ +#define RCC_CR_PLL3ON_Pos (10UL) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ +#define RCC_CR_PLL4ON_Pos (11UL) +#define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */ +#define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */ + +/******************** Bit definition for RCC_SR register ********************/ +#define RCC_SR_LSIRDY_Pos (0UL) +#define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */ +#define RCC_SR_LSERDY_Pos (1UL) +#define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */ +#define RCC_SR_MSIRDY_Pos (2UL) +#define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */ +#define RCC_SR_HSIRDY_Pos (3UL) +#define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */ +#define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_SR_HSERDY_Pos (4UL) +#define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */ +#define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_SR_PLL1RDY_Pos (8UL) +#define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */ +#define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_SR_PLL2RDY_Pos (9UL) +#define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */ +#define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_SR_PLL3RDY_Pos (10UL) +#define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */ +#define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_SR_PLL4RDY_Pos (11UL) +#define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */ +#define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ + +/****************** Bit definition for RCC_STOPCR register ******************/ +#define RCC_STOPCR_MSISTOPEN_Pos (0UL) +#define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */ +#define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCR_HSISTOPEN_Pos (1UL) +#define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */ +#define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */ + +/****************** Bit definition for RCC_CFGR1 register *******************/ +#define RCC_CFGR1_STOPWUCK_Pos (0UL) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */ +#define RCC_CFGR1_CPUSW_Pos (16UL) +#define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */ +#define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */ +#define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */ +#define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */ +#define RCC_CFGR1_CPUSWS_Pos (20UL) +#define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */ +#define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */ +#define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_SYSSW_Pos (24UL) +#define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */ +#define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */ +#define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_SYSSWS_Pos (28UL) +#define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */ +#define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for RCC_CFGR2 register *******************/ +#define RCC_CFGR2_PPRE1_Pos (0UL) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE2_Pos (4UL) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE4_Pos (12UL) +#define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */ +#define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_PPRE5_Pos (16UL) +#define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */ +#define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */ +#define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */ +#define RCC_CFGR2_HPRE_Pos (20UL) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_TIMPRE_Pos (24UL) +#define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */ +#define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */ +#define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */ +#define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_VSWRST_Pos (31UL) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */ + +/****************** Bit definition for RCC_HWRSR register *******************/ +#define RCC_HWRSR_RMVF_Pos (16UL) +#define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_HWRSR_LCKRSTF_Pos (17UL) +#define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_HWRSR_BORRSTF_Pos (21UL) +#define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_HWRSR_PINRSTF_Pos (22UL) +#define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_HWRSR_PORRSTF_Pos (23UL) +#define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_HWRSR_SFTRSTF_Pos (24UL) +#define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_HWRSR_IWDGRSTF_Pos (26UL) +#define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_HWRSR_WWDGRSTF_Pos (28UL) +#define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_HWRSR_LPWRRSTF_Pos (30UL) +#define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/******************* Bit definition for RCC_RSR register ********************/ +#define RCC_RSR_RMVF_Pos (16UL) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_LCKRSTF_Pos (17UL) +#define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_RSR_BORRSTF_Pos (21UL) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_RSR_PINRSTF_Pos (22UL) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_PORRSTF_Pos (23UL) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (24UL) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_RSR_IWDGRSTF_Pos (26UL) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (28UL) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (30UL) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/***************** Bit definition for RCC_LSECFGR register ******************/ +#define RCC_LSECFGR_LSECSSON_Pos (7UL) +#define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */ +#define RCC_LSECFGR_LSECSSRA_Pos (8UL) +#define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */ +#define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */ +#define RCC_LSECFGR_LSECSSD_Pos (9UL) +#define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */ +#define RCC_LSECFGR_LSEBYP_Pos (15UL) +#define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */ +#define RCC_LSECFGR_LSEEXT_Pos (16UL) +#define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */ +#define RCC_LSECFGR_LSEGFON_Pos (17UL) +#define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */ +#define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */ +#define RCC_LSECFGR_LSEDRV_Pos (18UL) +#define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */ +#define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */ +#define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for RCC_MSICFGR register ******************/ +#define RCC_MSICFGR_MSIFREQSEL_Pos (9UL) +#define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */ +#define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */ +#define RCC_MSICFGR_MSITRIM_Pos (16UL) +#define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */ +#define RCC_MSICFGR_MSICAL_Pos (23UL) +#define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */ +#define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (7UL) +#define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_Pos (16UL) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSICAL_Pos (23UL) +#define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ + +/****************** Bit definition for RCC_HSIMCR register ******************/ +#define RCC_HSIMCR_HSIREF_Pos (0UL) +#define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */ +#define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */ +#define RCC_HSIMCR_HSIDEV_Pos (16UL) +#define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */ +#define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */ +#define RCC_HSIMCR_HSIMONEN_Pos (31UL) +#define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */ +#define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */ + +/****************** Bit definition for RCC_HSIMSR register ******************/ +#define RCC_HSIMSR_HSIVAL_Pos (0UL) +#define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */ +#define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */ + +/***************** Bit definition for RCC_HSECFGR register ******************/ +#define RCC_HSECFGR_HSEDIV2SEL_Pos (6UL) +#define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */ +#define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */ +#define RCC_HSECFGR_HSECSSON_Pos (7UL) +#define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */ +#define RCC_HSECFGR_HSECSSD_Pos (9UL) +#define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */ +#define RCC_HSECFGR_HSECSSBYP_Pos (10UL) +#define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */ +#define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */ +#define RCC_HSECFGR_HSECSSBPRE_Pos (11UL) +#define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */ +#define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */ +#define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */ +#define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */ +#define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */ +#define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */ +#define RCC_HSECFGR_HSEBYP_Pos (15UL) +#define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_HSECFGR_HSEEXT_Pos (16UL) +#define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_PLL1DIVN_Pos (8UL) +#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */ +#define RCC_PLL1CFGR1_PLL1DIVM_Pos (20UL) +#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */ +#define RCC_PLL1CFGR1_PLL1BYP_Pos (27UL) +#define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */ +#define RCC_PLL1CFGR1_PLL1SEL_Pos (28UL) +#define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */ +#define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0UL) +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL1CFGR3 register *****************/ +#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0UL) +#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */ +#define RCC_PLL1CFGR3_PLL1DACEN_Pos (1UL) +#define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2UL) +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */ +#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3UL) +#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4UL) +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */ +#define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8UL) +#define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */ +#define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16UL) +#define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */ +#define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24UL) +#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */ +#define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27UL) +#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30UL) +#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_PLL2DIVN_Pos (8UL) +#define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */ +#define RCC_PLL2CFGR1_PLL2DIVM_Pos (20UL) +#define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */ +#define RCC_PLL2CFGR1_PLL2BYP_Pos (27UL) +#define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */ +#define RCC_PLL2CFGR1_PLL2SEL_Pos (28UL) +#define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */ +#define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0UL) +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL2CFGR3 register *****************/ +#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0UL) +#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */ +#define RCC_PLL2CFGR3_PLL2DACEN_Pos (1UL) +#define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2UL) +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */ +#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3UL) +#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4UL) +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */ +#define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8UL) +#define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */ +#define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16UL) +#define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */ +#define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24UL) +#define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */ +#define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27UL) +#define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30UL) +#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_PLL3DIVN_Pos (8UL) +#define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */ +#define RCC_PLL3CFGR1_PLL3DIVM_Pos (20UL) +#define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */ +#define RCC_PLL3CFGR1_PLL3BYP_Pos (27UL) +#define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */ +#define RCC_PLL3CFGR1_PLL3SEL_Pos (28UL) +#define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */ +#define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0UL) +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL3CFGR3 register *****************/ +#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0UL) +#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */ +#define RCC_PLL3CFGR3_PLL3DACEN_Pos (1UL) +#define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2UL) +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */ +#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3UL) +#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4UL) +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */ +#define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8UL) +#define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */ +#define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16UL) +#define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */ +#define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24UL) +#define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */ +#define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27UL) +#define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30UL) +#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_PLL4DIVN_Pos (8UL) +#define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */ +#define RCC_PLL4CFGR1_PLL4DIVM_Pos (20UL) +#define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */ +#define RCC_PLL4CFGR1_PLL4BYP_Pos (27UL) +#define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */ +#define RCC_PLL4CFGR1_PLL4SEL_Pos (28UL) +#define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */ +#define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0UL) +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL4CFGR3 register *****************/ +#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0UL) +#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */ +#define RCC_PLL4CFGR3_PLL4DACEN_Pos (1UL) +#define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2UL) +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */ +#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3UL) +#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4UL) +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */ +#define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8UL) +#define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */ +#define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16UL) +#define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */ +#define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24UL) +#define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */ +#define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27UL) +#define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30UL) +#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/***************** Bit definition for RCC_IC1CFGR register ******************/ +#define RCC_IC1CFGR_IC1INT_Pos (16UL) +#define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */ +#define RCC_IC1CFGR_IC1SEL_Pos (28UL) +#define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */ +#define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC2CFGR register ******************/ +#define RCC_IC2CFGR_IC2INT_Pos (16UL) +#define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */ +#define RCC_IC2CFGR_IC2SEL_Pos (28UL) +#define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */ +#define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC3CFGR register ******************/ +#define RCC_IC3CFGR_IC3INT_Pos (16UL) +#define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */ +#define RCC_IC3CFGR_IC3SEL_Pos (28UL) +#define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */ +#define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC4CFGR register ******************/ +#define RCC_IC4CFGR_IC4INT_Pos (16UL) +#define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */ +#define RCC_IC4CFGR_IC4SEL_Pos (28UL) +#define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */ +#define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC5CFGR register ******************/ +#define RCC_IC5CFGR_IC5INT_Pos (16UL) +#define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */ +#define RCC_IC5CFGR_IC5SEL_Pos (28UL) +#define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */ +#define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC6CFGR register ******************/ +#define RCC_IC6CFGR_IC6INT_Pos (16UL) +#define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */ +#define RCC_IC6CFGR_IC6SEL_Pos (28UL) +#define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */ +#define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC7CFGR register ******************/ +#define RCC_IC7CFGR_IC7INT_Pos (16UL) +#define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */ +#define RCC_IC7CFGR_IC7SEL_Pos (28UL) +#define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */ +#define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC8CFGR register ******************/ +#define RCC_IC8CFGR_IC8INT_Pos (16UL) +#define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */ +#define RCC_IC8CFGR_IC8SEL_Pos (28UL) +#define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */ +#define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC9CFGR register ******************/ +#define RCC_IC9CFGR_IC9INT_Pos (16UL) +#define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */ +#define RCC_IC9CFGR_IC9SEL_Pos (28UL) +#define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */ +#define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC10CFGR register *****************/ +#define RCC_IC10CFGR_IC10INT_Pos (16UL) +#define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */ +#define RCC_IC10CFGR_IC10SEL_Pos (28UL) +#define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */ +#define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC11CFGR register *****************/ +#define RCC_IC11CFGR_IC11INT_Pos (16UL) +#define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */ +#define RCC_IC11CFGR_IC11SEL_Pos (28UL) +#define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */ +#define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC12CFGR register *****************/ +#define RCC_IC12CFGR_IC12INT_Pos (16UL) +#define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */ +#define RCC_IC12CFGR_IC12SEL_Pos (28UL) +#define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */ +#define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC13CFGR register *****************/ +#define RCC_IC13CFGR_IC13INT_Pos (16UL) +#define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */ +#define RCC_IC13CFGR_IC13SEL_Pos (28UL) +#define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */ +#define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC14CFGR register *****************/ +#define RCC_IC14CFGR_IC14INT_Pos (16UL) +#define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */ +#define RCC_IC14CFGR_IC14SEL_Pos (28UL) +#define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */ +#define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC15CFGR register *****************/ +#define RCC_IC15CFGR_IC15INT_Pos (16UL) +#define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */ +#define RCC_IC15CFGR_IC15SEL_Pos (28UL) +#define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */ +#define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC16CFGR register *****************/ +#define RCC_IC16CFGR_IC16INT_Pos (16UL) +#define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */ +#define RCC_IC16CFGR_IC16SEL_Pos (28UL) +#define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */ +#define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC17CFGR register *****************/ +#define RCC_IC17CFGR_IC17INT_Pos (16UL) +#define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */ +#define RCC_IC17CFGR_IC17SEL_Pos (28UL) +#define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */ +#define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC18CFGR register *****************/ +#define RCC_IC18CFGR_IC18INT_Pos (16UL) +#define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */ +#define RCC_IC18CFGR_IC18SEL_Pos (28UL) +#define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */ +#define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC19CFGR register *****************/ +#define RCC_IC19CFGR_IC19INT_Pos (16UL) +#define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */ +#define RCC_IC19CFGR_IC19SEL_Pos (28UL) +#define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */ +#define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC20CFGR register *****************/ +#define RCC_IC20CFGR_IC20INT_Pos (16UL) +#define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */ +#define RCC_IC20CFGR_IC20SEL_Pos (28UL) +#define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */ +#define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for RCC_CIER register *******************/ +#define RCC_CIER_LSIRDYIE_Pos (0UL) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1UL) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_MSIRDYIE_Pos (2UL) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */ +#define RCC_CIER_HSIRDYIE_Pos (3UL) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (4UL) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ +#define RCC_CIER_PLL1RDYIE_Pos (8UL) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */ +#define RCC_CIER_PLL2RDYIE_Pos (9UL) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */ +#define RCC_CIER_PLL3RDYIE_Pos (10UL) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */ +#define RCC_CIER_PLL4RDYIE_Pos (11UL) +#define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */ +#define RCC_CIER_LSECSSIE_Pos (16UL) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */ +#define RCC_CIER_HSECSSIE_Pos (17UL) +#define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */ +#define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */ +#define RCC_CIER_WKUPIE_Pos (24UL) +#define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */ +#define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */ + +/******************* Bit definition for RCC_CIFR register *******************/ +#define RCC_CIFR_LSIRDYF_Pos (0UL) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1UL) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (2UL) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (3UL) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (4UL) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_PLL1RDYF_Pos (8UL) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */ +#define RCC_CIFR_PLL2RDYF_Pos (9UL) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */ +#define RCC_CIFR_PLL3RDYF_Pos (10UL) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */ +#define RCC_CIFR_PLL4RDYF_Pos (11UL) +#define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (16UL) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (17UL) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_WKUPF_Pos (24UL) +#define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */ +#define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */ + +/******************* Bit definition for RCC_CICR register *******************/ +#define RCC_CICR_LSIRDYC_Pos (0UL) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1UL) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_MSIRDYC_Pos (2UL) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */ +#define RCC_CICR_HSIRDYC_Pos (3UL) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (4UL) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_PLL1RDYC_Pos (8UL) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */ +#define RCC_CICR_PLL2RDYC_Pos (9UL) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */ +#define RCC_CICR_PLL3RDYC_Pos (10UL) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */ +#define RCC_CICR_PLL4RDYC_Pos (11UL) +#define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (16UL) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (17UL) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_WKUPFC_Pos (24UL) +#define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */ +#define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */ + +/****************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_ADF1SEL_Pos (0UL) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */ +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_ADC12SEL_Pos (4UL) +#define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */ +#define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_ADCPRE_Pos (8UL) +#define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */ +#define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */ +#define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_DCMIPPSEL_Pos (20UL) +#define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */ +#define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_ETH1PTPSEL_Pos (0UL) +#define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_ETH1PTPDIV_Pos (4UL) +#define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */ +#define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8UL) +#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1CLKSEL_Pos (12UL) +#define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ETH1SEL_Pos (16UL) +#define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20UL) +#define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24UL) +#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR3 register ******************/ +#define RCC_CCIPR3_FDCANSEL_Pos (0UL) +#define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */ +#define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_FMCSEL_Pos (4UL) +#define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */ +#define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_DFTSEL_Pos (8UL) +#define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */ + +/****************** Bit definition for RCC_CCIPR4 register ******************/ +#define RCC_CCIPR4_I2C1SEL_Pos (0UL) +#define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */ +#define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR4_I2C2SEL_Pos (4UL) +#define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */ +#define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR4_I2C3SEL_Pos (8UL) +#define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */ +#define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR4_I2C4SEL_Pos (12UL) +#define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */ +#define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR4_I3C1SEL_Pos (16UL) +#define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */ +#define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR4_I3C2SEL_Pos (20UL) +#define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */ +#define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR4_LTDCSEL_Pos (24UL) +#define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */ +#define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */ + +/****************** Bit definition for RCC_CCIPR5 register ******************/ +#define RCC_CCIPR5_MCO1SEL_Pos (0UL) +#define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */ +#define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR5_MCO1PRE_Pos (4UL) +#define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */ +#define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR5_MCO2SEL_Pos (8UL) +#define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */ +#define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR5_MCO2PRE_Pos (12UL) +#define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */ +#define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */ +#define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR5_MDF1SEL_Pos (16UL) +#define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */ +#define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for RCC_CCIPR6 register ******************/ +#define RCC_CCIPR6_XSPI1SEL_Pos (0UL) +#define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */ +#define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR6_XSPI2SEL_Pos (4UL) +#define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */ +#define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR6_XSPI3SEL_Pos (8UL) +#define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */ +#define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR6_OTGPHY1SEL_Pos (12UL) +#define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */ +#define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16UL) +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR6_OTGPHY2SEL_Pos (20UL) +#define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */ +#define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24UL) +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR7 register ******************/ +#define RCC_CCIPR7_PERSEL_Pos (0UL) +#define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */ +#define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR7_PSSISEL_Pos (4UL) +#define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */ +#define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR7_RTCSEL_Pos (8UL) +#define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */ +#define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR7_RTCPRE_Pos (12UL) +#define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */ +#define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */ +#define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR7_SAI1SEL_Pos (20UL) +#define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */ +#define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR7_SAI2SEL_Pos (24UL) +#define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */ +#define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */ + +/****************** Bit definition for RCC_CCIPR8 register ******************/ +#define RCC_CCIPR8_SDMMC1SEL_Pos (0UL) +#define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */ +#define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR8_SDMMC2SEL_Pos (4UL) +#define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */ +#define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */ + +/****************** Bit definition for RCC_CCIPR9 register ******************/ +#define RCC_CCIPR9_SPDIFRX1SEL_Pos (0UL) +#define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */ +#define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR9_SPI1SEL_Pos (4UL) +#define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */ +#define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR9_SPI2SEL_Pos (8UL) +#define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */ +#define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR9_SPI3SEL_Pos (12UL) +#define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */ +#define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR9_SPI4SEL_Pos (16UL) +#define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */ +#define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR9_SPI5SEL_Pos (20UL) +#define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */ +#define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR9_SPI6SEL_Pos (24UL) +#define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */ +#define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR12 register ******************/ +#define RCC_CCIPR12_LPTIM1SEL_Pos (8UL) +#define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */ +#define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR12_LPTIM2SEL_Pos (12UL) +#define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */ +#define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR12_LPTIM3SEL_Pos (16UL) +#define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */ +#define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR12_LPTIM4SEL_Pos (20UL) +#define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */ +#define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR12_LPTIM5SEL_Pos (24UL) +#define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */ +#define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR13 register ******************/ +#define RCC_CCIPR13_USART1SEL_Pos (0UL) +#define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */ +#define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR13_USART2SEL_Pos (4UL) +#define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */ +#define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR13_USART3SEL_Pos (8UL) +#define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */ +#define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR13_UART4SEL_Pos (12UL) +#define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */ +#define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR13_UART5SEL_Pos (16UL) +#define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */ +#define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR13_USART6SEL_Pos (20UL) +#define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */ +#define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR13_UART7SEL_Pos (24UL) +#define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */ +#define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR13_UART8SEL_Pos (28UL) +#define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */ +#define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */ +#define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */ + +/***************** Bit definition for RCC_CCIPR14 register ******************/ +#define RCC_CCIPR14_UART9SEL_Pos (0UL) +#define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */ +#define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR14_USART10SEL_Pos (4UL) +#define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */ +#define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR14_LPUART1SEL_Pos (8UL) +#define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */ +#define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */ + +/***************** Bit definition for RCC_MISCRSTR register *****************/ +#define RCC_MISCRSTR_DBGRST_Pos (0UL) +#define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */ +#define RCC_MISCRSTR_XSPIPHY1RST_Pos (4UL) +#define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTR_XSPIPHY2RST_Pos (5UL) +#define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7UL) +#define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8UL) +#define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTR register ******************/ +#define RCC_MEMRSTR_AXISRAM3RST_Pos (0UL) +#define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */ +#define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTR_AXISRAM4RST_Pos (1UL) +#define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */ +#define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTR_AXISRAM5RST_Pos (2UL) +#define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */ +#define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTR_AXISRAM6RST_Pos (3UL) +#define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */ +#define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTR_AHBSRAM1RST_Pos (4UL) +#define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */ +#define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTR_AHBSRAM2RST_Pos (5UL) +#define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */ +#define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTR_AXISRAM1RST_Pos (7UL) +#define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */ +#define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTR_AXISRAM2RST_Pos (8UL) +#define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */ +#define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTR_FLEXRAMRST_Pos (9UL) +#define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTR_VENCRAMRST_Pos (11UL) +#define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTR_BOOTROMRST_Pos (12UL) +#define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */ + +/***************** Bit definition for RCC_AHB1RSTR register *****************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4UL) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTR_ADC12RST_Pos (5UL) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */ + +/***************** Bit definition for RCC_AHB2RSTR register *****************/ +#define RCC_AHB2RSTR_RAMCFGRST_Pos (12UL) +#define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTR_MDF1RST_Pos (16UL) +#define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTR_ADF1RST_Pos (17UL) +#define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */ + +/***************** Bit definition for RCC_AHB3RSTR register *****************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0UL) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */ +#define RCC_AHB3RSTR_HASHRST_Pos (1UL) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB3RSTR_CRYPRST_Pos (2UL) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTR_SAESRST_Pos (4UL) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk /*!< SAES reset */ +#define RCC_AHB3RSTR_PKARST_Pos (8UL) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */ +#define RCC_AHB3RSTR_IACRST_Pos (10UL) +#define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */ + +/***************** Bit definition for RCC_AHB4RSTR register *****************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0UL) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTR_GPIOBRST_Pos (1UL) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTR_GPIOCRST_Pos (2UL) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTR_GPIODRST_Pos (3UL) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTR_GPIOERST_Pos (4UL) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTR_GPIOFRST_Pos (5UL) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTR_GPIOGRST_Pos (6UL) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTR_GPIOHRST_Pos (7UL) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTR_GPIONRST_Pos (13UL) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTR_GPIOORST_Pos (14UL) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTR_GPIOPRST_Pos (15UL) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTR_GPIOQRST_Pos (16UL) +#define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTR_PWRRST_Pos (18UL) +#define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */ +#define RCC_AHB4RSTR_CRCRST_Pos (19UL) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */ + +/***************** Bit definition for RCC_AHB5RSTR register *****************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0UL) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTR_DMA2DRST_Pos (1UL) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTR_JPEGRST_Pos (3UL) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTR_FMCRST_Pos (4UL) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */ +#define RCC_AHB5RSTR_XSPI1RST_Pos (5UL) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTR_PSSIRST_Pos (6UL) +#define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTR_SDMMC2RST_Pos (7UL) +#define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8UL) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTR_XSPI2RST_Pos (12UL) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTR_XSPIMRST_Pos (13UL) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTR_XSPI3RST_Pos (17UL) +#define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTR_GFXMMURST_Pos (19UL) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTR_GPU2DRST_Pos (20UL) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23UL) +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24UL) +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTR_ETH1RST_Pos (25UL) +#define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTR_OTG1RST_Pos (26UL) +#define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTR_OTGPHY1RST_Pos (27UL) +#define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */ +#define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTR_OTGPHY2RST_Pos (28UL) +#define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */ +#define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTR_OTG2RST_Pos (29UL) +#define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */ + +/**************** Bit definition for RCC_APB1RSTR1 register *****************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0UL) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTR1_TIM3RST_Pos (1UL) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTR1_TIM4RST_Pos (2UL) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTR1_TIM5RST_Pos (3UL) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTR1_TIM6RST_Pos (4UL) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTR1_TIM7RST_Pos (5UL) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTR1_TIM12RST_Pos (6UL) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTR1_TIM13RST_Pos (7UL) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTR1_TIM14RST_Pos (8UL) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9UL) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTR1_WWDGRST_Pos (11UL) +#define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */ +#define RCC_APB1RSTR1_TIM10RST_Pos (12UL) +#define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTR1_TIM11RST_Pos (13UL) +#define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTR1_SPI2RST_Pos (14UL) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTR1_SPI3RST_Pos (15UL) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16UL) +#define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTR1_USART2RST_Pos (17UL) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1RSTR1_USART3RST_Pos (18UL) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1RSTR1_UART4RST_Pos (19UL) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1RSTR1_UART5RST_Pos (20UL) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1RSTR1_I2C1RST_Pos (21UL) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTR1_I2C2RST_Pos (22UL) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTR1_I2C3RST_Pos (23UL) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTR1_I3C1RST_Pos (24UL) +#define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTR1_I3C2RST_Pos (25UL) +#define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTR1_UART7RST_Pos (30UL) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */ +#define RCC_APB1RSTR1_UART8RST_Pos (31UL) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTR2 register *****************/ +#define RCC_APB1RSTR2_MDIOSRST_Pos (5UL) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTR2_FDCANRST_Pos (8UL) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTR2_UCPD1RST_Pos (18UL) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0UL) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (1UL) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (4UL) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_USART6RST_Pos (5UL) +#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ +#define RCC_APB2RSTR_UART9RST_Pos (6UL) +#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */ +#define RCC_APB2RSTR_USART10RST_Pos (7UL) +#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */ +#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12UL) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST_Pos (13UL) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTR_TIM18RST_Pos (15UL) +#define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */ +#define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16UL) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17UL) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18UL) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_TIM9RST_Pos (19UL) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTR_SPI5RST_Pos (20UL) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTR_SAI1RST_Pos (21UL) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST_Pos (22UL) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTR1 register *****************/ +#define RCC_APB4RSTR1_HDPRST_Pos (2UL) +#define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */ +#define RCC_APB4RSTR1_LPUART1RST_Pos (3UL) +#define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTR1_SPI6RST_Pos (5UL) +#define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTR1_I2C4RST_Pos (7UL) +#define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */ +#define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTR1_LPTIM2RST_Pos (9UL) +#define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */ +#define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTR1_LPTIM3RST_Pos (10UL) +#define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */ +#define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTR1_LPTIM4RST_Pos (11UL) +#define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */ +#define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTR1_LPTIM5RST_Pos (12UL) +#define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */ +#define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTR1_VREFBUFRST_Pos (15UL) +#define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTR1_RTCRST_Pos (16UL) +#define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTR2 register *****************/ +#define RCC_APB4RSTR2_SYSCFGRST_Pos (0UL) +#define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */ +#define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTR2_DTSRST_Pos (2UL) +#define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */ + +/***************** Bit definition for RCC_APB5RSTR register *****************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1UL) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2UL) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTR_GFXTIMRST_Pos (4UL) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTR_VENCRST_Pos (5UL) +#define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */ +#define RCC_APB5RSTR_CSIRST_Pos (6UL) +#define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */ + +/****************** Bit definition for RCC_DIVENR register ******************/ +#define RCC_DIVENR_IC1EN_Pos (0UL) +#define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */ +#define RCC_DIVENR_IC2EN_Pos (1UL) +#define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */ +#define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */ +#define RCC_DIVENR_IC3EN_Pos (2UL) +#define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */ +#define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */ +#define RCC_DIVENR_IC4EN_Pos (3UL) +#define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */ +#define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */ +#define RCC_DIVENR_IC5EN_Pos (4UL) +#define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */ +#define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */ +#define RCC_DIVENR_IC6EN_Pos (5UL) +#define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */ +#define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */ +#define RCC_DIVENR_IC7EN_Pos (6UL) +#define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */ +#define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */ +#define RCC_DIVENR_IC8EN_Pos (7UL) +#define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */ +#define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */ +#define RCC_DIVENR_IC9EN_Pos (8UL) +#define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */ +#define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */ +#define RCC_DIVENR_IC10EN_Pos (9UL) +#define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */ +#define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */ +#define RCC_DIVENR_IC11EN_Pos (10UL) +#define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */ +#define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */ +#define RCC_DIVENR_IC12EN_Pos (11UL) +#define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */ +#define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */ +#define RCC_DIVENR_IC13EN_Pos (12UL) +#define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */ +#define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */ +#define RCC_DIVENR_IC14EN_Pos (13UL) +#define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */ +#define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */ +#define RCC_DIVENR_IC15EN_Pos (14UL) +#define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */ +#define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */ +#define RCC_DIVENR_IC16EN_Pos (15UL) +#define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */ +#define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */ +#define RCC_DIVENR_IC17EN_Pos (16UL) +#define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */ +#define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */ +#define RCC_DIVENR_IC18EN_Pos (17UL) +#define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */ +#define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */ +#define RCC_DIVENR_IC19EN_Pos (18UL) +#define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */ +#define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */ +#define RCC_DIVENR_IC20EN_Pos (19UL) +#define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */ +#define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */ + +/****************** Bit definition for RCC_BUSENR register ******************/ +#define RCC_BUSENR_ACLKNEN_Pos (0UL) +#define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */ +#define RCC_BUSENR_ACLKNCEN_Pos (1UL) +#define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */ +#define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */ +#define RCC_BUSENR_AHBMEN_Pos (2UL) +#define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */ +#define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */ +#define RCC_BUSENR_AHB1EN_Pos (3UL) +#define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */ +#define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */ +#define RCC_BUSENR_AHB2EN_Pos (4UL) +#define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */ +#define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */ +#define RCC_BUSENR_AHB3EN_Pos (5UL) +#define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */ +#define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */ +#define RCC_BUSENR_AHB4EN_Pos (6UL) +#define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */ +#define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */ +#define RCC_BUSENR_AHB5EN_Pos (7UL) +#define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */ +#define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */ +#define RCC_BUSENR_APB1EN_Pos (8UL) +#define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */ +#define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */ +#define RCC_BUSENR_APB2EN_Pos (9UL) +#define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */ +#define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */ +#define RCC_BUSENR_APB3EN_Pos (10UL) +#define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */ +#define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */ +#define RCC_BUSENR_APB4EN_Pos (11UL) +#define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */ +#define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */ +#define RCC_BUSENR_APB5EN_Pos (12UL) +#define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */ +#define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENR register ******************/ +#define RCC_MISCENR_DBGEN_Pos (0UL) +#define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */ +#define RCC_MISCENR_MCO1EN_Pos (1UL) +#define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */ +#define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */ +#define RCC_MISCENR_MCO2EN_Pos (2UL) +#define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */ +#define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */ +#define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3UL) +#define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENR_PEREN_Pos (6UL) +#define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */ +#define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */ + +/****************** Bit definition for RCC_MEMENR register ******************/ +#define RCC_MEMENR_AXISRAM3EN_Pos (0UL) +#define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */ +#define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENR_AXISRAM4EN_Pos (1UL) +#define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */ +#define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENR_AXISRAM5EN_Pos (2UL) +#define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */ +#define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENR_AXISRAM6EN_Pos (3UL) +#define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */ +#define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENR_AHBSRAM1EN_Pos (4UL) +#define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */ +#define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENR_AHBSRAM2EN_Pos (5UL) +#define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */ +#define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENR_BKPSRAMEN_Pos (6UL) +#define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENR_AXISRAM1EN_Pos (7UL) +#define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */ +#define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENR_AXISRAM2EN_Pos (8UL) +#define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */ +#define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENR_FLEXRAMEN_Pos (9UL) +#define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENR_VENCRAMEN_Pos (11UL) +#define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMENR_BOOTROMEN_Pos (12UL) +#define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENR register ******************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4UL) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENR_ADC12EN_Pos (5UL) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENR register ******************/ +#define RCC_AHB2ENR_RAMCFGEN_Pos (12UL) +#define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENR_MDF1EN_Pos (16UL) +#define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENR_ADF1EN_Pos (17UL) +#define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENR register ******************/ +#define RCC_AHB3ENR_RNGEN_Pos (0UL) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */ +#define RCC_AHB3ENR_HASHEN_Pos (1UL) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */ +#define RCC_AHB3ENR_CRYPEN_Pos (2UL) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk /*!< CRYP enable */ +#define RCC_AHB3ENR_SAESEN_Pos (4UL) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk /*!< SAES enable */ +#define RCC_AHB3ENR_PKAEN_Pos (8UL) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */ +#define RCC_AHB3ENR_RIFSCEN_Pos (9UL) +#define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENR_IACEN_Pos (10UL) +#define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */ +#define RCC_AHB3ENR_RISAFEN_Pos (14UL) +#define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENR register ******************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0UL) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENR_GPIOBEN_Pos (1UL) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENR_GPIOCEN_Pos (2UL) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENR_GPIODEN_Pos (3UL) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENR_GPIOEEN_Pos (4UL) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENR_GPIOFEN_Pos (5UL) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENR_GPIOGEN_Pos (6UL) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENR_GPIOHEN_Pos (7UL) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENR_GPIONEN_Pos (13UL) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENR_GPIOOEN_Pos (14UL) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENR_GPIOPEN_Pos (15UL) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENR_GPIOQEN_Pos (16UL) +#define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENR_PWREN_Pos (18UL) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */ +#define RCC_AHB4ENR_CRCEN_Pos (19UL) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENR register ******************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0UL) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENR_DMA2DEN_Pos (1UL) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENR_JPEGEN_Pos (3UL) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */ +#define RCC_AHB5ENR_FMCEN_Pos (4UL) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */ +#define RCC_AHB5ENR_XSPI1EN_Pos (5UL) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENR_PSSIEN_Pos (6UL) +#define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */ +#define RCC_AHB5ENR_SDMMC2EN_Pos (7UL) +#define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENR_SDMMC1EN_Pos (8UL) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENR_XSPI2EN_Pos (12UL) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENR_XSPIMEN_Pos (13UL) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENR_MCE1EN_Pos (14UL) +#define RCC_AHB5ENR_MCE1EN_Msk (0x1UL << RCC_AHB5ENR_MCE1EN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_MCE1EN RCC_AHB5ENR_MCE1EN_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENR_MCE2EN_Pos (15UL) +#define RCC_AHB5ENR_MCE2EN_Msk (0x1UL << RCC_AHB5ENR_MCE2EN_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENR_MCE2EN RCC_AHB5ENR_MCE2EN_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENR_MCE3EN_Pos (16UL) +#define RCC_AHB5ENR_MCE3EN_Msk (0x1UL << RCC_AHB5ENR_MCE3EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENR_MCE3EN RCC_AHB5ENR_MCE3EN_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENR_XSPI3EN_Pos (17UL) +#define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENR_MCE4EN_Pos (18UL) +#define RCC_AHB5ENR_MCE4EN_Msk (0x1UL << RCC_AHB5ENR_MCE4EN_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENR_MCE4EN RCC_AHB5ENR_MCE4EN_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENR_GFXMMUEN_Pos (19UL) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENR_GPU2DEN_Pos (20UL) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENR_ETH1MACEN_Pos (22UL) +#define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENR_ETH1TXEN_Pos (23UL) +#define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENR_ETH1RXEN_Pos (24UL) +#define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENR_ETH1EN_Pos (25UL) +#define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENR_OTG1EN_Pos (26UL) +#define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENR_OTGPHY1EN_Pos (27UL) +#define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENR_OTGPHY2EN_Pos (28UL) +#define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENR_OTG2EN_Pos (29UL) +#define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */ + +/***************** Bit definition for RCC_APB1ENR1 register *****************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0UL) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */ +#define RCC_APB1ENR1_TIM3EN_Pos (1UL) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */ +#define RCC_APB1ENR1_TIM4EN_Pos (2UL) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */ +#define RCC_APB1ENR1_TIM5EN_Pos (3UL) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */ +#define RCC_APB1ENR1_TIM6EN_Pos (4UL) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */ +#define RCC_APB1ENR1_TIM7EN_Pos (5UL) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */ +#define RCC_APB1ENR1_TIM12EN_Pos (6UL) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */ +#define RCC_APB1ENR1_TIM13EN_Pos (7UL) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */ +#define RCC_APB1ENR1_TIM14EN_Pos (8UL) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */ +#define RCC_APB1ENR1_LPTIM1EN_Pos (9UL) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENR1_WWDGEN_Pos (11UL) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */ +#define RCC_APB1ENR1_TIM10EN_Pos (12UL) +#define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */ +#define RCC_APB1ENR1_TIM11EN_Pos (13UL) +#define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */ +#define RCC_APB1ENR1_SPI2EN_Pos (14UL) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */ +#define RCC_APB1ENR1_SPI3EN_Pos (15UL) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */ +#define RCC_APB1ENR1_SPDIFRX1EN_Pos (16UL) +#define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENR1_USART2EN_Pos (17UL) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */ +#define RCC_APB1ENR1_USART3EN_Pos (18UL) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */ +#define RCC_APB1ENR1_UART4EN_Pos (19UL) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */ +#define RCC_APB1ENR1_UART5EN_Pos (20UL) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */ +#define RCC_APB1ENR1_I2C1EN_Pos (21UL) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */ +#define RCC_APB1ENR1_I2C2EN_Pos (22UL) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */ +#define RCC_APB1ENR1_I2C3EN_Pos (23UL) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */ +#define RCC_APB1ENR1_I3C1EN_Pos (24UL) +#define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */ +#define RCC_APB1ENR1_I3C2EN_Pos (25UL) +#define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */ +#define RCC_APB1ENR1_UART7EN_Pos (30UL) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */ +#define RCC_APB1ENR1_UART8EN_Pos (31UL) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */ + +/***************** Bit definition for RCC_APB1ENR2 register *****************/ +#define RCC_APB1ENR2_MDIOSEN_Pos (5UL) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */ +#define RCC_APB1ENR2_FDCANEN_Pos (8UL) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */ +#define RCC_APB1ENR2_UCPD1EN_Pos (18UL) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENR register ******************/ +#define RCC_APB2ENR_TIM1EN_Pos (0UL) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */ +#define RCC_APB2ENR_TIM8EN_Pos (1UL) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */ +#define RCC_APB2ENR_USART1EN_Pos (4UL) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */ +#define RCC_APB2ENR_USART6EN_Pos (5UL) +#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */ +#define RCC_APB2ENR_UART9EN_Pos (6UL) +#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */ +#define RCC_APB2ENR_USART10EN_Pos (7UL) +#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12UL) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */ +#define RCC_APB2ENR_SPI4EN_Pos (13UL) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */ +#define RCC_APB2ENR_TIM18EN_Pos (15UL) +#define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16UL) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17UL) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18UL) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */ +#define RCC_APB2ENR_TIM9EN_Pos (19UL) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */ +#define RCC_APB2ENR_SPI5EN_Pos (20UL) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */ +#define RCC_APB2ENR_SAI1EN_Pos (21UL) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */ +#define RCC_APB2ENR_SAI2EN_Pos (22UL) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENR register ******************/ +#define RCC_APB3ENR_DFTEN_Pos (2UL) +#define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */ + +/***************** Bit definition for RCC_APB4ENR1 register *****************/ +#define RCC_APB4ENR1_HDPEN_Pos (2UL) +#define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */ +#define RCC_APB4ENR1_LPUART1EN_Pos (3UL) +#define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENR1_SPI6EN_Pos (5UL) +#define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */ +#define RCC_APB4ENR1_I2C4EN_Pos (7UL) +#define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */ +#define RCC_APB4ENR1_LPTIM2EN_Pos (9UL) +#define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENR1_LPTIM3EN_Pos (10UL) +#define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENR1_LPTIM4EN_Pos (11UL) +#define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENR1_LPTIM5EN_Pos (12UL) +#define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENR1_VREFBUFEN_Pos (15UL) +#define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENR1_RTCEN_Pos (16UL) +#define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */ +#define RCC_APB4ENR1_RTCAPBEN_Pos (17UL) +#define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */ + +/***************** Bit definition for RCC_APB4ENR2 register *****************/ +#define RCC_APB4ENR2_SYSCFGEN_Pos (0UL) +#define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENR2_BSECEN_Pos (1UL) +#define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */ +#define RCC_APB4ENR2_DTSEN_Pos (2UL) +#define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENR register ******************/ +#define RCC_APB5ENR_LTDCEN_Pos (1UL) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */ +#define RCC_APB5ENR_DCMIPPEN_Pos (2UL) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENR_GFXTIMEN_Pos (4UL) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENR_VENCEN_Pos (5UL) +#define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */ +#define RCC_APB5ENR_CSIEN_Pos (6UL) +#define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */ + +/***************** Bit definition for RCC_BUSLPENR register *****************/ +#define RCC_BUSLPENR_ACLKNLPEN_Pos (0UL) +#define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENR_ACLKNCLPEN_Pos (1UL) +#define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */ +#define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENR register *****************/ +#define RCC_MISCLPENR_DBGLPEN_Pos (0UL) +#define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3UL) +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENR_PERLPEN_Pos (6UL) +#define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMLPENR register *****************/ +#define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0UL) +#define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1UL) +#define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2UL) +#define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3UL) +#define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4UL) +#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5UL) +#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6UL) +#define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7UL) +#define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8UL) +#define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9UL) +#define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENR_VENCRAMLPEN_Pos (11UL) +#define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENR_BOOTROMLPEN_Pos (12UL) +#define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENR register *****************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4UL) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5UL) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENR register *****************/ +#define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12UL) +#define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENR_MDF1LPEN_Pos (16UL) +#define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENR_ADF1LPEN_Pos (17UL) +#define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENR register *****************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0UL) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */ +#define RCC_AHB3LPENR_HASHLPEN_Pos (1UL) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */ +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2UL) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk /*!< CRYP enable */ +#define RCC_AHB3LPENR_SAESLPEN_Pos (4UL) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk /*!< SAES enable */ +#define RCC_AHB3LPENR_PKALPEN_Pos (8UL) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */ +#define RCC_AHB3LPENR_RIFSCLPEN_Pos (9UL) +#define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */ +#define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENR_IACLPEN_Pos (10UL) +#define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */ +#define RCC_AHB3LPENR_RISAFLPEN_Pos (14UL) +#define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENR register *****************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0UL) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1UL) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2UL) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3UL) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4UL) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5UL) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6UL) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7UL) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13UL) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14UL) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15UL) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENR_GPIOQLPEN_Pos (16UL) +#define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */ +#define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENR_PWRLPEN_Pos (18UL) +#define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */ +#define RCC_AHB4LPENR_CRCLPEN_Pos (19UL) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENR register *****************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0UL) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1UL) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3UL) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENR_FMCLPEN_Pos (4UL) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */ +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5UL) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENR_PSSILPEN_Pos (6UL) +#define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7UL) +#define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8UL) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12UL) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (13UL) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENR_MCE1LPEN_Pos (14UL) +#define RCC_AHB5LPENR_MCE1LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_MCE1LPEN RCC_AHB5LPENR_MCE1LPEN_Msk /*!< MCE1 enable */ +#define RCC_AHB5LPENR_MCE2LPEN_Pos (15UL) +#define RCC_AHB5LPENR_MCE2LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENR_MCE2LPEN RCC_AHB5LPENR_MCE2LPEN_Msk /*!< MCE2 enable */ +#define RCC_AHB5LPENR_MCE3LPEN_Pos (16UL) +#define RCC_AHB5LPENR_MCE3LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENR_MCE3LPEN RCC_AHB5LPENR_MCE3LPEN_Msk /*!< MCE3 enable */ +#define RCC_AHB5LPENR_XSPI3LPEN_Pos (17UL) +#define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENR_MCE4LPEN_Pos (18UL) +#define RCC_AHB5LPENR_MCE4LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENR_MCE4LPEN RCC_AHB5LPENR_MCE4LPEN_Msk /*!< MCE4 enable */ +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19UL) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20UL) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22UL) +#define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23UL) +#define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24UL) +#define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENR_ETH1LPEN_Pos (25UL) +#define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENR_OTG1LPEN_Pos (26UL) +#define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27UL) +#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28UL) +#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENR_OTG2LPEN_Pos (29UL) +#define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */ + +/**************** Bit definition for RCC_APB1LPENR1 register ****************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0UL) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1UL) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2UL) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3UL) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4UL) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5UL) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6UL) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7UL) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8UL) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9UL) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11UL) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */ +#define RCC_APB1LPENR1_TIM10LPEN_Pos (12UL) +#define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENR1_TIM11LPEN_Pos (13UL) +#define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14UL) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15UL) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16UL) +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENR1_USART2LPEN_Pos (17UL) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */ +#define RCC_APB1LPENR1_USART3LPEN_Pos (18UL) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */ +#define RCC_APB1LPENR1_UART4LPEN_Pos (19UL) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */ +#define RCC_APB1LPENR1_UART5LPEN_Pos (20UL) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */ +#define RCC_APB1LPENR1_I2C1LPEN_Pos (21UL) +#define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22UL) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23UL) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENR1_I3C1LPEN_Pos (24UL) +#define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */ +#define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENR1_I3C2LPEN_Pos (25UL) +#define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */ +#define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENR1_UART7LPEN_Pos (30UL) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */ +#define RCC_APB1LPENR1_UART8LPEN_Pos (31UL) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1LPENR2 register ****************/ +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5UL) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */ +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8UL) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */ +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (18UL) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */ + +/**************** Bit definition for RCC_APB2LPENR register *****************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0UL) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (1UL) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENR_USART1LPEN_Pos (4UL) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */ +#define RCC_APB2LPENR_USART6LPEN_Pos (5UL) +#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */ +#define RCC_APB2LPENR_UART9LPEN_Pos (6UL) +#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */ +#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */ +#define RCC_APB2LPENR_USART10LPEN_Pos (7UL) +#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12UL) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENR_SPI4LPEN_Pos (13UL) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENR_TIM18LPEN_Pos (15UL) +#define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16UL) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17UL) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18UL) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENR_TIM9LPEN_Pos (19UL) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENR_SPI5LPEN_Pos (20UL) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENR_SAI1LPEN_Pos (21UL) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENR_SAI2LPEN_Pos (22UL) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENR register *****************/ +#define RCC_APB3LPENR_DFTLPEN_Pos (2UL) +#define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4LPENR1 register ****************/ +#define RCC_APB4LPENR1_HDPLPEN_Pos (2UL) +#define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */ +#define RCC_APB4LPENR1_LPUART1LPEN_Pos (3UL) +#define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENR1_SPI6LPEN_Pos (5UL) +#define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENR1_I2C4LPEN_Pos (7UL) +#define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */ +#define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9UL) +#define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10UL) +#define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11UL) +#define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12UL) +#define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15UL) +#define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENR1_RTCLPEN_Pos (16UL) +#define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */ +#define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17UL) +#define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4LPENR2 register ****************/ +#define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0UL) +#define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENR2_BSECLPEN_Pos (1UL) +#define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */ +#define RCC_APB4LPENR2_DTSLPEN_Pos (2UL) +#define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENR register *****************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1UL) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2UL) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4UL) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENR_VENCLPEN_Pos (5UL) +#define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */ +#define RCC_APB5LPENR_CSILPEN_Pos (6UL) +#define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */ + +/******************* Bit definition for RCC_RDCR register *******************/ +#define RCC_RDCR_MRD_Pos (16UL) +#define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */ + +/***************** Bit definition for RCC_SECCFGR0 register *****************/ +#define RCC_SECCFGR0_LSISEC_Pos (0UL) +#define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */ +#define RCC_SECCFGR0_LSESEC_Pos (1UL) +#define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */ +#define RCC_SECCFGR0_MSISEC_Pos (2UL) +#define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSISEC_Pos (3UL) +#define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSESEC_Pos (4UL) +#define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR0 register *****************/ +#define RCC_PRIVCFGR0_LSIPRIV_Pos (0UL) +#define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_LSEPRIV_Pos (1UL) +#define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */ +#define RCC_PRIVCFGR0_MSIPRIV_Pos (2UL) +#define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSIPRIV_Pos (3UL) +#define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSEPRIV_Pos (4UL) +#define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR0 register *****************/ +#define RCC_LOCKCFGR0_LSILOCK_Pos (0UL) +#define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_LSELOCK_Pos (1UL) +#define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */ +#define RCC_LOCKCFGR0_MSILOCK_Pos (2UL) +#define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSILOCK_Pos (3UL) +#define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSELOCK_Pos (4UL) +#define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR0 register *****************/ +#define RCC_PUBCFGR0_LSIPUB_Pos (0UL) +#define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */ +#define RCC_PUBCFGR0_LSEPUB_Pos (1UL) +#define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */ +#define RCC_PUBCFGR0_MSIPUB_Pos (2UL) +#define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSIPUB_Pos (3UL) +#define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSEPUB_Pos (4UL) +#define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_SECCFGR1 register *****************/ +#define RCC_SECCFGR1_PLL1SEC_Pos (0UL) +#define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */ +#define RCC_SECCFGR1_PLL2SEC_Pos (1UL) +#define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */ +#define RCC_SECCFGR1_PLL3SEC_Pos (2UL) +#define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */ +#define RCC_SECCFGR1_PLL4SEC_Pos (3UL) +#define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR1 register *****************/ +#define RCC_PRIVCFGR1_PLL1PRIV_Pos (0UL) +#define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */ +#define RCC_PRIVCFGR1_PLL2PRIV_Pos (1UL) +#define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */ +#define RCC_PRIVCFGR1_PLL3PRIV_Pos (2UL) +#define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */ +#define RCC_PRIVCFGR1_PLL4PRIV_Pos (3UL) +#define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR1 register *****************/ +#define RCC_LOCKCFGR1_PLL1LOCK_Pos (0UL) +#define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */ +#define RCC_LOCKCFGR1_PLL2LOCK_Pos (1UL) +#define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */ +#define RCC_LOCKCFGR1_PLL3LOCK_Pos (2UL) +#define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */ +#define RCC_LOCKCFGR1_PLL4LOCK_Pos (3UL) +#define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR1 register *****************/ +#define RCC_PUBCFGR1_PLL1PUB_Pos (0UL) +#define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */ +#define RCC_PUBCFGR1_PLL2PUB_Pos (1UL) +#define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */ +#define RCC_PUBCFGR1_PLL3PUB_Pos (2UL) +#define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */ +#define RCC_PUBCFGR1_PLL4PUB_Pos (3UL) +#define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_SECCFGR2 register *****************/ +#define RCC_SECCFGR2_IC1SEC_Pos (0UL) +#define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */ +#define RCC_SECCFGR2_IC2SEC_Pos (1UL) +#define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */ +#define RCC_SECCFGR2_IC3SEC_Pos (2UL) +#define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */ +#define RCC_SECCFGR2_IC4SEC_Pos (3UL) +#define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */ +#define RCC_SECCFGR2_IC5SEC_Pos (4UL) +#define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */ +#define RCC_SECCFGR2_IC6SEC_Pos (5UL) +#define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */ +#define RCC_SECCFGR2_IC7SEC_Pos (6UL) +#define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */ +#define RCC_SECCFGR2_IC8SEC_Pos (7UL) +#define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */ +#define RCC_SECCFGR2_IC9SEC_Pos (8UL) +#define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */ +#define RCC_SECCFGR2_IC10SEC_Pos (9UL) +#define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */ +#define RCC_SECCFGR2_IC11SEC_Pos (10UL) +#define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */ +#define RCC_SECCFGR2_IC12SEC_Pos (11UL) +#define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */ +#define RCC_SECCFGR2_IC13SEC_Pos (12UL) +#define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */ +#define RCC_SECCFGR2_IC14SEC_Pos (13UL) +#define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */ +#define RCC_SECCFGR2_IC15SEC_Pos (14UL) +#define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */ +#define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */ +#define RCC_SECCFGR2_IC16SEC_Pos (15UL) +#define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */ +#define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */ +#define RCC_SECCFGR2_IC17SEC_Pos (16UL) +#define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */ +#define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */ +#define RCC_SECCFGR2_IC18SEC_Pos (17UL) +#define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */ +#define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */ +#define RCC_SECCFGR2_IC19SEC_Pos (18UL) +#define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */ +#define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */ +#define RCC_SECCFGR2_IC20SEC_Pos (19UL) +#define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */ +#define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR2 register *****************/ +#define RCC_PRIVCFGR2_IC1PRIV_Pos (0UL) +#define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */ +#define RCC_PRIVCFGR2_IC2PRIV_Pos (1UL) +#define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */ +#define RCC_PRIVCFGR2_IC3PRIV_Pos (2UL) +#define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */ +#define RCC_PRIVCFGR2_IC4PRIV_Pos (3UL) +#define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */ +#define RCC_PRIVCFGR2_IC5PRIV_Pos (4UL) +#define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */ +#define RCC_PRIVCFGR2_IC6PRIV_Pos (5UL) +#define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */ +#define RCC_PRIVCFGR2_IC7PRIV_Pos (6UL) +#define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */ +#define RCC_PRIVCFGR2_IC8PRIV_Pos (7UL) +#define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */ +#define RCC_PRIVCFGR2_IC9PRIV_Pos (8UL) +#define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */ +#define RCC_PRIVCFGR2_IC10PRIV_Pos (9UL) +#define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */ +#define RCC_PRIVCFGR2_IC11PRIV_Pos (10UL) +#define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */ +#define RCC_PRIVCFGR2_IC12PRIV_Pos (11UL) +#define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */ +#define RCC_PRIVCFGR2_IC13PRIV_Pos (12UL) +#define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */ +#define RCC_PRIVCFGR2_IC14PRIV_Pos (13UL) +#define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */ +#define RCC_PRIVCFGR2_IC15PRIV_Pos (14UL) +#define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */ +#define RCC_PRIVCFGR2_IC16PRIV_Pos (15UL) +#define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */ +#define RCC_PRIVCFGR2_IC17PRIV_Pos (16UL) +#define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */ +#define RCC_PRIVCFGR2_IC18PRIV_Pos (17UL) +#define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */ +#define RCC_PRIVCFGR2_IC19PRIV_Pos (18UL) +#define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */ +#define RCC_PRIVCFGR2_IC20PRIV_Pos (19UL) +#define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR2 register *****************/ +#define RCC_LOCKCFGR2_IC1LOCK_Pos (0UL) +#define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */ +#define RCC_LOCKCFGR2_IC2LOCK_Pos (1UL) +#define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */ +#define RCC_LOCKCFGR2_IC3LOCK_Pos (2UL) +#define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */ +#define RCC_LOCKCFGR2_IC4LOCK_Pos (3UL) +#define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */ +#define RCC_LOCKCFGR2_IC5LOCK_Pos (4UL) +#define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */ +#define RCC_LOCKCFGR2_IC6LOCK_Pos (5UL) +#define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */ +#define RCC_LOCKCFGR2_IC7LOCK_Pos (6UL) +#define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */ +#define RCC_LOCKCFGR2_IC8LOCK_Pos (7UL) +#define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */ +#define RCC_LOCKCFGR2_IC9LOCK_Pos (8UL) +#define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */ +#define RCC_LOCKCFGR2_IC10LOCK_Pos (9UL) +#define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */ +#define RCC_LOCKCFGR2_IC11LOCK_Pos (10UL) +#define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */ +#define RCC_LOCKCFGR2_IC12LOCK_Pos (11UL) +#define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */ +#define RCC_LOCKCFGR2_IC13LOCK_Pos (12UL) +#define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */ +#define RCC_LOCKCFGR2_IC14LOCK_Pos (13UL) +#define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */ +#define RCC_LOCKCFGR2_IC15LOCK_Pos (14UL) +#define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */ +#define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */ +#define RCC_LOCKCFGR2_IC16LOCK_Pos (15UL) +#define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */ +#define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */ +#define RCC_LOCKCFGR2_IC17LOCK_Pos (16UL) +#define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */ +#define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */ +#define RCC_LOCKCFGR2_IC18LOCK_Pos (17UL) +#define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */ +#define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */ +#define RCC_LOCKCFGR2_IC19LOCK_Pos (18UL) +#define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */ +#define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */ +#define RCC_LOCKCFGR2_IC20LOCK_Pos (19UL) +#define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */ +#define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR2 register *****************/ +#define RCC_PUBCFGR2_IC1PUB_Pos (0UL) +#define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */ +#define RCC_PUBCFGR2_IC2PUB_Pos (1UL) +#define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */ +#define RCC_PUBCFGR2_IC3PUB_Pos (2UL) +#define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */ +#define RCC_PUBCFGR2_IC4PUB_Pos (3UL) +#define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */ +#define RCC_PUBCFGR2_IC5PUB_Pos (4UL) +#define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */ +#define RCC_PUBCFGR2_IC6PUB_Pos (5UL) +#define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */ +#define RCC_PUBCFGR2_IC7PUB_Pos (6UL) +#define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */ +#define RCC_PUBCFGR2_IC8PUB_Pos (7UL) +#define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */ +#define RCC_PUBCFGR2_IC9PUB_Pos (8UL) +#define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */ +#define RCC_PUBCFGR2_IC10PUB_Pos (9UL) +#define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */ +#define RCC_PUBCFGR2_IC11PUB_Pos (10UL) +#define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */ +#define RCC_PUBCFGR2_IC12PUB_Pos (11UL) +#define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */ +#define RCC_PUBCFGR2_IC13PUB_Pos (12UL) +#define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */ +#define RCC_PUBCFGR2_IC14PUB_Pos (13UL) +#define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */ +#define RCC_PUBCFGR2_IC15PUB_Pos (14UL) +#define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */ +#define RCC_PUBCFGR2_IC16PUB_Pos (15UL) +#define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */ +#define RCC_PUBCFGR2_IC17PUB_Pos (16UL) +#define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */ +#define RCC_PUBCFGR2_IC18PUB_Pos (17UL) +#define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */ +#define RCC_PUBCFGR2_IC19PUB_Pos (18UL) +#define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */ +#define RCC_PUBCFGR2_IC20PUB_Pos (19UL) +#define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_SECCFGR3 register *****************/ +#define RCC_SECCFGR3_MODSEC_Pos (0UL) +#define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */ +#define RCC_SECCFGR3_SYSSEC_Pos (1UL) +#define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */ +#define RCC_SECCFGR3_BUSSEC_Pos (2UL) +#define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */ +#define RCC_SECCFGR3_PERSEC_Pos (3UL) +#define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */ +#define RCC_SECCFGR3_INTSEC_Pos (4UL) +#define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */ +#define RCC_SECCFGR3_RSTSEC_Pos (5UL) +#define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR3 register *****************/ +#define RCC_PRIVCFGR3_MODPRIV_Pos (0UL) +#define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */ +#define RCC_PRIVCFGR3_SYSPRIV_Pos (1UL) +#define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */ +#define RCC_PRIVCFGR3_BUSPRIV_Pos (2UL) +#define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */ +#define RCC_PRIVCFGR3_PERPRIV_Pos (3UL) +#define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */ +#define RCC_PRIVCFGR3_INTPRIV_Pos (4UL) +#define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */ +#define RCC_PRIVCFGR3_RSTPRIV_Pos (5UL) +#define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR3 register *****************/ +#define RCC_LOCKCFGR3_MODLOCK_Pos (0UL) +#define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */ +#define RCC_LOCKCFGR3_SYSLOCK_Pos (1UL) +#define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */ +#define RCC_LOCKCFGR3_BUSLOCK_Pos (2UL) +#define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */ +#define RCC_LOCKCFGR3_PERLOCK_Pos (3UL) +#define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */ +#define RCC_LOCKCFGR3_INTLOCK_Pos (4UL) +#define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */ +#define RCC_LOCKCFGR3_RSTLOCK_Pos (5UL) +#define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR3 register *****************/ +#define RCC_PUBCFGR3_MODPUB_Pos (0UL) +#define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */ +#define RCC_PUBCFGR3_SYSPUB_Pos (1UL) +#define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */ +#define RCC_PUBCFGR3_BUSPUB_Pos (2UL) +#define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */ +#define RCC_PUBCFGR3_PERPUB_Pos (3UL) +#define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */ +#define RCC_PUBCFGR3_INTPUB_Pos (4UL) +#define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */ +#define RCC_PUBCFGR3_RSTPUB_Pos (5UL) +#define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */ + +/***************** Bit definition for RCC_SECCFGR4 register *****************/ +#define RCC_SECCFGR4_ACLKNSEC_Pos (0UL) +#define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */ +#define RCC_SECCFGR4_ACLKNCSEC_Pos (1UL) +#define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */ +#define RCC_SECCFGR4_AHBMSEC_Pos (2UL) +#define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */ +#define RCC_SECCFGR4_AHB1SEC_Pos (3UL) +#define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */ +#define RCC_SECCFGR4_AHB2SEC_Pos (4UL) +#define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */ +#define RCC_SECCFGR4_AHB3SEC_Pos (5UL) +#define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */ +#define RCC_SECCFGR4_AHB4SEC_Pos (6UL) +#define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */ +#define RCC_SECCFGR4_AHB5SEC_Pos (7UL) +#define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */ +#define RCC_SECCFGR4_APB1SEC_Pos (8UL) +#define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */ +#define RCC_SECCFGR4_APB2SEC_Pos (9UL) +#define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */ +#define RCC_SECCFGR4_APB3SEC_Pos (10UL) +#define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */ +#define RCC_SECCFGR4_APB4SEC_Pos (11UL) +#define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */ +#define RCC_SECCFGR4_APB5SEC_Pos (12UL) +#define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */ +#define RCC_SECCFGR4_NOCSEC_Pos (13UL) +#define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR4 register *****************/ +#define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0UL) +#define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */ +#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1UL) +#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */ +#define RCC_PRIVCFGR4_AHBMPRIV_Pos (2UL) +#define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */ +#define RCC_PRIVCFGR4_AHB1PRIV_Pos (3UL) +#define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB2PRIV_Pos (4UL) +#define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB3PRIV_Pos (5UL) +#define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB4PRIV_Pos (6UL) +#define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB5PRIV_Pos (7UL) +#define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */ +#define RCC_PRIVCFGR4_APB1PRIV_Pos (8UL) +#define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */ +#define RCC_PRIVCFGR4_APB2PRIV_Pos (9UL) +#define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */ +#define RCC_PRIVCFGR4_APB3PRIV_Pos (10UL) +#define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */ +#define RCC_PRIVCFGR4_APB4PRIV_Pos (11UL) +#define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */ +#define RCC_PRIVCFGR4_APB5PRIV_Pos (12UL) +#define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */ +#define RCC_PRIVCFGR4_NOCPRIV_Pos (13UL) +#define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR4 register *****************/ +#define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0UL) +#define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */ +#define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */ +#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1UL) +#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */ +#define RCC_LOCKCFGR4_AHBMLOCK_Pos (2UL) +#define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */ +#define RCC_LOCKCFGR4_AHB1LOCK_Pos (3UL) +#define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB2LOCK_Pos (4UL) +#define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB3LOCK_Pos (5UL) +#define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB4LOCK_Pos (6UL) +#define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB5LOCK_Pos (7UL) +#define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */ +#define RCC_LOCKCFGR4_APB1LOCK_Pos (8UL) +#define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */ +#define RCC_LOCKCFGR4_APB2LOCK_Pos (9UL) +#define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */ +#define RCC_LOCKCFGR4_APB3LOCK_Pos (10UL) +#define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */ +#define RCC_LOCKCFGR4_APB4LOCK_Pos (11UL) +#define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */ +#define RCC_LOCKCFGR4_APB5LOCK_Pos (12UL) +#define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */ +#define RCC_LOCKCFGR4_NOCLOCK_Pos (13UL) +#define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR4 register *****************/ +#define RCC_PUBCFGR4_ACLKNPUB_Pos (0UL) +#define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */ +#define RCC_PUBCFGR4_ACLKNCPUB_Pos (1UL) +#define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */ +#define RCC_PUBCFGR4_AHBMPUB_Pos (2UL) +#define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */ +#define RCC_PUBCFGR4_AHB1PUB_Pos (3UL) +#define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */ +#define RCC_PUBCFGR4_AHB2PUB_Pos (4UL) +#define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */ +#define RCC_PUBCFGR4_AHB3PUB_Pos (5UL) +#define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */ +#define RCC_PUBCFGR4_AHB4PUB_Pos (6UL) +#define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */ +#define RCC_PUBCFGR4_AHB5PUB_Pos (7UL) +#define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */ +#define RCC_PUBCFGR4_APB1PUB_Pos (8UL) +#define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */ +#define RCC_PUBCFGR4_APB2PUB_Pos (9UL) +#define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */ +#define RCC_PUBCFGR4_APB3PUB_Pos (10UL) +#define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */ +#define RCC_PUBCFGR4_APB4PUB_Pos (11UL) +#define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */ +#define RCC_PUBCFGR4_APB5PUB_Pos (12UL) +#define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */ +#define RCC_PUBCFGR4_NOCPUB_Pos (13UL) +#define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR5 register *****************/ +#define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0UL) +#define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1UL) +#define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2UL) +#define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3UL) +#define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4UL) +#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5UL) +#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6UL) +#define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */ +#define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7UL) +#define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8UL) +#define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9UL) +#define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */ +#define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */ +#define RCC_PUBCFGR5_VENCRAMPUB_Pos (11UL) +#define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */ +#define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSIONS_Pos (0UL) +#define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */ +#define RCC_CSR_LSEONS_Pos (1UL) +#define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */ +#define RCC_CSR_MSIONS_Pos (2UL) +#define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */ +#define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */ +#define RCC_CSR_HSIONS_Pos (3UL) +#define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */ +#define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */ +#define RCC_CSR_HSEONS_Pos (4UL) +#define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */ +#define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */ +#define RCC_CSR_PLL1ONS_Pos (8UL) +#define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */ +#define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */ +#define RCC_CSR_PLL2ONS_Pos (9UL) +#define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */ +#define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */ +#define RCC_CSR_PLL3ONS_Pos (10UL) +#define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */ +#define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */ +#define RCC_CSR_PLL4ONS_Pos (11UL) +#define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */ +#define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCSR register ******************/ +#define RCC_STOPCSR_MSISTOPENS_Pos (0UL) +#define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */ +#define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCSR_HSISTOPENS_Pos (1UL) +#define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */ +#define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTSR register *****************/ +#define RCC_MISCRSTSR_DBGRSTS_Pos (0UL) +#define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4UL) +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5UL) +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7UL) +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8UL) +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTSR register *****************/ +#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0UL) +#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1UL) +#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2UL) +#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3UL) +#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4UL) +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5UL) +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7UL) +#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8UL) +#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9UL) +#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11UL) +#define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12UL) +#define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTSR register *****************/ +#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4UL) +#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTSR_ADC12RSTS_Pos (5UL) +#define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTSR register *****************/ +#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12UL) +#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTSR_MDF1RSTS_Pos (16UL) +#define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTSR_ADF1RSTS_Pos (17UL) +#define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTSR register *****************/ +#define RCC_AHB3RSTSR_RNGRSTS_Pos (0UL) +#define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */ +#define RCC_AHB3RSTSR_HASHRSTS_Pos (1UL) +#define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */ +#define RCC_AHB3RSTSR_CRYPRSTS_Pos (2UL) +#define RCC_AHB3RSTSR_CRYPRSTS_Msk (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTSR_CRYPRSTS RCC_AHB3RSTSR_CRYPRSTS_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTSR_SAESRSTS_Pos (4UL) +#define RCC_AHB3RSTSR_SAESRSTS_Msk (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSR_SAESRSTS RCC_AHB3RSTSR_SAESRSTS_Msk /*!< SAES reset */ +#define RCC_AHB3RSTSR_PKARSTS_Pos (8UL) +#define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */ +#define RCC_AHB3RSTSR_IACRSTS_Pos (10UL) +#define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTSR register *****************/ +#define RCC_AHB4RSTSR_GPIOARSTS_Pos (0UL) +#define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1UL) +#define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2UL) +#define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTSR_GPIODRSTS_Pos (3UL) +#define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTSR_GPIOERSTS_Pos (4UL) +#define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5UL) +#define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6UL) +#define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7UL) +#define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTSR_GPIONRSTS_Pos (13UL) +#define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTSR_GPIOORSTS_Pos (14UL) +#define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15UL) +#define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16UL) +#define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTSR_PWRRSTS_Pos (18UL) +#define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */ +#define RCC_AHB4RSTSR_CRCRSTS_Pos (19UL) +#define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTSR register *****************/ +#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0UL) +#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1UL) +#define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTSR_JPEGRSTS_Pos (3UL) +#define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTSR_FMCRSTS_Pos (4UL) +#define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */ +#define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5UL) +#define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTSR_PSSIRSTS_Pos (6UL) +#define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7UL) +#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8UL) +#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12UL) +#define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13UL) +#define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17UL) +#define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19UL) +#define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20UL) +#define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23UL) +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24UL) +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTSR_ETH1RSTS_Pos (25UL) +#define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTSR_OTG1RSTS_Pos (26UL) +#define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27UL) +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28UL) +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTSR_OTG2RSTS_Pos (29UL) +#define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */ + +/**************** Bit definition for RCC_APB1RSTSR1 register ****************/ +#define RCC_APB1RSTSR1_TIM2RSTS_Pos (0UL) +#define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTSR1_TIM3RSTS_Pos (1UL) +#define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTSR1_TIM4RSTS_Pos (2UL) +#define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTSR1_TIM5RSTS_Pos (3UL) +#define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTSR1_TIM6RSTS_Pos (4UL) +#define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTSR1_TIM7RSTS_Pos (5UL) +#define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTSR1_TIM12RSTS_Pos (6UL) +#define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTSR1_TIM13RSTS_Pos (7UL) +#define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTSR1_TIM14RSTS_Pos (8UL) +#define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9UL) +#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTSR1_WWDGRSTS_Pos (11UL) +#define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */ +#define RCC_APB1RSTSR1_TIM10RSTS_Pos (12UL) +#define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTSR1_TIM11RSTS_Pos (13UL) +#define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTSR1_SPI2RSTS_Pos (14UL) +#define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTSR1_SPI3RSTS_Pos (15UL) +#define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16UL) +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTSR1_USART2RSTS_Pos (17UL) +#define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */ +#define RCC_APB1RSTSR1_USART3RSTS_Pos (18UL) +#define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */ +#define RCC_APB1RSTSR1_UART4RSTS_Pos (19UL) +#define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */ +#define RCC_APB1RSTSR1_UART5RSTS_Pos (20UL) +#define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */ +#define RCC_APB1RSTSR1_I2C1RSTS_Pos (21UL) +#define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTSR1_I2C2RSTS_Pos (22UL) +#define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTSR1_I2C3RSTS_Pos (23UL) +#define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTSR1_I3C1RSTS_Pos (24UL) +#define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTSR1_I3C2RSTS_Pos (25UL) +#define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTSR1_UART7RSTS_Pos (30UL) +#define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */ +#define RCC_APB1RSTSR1_UART8RSTS_Pos (31UL) +#define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTSR2 register ****************/ +#define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5UL) +#define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTSR2_FDCANRSTS_Pos (8UL) +#define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18UL) +#define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTSR register *****************/ +#define RCC_APB2RSTSR_TIM1RSTS_Pos (0UL) +#define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTSR_TIM8RSTS_Pos (1UL) +#define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTSR_USART1RSTS_Pos (4UL) +#define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */ +#define RCC_APB2RSTSR_USART6RSTS_Pos (5UL) +#define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */ +#define RCC_APB2RSTSR_UART9RSTS_Pos (6UL) +#define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */ +#define RCC_APB2RSTSR_USART10RSTS_Pos (7UL) +#define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */ +#define RCC_APB2RSTSR_SPI1RSTS_Pos (12UL) +#define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTSR_SPI4RSTS_Pos (13UL) +#define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTSR_TIM18RSTS_Pos (15UL) +#define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTSR_TIM15RSTS_Pos (16UL) +#define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTSR_TIM16RSTS_Pos (17UL) +#define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTSR_TIM17RSTS_Pos (18UL) +#define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTSR_TIM9RSTS_Pos (19UL) +#define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTSR_SPI5RSTS_Pos (20UL) +#define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTSR_SAI1RSTS_Pos (21UL) +#define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTSR_SAI2RSTS_Pos (22UL) +#define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTSR1 register ****************/ +#define RCC_APB4RSTSR1_HDPRSTS_Pos (2UL) +#define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */ +#define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3UL) +#define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTSR1_SPI6RSTS_Pos (5UL) +#define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTSR1_I2C4RSTS_Pos (7UL) +#define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9UL) +#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10UL) +#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11UL) +#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12UL) +#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15UL) +#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTSR1_RTCRSTS_Pos (16UL) +#define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTSR2 register ****************/ +#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0UL) +#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTSR2_DTSRSTS_Pos (2UL) +#define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTSR register *****************/ +#define RCC_APB5RSTSR_LTDCRSTS_Pos (1UL) +#define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */ +#define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2UL) +#define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4UL) +#define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTSR_VENCRSTS_Pos (5UL) +#define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */ +#define RCC_APB5RSTSR_CSIRSTS_Pos (6UL) +#define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENSR register ******************/ +#define RCC_DIVENSR_IC1ENS_Pos (0UL) +#define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */ +#define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */ +#define RCC_DIVENSR_IC2ENS_Pos (1UL) +#define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */ +#define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */ +#define RCC_DIVENSR_IC3ENS_Pos (2UL) +#define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */ +#define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */ +#define RCC_DIVENSR_IC4ENS_Pos (3UL) +#define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */ +#define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */ +#define RCC_DIVENSR_IC5ENS_Pos (4UL) +#define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */ +#define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */ +#define RCC_DIVENSR_IC6ENS_Pos (5UL) +#define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */ +#define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */ +#define RCC_DIVENSR_IC7ENS_Pos (6UL) +#define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */ +#define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */ +#define RCC_DIVENSR_IC8ENS_Pos (7UL) +#define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */ +#define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */ +#define RCC_DIVENSR_IC9ENS_Pos (8UL) +#define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */ +#define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */ +#define RCC_DIVENSR_IC10ENS_Pos (9UL) +#define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */ +#define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */ +#define RCC_DIVENSR_IC11ENS_Pos (10UL) +#define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */ +#define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */ +#define RCC_DIVENSR_IC12ENS_Pos (11UL) +#define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */ +#define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */ +#define RCC_DIVENSR_IC13ENS_Pos (12UL) +#define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */ +#define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */ +#define RCC_DIVENSR_IC14ENS_Pos (13UL) +#define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */ +#define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */ +#define RCC_DIVENSR_IC15ENS_Pos (14UL) +#define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */ +#define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */ +#define RCC_DIVENSR_IC16ENS_Pos (15UL) +#define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */ +#define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */ +#define RCC_DIVENSR_IC17ENS_Pos (16UL) +#define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */ +#define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */ +#define RCC_DIVENSR_IC18ENS_Pos (17UL) +#define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */ +#define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */ +#define RCC_DIVENSR_IC19ENS_Pos (18UL) +#define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */ +#define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */ +#define RCC_DIVENSR_IC20ENS_Pos (19UL) +#define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */ +#define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENSR register ******************/ +#define RCC_BUSENSR_ACLKNENS_Pos (0UL) +#define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */ +#define RCC_BUSENSR_ACLKNCENS_Pos (1UL) +#define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */ +#define RCC_BUSENSR_AHBMENS_Pos (2UL) +#define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */ +#define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */ +#define RCC_BUSENSR_AHB1ENS_Pos (3UL) +#define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */ +#define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */ +#define RCC_BUSENSR_AHB2ENS_Pos (4UL) +#define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */ +#define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */ +#define RCC_BUSENSR_AHB3ENS_Pos (5UL) +#define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */ +#define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */ +#define RCC_BUSENSR_AHB4ENS_Pos (6UL) +#define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */ +#define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */ +#define RCC_BUSENSR_AHB5ENS_Pos (7UL) +#define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */ +#define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */ +#define RCC_BUSENSR_APB1ENS_Pos (8UL) +#define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */ +#define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */ +#define RCC_BUSENSR_APB2ENS_Pos (9UL) +#define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */ +#define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */ +#define RCC_BUSENSR_APB3ENS_Pos (10UL) +#define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */ +#define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */ +#define RCC_BUSENSR_APB4ENS_Pos (11UL) +#define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */ +#define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */ +#define RCC_BUSENSR_APB5ENS_Pos (12UL) +#define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */ +#define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENSR register *****************/ +#define RCC_MISCENSR_DBGENS_Pos (0UL) +#define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */ +#define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */ +#define RCC_MISCENSR_MCO1ENS_Pos (1UL) +#define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */ +#define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */ +#define RCC_MISCENSR_MCO2ENS_Pos (2UL) +#define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */ +#define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */ +#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3UL) +#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENSR_PERENS_Pos (6UL) +#define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */ +#define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENSR register ******************/ +#define RCC_MEMENSR_AXISRAM3ENS_Pos (0UL) +#define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */ +#define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENSR_AXISRAM4ENS_Pos (1UL) +#define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */ +#define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENSR_AXISRAM5ENS_Pos (2UL) +#define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */ +#define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENSR_AXISRAM6ENS_Pos (3UL) +#define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */ +#define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENSR_AHBSRAM1ENS_Pos (4UL) +#define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */ +#define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENSR_AHBSRAM2ENS_Pos (5UL) +#define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */ +#define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENSR_BKPSRAMENS_Pos (6UL) +#define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENSR_AXISRAM1ENS_Pos (7UL) +#define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */ +#define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENSR_AXISRAM2ENS_Pos (8UL) +#define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */ +#define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENSR_FLEXRAMENS_Pos (9UL) +#define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENSR_VENCRAMENS_Pos (11UL) +#define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMENSR_BOOTROMENS_Pos (12UL) +#define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENSR register *****************/ +#define RCC_AHB1ENSR_GPDMA1ENS_Pos (4UL) +#define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENSR_ADC12ENS_Pos (5UL) +#define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENSR register *****************/ +#define RCC_AHB2ENSR_RAMCFGENS_Pos (12UL) +#define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENSR_MDF1ENS_Pos (16UL) +#define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENSR_ADF1ENS_Pos (17UL) +#define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENSR register *****************/ +#define RCC_AHB3ENSR_RNGENS_Pos (0UL) +#define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */ +#define RCC_AHB3ENSR_HASHENS_Pos (1UL) +#define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */ +#define RCC_AHB3ENSR_CRYPENS_Pos (2UL) +#define RCC_AHB3ENSR_CRYPENS_Msk (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENSR_CRYPENS RCC_AHB3ENSR_CRYPENS_Msk /*!< CRYP enable */ +#define RCC_AHB3ENSR_SAESENS_Pos (4UL) +#define RCC_AHB3ENSR_SAESENS_Msk (0x1UL << RCC_AHB3ENSR_SAESENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENSR_SAESENS RCC_AHB3ENSR_SAESENS_Msk /*!< SAES enable */ +#define RCC_AHB3ENSR_PKAENS_Pos (8UL) +#define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */ +#define RCC_AHB3ENSR_RIFSCENS_Pos (9UL) +#define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENSR_IACENS_Pos (10UL) +#define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */ +#define RCC_AHB3ENSR_RISAFENS_Pos (14UL) +#define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENSR register *****************/ +#define RCC_AHB4ENSR_GPIOAENS_Pos (0UL) +#define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENSR_GPIOBENS_Pos (1UL) +#define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENSR_GPIOCENS_Pos (2UL) +#define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENSR_GPIODENS_Pos (3UL) +#define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENSR_GPIOEENS_Pos (4UL) +#define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENSR_GPIOFENS_Pos (5UL) +#define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENSR_GPIOGENS_Pos (6UL) +#define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENSR_GPIOHENS_Pos (7UL) +#define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENSR_GPIONENS_Pos (13UL) +#define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENSR_GPIOOENS_Pos (14UL) +#define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENSR_GPIOPENS_Pos (15UL) +#define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENSR_GPIOQENS_Pos (16UL) +#define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENSR_PWRENS_Pos (18UL) +#define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */ +#define RCC_AHB4ENSR_CRCENS_Pos (19UL) +#define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENSR register *****************/ +#define RCC_AHB5ENSR_HPDMA1ENS_Pos (0UL) +#define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENSR_DMA2DENS_Pos (1UL) +#define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENSR_JPEGENS_Pos (3UL) +#define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */ +#define RCC_AHB5ENSR_FMCENS_Pos (4UL) +#define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */ +#define RCC_AHB5ENSR_XSPI1ENS_Pos (5UL) +#define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENSR_PSSIENS_Pos (6UL) +#define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */ +#define RCC_AHB5ENSR_SDMMC2ENS_Pos (7UL) +#define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENSR_SDMMC1ENS_Pos (8UL) +#define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENSR_XSPI2ENS_Pos (12UL) +#define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENSR_XSPIMENS_Pos (13UL) +#define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENSR_MCE1ENS_Pos (14UL) +#define RCC_AHB5ENSR_MCE1ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENSR_MCE1ENS RCC_AHB5ENSR_MCE1ENS_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENSR_MCE2ENS_Pos (15UL) +#define RCC_AHB5ENSR_MCE2ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENSR_MCE2ENS RCC_AHB5ENSR_MCE2ENS_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENSR_MCE3ENS_Pos (16UL) +#define RCC_AHB5ENSR_MCE3ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENSR_MCE3ENS RCC_AHB5ENSR_MCE3ENS_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENSR_XSPI3ENS_Pos (17UL) +#define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENSR_MCE4ENS_Pos (18UL) +#define RCC_AHB5ENSR_MCE4ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENSR_MCE4ENS RCC_AHB5ENSR_MCE4ENS_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENSR_GFXMMUENS_Pos (19UL) +#define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENSR_GPU2DENS_Pos (20UL) +#define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENSR_ETH1MACENS_Pos (22UL) +#define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENSR_ETH1TXENS_Pos (23UL) +#define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENSR_ETH1RXENS_Pos (24UL) +#define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENSR_ETH1ENS_Pos (25UL) +#define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENSR_OTG1ENS_Pos (26UL) +#define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27UL) +#define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28UL) +#define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENSR_OTG2ENS_Pos (29UL) +#define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */ + +/**************** Bit definition for RCC_APB1ENSR1 register *****************/ +#define RCC_APB1ENSR1_TIM2ENS_Pos (0UL) +#define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */ +#define RCC_APB1ENSR1_TIM3ENS_Pos (1UL) +#define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */ +#define RCC_APB1ENSR1_TIM4ENS_Pos (2UL) +#define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */ +#define RCC_APB1ENSR1_TIM5ENS_Pos (3UL) +#define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */ +#define RCC_APB1ENSR1_TIM6ENS_Pos (4UL) +#define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */ +#define RCC_APB1ENSR1_TIM7ENS_Pos (5UL) +#define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */ +#define RCC_APB1ENSR1_TIM12ENS_Pos (6UL) +#define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */ +#define RCC_APB1ENSR1_TIM13ENS_Pos (7UL) +#define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */ +#define RCC_APB1ENSR1_TIM14ENS_Pos (8UL) +#define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */ +#define RCC_APB1ENSR1_LPTIM1ENS_Pos (9UL) +#define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENSR1_WWDGENS_Pos (11UL) +#define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */ +#define RCC_APB1ENSR1_TIM10ENS_Pos (12UL) +#define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */ +#define RCC_APB1ENSR1_TIM11ENS_Pos (13UL) +#define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */ +#define RCC_APB1ENSR1_SPI2ENS_Pos (14UL) +#define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */ +#define RCC_APB1ENSR1_SPI3ENS_Pos (15UL) +#define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */ +#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16UL) +#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENSR1_USART2ENS_Pos (17UL) +#define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */ +#define RCC_APB1ENSR1_USART3ENS_Pos (18UL) +#define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */ +#define RCC_APB1ENSR1_UART4ENS_Pos (19UL) +#define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */ +#define RCC_APB1ENSR1_UART5ENS_Pos (20UL) +#define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */ +#define RCC_APB1ENSR1_I2C1ENS_Pos (21UL) +#define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */ +#define RCC_APB1ENSR1_I2C2ENS_Pos (22UL) +#define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */ +#define RCC_APB1ENSR1_I2C3ENS_Pos (23UL) +#define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */ +#define RCC_APB1ENSR1_I3C1ENS_Pos (24UL) +#define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */ +#define RCC_APB1ENSR1_I3C2ENS_Pos (25UL) +#define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */ +#define RCC_APB1ENSR1_UART7ENS_Pos (30UL) +#define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */ +#define RCC_APB1ENSR1_UART8ENS_Pos (31UL) +#define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENSR2 register *****************/ +#define RCC_APB1ENSR2_MDIOSENS_Pos (5UL) +#define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */ +#define RCC_APB1ENSR2_FDCANENS_Pos (8UL) +#define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */ +#define RCC_APB1ENSR2_UCPD1ENS_Pos (18UL) +#define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENSR register *****************/ +#define RCC_APB2ENSR_TIM1ENS_Pos (0UL) +#define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */ +#define RCC_APB2ENSR_TIM8ENS_Pos (1UL) +#define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */ +#define RCC_APB2ENSR_USART1ENS_Pos (4UL) +#define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */ +#define RCC_APB2ENSR_USART6ENS_Pos (5UL) +#define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */ +#define RCC_APB2ENSR_UART9ENS_Pos (6UL) +#define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */ +#define RCC_APB2ENSR_USART10ENS_Pos (7UL) +#define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */ +#define RCC_APB2ENSR_SPI1ENS_Pos (12UL) +#define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */ +#define RCC_APB2ENSR_SPI4ENS_Pos (13UL) +#define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */ +#define RCC_APB2ENSR_TIM18ENS_Pos (15UL) +#define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */ +#define RCC_APB2ENSR_TIM15ENS_Pos (16UL) +#define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */ +#define RCC_APB2ENSR_TIM16ENS_Pos (17UL) +#define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */ +#define RCC_APB2ENSR_TIM17ENS_Pos (18UL) +#define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */ +#define RCC_APB2ENSR_TIM9ENS_Pos (19UL) +#define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */ +#define RCC_APB2ENSR_SPI5ENS_Pos (20UL) +#define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */ +#define RCC_APB2ENSR_SAI1ENS_Pos (21UL) +#define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */ +#define RCC_APB2ENSR_SAI2ENS_Pos (22UL) +#define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENSR register *****************/ +#define RCC_APB3ENSR_DFTENS_Pos (2UL) +#define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENSR1 register *****************/ +#define RCC_APB4ENSR1_HDPENS_Pos (2UL) +#define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */ +#define RCC_APB4ENSR1_LPUART1ENS_Pos (3UL) +#define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENSR1_SPI6ENS_Pos (5UL) +#define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */ +#define RCC_APB4ENSR1_I2C4ENS_Pos (7UL) +#define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */ +#define RCC_APB4ENSR1_LPTIM2ENS_Pos (9UL) +#define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENSR1_LPTIM3ENS_Pos (10UL) +#define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENSR1_LPTIM4ENS_Pos (11UL) +#define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENSR1_LPTIM5ENS_Pos (12UL) +#define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENSR1_VREFBUFENS_Pos (15UL) +#define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENSR1_RTCENS_Pos (16UL) +#define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */ +#define RCC_APB4ENSR1_RTCAPBENS_Pos (17UL) +#define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENSR2 register *****************/ +#define RCC_APB4ENSR2_SYSCFGENS_Pos (0UL) +#define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENSR2_BSECENS_Pos (1UL) +#define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */ +#define RCC_APB4ENSR2_DTSENS_Pos (2UL) +#define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENSR register *****************/ +#define RCC_APB5ENSR_LTDCENS_Pos (1UL) +#define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */ +#define RCC_APB5ENSR_DCMIPPENS_Pos (2UL) +#define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENSR_GFXTIMENS_Pos (4UL) +#define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENSR_VENCENS_Pos (5UL) +#define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */ +#define RCC_APB5ENSR_CSIENS_Pos (6UL) +#define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENSR register *****************/ +#define RCC_BUSLPENSR_ACLKNLPENS_Pos (0UL) +#define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1UL) +#define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENSR register ****************/ +#define RCC_MISCLPENSR_DBGLPENS_Pos (0UL) +#define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3UL) +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENSR_PERLPENS_Pos (6UL) +#define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */ + +/**************** Bit definition for RCC_MEMLPENSR register *****************/ +#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0UL) +#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1UL) +#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2UL) +#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3UL) +#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4UL) +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5UL) +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6UL) +#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7UL) +#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8UL) +#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9UL) +#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11UL) +#define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12UL) +#define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENSR register ****************/ +#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4UL) +#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENSR_ADC12LPENS_Pos (5UL) +#define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENSR register ****************/ +#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12UL) +#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENSR_MDF1LPENS_Pos (16UL) +#define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENSR_ADF1LPENS_Pos (17UL) +#define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENSR register ****************/ +#define RCC_AHB3LPENSR_RNGLPENS_Pos (0UL) +#define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */ +#define RCC_AHB3LPENSR_HASHLPENS_Pos (1UL) +#define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */ +#define RCC_AHB3LPENSR_CRYPLPENS_Pos (2UL) +#define RCC_AHB3LPENSR_CRYPLPENS_Msk (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENSR_CRYPLPENS RCC_AHB3LPENSR_CRYPLPENS_Msk /*!< CRYP enable */ +#define RCC_AHB3LPENSR_SAESLPENS_Pos (4UL) +#define RCC_AHB3LPENSR_SAESLPENS_Msk (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENSR_SAESLPENS RCC_AHB3LPENSR_SAESLPENS_Msk /*!< SAES enable */ +#define RCC_AHB3LPENSR_PKALPENS_Pos (8UL) +#define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */ +#define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9UL) +#define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENSR_IACLPENS_Pos (10UL) +#define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENSR_RISAFLPENS_Pos (14UL) +#define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENSR register ****************/ +#define RCC_AHB4LPENSR_GPIOALPENS_Pos (0UL) +#define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1UL) +#define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2UL) +#define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENSR_GPIODLPENS_Pos (3UL) +#define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENSR_GPIOELPENS_Pos (4UL) +#define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5UL) +#define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6UL) +#define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7UL) +#define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENSR_GPIONLPENS_Pos (13UL) +#define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14UL) +#define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15UL) +#define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16UL) +#define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENSR_PWRLPENS_Pos (18UL) +#define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */ +#define RCC_AHB4LPENSR_CRCLPENS_Pos (19UL) +#define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENSR register ****************/ +#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0UL) +#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1UL) +#define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENSR_JPEGLPENS_Pos (3UL) +#define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENSR_FMCLPENS_Pos (4UL) +#define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */ +#define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5UL) +#define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENSR_PSSILPENS_Pos (6UL) +#define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7UL) +#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8UL) +#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12UL) +#define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13UL) +#define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENSR_MCE1LPENS_Pos (14UL) +#define RCC_AHB5LPENSR_MCE1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENSR_MCE1LPENS RCC_AHB5LPENSR_MCE1LPENS_Msk /*!< MCE1 enable */ +#define RCC_AHB5LPENSR_MCE2LPENS_Pos (15UL) +#define RCC_AHB5LPENSR_MCE2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENSR_MCE2LPENS RCC_AHB5LPENSR_MCE2LPENS_Msk /*!< MCE2 enable */ +#define RCC_AHB5LPENSR_MCE3LPENS_Pos (16UL) +#define RCC_AHB5LPENSR_MCE3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENSR_MCE3LPENS RCC_AHB5LPENSR_MCE3LPENS_Msk /*!< MCE3 enable */ +#define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17UL) +#define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENSR_MCE4LPENS_Pos (18UL) +#define RCC_AHB5LPENSR_MCE4LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENSR_MCE4LPENS RCC_AHB5LPENSR_MCE4LPENS_Msk /*!< MCE4 enable */ +#define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19UL) +#define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20UL) +#define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22UL) +#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23UL) +#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24UL) +#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENSR_ETH1LPENS_Pos (25UL) +#define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENSR_OTG1LPENS_Pos (26UL) +#define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27UL) +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28UL) +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENSR_OTG2LPENS_Pos (29UL) +#define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */ + +/*************** Bit definition for RCC_APB1LPENSR1 register ****************/ +#define RCC_APB1LPENSR1_TIM2LPENS_Pos (0UL) +#define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENSR1_TIM3LPENS_Pos (1UL) +#define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENSR1_TIM4LPENS_Pos (2UL) +#define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENSR1_TIM5LPENS_Pos (3UL) +#define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENSR1_TIM6LPENS_Pos (4UL) +#define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENSR1_TIM7LPENS_Pos (5UL) +#define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENSR1_TIM12LPENS_Pos (6UL) +#define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENSR1_TIM13LPENS_Pos (7UL) +#define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENSR1_TIM14LPENS_Pos (8UL) +#define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9UL) +#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENSR1_WWDGLPENS_Pos (11UL) +#define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */ +#define RCC_APB1LPENSR1_TIM10LPENS_Pos (12UL) +#define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENSR1_TIM11LPENS_Pos (13UL) +#define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENSR1_SPI2LPENS_Pos (14UL) +#define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENSR1_SPI3LPENS_Pos (15UL) +#define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16UL) +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENSR1_USART2LPENS_Pos (17UL) +#define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */ +#define RCC_APB1LPENSR1_USART3LPENS_Pos (18UL) +#define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */ +#define RCC_APB1LPENSR1_UART4LPENS_Pos (19UL) +#define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */ +#define RCC_APB1LPENSR1_UART5LPENS_Pos (20UL) +#define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */ +#define RCC_APB1LPENSR1_I2C1LPENS_Pos (21UL) +#define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENSR1_I2C2LPENS_Pos (22UL) +#define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENSR1_I2C3LPENS_Pos (23UL) +#define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENSR1_I3C1LPENS_Pos (24UL) +#define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENSR1_I3C2LPENS_Pos (25UL) +#define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENSR1_UART7LPENS_Pos (30UL) +#define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */ +#define RCC_APB1LPENSR1_UART8LPENS_Pos (31UL) +#define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENSR2 register ****************/ +#define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5UL) +#define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENSR2_FDCANLPENS_Pos (8UL) +#define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18UL) +#define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENSR register ****************/ +#define RCC_APB2LPENSR_TIM1LPENS_Pos (0UL) +#define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENSR_TIM8LPENS_Pos (1UL) +#define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENSR_USART1LPENS_Pos (4UL) +#define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */ +#define RCC_APB2LPENSR_USART6LPENS_Pos (5UL) +#define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */ +#define RCC_APB2LPENSR_UART9LPENS_Pos (6UL) +#define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */ +#define RCC_APB2LPENSR_USART10LPENS_Pos (7UL) +#define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */ +#define RCC_APB2LPENSR_SPI1LPENS_Pos (12UL) +#define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENSR_SPI4LPENS_Pos (13UL) +#define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENSR_TIM18LPENS_Pos (15UL) +#define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENSR_TIM15LPENS_Pos (16UL) +#define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENSR_TIM16LPENS_Pos (17UL) +#define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENSR_TIM17LPENS_Pos (18UL) +#define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENSR_TIM9LPENS_Pos (19UL) +#define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENSR_SPI5LPENS_Pos (20UL) +#define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENSR_SAI1LPENS_Pos (21UL) +#define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENSR_SAI2LPENS_Pos (22UL) +#define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENSR register ****************/ +#define RCC_APB3LPENSR_DFTLPENS_Pos (2UL) +#define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENSR1 register ****************/ +#define RCC_APB4LPENSR1_HDPLPENS_Pos (2UL) +#define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */ +#define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3UL) +#define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENSR1_SPI6LPENS_Pos (5UL) +#define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENSR1_I2C4LPENS_Pos (7UL) +#define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9UL) +#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10UL) +#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11UL) +#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12UL) +#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15UL) +#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENSR1_RTCLPENS_Pos (16UL) +#define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */ +#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17UL) +#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENSR2 register ****************/ +#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0UL) +#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENSR2_BSECLPENS_Pos (1UL) +#define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */ +#define RCC_APB4LPENSR2_DTSLPENS_Pos (2UL) +#define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENSR register ****************/ +#define RCC_APB5LPENSR_LTDCLPENS_Pos (1UL) +#define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */ +#define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2UL) +#define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4UL) +#define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENSR_VENCLPENS_Pos (5UL) +#define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */ +#define RCC_APB5LPENSR_CSILPENS_Pos (6UL) +#define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_PRIVCFGSR0 register ****************/ +#define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR0 register *****************/ +#define RCC_PUBCFGSR0_LSIPUBS_Pos (0UL) +#define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_LSEPUBS_Pos (1UL) +#define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_MSIPUBS_Pos (2UL) +#define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSIPUBS_Pos (3UL) +#define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSEPUBS_Pos (4UL) +#define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR1 register ****************/ +#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR1 register *****************/ +#define RCC_PUBCFGSR1_PLL1PUBS_Pos (0UL) +#define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL2PUBS_Pos (1UL) +#define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL3PUBS_Pos (2UL) +#define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL4PUBS_Pos (3UL) +#define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR2 register ****************/ +#define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13UL) +#define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14UL) +#define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15UL) +#define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16UL) +#define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17UL) +#define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18UL) +#define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19UL) +#define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR2 register *****************/ +#define RCC_PUBCFGSR2_IC1PUBS_Pos (0UL) +#define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC2PUBS_Pos (1UL) +#define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC3PUBS_Pos (2UL) +#define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC4PUBS_Pos (3UL) +#define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC5PUBS_Pos (4UL) +#define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC6PUBS_Pos (5UL) +#define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC7PUBS_Pos (6UL) +#define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC8PUBS_Pos (7UL) +#define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC9PUBS_Pos (8UL) +#define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC10PUBS_Pos (9UL) +#define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC11PUBS_Pos (10UL) +#define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC12PUBS_Pos (11UL) +#define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC13PUBS_Pos (12UL) +#define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC14PUBS_Pos (13UL) +#define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC15PUBS_Pos (14UL) +#define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC16PUBS_Pos (15UL) +#define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */ +#define RCC_PUBCFGSR2_IC17PUBS_Pos (16UL) +#define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC18PUBS_Pos (17UL) +#define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC19PUBS_Pos (18UL) +#define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC20PUBS_Pos (19UL) +#define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR3 register ****************/ +#define RCC_PRIVCFGSR3_MODPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_PERPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_INTPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5UL) +#define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR3 register *****************/ +#define RCC_PUBCFGSR3_MODPUBS_Pos (0UL) +#define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_SYSPUBS_Pos (1UL) +#define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_BUSPUBS_Pos (2UL) +#define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_PERPUBS_Pos (3UL) +#define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_INTPUBS_Pos (4UL) +#define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_RSTPUBS_Pos (5UL) +#define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR4 register ****************/ +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13UL) +#define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR4 register *****************/ +#define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0UL) +#define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1UL) +#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHBMPUBS_Pos (2UL) +#define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB1PUBS_Pos (3UL) +#define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB2PUBS_Pos (4UL) +#define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB3PUBS_Pos (5UL) +#define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB4PUBS_Pos (6UL) +#define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB5PUBS_Pos (7UL) +#define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB1PUBS_Pos (8UL) +#define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB2PUBS_Pos (9UL) +#define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB3PUBS_Pos (10UL) +#define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB4PUBS_Pos (11UL) +#define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB5PUBS_Pos (12UL) +#define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_NOCPUBS_Pos (13UL) +#define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR5 register *****************/ +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0UL) +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1UL) +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2UL) +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3UL) +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4UL) +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5UL) +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6UL) +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7UL) +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8UL) +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9UL) +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11UL) +#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + +/******************* Bit definition for RCC_CCR register ********************/ +#define RCC_CCR_LSIONC_Pos (0UL) +#define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */ +#define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */ +#define RCC_CCR_LSEONC_Pos (1UL) +#define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */ +#define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */ +#define RCC_CCR_MSIONC_Pos (2UL) +#define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */ +#define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */ +#define RCC_CCR_HSIONC_Pos (3UL) +#define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */ +#define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */ +#define RCC_CCR_HSEONC_Pos (4UL) +#define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */ +#define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */ +#define RCC_CCR_PLL1ONC_Pos (8UL) +#define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */ +#define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */ +#define RCC_CCR_PLL2ONC_Pos (9UL) +#define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */ +#define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */ +#define RCC_CCR_PLL3ONC_Pos (10UL) +#define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */ +#define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */ +#define RCC_CCR_PLL4ONC_Pos (11UL) +#define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */ +#define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCCR register ******************/ +#define RCC_STOPCCR_MSISTOPENC_Pos (0UL) +#define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */ +#define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCCR_HSISTOPENC_Pos (1UL) +#define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */ +#define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTCR register *****************/ +#define RCC_MISCRSTCR_DBGRSTC_Pos (0UL) +#define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4UL) +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5UL) +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7UL) +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8UL) +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTCR register *****************/ +#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0UL) +#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1UL) +#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2UL) +#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3UL) +#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4UL) +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5UL) +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7UL) +#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8UL) +#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9UL) +#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11UL) +#define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12UL) +#define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTCR register *****************/ +#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4UL) +#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTCR_ADC12RSTC_Pos (5UL) +#define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTCR register *****************/ +#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12UL) +#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTCR_MDF1RSTC_Pos (16UL) +#define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTCR_ADF1RSTC_Pos (17UL) +#define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTCR register *****************/ +#define RCC_AHB3RSTCR_RNGRSTC_Pos (0UL) +#define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */ +#define RCC_AHB3RSTCR_HASHRSTC_Pos (1UL) +#define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */ +#define RCC_AHB3RSTCR_CRYPRSTC_Pos (2UL) +#define RCC_AHB3RSTCR_CRYPRSTC_Msk (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTCR_CRYPRSTC RCC_AHB3RSTCR_CRYPRSTC_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTCR_SAESRSTC_Pos (4UL) +#define RCC_AHB3RSTCR_SAESRSTC_Msk (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCR_SAESRSTC RCC_AHB3RSTCR_SAESRSTC_Msk /*!< SAES reset */ +#define RCC_AHB3RSTCR_PKARSTC_Pos (8UL) +#define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */ +#define RCC_AHB3RSTCR_IACRSTC_Pos (10UL) +#define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTCR register *****************/ +#define RCC_AHB4RSTCR_GPIOARSTC_Pos (0UL) +#define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1UL) +#define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2UL) +#define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTCR_GPIODRSTC_Pos (3UL) +#define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTCR_GPIOERSTC_Pos (4UL) +#define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5UL) +#define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6UL) +#define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7UL) +#define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTCR_GPIONRSTC_Pos (13UL) +#define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTCR_GPIOORSTC_Pos (14UL) +#define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15UL) +#define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16UL) +#define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTCR_PWRRSTC_Pos (18UL) +#define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */ +#define RCC_AHB4RSTCR_CRCRSTC_Pos (19UL) +#define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTCR register *****************/ +#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0UL) +#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1UL) +#define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTCR_JPEGRSTC_Pos (3UL) +#define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTCR_FMCRSTC_Pos (4UL) +#define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */ +#define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5UL) +#define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTCR_PSSIRSTC_Pos (6UL) +#define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7UL) +#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8UL) +#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12UL) +#define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13UL) +#define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17UL) +#define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19UL) +#define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20UL) +#define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23UL) +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24UL) +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTCR_ETH1RSTC_Pos (25UL) +#define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTCR_OTG1RSTC_Pos (26UL) +#define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27UL) +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28UL) +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTCR_OTG2RSTC_Pos (29UL) +#define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */ + +/**************** Bit definition for RCC_APB1RSTCR1 register ****************/ +#define RCC_APB1RSTCR1_TIM2RSTC_Pos (0UL) +#define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTCR1_TIM3RSTC_Pos (1UL) +#define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTCR1_TIM4RSTC_Pos (2UL) +#define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTCR1_TIM5RSTC_Pos (3UL) +#define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTCR1_TIM6RSTC_Pos (4UL) +#define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTCR1_TIM7RSTC_Pos (5UL) +#define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTCR1_TIM12RSTC_Pos (6UL) +#define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTCR1_TIM13RSTC_Pos (7UL) +#define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTCR1_TIM14RSTC_Pos (8UL) +#define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9UL) +#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTCR1_WWDGRSTC_Pos (11UL) +#define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */ +#define RCC_APB1RSTCR1_TIM10RSTC_Pos (12UL) +#define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTCR1_TIM11RSTC_Pos (13UL) +#define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTCR1_SPI2RSTC_Pos (14UL) +#define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTCR1_SPI3RSTC_Pos (15UL) +#define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16UL) +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTCR1_USART2RSTC_Pos (17UL) +#define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */ +#define RCC_APB1RSTCR1_USART3RSTC_Pos (18UL) +#define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */ +#define RCC_APB1RSTCR1_UART4RSTC_Pos (19UL) +#define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */ +#define RCC_APB1RSTCR1_UART5RSTC_Pos (20UL) +#define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */ +#define RCC_APB1RSTCR1_I2C1RSTC_Pos (21UL) +#define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTCR1_I2C2RSTC_Pos (22UL) +#define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTCR1_I2C3RSTC_Pos (23UL) +#define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTCR1_I3C1RSTC_Pos (24UL) +#define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTCR1_I3C2RSTC_Pos (25UL) +#define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTCR1_UART7RSTC_Pos (30UL) +#define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */ +#define RCC_APB1RSTCR1_UART8RSTC_Pos (31UL) +#define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTCR2 register ****************/ +#define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5UL) +#define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTCR2_FDCANRSTC_Pos (8UL) +#define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18UL) +#define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTCR register *****************/ +#define RCC_APB2RSTCR_TIM1RSTC_Pos (0UL) +#define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTCR_TIM8RSTC_Pos (1UL) +#define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTCR_USART1RSTC_Pos (4UL) +#define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */ +#define RCC_APB2RSTCR_USART6RSTC_Pos (5UL) +#define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */ +#define RCC_APB2RSTCR_UART9RSTC_Pos (6UL) +#define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */ +#define RCC_APB2RSTCR_USART10RSTC_Pos (7UL) +#define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */ +#define RCC_APB2RSTCR_SPI1RSTC_Pos (12UL) +#define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTCR_SPI4RSTC_Pos (13UL) +#define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTCR_TIM18RSTC_Pos (15UL) +#define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTCR_TIM15RSTC_Pos (16UL) +#define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTCR_TIM16RSTC_Pos (17UL) +#define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTCR_TIM17RSTC_Pos (18UL) +#define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTCR_TIM9RSTC_Pos (19UL) +#define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTCR_SPI5RSTC_Pos (20UL) +#define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTCR_SAI1RSTC_Pos (21UL) +#define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTCR_SAI2RSTC_Pos (22UL) +#define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTCR1 register ****************/ +#define RCC_APB4RSTCR1_HDPRSTC_Pos (2UL) +#define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */ +#define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3UL) +#define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTCR1_SPI6RSTC_Pos (5UL) +#define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTCR1_I2C4RSTC_Pos (7UL) +#define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9UL) +#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10UL) +#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11UL) +#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12UL) +#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15UL) +#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTCR1_RTCRSTC_Pos (16UL) +#define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTCR2 register ****************/ +#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0UL) +#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTCR2_DTSRSTC_Pos (2UL) +#define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTCR register *****************/ +#define RCC_APB5RSTCR_LTDCRSTC_Pos (1UL) +#define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */ +#define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2UL) +#define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4UL) +#define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTCR_VENCRSTC_Pos (5UL) +#define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */ +#define RCC_APB5RSTCR_CSIRSTC_Pos (6UL) +#define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENCR register ******************/ +#define RCC_DIVENCR_IC1ENC_Pos (0UL) +#define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */ +#define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */ +#define RCC_DIVENCR_IC2ENC_Pos (1UL) +#define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */ +#define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */ +#define RCC_DIVENCR_IC3ENC_Pos (2UL) +#define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */ +#define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */ +#define RCC_DIVENCR_IC4ENC_Pos (3UL) +#define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */ +#define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */ +#define RCC_DIVENCR_IC5ENC_Pos (4UL) +#define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */ +#define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */ +#define RCC_DIVENCR_IC6ENC_Pos (5UL) +#define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */ +#define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */ +#define RCC_DIVENCR_IC7ENC_Pos (6UL) +#define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */ +#define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */ +#define RCC_DIVENCR_IC8ENC_Pos (7UL) +#define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */ +#define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */ +#define RCC_DIVENCR_IC9ENC_Pos (8UL) +#define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */ +#define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */ +#define RCC_DIVENCR_IC10ENC_Pos (9UL) +#define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */ +#define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */ +#define RCC_DIVENCR_IC11ENC_Pos (10UL) +#define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */ +#define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */ +#define RCC_DIVENCR_IC12ENC_Pos (11UL) +#define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */ +#define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */ +#define RCC_DIVENCR_IC13ENC_Pos (12UL) +#define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */ +#define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */ +#define RCC_DIVENCR_IC14ENC_Pos (13UL) +#define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */ +#define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */ +#define RCC_DIVENCR_IC15ENC_Pos (14UL) +#define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */ +#define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */ +#define RCC_DIVENCR_IC16ENC_Pos (15UL) +#define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */ +#define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */ +#define RCC_DIVENCR_IC17ENC_Pos (16UL) +#define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */ +#define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */ +#define RCC_DIVENCR_IC18ENC_Pos (17UL) +#define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */ +#define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */ +#define RCC_DIVENCR_IC19ENC_Pos (18UL) +#define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */ +#define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */ +#define RCC_DIVENCR_IC20ENC_Pos (19UL) +#define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */ +#define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENCR register ******************/ +#define RCC_BUSENCR_ACLKNENC_Pos (0UL) +#define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */ +#define RCC_BUSENCR_ACLKNCENC_Pos (1UL) +#define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */ +#define RCC_BUSENCR_AHBMENC_Pos (2UL) +#define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */ +#define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */ +#define RCC_BUSENCR_AHB1ENC_Pos (3UL) +#define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */ +#define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */ +#define RCC_BUSENCR_AHB2ENC_Pos (4UL) +#define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */ +#define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */ +#define RCC_BUSENCR_AHB3ENC_Pos (5UL) +#define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */ +#define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */ +#define RCC_BUSENCR_AHB4ENC_Pos (6UL) +#define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */ +#define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */ +#define RCC_BUSENCR_AHB5ENC_Pos (7UL) +#define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */ +#define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */ +#define RCC_BUSENCR_APB1ENC_Pos (8UL) +#define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */ +#define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */ +#define RCC_BUSENCR_APB2ENC_Pos (9UL) +#define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */ +#define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */ +#define RCC_BUSENCR_APB3ENC_Pos (10UL) +#define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */ +#define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */ +#define RCC_BUSENCR_APB4ENC_Pos (11UL) +#define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */ +#define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */ +#define RCC_BUSENCR_APB5ENC_Pos (12UL) +#define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */ +#define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENCR register *****************/ +#define RCC_MISCENCR_DBGENC_Pos (0UL) +#define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */ +#define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */ +#define RCC_MISCENCR_MCO1ENC_Pos (1UL) +#define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */ +#define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */ +#define RCC_MISCENCR_MCO2ENC_Pos (2UL) +#define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */ +#define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */ +#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3UL) +#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENCR_PERENC_Pos (6UL) +#define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */ +#define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENCR register ******************/ +#define RCC_MEMENCR_AXISRAM3ENC_Pos (0UL) +#define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */ +#define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENCR_AXISRAM4ENC_Pos (1UL) +#define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */ +#define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENCR_AXISRAM5ENC_Pos (2UL) +#define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */ +#define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENCR_AXISRAM6ENC_Pos (3UL) +#define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */ +#define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENCR_AHBSRAM1ENC_Pos (4UL) +#define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */ +#define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENCR_AHBSRAM2ENC_Pos (5UL) +#define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */ +#define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENCR_BKPSRAMENC_Pos (6UL) +#define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENCR_AXISRAM1ENC_Pos (7UL) +#define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */ +#define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENCR_AXISRAM2ENC_Pos (8UL) +#define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */ +#define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENCR_FLEXRAMENC_Pos (9UL) +#define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENCR_VENCRAMENC_Pos (11UL) +#define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */ +#define RCC_MEMENCR_BOOTROMENC_Pos (12UL) +#define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENCR register *****************/ +#define RCC_AHB1ENCR_GPDMA1ENC_Pos (4UL) +#define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENCR_ADC12ENC_Pos (5UL) +#define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENCR register *****************/ +#define RCC_AHB2ENCR_RAMCFGENC_Pos (12UL) +#define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENCR_MDF1ENC_Pos (16UL) +#define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENCR_ADF1ENC_Pos (17UL) +#define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENCR register *****************/ +#define RCC_AHB3ENCR_RNGENC_Pos (0UL) +#define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */ +#define RCC_AHB3ENCR_HASHENC_Pos (1UL) +#define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */ +#define RCC_AHB3ENCR_CRYPENC_Pos (2UL) +#define RCC_AHB3ENCR_CRYPENC_Msk (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENCR_CRYPENC RCC_AHB3ENCR_CRYPENC_Msk /*!< CRYP enable */ +#define RCC_AHB3ENCR_SAESENC_Pos (4UL) +#define RCC_AHB3ENCR_SAESENC_Msk (0x1UL << RCC_AHB3ENCR_SAESENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENCR_SAESENC RCC_AHB3ENCR_SAESENC_Msk /*!< SAES enable */ +#define RCC_AHB3ENCR_PKAENC_Pos (8UL) +#define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */ +#define RCC_AHB3ENCR_RIFSCENC_Pos (9UL) +#define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENCR_IACENC_Pos (10UL) +#define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */ +#define RCC_AHB3ENCR_RISAFENC_Pos (14UL) +#define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENCR register *****************/ +#define RCC_AHB4ENCR_GPIOAENC_Pos (0UL) +#define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENCR_GPIOBENC_Pos (1UL) +#define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENCR_GPIOCENC_Pos (2UL) +#define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENCR_GPIODENC_Pos (3UL) +#define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENCR_GPIOEENC_Pos (4UL) +#define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENCR_GPIOFENC_Pos (5UL) +#define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENCR_GPIOGENC_Pos (6UL) +#define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENCR_GPIOHENC_Pos (7UL) +#define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENCR_GPIONENC_Pos (13UL) +#define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENCR_GPIOOENC_Pos (14UL) +#define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENCR_GPIOPENC_Pos (15UL) +#define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENCR_GPIOQENC_Pos (16UL) +#define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENCR_PWRENC_Pos (18UL) +#define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */ +#define RCC_AHB4ENCR_CRCENC_Pos (19UL) +#define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENCR register *****************/ +#define RCC_AHB5ENCR_HPDMA1ENC_Pos (0UL) +#define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENCR_DMA2DENC_Pos (1UL) +#define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENCR_JPEGENC_Pos (3UL) +#define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */ +#define RCC_AHB5ENCR_FMCENC_Pos (4UL) +#define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */ +#define RCC_AHB5ENCR_XSPI1ENC_Pos (5UL) +#define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENCR_PSSIENC_Pos (6UL) +#define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */ +#define RCC_AHB5ENCR_SDMMC2ENC_Pos (7UL) +#define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENCR_SDMMC1ENC_Pos (8UL) +#define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENCR_XSPI2ENC_Pos (12UL) +#define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENCR_XSPIMENC_Pos (13UL) +#define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENCR_MCE1ENC_Pos (14UL) +#define RCC_AHB5ENCR_MCE1ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENCR_MCE1ENC RCC_AHB5ENCR_MCE1ENC_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENCR_MCE2ENC_Pos (15UL) +#define RCC_AHB5ENCR_MCE2ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENCR_MCE2ENC RCC_AHB5ENCR_MCE2ENC_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENCR_MCE3ENC_Pos (16UL) +#define RCC_AHB5ENCR_MCE3ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENCR_MCE3ENC RCC_AHB5ENCR_MCE3ENC_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENCR_XSPI3ENC_Pos (17UL) +#define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENCR_MCE4ENC_Pos (18UL) +#define RCC_AHB5ENCR_MCE4ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENCR_MCE4ENC RCC_AHB5ENCR_MCE4ENC_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENCR_GFXMMUENC_Pos (19UL) +#define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENCR_GPU2DENC_Pos (20UL) +#define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENCR_ETH1MACENC_Pos (22UL) +#define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENCR_ETH1TXENC_Pos (23UL) +#define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENCR_ETH1RXENC_Pos (24UL) +#define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENCR_ETH1ENC_Pos (25UL) +#define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENCR_OTG1ENC_Pos (26UL) +#define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27UL) +#define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28UL) +#define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENCR_OTG2ENC_Pos (29UL) +#define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */ + +/**************** Bit definition for RCC_APB1ENCR1 register *****************/ +#define RCC_APB1ENCR1_TIM2ENC_Pos (0UL) +#define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */ +#define RCC_APB1ENCR1_TIM3ENC_Pos (1UL) +#define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */ +#define RCC_APB1ENCR1_TIM4ENC_Pos (2UL) +#define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */ +#define RCC_APB1ENCR1_TIM5ENC_Pos (3UL) +#define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */ +#define RCC_APB1ENCR1_TIM6ENC_Pos (4UL) +#define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */ +#define RCC_APB1ENCR1_TIM7ENC_Pos (5UL) +#define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */ +#define RCC_APB1ENCR1_TIM12ENC_Pos (6UL) +#define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */ +#define RCC_APB1ENCR1_TIM13ENC_Pos (7UL) +#define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */ +#define RCC_APB1ENCR1_TIM14ENC_Pos (8UL) +#define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */ +#define RCC_APB1ENCR1_LPTIM1ENC_Pos (9UL) +#define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENCR1_TIM10ENC_Pos (12UL) +#define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */ +#define RCC_APB1ENCR1_TIM11ENC_Pos (13UL) +#define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */ +#define RCC_APB1ENCR1_SPI2ENC_Pos (14UL) +#define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */ +#define RCC_APB1ENCR1_SPI3ENC_Pos (15UL) +#define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */ +#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16UL) +#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENCR1_USART2ENC_Pos (17UL) +#define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */ +#define RCC_APB1ENCR1_USART3ENC_Pos (18UL) +#define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */ +#define RCC_APB1ENCR1_UART4ENC_Pos (19UL) +#define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */ +#define RCC_APB1ENCR1_UART5ENC_Pos (20UL) +#define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */ +#define RCC_APB1ENCR1_I2C1ENC_Pos (21UL) +#define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */ +#define RCC_APB1ENCR1_I2C2ENC_Pos (22UL) +#define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */ +#define RCC_APB1ENCR1_I2C3ENC_Pos (23UL) +#define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */ +#define RCC_APB1ENCR1_I3C1ENC_Pos (24UL) +#define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */ +#define RCC_APB1ENCR1_I3C2ENC_Pos (25UL) +#define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */ +#define RCC_APB1ENCR1_UART7ENC_Pos (30UL) +#define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */ +#define RCC_APB1ENCR1_UART8ENC_Pos (31UL) +#define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENCR2 register *****************/ +#define RCC_APB1ENCR2_MDIOSENC_Pos (5UL) +#define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */ +#define RCC_APB1ENCR2_FDCANENC_Pos (8UL) +#define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */ +#define RCC_APB1ENCR2_UCPD1ENC_Pos (18UL) +#define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENCR register *****************/ +#define RCC_APB2ENCR_TIM1ENC_Pos (0UL) +#define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */ +#define RCC_APB2ENCR_TIM8ENC_Pos (1UL) +#define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */ +#define RCC_APB2ENCR_USART1ENC_Pos (4UL) +#define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */ +#define RCC_APB2ENCR_USART6ENC_Pos (5UL) +#define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */ +#define RCC_APB2ENCR_UART9ENC_Pos (6UL) +#define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */ +#define RCC_APB2ENCR_USART10ENC_Pos (7UL) +#define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */ +#define RCC_APB2ENCR_SPI1ENC_Pos (12UL) +#define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */ +#define RCC_APB2ENCR_SPI4ENC_Pos (13UL) +#define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */ +#define RCC_APB2ENCR_TIM18ENC_Pos (15UL) +#define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */ +#define RCC_APB2ENCR_TIM15ENC_Pos (16UL) +#define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */ +#define RCC_APB2ENCR_TIM16ENC_Pos (17UL) +#define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */ +#define RCC_APB2ENCR_TIM17ENC_Pos (18UL) +#define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */ +#define RCC_APB2ENCR_TIM9ENC_Pos (19UL) +#define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */ +#define RCC_APB2ENCR_SPI5ENC_Pos (20UL) +#define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */ +#define RCC_APB2ENCR_SAI1ENC_Pos (21UL) +#define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */ +#define RCC_APB2ENCR_SAI2ENC_Pos (22UL) +#define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENCR register *****************/ +#define RCC_APB3ENCR_DFTENC_Pos (2UL) +#define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENCR1 register *****************/ +#define RCC_APB4ENCR1_HDPENC_Pos (2UL) +#define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */ +#define RCC_APB4ENCR1_LPUART1ENC_Pos (3UL) +#define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENCR1_SPI6ENC_Pos (5UL) +#define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */ +#define RCC_APB4ENCR1_I2C4ENC_Pos (7UL) +#define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */ +#define RCC_APB4ENCR1_LPTIM2ENC_Pos (9UL) +#define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENCR1_LPTIM3ENC_Pos (10UL) +#define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENCR1_LPTIM4ENC_Pos (11UL) +#define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENCR1_LPTIM5ENC_Pos (12UL) +#define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENCR1_VREFBUFENC_Pos (15UL) +#define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENCR1_RTCENC_Pos (16UL) +#define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */ +#define RCC_APB4ENCR1_RTCAPBENC_Pos (17UL) +#define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENCR2 register *****************/ +#define RCC_APB4ENCR2_SYSCFGENC_Pos (0UL) +#define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENCR2_BSECENC_Pos (1UL) +#define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */ +#define RCC_APB4ENCR2_DTSENC_Pos (2UL) +#define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENCR register *****************/ +#define RCC_APB5ENCR_LTDCENC_Pos (1UL) +#define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */ +#define RCC_APB5ENCR_DCMIPPENC_Pos (2UL) +#define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENCR_GFXTIMENC_Pos (4UL) +#define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENCR_VENCENC_Pos (5UL) +#define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */ +#define RCC_APB5ENCR_CSIENC_Pos (6UL) +#define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENCR register *****************/ +#define RCC_BUSLPENCR_ACLKNLPENC_Pos (0UL) +#define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */ +#define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1UL) +#define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */ + +/**************** Bit definition for RCC_MISCLPENCR register ****************/ +#define RCC_MISCLPENCR_DBGLPENC_Pos (0UL) +#define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3UL) +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */ +#define RCC_MISCLPENCR_PERLPENC_Pos (6UL) +#define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */ + +/**************** Bit definition for RCC_MEMLPENCR register *****************/ +#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0UL) +#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1UL) +#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2UL) +#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3UL) +#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4UL) +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5UL) +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6UL) +#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7UL) +#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8UL) +#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9UL) +#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11UL) +#define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12UL) +#define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB1LPENCR register ****************/ +#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4UL) +#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */ +#define RCC_AHB1LPENCR_ADC12LPENC_Pos (5UL) +#define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB2LPENCR register ****************/ +#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12UL) +#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */ +#define RCC_AHB2LPENCR_MDF1LPENC_Pos (16UL) +#define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */ +#define RCC_AHB2LPENCR_ADF1LPENC_Pos (17UL) +#define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB3LPENCR register ****************/ +#define RCC_AHB3LPENCR_RNGLPENC_Pos (0UL) +#define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */ +#define RCC_AHB3LPENCR_HASHLPENC_Pos (1UL) +#define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */ +#define RCC_AHB3LPENCR_CRYPLPENC_Pos (2UL) +#define RCC_AHB3LPENCR_CRYPLPENC_Msk (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENCR_CRYPLPENC RCC_AHB3LPENCR_CRYPLPENC_Msk /*!< CRYP enable in Sleep mode */ +#define RCC_AHB3LPENCR_SAESLPENC_Pos (4UL) +#define RCC_AHB3LPENCR_SAESLPENC_Msk (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENCR_SAESLPENC RCC_AHB3LPENCR_SAESLPENC_Msk /*!< SAES enable in Sleep mode */ +#define RCC_AHB3LPENCR_PKALPENC_Pos (8UL) +#define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */ +#define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9UL) +#define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */ +#define RCC_AHB3LPENCR_IACLPENC_Pos (10UL) +#define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENCR_RISAFLPENC_Pos (14UL) +#define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB4LPENCR register ****************/ +#define RCC_AHB4LPENCR_GPIOALPENC_Pos (0UL) +#define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1UL) +#define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2UL) +#define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIODLPENC_Pos (3UL) +#define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOELPENC_Pos (4UL) +#define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5UL) +#define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6UL) +#define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7UL) +#define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIONLPENC_Pos (13UL) +#define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14UL) +#define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15UL) +#define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16UL) +#define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */ +#define RCC_AHB4LPENCR_PWRLPENC_Pos (18UL) +#define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */ +#define RCC_AHB4LPENCR_CRCLPENC_Pos (19UL) +#define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB5LPENCR register ****************/ +#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0UL) +#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1UL) +#define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_JPEGLPENC_Pos (3UL) +#define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */ +#define RCC_AHB5LPENCR_FMCLPENC_Pos (4UL) +#define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5UL) +#define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_PSSILPENC_Pos (6UL) +#define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7UL) +#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8UL) +#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12UL) +#define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13UL) +#define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE1LPENC_Pos (14UL) +#define RCC_AHB5LPENCR_MCE1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENCR_MCE1LPENC RCC_AHB5LPENCR_MCE1LPENC_Msk /*!< MCE1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE2LPENC_Pos (15UL) +#define RCC_AHB5LPENCR_MCE2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENCR_MCE2LPENC RCC_AHB5LPENCR_MCE2LPENC_Msk /*!< MCE2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE3LPENC_Pos (16UL) +#define RCC_AHB5LPENCR_MCE3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENCR_MCE3LPENC RCC_AHB5LPENCR_MCE3LPENC_Msk /*!< MCE3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17UL) +#define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE4LPENC_Pos (18UL) +#define RCC_AHB5LPENCR_MCE4LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENCR_MCE4LPENC RCC_AHB5LPENCR_MCE4LPENC_Msk /*!< MCE4 enable in Sleep mode */ +#define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19UL) +#define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */ +#define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20UL) +#define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22UL) +#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23UL) +#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24UL) +#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1LPENC_Pos (25UL) +#define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG1LPENC_Pos (26UL) +#define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27UL) +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28UL) +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG2LPENC_Pos (29UL) +#define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */ + +/*************** Bit definition for RCC_APB1LPENCR1 register ****************/ +#define RCC_APB1LPENCR1_TIM2LPENC_Pos (0UL) +#define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENCR1_TIM3LPENC_Pos (1UL) +#define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENCR1_TIM4LPENC_Pos (2UL) +#define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENCR1_TIM5LPENC_Pos (3UL) +#define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENCR1_TIM6LPENC_Pos (4UL) +#define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENCR1_TIM7LPENC_Pos (5UL) +#define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENCR1_TIM12LPENC_Pos (6UL) +#define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENCR1_TIM13LPENC_Pos (7UL) +#define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENCR1_TIM14LPENC_Pos (8UL) +#define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9UL) +#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENCR1_WWDGLPENC_Pos (11UL) +#define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */ +#define RCC_APB1LPENCR1_TIM10LPENC_Pos (12UL) +#define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENCR1_TIM11LPENC_Pos (13UL) +#define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENCR1_SPI2LPENC_Pos (14UL) +#define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENCR1_SPI3LPENC_Pos (15UL) +#define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16UL) +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENCR1_USART2LPENC_Pos (17UL) +#define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */ +#define RCC_APB1LPENCR1_USART3LPENC_Pos (18UL) +#define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */ +#define RCC_APB1LPENCR1_UART4LPENC_Pos (19UL) +#define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */ +#define RCC_APB1LPENCR1_UART5LPENC_Pos (20UL) +#define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */ +#define RCC_APB1LPENCR1_I2C1LPENC_Pos (21UL) +#define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENCR1_I2C2LPENC_Pos (22UL) +#define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENCR1_I2C3LPENC_Pos (23UL) +#define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENCR1_I3C1LPENC_Pos (24UL) +#define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENCR1_I3C2LPENC_Pos (25UL) +#define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENCR1_UART7LPENC_Pos (30UL) +#define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */ +#define RCC_APB1LPENCR1_UART8LPENC_Pos (31UL) +#define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENCR2 register ****************/ +#define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5UL) +#define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENCR2_FDCANLPENC_Pos (8UL) +#define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18UL) +#define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENCR register ****************/ +#define RCC_APB2LPENCR_TIM1LPENC_Pos (0UL) +#define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENCR_TIM8LPENC_Pos (1UL) +#define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENCR_USART1LPENC_Pos (4UL) +#define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */ +#define RCC_APB2LPENCR_USART6LPENC_Pos (5UL) +#define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */ +#define RCC_APB2LPENCR_UART9LPENC_Pos (6UL) +#define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */ +#define RCC_APB2LPENCR_USART10LPENC_Pos (7UL) +#define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */ +#define RCC_APB2LPENCR_SPI1LPENC_Pos (12UL) +#define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENCR_SPI4LPENC_Pos (13UL) +#define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENCR_TIM18LPENC_Pos (15UL) +#define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENCR_TIM15LPENC_Pos (16UL) +#define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENCR_TIM16LPENC_Pos (17UL) +#define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENCR_TIM17LPENC_Pos (18UL) +#define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENCR_TIM9LPENC_Pos (19UL) +#define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENCR_SPI5LPENC_Pos (20UL) +#define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENCR_SAI1LPENC_Pos (21UL) +#define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENCR_SAI2LPENC_Pos (22UL) +#define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENCR register ****************/ +#define RCC_APB3LPENCR_DFTLPENC_Pos (2UL) +#define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENCR1 register ****************/ +#define RCC_APB4LPENCR1_HDPLPENC_Pos (2UL) +#define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */ +#define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3UL) +#define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENCR1_SPI6LPENC_Pos (5UL) +#define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENCR1_I2C4LPENC_Pos (7UL) +#define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9UL) +#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10UL) +#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11UL) +#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12UL) +#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15UL) +#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENCR1_RTCLPENC_Pos (16UL) +#define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */ +#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17UL) +#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENCR2 register ****************/ +#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0UL) +#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENCR2_BSECLPENC_Pos (1UL) +#define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */ +#define RCC_APB4LPENCR2_DTSLPENC_Pos (2UL) +#define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENCR register ****************/ +#define RCC_APB5LPENCR_LTDCLPENC_Pos (1UL) +#define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */ +#define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2UL) +#define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */ +#define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4UL) +#define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */ +#define RCC_APB5LPENCR_VENCLPENC_Pos (5UL) +#define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */ +#define RCC_APB5LPENCR_CSILPENC_Pos (6UL) +#define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */ + +/**************** Bit definition for RCC_PRIVCFGCR0 register ****************/ +#define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR0 register *****************/ +#define RCC_PUBCFGCR0_LSIPUBC_Pos (0UL) +#define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_LSEPUBC_Pos (1UL) +#define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_MSIPUBC_Pos (2UL) +#define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSIPUBC_Pos (3UL) +#define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSEPUBC_Pos (4UL) +#define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR1 register ****************/ +#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR1 register *****************/ +#define RCC_PUBCFGCR1_PLL1PUBC_Pos (0UL) +#define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL2PUBC_Pos (1UL) +#define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL3PUBC_Pos (2UL) +#define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL4PUBC_Pos (3UL) +#define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR2 register ****************/ +#define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13UL) +#define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14UL) +#define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15UL) +#define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16UL) +#define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17UL) +#define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18UL) +#define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19UL) +#define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR2 register *****************/ +#define RCC_PUBCFGCR2_IC1PUBC_Pos (0UL) +#define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC2PUBC_Pos (1UL) +#define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC3PUBC_Pos (2UL) +#define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC4PUBC_Pos (3UL) +#define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC5PUBC_Pos (4UL) +#define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC6PUBC_Pos (5UL) +#define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC7PUBC_Pos (6UL) +#define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC8PUBC_Pos (7UL) +#define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC9PUBC_Pos (8UL) +#define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC10PUBC_Pos (9UL) +#define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC11PUBC_Pos (10UL) +#define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC12PUBC_Pos (11UL) +#define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC13PUBC_Pos (12UL) +#define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC14PUBC_Pos (13UL) +#define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC15PUBC_Pos (14UL) +#define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC16PUBC_Pos (15UL) +#define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC17PUBC_Pos (16UL) +#define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC18PUBC_Pos (17UL) +#define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC19PUBC_Pos (18UL) +#define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC20PUBC_Pos (19UL) +#define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR3 register ****************/ +#define RCC_PRIVCFGCR3_MODPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_PERPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_INTPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5UL) +#define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR3 register *****************/ +#define RCC_PUBCFGCR3_MODPUBC_Pos (0UL) +#define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_SYSPUBC_Pos (1UL) +#define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_BUSPUBC_Pos (2UL) +#define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_PERPUBC_Pos (3UL) +#define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_INTPUBC_Pos (4UL) +#define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_RSTPUBC_Pos (5UL) +#define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR4 register ****************/ +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13UL) +#define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR4 register *****************/ +#define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0UL) +#define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1UL) +#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHBMPUBC_Pos (2UL) +#define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB1PUBC_Pos (3UL) +#define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB2PUBC_Pos (4UL) +#define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB3PUBC_Pos (5UL) +#define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB4PUBC_Pos (6UL) +#define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB5PUBC_Pos (7UL) +#define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB1PUBC_Pos (8UL) +#define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB2PUBC_Pos (9UL) +#define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB3PUBC_Pos (10UL) +#define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB4PUBC_Pos (11UL) +#define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB5PUBC_Pos (12UL) +#define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_NOCPUBC_Pos (13UL) +#define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR5 register *****************/ +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0UL) +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1UL) +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2UL) +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3UL) +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4UL) +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5UL) +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6UL) +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7UL) +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8UL) +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9UL) +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11UL) +#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + + +/******************************************************************************/ +/* */ +/* Resource Isolation Framework Security Controller (RIFSC) */ +/* */ +/******************************************************************************/ +/**************** Bit definition for RIFSC_RISC_CR register *****************/ +#define RIFSC_RISC_CR_GLOCK_Pos (0UL) +#define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */ + +/************* Bit definition for RIFSC_RISC_SECCFGRx register **************/ +#define RIFSC_RISC_SECCFGRx_SEC0_Pos (0UL) +#define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */ +#define RIFSC_RISC_SECCFGRx_SEC1_Pos (1UL) +#define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */ +#define RIFSC_RISC_SECCFGRx_SEC2_Pos (2UL) +#define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */ +#define RIFSC_RISC_SECCFGRx_SEC3_Pos (3UL) +#define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */ +#define RIFSC_RISC_SECCFGRx_SEC4_Pos (4UL) +#define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */ +#define RIFSC_RISC_SECCFGRx_SEC5_Pos (5UL) +#define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */ +#define RIFSC_RISC_SECCFGRx_SEC6_Pos (6UL) +#define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */ +#define RIFSC_RISC_SECCFGRx_SEC7_Pos (7UL) +#define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */ +#define RIFSC_RISC_SECCFGRx_SEC8_Pos (8UL) +#define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */ +#define RIFSC_RISC_SECCFGRx_SEC9_Pos (9UL) +#define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */ +#define RIFSC_RISC_SECCFGRx_SEC10_Pos (10UL) +#define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */ +#define RIFSC_RISC_SECCFGRx_SEC11_Pos (11UL) +#define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */ +#define RIFSC_RISC_SECCFGRx_SEC12_Pos (12UL) +#define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */ +#define RIFSC_RISC_SECCFGRx_SEC13_Pos (13UL) +#define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */ +#define RIFSC_RISC_SECCFGRx_SEC14_Pos (14UL) +#define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */ +#define RIFSC_RISC_SECCFGRx_SEC15_Pos (15UL) +#define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */ +#define RIFSC_RISC_SECCFGRx_SEC16_Pos (16UL) +#define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */ +#define RIFSC_RISC_SECCFGRx_SEC17_Pos (17UL) +#define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */ +#define RIFSC_RISC_SECCFGRx_SEC18_Pos (18UL) +#define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */ +#define RIFSC_RISC_SECCFGRx_SEC19_Pos (19UL) +#define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */ +#define RIFSC_RISC_SECCFGRx_SEC20_Pos (20UL) +#define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */ +#define RIFSC_RISC_SECCFGRx_SEC21_Pos (21UL) +#define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */ +#define RIFSC_RISC_SECCFGRx_SEC22_Pos (22UL) +#define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */ +#define RIFSC_RISC_SECCFGRx_SEC23_Pos (23UL) +#define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */ +#define RIFSC_RISC_SECCFGRx_SEC24_Pos (24UL) +#define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */ +#define RIFSC_RISC_SECCFGRx_SEC25_Pos (25UL) +#define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */ +#define RIFSC_RISC_SECCFGRx_SEC26_Pos (26UL) +#define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */ +#define RIFSC_RISC_SECCFGRx_SEC27_Pos (27UL) +#define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */ +#define RIFSC_RISC_SECCFGRx_SEC28_Pos (28UL) +#define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */ +#define RIFSC_RISC_SECCFGRx_SEC29_Pos (29UL) +#define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */ +#define RIFSC_RISC_SECCFGRx_SEC30_Pos (30UL) +#define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */ +#define RIFSC_RISC_SECCFGRx_SEC31_Pos (31UL) +#define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/ +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */ + +/**************** Bit definition for RIFSC_RIMC_CR register *****************/ +#define RIFSC_RIMC_CR_GLOCK_Pos (0UL) +#define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */ +#define RIFSC_RIMC_CR_DAPCID_Pos (8UL) +#define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */ +#define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */ +#define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */ + +/*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/ +#define RIFSC_RIMC_ATTRx_MCID_Pos (4UL) +#define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */ +#define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */ +#define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */ +#define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */ +#define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */ +#define RIFSC_RIMC_ATTRx_MSEC_Pos (8UL) +#define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */ +#define RIFSC_RIMC_ATTRx_MPRIV_Pos (9UL) +#define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */ + +/******************************************************************************/ +/* */ +/* Resource Isolation Slave unit for Address space protection (RISAF) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RISAF_CR register *******************/ +#define RISAF_CR_GLOCK_Pos (0UL) +#define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */ + +/****************** Bit definition for RISAF_IASR register ******************/ +#define RISAF_IASR_CAEF_Pos (0UL) +#define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IASR_IAEF_Pos (1UL) +#define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */ + +/****************** Bit definition for RISAF_IACR register ******************/ +#define RISAF_IACR_CAEF_Pos (0UL) +#define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IACR_IAEF_Pos (1UL) +#define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */ + +/***************** Bit definition for RISAF_IAESR register *****************/ +#define RISAF_IAESR_IACID_Pos (0UL) +#define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */ +#define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */ +#define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */ +#define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */ +#define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */ +#define RISAF_IAESR_IAPRIV_Pos (4UL) +#define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */ +#define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */ +#define RISAF_IAESR_IASEC_Pos (5UL) +#define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */ +#define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */ +#define RISAF_IAESR_IANRW_Pos (7UL) +#define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */ +#define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */ + +/***************** Bit definition for RISAF_IADDR register *****************/ +#define RISAF_IADDR_IADD_Pos (0UL) +#define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */ +#define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */ +#define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */ +#define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */ +#define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */ +#define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */ +#define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */ +#define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */ +#define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */ +#define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */ +#define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */ +#define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */ +#define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */ +#define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */ +#define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */ +#define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */ +#define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */ +#define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */ +#define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */ +#define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */ +#define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */ +#define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */ +#define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */ +#define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */ +#define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */ +#define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */ +#define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */ +#define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */ +#define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */ +#define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */ +#define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */ +#define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */ +#define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_CFGR register ****************/ +#define RISAF_REGx_CFGR_BREN_Pos (0UL) +#define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */ +#define RISAF_REGx_CFGR_SEC_Pos (8UL) +#define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */ +#define RISAF_REGx_CFGR_PRIVC0_Pos (16UL) +#define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */ +#define RISAF_REGx_CFGR_PRIVC1_Pos (17UL) +#define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */ +#define RISAF_REGx_CFGR_PRIVC2_Pos (18UL) +#define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */ +#define RISAF_REGx_CFGR_PRIVC3_Pos (19UL) +#define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */ +#define RISAF_REGx_CFGR_PRIVC4_Pos (20UL) +#define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */ +#define RISAF_REGx_CFGR_PRIVC5_Pos (21UL) +#define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */ +#define RISAF_REGx_CFGR_PRIVC6_Pos (22UL) +#define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */ +#define RISAF_REGx_CFGR_PRIVC7_Pos (23UL) +#define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */ + +/************** Bit definition for RISAF_REGx_STARTR register ***************/ +#define RISAF_REGx_STARTR_BADDSTART_Pos (0UL) +#define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */ +#define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_ENDR register ****************/ +#define RISAF_REGx_ENDR_BADDEND_Pos (0UL) +#define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */ +#define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_CIDCFGR register **************/ +#define RISAF_REGx_CIDCFGR_RDENC0_Pos (0UL) +#define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_RDENC1_Pos (1UL) +#define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_RDENC2_Pos (2UL) +#define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_RDENC3_Pos (3UL) +#define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_RDENC4_Pos (4UL) +#define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_RDENC5_Pos (5UL) +#define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_RDENC6_Pos (6UL) +#define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_RDENC7_Pos (7UL) +#define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */ +#define RISAF_REGx_CIDCFGR_WRENC0_Pos (16UL) +#define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_WRENC1_Pos (17UL) +#define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_WRENC2_Pos (18UL) +#define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_WRENC3_Pos (19UL) +#define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_WRENC4_Pos (20UL) +#define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_WRENC5_Pos (21UL) +#define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_WRENC6_Pos (22UL) +#define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_WRENC7_Pos (23UL) +#define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */ + +/*************** Bit definition for RISAF_REGx_zCFGR register ***************/ +#define RISAF_REGx_zCFGR_SREN_Pos (0UL) +#define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */ +#define RISAF_REGx_zCFGR_RLOCK_Pos (1UL) +#define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */ +#define RISAF_REGx_zCFGR_SRCID_Pos (4UL) +#define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */ +#define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zCFGR_SEC_Pos (8UL) +#define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */ +#define RISAF_REGx_zCFGR_PRIV_Pos (9UL) +#define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */ +#define RISAF_REGx_zCFGR_RDEN_Pos (12UL) +#define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */ +#define RISAF_REGx_zCFGR_WREN_Pos (13UL) +#define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */ + +/************** Bit definition for RISAF_REGx_zSTARTR register **************/ +#define RISAF_REGx_zSTARTR_SADDSTART_Pos (0UL) +#define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */ +#define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_zENDR register ***************/ +#define RISAF_REGx_zENDR_SADDEND_Pos (0UL) +#define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */ +#define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_zNESTR register ***************/ +#define RISAF_REGx_zNESTR_DCEN_Pos (2UL) +#define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */ +#define RISAF_REGx_zNESTR_DCCID_Pos (4UL) +#define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */ +#define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */ + +/******************************************************************************/ +/* */ +/* (IAC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IAC_IER0 register *******************/ +#define IAC_IERx_IAIE0_Pos (0UL) +#define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */ +#define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_IERx_IAIE1_Pos (1UL) +#define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */ +#define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_IERx_IAIE2_Pos (2UL) +#define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */ +#define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_IERx_IAIE3_Pos (3UL) +#define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */ +#define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_IERx_IAIE4_Pos (4UL) +#define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */ +#define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_IERx_IAIE5_Pos (5UL) +#define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */ +#define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_IERx_IAIE6_Pos (6UL) +#define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */ +#define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_IERx_IAIE7_Pos (7UL) +#define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */ +#define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_IERx_IAIE8_Pos (8UL) +#define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */ +#define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_IERx_IAIE9_Pos (9UL) +#define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */ +#define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_IERx_IAIE10_Pos (10UL) +#define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */ +#define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_IERx_IAIE11_Pos (11UL) +#define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */ +#define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_IERx_IAIE12_Pos (12UL) +#define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */ +#define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_IERx_IAIE13_Pos (13UL) +#define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */ +#define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_IERx_IAIE14_Pos (14UL) +#define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */ +#define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_IERx_IAIE15_Pos (15UL) +#define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */ +#define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_IERx_IAIE16_Pos (16UL) +#define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */ +#define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_IERx_IAIE17_Pos (17UL) +#define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */ +#define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_IERx_IAIE18_Pos (18UL) +#define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */ +#define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_IERx_IAIE19_Pos (19UL) +#define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */ +#define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_IERx_IAIE20_Pos (20UL) +#define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */ +#define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_IERx_IAIE21_Pos (21UL) +#define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */ +#define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_IERx_IAIE22_Pos (22UL) +#define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */ +#define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_IERx_IAIE23_Pos (23UL) +#define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */ +#define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_IERx_IAIE24_Pos (24UL) +#define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */ +#define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_IERx_IAIE25_Pos (25UL) +#define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */ +#define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_IERx_IAIE26_Pos (26UL) +#define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */ +#define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_IERx_IAIE27_Pos (27UL) +#define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */ +#define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_IERx_IAIE28_Pos (28UL) +#define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */ +#define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_IERx_IAIE29_Pos (29UL) +#define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */ +#define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_IERx_IAIE30_Pos (30UL) +#define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */ +#define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_IERx_IAIE31_Pos (31UL) +#define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */ +#define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ISRx register *******************/ +#define IAC_ISRx_IAF0_Pos (0UL) +#define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_ISRx_IAF1_Pos (1UL) +#define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_ISRx_IAF2_Pos (2UL) +#define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_ISRx_IAF3_Pos (3UL) +#define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_ISRx_IAF4_Pos (4UL) +#define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_ISRx_IAF5_Pos (5UL) +#define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_ISRx_IAF6_Pos (6UL) +#define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_ISRx_IAF7_Pos (7UL) +#define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_ISRx_IAF8_Pos (8UL) +#define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_ISRx_IAF9_Pos (9UL) +#define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_ISRx_IAF10_Pos (10UL) +#define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_ISRx_IAF11_Pos (11UL) +#define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_ISRx_IAF12_Pos (12UL) +#define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_ISRx_IAF13_Pos (13UL) +#define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_ISRx_IAF14_Pos (14UL) +#define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_ISRx_IAF15_Pos (15UL) +#define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_ISRx_IAF16_Pos (16UL) +#define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_ISRx_IAF17_Pos (17UL) +#define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_ISRx_IAF18_Pos (18UL) +#define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_ISRx_IAF19_Pos (19UL) +#define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_ISRx_IAF20_Pos (20UL) +#define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_ISRx_IAF21_Pos (21UL) +#define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_ISRx_IAF22_Pos (22UL) +#define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_ISRx_IAF23_Pos (23UL) +#define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_ISRx_IAF24_Pos (24UL) +#define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_ISRx_IAF25_Pos (25UL) +#define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_ISRx_IAF26_Pos (26UL) +#define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_ISRx_IAF27_Pos (27UL) +#define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_ISRx_IAF28_Pos (28UL) +#define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_ISRx_IAF29_Pos (29UL) +#define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_ISRx_IAF30_Pos (30UL) +#define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_ISRx_IAF31_Pos (31UL) +#define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ICRx register *******************/ +#define IAC_ICRx_IAF0_Pos (0UL) +#define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */ +#define IAC_ICRx_IAF1_Pos (1UL) +#define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */ +#define IAC_ICRx_IAF2_Pos (2UL) +#define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */ +#define IAC_ICRx_IAF3_Pos (3UL) +#define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */ +#define IAC_ICRx_IAF4_Pos (4UL) +#define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */ +#define IAC_ICRx_IAF5_Pos (5UL) +#define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */ +#define IAC_ICRx_IAF6_Pos (6UL) +#define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */ +#define IAC_ICRx_IAF7_Pos (7UL) +#define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */ +#define IAC_ICRx_IAF8_Pos (8UL) +#define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */ +#define IAC_ICRx_IAF9_Pos (9UL) +#define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */ +#define IAC_ICRx_IAF10_Pos (10UL) +#define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */ +#define IAC_ICRx_IAF11_Pos (11UL) +#define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */ +#define IAC_ICRx_IAF12_Pos (12UL) +#define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */ +#define IAC_ICRx_IAF13_Pos (13UL) +#define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */ +#define IAC_ICRx_IAF14_Pos (14UL) +#define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */ +#define IAC_ICRx_IAF15_Pos (15UL) +#define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */ +#define IAC_ICRx_IAF16_Pos (16UL) +#define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */ +#define IAC_ICRx_IAF17_Pos (17UL) +#define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */ +#define IAC_ICRx_IAF18_Pos (18UL) +#define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */ +#define IAC_ICRx_IAF19_Pos (19UL) +#define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */ +#define IAC_ICRx_IAF20_Pos (20UL) +#define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */ +#define IAC_ICRx_IAF21_Pos (21UL) +#define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */ +#define IAC_ICRx_IAF22_Pos (22UL) +#define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */ +#define IAC_ICRx_IAF23_Pos (23UL) +#define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */ +#define IAC_ICRx_IAF24_Pos (24UL) +#define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */ +#define IAC_ICRx_IAF25_Pos (25UL) +#define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */ +#define IAC_ICRx_IAF26_Pos (26UL) +#define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */ +#define IAC_ICRx_IAF27_Pos (27UL) +#define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */ +#define IAC_ICRx_IAF28_Pos (28UL) +#define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */ +#define IAC_ICRx_IAF29_Pos (29UL) +#define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */ +#define IAC_ICRx_IAF30_Pos (30UL) +#define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */ +#define IAC_ICRx_IAF31_Pos (31UL) +#define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */ + +/****************** Bit definition for IAC_IISRx register *******************/ +#define IAC_IISRx_ILACIN0_Pos (0UL) +#define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */ +#define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN1_Pos (1UL) +#define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */ +#define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN2_Pos (2UL) +#define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */ +#define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN3_Pos (3UL) +#define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */ +#define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN4_Pos (4UL) +#define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */ +#define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN5_Pos (5UL) +#define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */ +#define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN6_Pos (6UL) +#define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */ +#define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN7_Pos (7UL) +#define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */ +#define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN8_Pos (8UL) +#define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */ +#define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN9_Pos (9UL) +#define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */ +#define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN10_Pos (10UL) +#define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */ +#define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN11_Pos (11UL) +#define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */ +#define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN12_Pos (12UL) +#define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */ +#define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN13_Pos (13UL) +#define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */ +#define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN14_Pos (14UL) +#define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */ +#define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN15_Pos (15UL) +#define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */ +#define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN16_Pos (16UL) +#define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */ +#define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN17_Pos (17UL) +#define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */ +#define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN18_Pos (18UL) +#define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */ +#define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN19_Pos (19UL) +#define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */ +#define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN20_Pos (20UL) +#define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */ +#define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN21_Pos (21UL) +#define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */ +#define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN22_Pos (22UL) +#define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */ +#define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN23_Pos (23UL) +#define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */ +#define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN24_Pos (24UL) +#define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */ +#define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN25_Pos (25UL) +#define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */ +#define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN26_Pos (26UL) +#define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */ +#define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN27_Pos (27UL) +#define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */ +#define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN28_Pos (28UL) +#define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */ +#define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN29_Pos (29UL) +#define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */ +#define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN30_Pos (30UL) +#define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */ +#define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN31_Pos (31UL) +#define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */ +#define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0UL) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4UL) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8UL) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12UL) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16UL) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20UL) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22UL) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0UL) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4UL) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8UL) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12UL) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13UL) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16UL) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20UL) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0UL) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2UL) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3UL) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4UL) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5UL) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6UL) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7UL) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8UL) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10UL) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16UL) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0UL) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16UL) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0UL) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16UL) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0UL) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3UL) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4UL) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5UL) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6UL) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7UL) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8UL) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9UL) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10UL) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11UL) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12UL) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13UL) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14UL) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15UL) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16UL) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17UL) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18UL) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19UL) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20UL) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21UL) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23UL) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24UL) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0UL) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1UL) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3UL) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5UL) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x1UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020*/ +#define SAES_CR_CHMOD_1 (0x2UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11UL) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12UL) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13UL) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x0006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM or CCM phase selection */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00020000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE_Pos (18UL) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_KEYPROT_Pos (19UL) +#define SAES_CR_KEYPROT_Msk (0x1UL << SAES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define SAES_CR_KEYPROT SAES_CR_KEYPROT_Msk /*!< Key protection */ +#define SAES_CR_NPBLB_Pos (20UL) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24UL) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26UL) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KSHAREID_0 (0x1UL << SAES_CR_KSHAREID_Pos) /*!< 0x04000000 */ +#define SAES_CR_KSHAREID_1 (0x2UL << SAES_CR_KSHAREID_Pos) /*!< 0x08000000 */ +#define SAES_CR_KEYSEL_Pos (28UL) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define SAES_CR_IPRST_Pos (31UL) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0UL) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1UL) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2UL) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3UL) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7UL) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< Key valid Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0UL) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0UL) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0UL) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES cryptographic key, bits [31:0] */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0UL) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES cryptographic key, bits [63:32] */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0UL) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES cryptographic key, bits [95:64] */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0UL) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0UL) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0UL) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0UL) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0UL) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0UL) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES initialization vector input, bits [31:0] */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0UL) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES initialization vector input, bits [63:32] */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0UL) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES initialization vector input, bits [95:64] */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0UL) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES initialization vector input, bits [127:96] */ + +/******************* Bits definition for SAES_DPACFGR register ******************/ +#define SAES_DPACFGR_REDCFG_Pos (0UL) +#define SAES_DPACFGR_REDCFG_Msk (0x3UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000003 */ +#define SAES_DPACFGR_REDCFG SAES_DPACFGR_REDCFG_Msk /*!< Redundancy configuration*/ +#define SAES_DPACFGR_REDCFG_0 (0x1UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000001 */ +#define SAES_DPACFGR_REDCFG_1 (0x2UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000002 */ +#define SAES_DPACFGR_RESEED_Pos (2UL) +#define SAES_DPACFGR_RESEED_Msk (0x1UL << SAES_DPACFGR_RESEED_Pos) /*!< 0x00000004 */ +#define SAES_DPACFGR_RESEED SAES_DPACFGR_RESEED_Msk /*!< Automatic reseed enable */ +#define SAES_DPACFGR_TRIMCFG_Pos (3UL) +#define SAES_DPACFGR_TRIMCFG_Msk (0x3UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000018 */ +#define SAES_DPACFGR_TRIMCFG SAES_DPACFGR_TRIMCFG_Msk /*!< Clock trimming */ +#define SAES_DPACFGR_TRIMCFG_0 (0x1UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000008 */ +#define SAES_DPACFGR_TRIMCFG_1 (0x2UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000010 */ +#define SAES_DPACFGR_CONFIGLOCK_Pos (31UL) +#define SAES_DPACFGR_CONFIGLOCK_Msk (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define SAES_DPACFGR_CONFIGLOCK SAES_DPACFGR_CONFIGLOCK_Msk /*!< DPA configuration lock */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0UL) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1UL) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2UL) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3UL) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< RNG error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0UL) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1UL) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2UL) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3UL) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< RNG error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0UL) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1UL) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2UL) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3UL) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< RNG error interrupt flag clear */ + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0UL) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief RAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */ + __IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */ + __IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */ + __IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */ + uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */ + __IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */ + __IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */ + __IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */ + __IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */ + __IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */ + __IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */ + __IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */ + __IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */ + __IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */ + __IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */ + __IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */ + __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */ + __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */ + __IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */ + __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */ + __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */ + __IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */ + __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */ + __IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */ + __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */ + __IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */ + __IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */ + __IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */ + __IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */ + __IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */ + __IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */ + __IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */ + __IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */ + __IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */ + __IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */ + __IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */ + __IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */ + __IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */ + __IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */ + __IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */ + __IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */ + __IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */ + __IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */ + __IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */ + __IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */ + __IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */ + uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */ + __IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */ + __IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */ + __IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */ + __IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */ + __IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */ + __IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */ + __IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */ + __IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */ + __IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */ + __IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */ + __IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */ + __IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */ + uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */ + __IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */ + __IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */ + __IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */ + uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */ + __IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */ + __IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */ + __IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */ + __IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */ + __IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */ + __IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */ + __IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */ + __IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */ + __IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */ + __IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */ + __IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */ + __IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */ + __IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */ + __IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */ + __IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */ + __IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */ + uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */ + __IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */ + uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */ + __IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */ + __IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */ + __IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */ + __IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */ + __IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */ + __IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */ + __IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */ + __IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */ + __IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */ + __IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */ + __IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */ + __IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */ + __IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */ + __IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */ + __IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */ + __IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */ + __IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */ + __IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */ + __IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */ + __IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */ + __IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */ + uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */ + __IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */ + __IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */ + uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */ + __IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */ + __IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */ + __IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */ + __IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */ + __IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */ + __IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */ + __IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */ + __IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */ + __IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */ + __IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */ + __IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */ + __IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */ + __IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */ + __IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */ + __IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */ + __IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */ + __IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */ + __IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */ + __IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */ + __IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */ + __IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */ + __IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */ + __IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */ + __IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */ + __IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */ + __IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */ + __IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */ + __IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */ + __IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */ + __IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */ + __IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */ + __IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */ + __IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */ + __IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */ + __IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */ + __IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */ + __IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */ + __IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */ + __IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */ + __IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */ + __IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */ + __IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */ + __IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */ + __IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */ + uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */ + __IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */ + __IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */ + __IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */ + uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */ + __IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */ + __IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */ + uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */ + __IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */ + __IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */ + uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */ + __IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */ + uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */ + __IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */ + __IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */ + __IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */ + uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */ + __IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */ + uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */ + __IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */ + uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */ + __IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */ + __IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */ + __IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */ + __IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */ + __IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */ + __IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */ + __IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */ + __IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */ + __IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */ + __IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */ + __IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */ + __IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */ + __IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */ + __IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */ + __IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */ + __IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */ + __IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */ + __IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */ + __IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */ + __IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */ + __IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */ + __IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */ + __IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */ + __IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */ + __IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */ + __IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */ + __IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */ + __IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */ + __IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */ + __IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */ + __IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */ + __IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */ + __IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */ + __IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */ + __IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */ + __IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */ + __IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */ + __IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */ + __IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */ + __IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */ + __IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */ + __IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */ + __IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */ + __IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */ + uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */ + __IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */ + uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */ + __IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */ + __IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */ + __IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */ + __IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */ + __IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */ + __IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */ + __IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */ + __IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */ + __IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */ + __IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */ +} RCC_TypeDef; + +/* + * @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1) + */ +typedef struct +{ + __IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */ + __IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */ + __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */ + uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */ + __IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */ + __IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */ + uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */ + __IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */ + uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */ +} RIFSC_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) + */ +typedef struct +{ + __IO uint32_t CFGR; /*!< RISAF Region X configuration register */ + __IO uint32_t STARTR; /*!< RISAF Region X start address register */ + __IO uint32_t ENDR; /*!< RISAF Region X end address register */ + __IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */ + __IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */ + __IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */ + __IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */ + __IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */ + __IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */ + __IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */ + __IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */ + __IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */ + uint32_t RESERVED0[4]; /*!< Reserved */ +} RISAF_Region_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t IAESR; /*!< RISAF Illegal access error status register */ + __IO uint32_t IADDR; /*!< RISAF Illegal address register, */ +} RISAF_Illegal_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */ + RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */ + RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */ +} RISAF_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 7U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ +__IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x004 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x008 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x00C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x010 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x014 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x018 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x01C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x020 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x024 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x028 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x02C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x030 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x034 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x038 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x03C */ + uint32_t RESERVED1[48]; /*!< Reserved, Address offset: 0x040 -- 0x0FC */ + __IO uint32_t DPACFGR; /*!< SAES DPA configuration register, Address offset: 0x100 */ + uint32_t RESERVED2[127]; /*!< Reserved, Address offset: 0x104 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + __IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */ +} USB_PHY_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + __IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + __IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + __IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + __IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + __IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */ +} USB_HS_PHYC_GlobalTypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */ + __IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */ + __IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */ + __IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */ + __IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */ + __IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */ + __IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */ + __IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */ + __IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */ + __IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */ + __IO uint32_t NPUNICQOSCR; /*!< SYSCFG NPUNIC QoS control register, Address offset: 0x28 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2C-0x30 */ + __IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */ + __IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */ + __IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x44 */ + __IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x48 */ + __IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x4C */ + __IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x50 */ + __IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x54 */ + __IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x58 */ + __IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x5C */ + __IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x60 */ + __IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */ + __IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */ + __IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */ + __IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */ + __IO uint32_t NPU_ICNCR; /*!< SYSCFG NPU RAM interleaving control register, Address offset: 0x78 */ + uint32_t RESERVED3[33]; /*!< Reserved, Address offset: 0x7C-0xFC */ + __IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */ + __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */ + uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */ + __IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */ + uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */ + __IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Extended-SPI Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** @} */ /* End of group STM32N6xx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal RAMs sizes */ +#define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */ +#define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */ +#define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */ +#define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */ +#define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */ +#define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */ +#define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */ +#define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */ +#define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */ +#define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */ +#define CACHEAXI_RAM_SIZE 0x40000UL /*!< CACHEAXI RAM = 256 Kbytes */ +#define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */ + + +#define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */ +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK5_1 FMC_BANK5 +#define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL) +#define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL) +#define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL) +#define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK6_1 FMC_BANK6 +#define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL) +#define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL) +#define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL) +#define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */ +#define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */ +#define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */ + +/**************************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */ +/* */ +/**************************************************************************/ + +#define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define CACHEAXI_RAM_BASE_NS 0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ +#define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL) +#define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL) +#define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL) +#define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL) +#define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL) +#define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL) +#define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL) +#define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL) +#define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL) +#define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL) +#define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) +#define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL) +#define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL) +#define CRYP_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define SAES_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL) +#define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL) +#define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL) +#define RISAF4_BASE_NS (AHB3PERIPH_BASE_NS + 0x9000UL) +#define RISAF5_BASE_NS (AHB3PERIPH_BASE_NS + 0xA000UL) +#define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL) +#define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL) +#define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL) +#define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL) +#define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL) +#define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL) +#define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL) +#define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL) +#define RISAF15_BASE_NS (AHB3PERIPH_BASE_NS + 0x014000UL) +#define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL) +#define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL) +#define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL) +#define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL) +#define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL) +#define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL) +#define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL) +#define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL) +#define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL) +#define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL) +#define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL) +#define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL) +#define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL) +#define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL) +#define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL) +#define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL) +#define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL) +#define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL) +#define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL) +#define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL) +#define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL) +#define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL) +#define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL) +#define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL) +#define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL) +#define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL) +#define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL) +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL) +#define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL) +#define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL) +#define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL) +#define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL) +#define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL) +#define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL) +#define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL) +#define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL) +#define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL) +#define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL) +#define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL) +#define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL) +#define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL) +#define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL) +#define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL) +#define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL) +#define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL) +#define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL) +#define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL) +#define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL) +#define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL) +#define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL) +#define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL) +#define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL) +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) +#define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL) +#define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL) +#define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL) +#define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL) +#define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL) +#define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL) +#define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL) +#define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL) +#define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL) +#define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL) +#define MCE1_BASE_NS (AHB5PERIPH_BASE_NS + 0xB800UL) +#define MCE1_REGION1_BASE_NS (MCE1_BASE_NS + 0x040UL) +#define MCE1_REGION2_BASE_NS (MCE1_BASE_NS + 0x050UL) +#define MCE1_REGION3_BASE_NS (MCE1_BASE_NS + 0x060UL) +#define MCE1_REGION4_BASE_NS (MCE1_BASE_NS + 0x070UL) +#define MCE1_CONTEXT1_BASE_NS (MCE1_BASE_NS + 0x240UL) +#define MCE1_CONTEXT2_BASE_NS (MCE1_BASE_NS + 0x270UL) +#define MCE2_BASE_NS (AHB5PERIPH_BASE_NS + 0xBC00UL) +#define MCE2_REGION1_BASE_NS (MCE2_BASE_NS + 0x040UL) +#define MCE2_REGION2_BASE_NS (MCE2_BASE_NS + 0x050UL) +#define MCE2_REGION3_BASE_NS (MCE2_BASE_NS + 0x060UL) +#define MCE2_REGION4_BASE_NS (MCE2_BASE_NS + 0x070UL) +#define MCE2_CONTEXT1_BASE_NS (MCE2_BASE_NS + 0x240UL) +#define MCE2_CONTEXT2_BASE_NS (MCE2_BASE_NS + 0x270UL) +#define MCE3_BASE_NS (AHB5PERIPH_BASE_NS + 0xC000UL) +#define MCE3_REGION1_BASE_NS (MCE3_BASE_NS + 0x040UL) +#define MCE3_REGION2_BASE_NS (MCE3_BASE_NS + 0x050UL) +#define MCE3_REGION3_BASE_NS (MCE3_BASE_NS + 0x060UL) +#define MCE3_REGION4_BASE_NS (MCE3_BASE_NS + 0x070UL) +#define MCE3_CONTEXT1_BASE_NS (MCE3_BASE_NS + 0x240UL) +#define MCE3_CONTEXT2_BASE_NS (MCE3_BASE_NS + 0x270UL) +#define MCE4_BASE_NS (AHB5PERIPH_BASE_NS + 0xE000UL) +#define MCE4_REGION1_BASE_NS (MCE4_BASE_NS + 0x040UL) +#define MCE4_REGION2_BASE_NS (MCE4_BASE_NS + 0x050UL) +#define MCE4_REGION3_BASE_NS (MCE4_BASE_NS + 0x060UL) +#define MCE4_REGION4_BASE_NS (MCE4_BASE_NS + 0x070UL) +#define MCE4_CONTEXT1_BASE_NS (MCE4_BASE_NS + 0x240UL) +#define MCE4_CONTEXT2_BASE_NS (MCE4_BASE_NS + 0x270UL) +#define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL) +#define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL) +#define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL) +#define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL) +#define ETH1_MAC_BASE_NS (ETH1_BASE_NS) +#define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL) +#define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL) +#define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL) +#define CACHEAXI_BASE_NS (AHB5PERIPH_BASE_NS + 0x0BFC00UL) +#define NPU_BASE_NS (AHB5PERIPH_BASE_NS + 0x0C0000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_NS (0x46009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_NS (BOOTROM_BASE_NS + 0x001004UL) + + +#if defined (CPU_IN_SECURE_STATE) +/*********************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */ +/* */ +/*********************************************************************/ +#define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define CACHEAXI_RAM_BASE_S 0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ +#define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL) +#define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL) +#define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL) +#define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL) +#define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL) +#define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL) +#define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL) +#define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL) +#define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL) +#define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL) +#define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) +#define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL) +#define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL) +#define CRYP_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define SAES_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL) +#define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL) +#define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL) +#define RISAF4_BASE_S (AHB3PERIPH_BASE_S + 0x9000UL) +#define RISAF5_BASE_S (AHB3PERIPH_BASE_S + 0xA000UL) +#define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL) +#define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL) +#define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL) +#define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL) +#define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL) +#define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL) +#define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL) +#define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL) +#define RISAF15_BASE_S (AHB3PERIPH_BASE_S + 0x014000UL) +#define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL) +#define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL) +#define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL) +#define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL) +#define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL) +#define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL) +#define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL) +#define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL) +#define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL) +#define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL) +#define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL) +#define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL) +#define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL) +#define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL) + +#define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL) +#define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL) +#define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL) +#define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL) +#define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL) +#define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL) +#define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL) +#define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL) +#define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL) +#define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL) +#define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL) +#define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL) +#define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL) +#define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL) +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL) +#define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL) +#define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL) +#define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL) +#define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL) +#define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL) +#define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL) +#define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL) +#define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL) +#define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL) +#define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL) +#define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL) +#define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL) +#define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL) +#define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL) +#define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL) +#define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL) +#define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL) +#define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL) +#define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL) +#define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL) +#define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL) +#define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL) +#define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL) +#define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) +#define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL) +#define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL) +#define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL) +#define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL) +#define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL) +#define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL) +#define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL) +#define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL) +#define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL) +#define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL) +#define MCE1_BASE_S (AHB5PERIPH_BASE_S + 0xB800UL) +#define MCE1_REGION1_BASE_S (MCE1_BASE_S + 0x040UL) +#define MCE1_REGION2_BASE_S (MCE1_BASE_S + 0x050UL) +#define MCE1_REGION3_BASE_S (MCE1_BASE_S + 0x060UL) +#define MCE1_REGION4_BASE_S (MCE1_BASE_S + 0x070UL) +#define MCE1_CONTEXT1_BASE_S (MCE1_BASE_S + 0x240UL) +#define MCE1_CONTEXT2_BASE_S (MCE1_BASE_S + 0x270UL) +#define MCE2_BASE_S (AHB5PERIPH_BASE_S + 0xBC00UL) +#define MCE2_REGION1_BASE_S (MCE2_BASE_S + 0x040UL) +#define MCE2_REGION2_BASE_S (MCE2_BASE_S + 0x050UL) +#define MCE2_REGION3_BASE_S (MCE2_BASE_S + 0x060UL) +#define MCE2_REGION4_BASE_S (MCE2_BASE_S + 0x070UL) +#define MCE2_CONTEXT1_BASE_S (MCE2_BASE_S + 0x240UL) +#define MCE2_CONTEXT2_BASE_S (MCE2_BASE_S + 0x270UL) +#define MCE3_BASE_S (AHB5PERIPH_BASE_S + 0xC000UL) +#define MCE3_REGION1_BASE_S (MCE3_BASE_S + 0x040UL) +#define MCE3_REGION2_BASE_S (MCE3_BASE_S + 0x050UL) +#define MCE3_REGION3_BASE_S (MCE3_BASE_S + 0x060UL) +#define MCE3_REGION4_BASE_S (MCE3_BASE_S + 0x070UL) +#define MCE3_CONTEXT1_BASE_S (MCE3_BASE_S + 0x240UL) +#define MCE3_CONTEXT2_BASE_S (MCE3_BASE_S + 0x270UL) +#define MCE4_BASE_S (AHB5PERIPH_BASE_S + 0xE000UL) +#define MCE4_REGION1_BASE_S (MCE4_BASE_S + 0x040UL) +#define MCE4_REGION2_BASE_S (MCE4_BASE_S + 0x050UL) +#define MCE4_REGION3_BASE_S (MCE4_BASE_S + 0x060UL) +#define MCE4_REGION4_BASE_S (MCE4_BASE_S + 0x070UL) +#define MCE4_CONTEXT1_BASE_S (MCE4_BASE_S + 0x240UL) +#define MCE4_CONTEXT2_BASE_S (MCE4_BASE_S + 0x270UL) +#define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL) +#define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL) +#define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL) +#define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL) +#define ETH1_MAC_BASE_S (ETH1_BASE_S) +#define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL) +#define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL) +#define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL) +#define CACHEAXI_BASE_S (AHB5PERIPH_BASE_S + 0x0BFC00UL) +#define NPU_BASE_S (AHB5PERIPH_BASE_S + 0x0C0000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_S (0x56009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_S (BOOTROM_BASE_S + 0x001004UL) + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS) +#define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS) +#define CACHEAXI_NS ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CRYP_NS ((CRYP_TypeDef *) CRYP_BASE_NS) +#define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS) +#define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS) +#define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS) +#define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS) +#define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS) +#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS) +#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) +#define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS) +#define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS) +#define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS) +#define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS) +#define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS) +#define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS) +#define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS) +#define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS) +#define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS) +#define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS) +#define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS) +#define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS) +#define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS) +#define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS) +#define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS) +#define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS) +#define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS) +#define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS) +#define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS) +#define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS) +#define MCE1_NS ((MCE_TypeDef *) MCE1_BASE_NS) +#define MCE1_REGION1_NS ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS) +#define MCE1_REGION2_NS ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS) +#define MCE1_REGION3_NS ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS) +#define MCE1_REGION4_NS ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS) +#define MCE1_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS) +#define MCE1_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS) +#define MCE2_NS ((MCE_TypeDef *) MCE2_BASE_NS) +#define MCE2_REGION1_NS ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS) +#define MCE2_REGION2_NS ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS) +#define MCE2_REGION3_NS ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS) +#define MCE2_REGION4_NS ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS) +#define MCE2_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS) +#define MCE2_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS) +#define MCE3_NS ((MCE_TypeDef *) MCE3_BASE_NS) +#define MCE3_REGION1_NS ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS) +#define MCE3_REGION2_NS ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS) +#define MCE3_REGION3_NS ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS) +#define MCE3_REGION4_NS ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS) +#define MCE3_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS) +#define MCE3_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS) +#define MCE4_NS ((MCE_TypeDef *) MCE4_BASE_NS) +#define MCE4_REGION1_NS ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS) +#define MCE4_REGION2_NS ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS) +#define MCE4_REGION3_NS ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS) +#define MCE4_REGION4_NS ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS) +#define MCE4_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS) +#define MCE4_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS) +#define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS) +#define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS) +#define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS) +#define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS) +#define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS) +#define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS) +#define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS) +#define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS) +#define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS) +#define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS) +#define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS) +#define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS) +#define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS) +#define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS) +#define RISAF4_NS ((RISAF_TypeDef *) RISAF4_BASE_NS) +#define RISAF5_NS ((RISAF_TypeDef *) RISAF5_BASE_NS) +#define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS) +#define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS) +#define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS) +#define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS) +#define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS) +#define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS) +#define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS) +#define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS) +#define RISAF15_NS ((RISAF_TypeDef *) RISAF15_BASE_NS) +#define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS) +#define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS) +#define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((SAES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS) +#define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS) +#define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define UART7_NS ((USART_TypeDef *) UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *) UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *) UART9_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *) USART10_BASE_NS) +#define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS) +#define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS) +#define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS) +#define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS) +#define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS) +#define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS) +#define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS) +#define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S) +#define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S) +#define CACHEAXI_S ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CRYP_S ((CRYP_TypeDef *) CRYP_BASE_S) +#define CSI_S ((CSI_TypeDef *) CSI_BASE_S) +#define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define DTS_S ((DTS_TypeDef *) DTS_BASE_S) +#define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S) +#define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S) +#define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S) +#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S) +#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) +#define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPION_S ((GPIO_TypeDef *) GPION_BASE_S) +#define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S) +#define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S) +#define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S) +#define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S) +#define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S) +#define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S) +#define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S) +#define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S) +#define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S) +#define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S) +#define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S) +#define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S) +#define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S) +#define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S) +#define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S) +#define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S) +#define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S) +#define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S) +#define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define IAC_S ((IAC_TypeDef *) IAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S) +#define MCE1_S ((MCE_TypeDef *) MCE1_BASE_S) +#define MCE1_REGION1_S ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S) +#define MCE1_REGION2_S ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S) +#define MCE1_REGION3_S ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S) +#define MCE1_REGION4_S ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S) +#define MCE1_CONTEXT1_S ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S) +#define MCE1_CONTEXT2_S ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S) +#define MCE2_S ((MCE_TypeDef *) MCE2_BASE_S) +#define MCE2_REGION1_S ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S) +#define MCE2_REGION2_S ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S) +#define MCE2_REGION3_S ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S) +#define MCE2_REGION4_S ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S) +#define MCE2_CONTEXT1_S ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S) +#define MCE2_CONTEXT2_S ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S) +#define MCE3_S ((MCE_TypeDef *) MCE3_BASE_S) +#define MCE3_REGION1_S ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S) +#define MCE3_REGION2_S ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S) +#define MCE3_REGION3_S ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S) +#define MCE3_REGION4_S ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S) +#define MCE3_CONTEXT1_S ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S) +#define MCE3_CONTEXT2_S ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S) +#define MCE4_S ((MCE_TypeDef *) MCE4_BASE_S) +#define MCE4_REGION1_S ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S) +#define MCE4_REGION2_S ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S) +#define MCE4_REGION3_S ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S) +#define MCE4_REGION4_S ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S) +#define MCE4_CONTEXT1_S ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S) +#define MCE4_CONTEXT2_S ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S) +#define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S) +#define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S) +#define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S) +#define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S) +#define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S) +#define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S) +#define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S) +#define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S) +#define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S) +#define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S) +#define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S) +#define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S) +#define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S) +#define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S) +#define RISAF4_S ((RISAF_TypeDef *) RISAF4_BASE_S) +#define RISAF5_S ((RISAF_TypeDef *) RISAF5_BASE_S) +#define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S) +#define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S) +#define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S) +#define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S) +#define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S) +#define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S) +#define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S) +#define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S) +#define RISAF15_S ((RISAF_TypeDef *) RISAF15_BASE_S) +#define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S) +#define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S) +#define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((SAES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S) +#define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S) +#define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define UART7_S ((USART_TypeDef *) UART7_BASE_S) +#define UART8_S ((USART_TypeDef *) UART8_BASE_S) +#define UART9_S ((USART_TypeDef *) UART9_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define USART10_S ((USART_TypeDef *) USART10_BASE_S) +#define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S) +#define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S) +#define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S) +#define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S) +#define VENC_S ((VENC_TypeDef *) VENC_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S) +#define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S) +#define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S) +#define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S) +#endif + +/*!< Peripheral Instance aliases for Non-Secure/Secure execution */ +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define BSEC BSEC_S +#define BSEC_BASE BSEC_BASE_S + +#define CACHEAXI CACHEAXI_S +#define CACHEAXI_BASE CACHEAXI_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define CRYP CRYP_S +#define CRYP_BASE CRYP_BASE_S + +#define CSI CSI_S +#define CSI_BASE CSI_BASE_S + +#define DBGMCU DBGMCU_S +#define DBGMCU_BASE DBGMCU_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define DCMIPP DCMIPP_S +#define DCMIPP_BASE DCMIPP_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define DTS_Sensor0 DTS_Sensor0_S +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_S + +#define DTS_Sensor1 DTS_Sensor1_S +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_S + +#define ETH1 ETH1_S +#define ETH1_BASE ETH1_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define FDCAN3 FDCAN3_S +#define FDCAN3_BASE FDCAN3_BASE_S + +#define FDCAN_CCU FDCAN_CCU_S +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S + +#define FMC_R_BASE FMC_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define FMC_Common_R FMC_Common_R_S +#define FMC_Common_R_BASE FMC_Common_R_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPION GPION_S +#define GPION_BASE GPION_BASE_S + +#define GPIOO GPIOO_S +#define GPIOO_BASE GPIOO_BASE_S + +#define GPIOP GPIOP_S +#define GPIOP_BASE GPIOP_BASE_S + +#define GPIOQ GPIOQ_S +#define GPIOQ_BASE GPIOQ_BASE_S + +#define GPU2D GPU2D_BASE_S +#define GPU2D_BASE GPU2D_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define HPDMA1 HPDMA1_S +#define HPDMA1_BASE HPDMA1_BASE_S + +#define HPDMA1_Channel0 HPDMA1_Channel0_S +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S + +#define HPDMA1_Channel1 HPDMA1_Channel1_S +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S + +#define HPDMA1_Channel2 HPDMA1_Channel2_S +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S + +#define HPDMA1_Channel3 HPDMA1_Channel3_S +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S + +#define HPDMA1_Channel4 HPDMA1_Channel4_S +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S + +#define HPDMA1_Channel5 HPDMA1_Channel5_S +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S + +#define HPDMA1_Channel6 HPDMA1_Channel6_S +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S + +#define HPDMA1_Channel7 HPDMA1_Channel7_S +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S + +#define HPDMA1_Channel8 HPDMA1_Channel8_S +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S + +#define HPDMA1_Channel9 HPDMA1_Channel9_S +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S + +#define HPDMA1_Channel10 HPDMA1_Channel10_S +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S + +#define HPDMA1_Channel11 HPDMA1_Channel11_S +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S + +#define HPDMA1_Channel12 HPDMA1_Channel12_S +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S + +#define HPDMA1_Channel13 HPDMA1_Channel13_S +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S + +#define HPDMA1_Channel14 HPDMA1_Channel14_S +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S + +#define HPDMA1_Channel15 HPDMA1_Channel15_S +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define IAC IAC_S +#define IAC_BASE IAC_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1 LTDC_Layer1_S +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S + +#define LTDC_Layer2 LTDC_Layer2_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define MCE1 MCE1_S +#define MCE1_BASE MCE1_BASE_S + +#define MCE1_REGION1 MCE1_REGION1_S +#define MCE1_REGION1_BASE MCE1_REGION1_BASE_S + +#define MCE1_REGION2 MCE1_REGION2_S +#define MCE1_REGION2_BASE MCE1_REGION2_BASE_S + +#define MCE1_REGION3 MCE1_REGION3_S +#define MCE1_REGION3_BASE MCE1_REGION3_BASE_S + +#define MCE1_REGION4 MCE1_REGION4_S +#define MCE1_REGION4_BASE MCE1_REGION4_BASE_S + +#define MCE1_CONTEXT1 MCE1_CONTEXT1_S +#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_S + +#define MCE1_CONTEXT2 MCE1_CONTEXT2_S +#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_S + +#define MCE2 MCE2_S +#define MCE2_BASE MCE2_BASE_S + +#define MCE2_REGION1 MCE2_REGION1_S +#define MCE2_REGION1_BASE MCE2_REGION1_BASE_S + +#define MCE2_REGION2 MCE2_REGION2_S +#define MCE2_REGION2_BASE MCE2_REGION2_BASE_S + +#define MCE2_REGION3 MCE2_REGION3_S +#define MCE2_REGION3_BASE MCE2_REGION3_BASE_S + +#define MCE2_REGION4 MCE2_REGION4_S +#define MCE2_REGION4_BASE MCE2_REGION4_BASE_S + +#define MCE2_CONTEXT1 MCE2_CONTEXT1_S +#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_S + +#define MCE2_CONTEXT2 MCE2_CONTEXT2_S +#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_S + +#define MCE3 MCE3_S +#define MCE3_BASE MCE3_BASE_S + +#define MCE3_REGION1 MCE3_REGION1_S +#define MCE3_REGION1_BASE MCE3_REGION1_BASE_S + +#define MCE3_REGION2 MCE3_REGION2_S +#define MCE3_REGION2_BASE MCE3_REGION2_BASE_S + +#define MCE3_REGION3 MCE3_REGION3_S +#define MCE3_REGION3_BASE MCE3_REGION3_BASE_S + +#define MCE3_REGION4 MCE3_REGION4_S +#define MCE3_REGION4_BASE MCE3_REGION4_BASE_S + +#define MCE3_CONTEXT1 MCE3_CONTEXT1_S +#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_S + +#define MCE3_CONTEXT2 MCE3_CONTEXT2_S +#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_S + +#define MCE4 MCE4_S +#define MCE4_BASE MCE4_BASE_S + +#define MCE4_REGION1 MCE4_REGION1_S +#define MCE4_REGION1_BASE MCE4_REGION1_BASE_S + +#define MCE4_REGION2 MCE4_REGION2_S +#define MCE4_REGION2_BASE MCE4_REGION2_BASE_S + +#define MCE4_REGION3 MCE4_REGION3_S +#define MCE4_REGION3_BASE MCE4_REGION3_BASE_S + +#define MCE4_REGION4 MCE4_REGION4_S +#define MCE4_REGION4_BASE MCE4_REGION4_BASE_S + +#define MCE4_CONTEXT1 MCE4_CONTEXT1_S +#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_S + +#define MCE4_CONTEXT2 MCE4_CONTEXT2_S +#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define MDIOS MDIOS_S +#define MDIOS_BASE MDIOS_BASE_S + +#define NPU_PRESENT +#define NPU_BASE NPU_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG RAMCFG_S +#define RAMCFG_BASE RAMCFG_BASE_S + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define RIFSC RIFSC_S +#define RIFSC_BASE RIFSC_BASE_S + +#define RISAF1 RISAF1_S +#define RISAF1_BASE RISAF1_BASE_S + +#define RISAF2 RISAF2_S +#define RISAF2_BASE RISAF2_BASE_S + +#define RISAF3 RISAF3_S +#define RISAF3_BASE RISAF3_BASE_S + +#define RISAF4 RISAF4_S +#define RISAF4_BASE RISAF4_BASE_S + +#define RISAF5 RISAF5_S +#define RISAF5_BASE RISAF5_BASE_S + +#define RISAF6 RISAF6_S +#define RISAF6_BASE RISAF6_BASE_S + +#define RISAF7 RISAF7_S +#define RISAF7_BASE RISAF7_BASE_S + +#define RISAF8 RISAF8_S +#define RISAF8_BASE RISAF8_BASE_S + +#define RISAF9 RISAF9_S +#define RISAF9_BASE RISAF9_BASE_S + +#define RISAF11 RISAF11_S +#define RISAF11_BASE RISAF11_BASE_S + +#define RISAF12 RISAF12_S +#define RISAF12_BASE RISAF12_BASE_S + +#define RISAF13 RISAF13_S +#define RISAF13_BASE RISAF13_BASE_S + +#define RISAF14 RISAF14_S +#define RISAF14_BASE RISAF14_BASE_S + +#define RISAF15 RISAF15_S +#define RISAF15_BASE RISAF15_BASE_S + +#define RISAF21 RISAF21_S +#define RISAF21_BASE RISAF21_BASE_S + +#define RISAF22 RISAF22_S +#define RISAF22_BASE RISAF22_BASE_S + +#define RISAF23 RISAF23_S +#define RISAF23_BASE RISAF23_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define SPDIFRX SPDIFRX_S +#define SPDIFRX_BASE SPDIFRX_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM9 TIM9_S +#define TIM9_BASE TIM9_BASE_S + +#define TIM10 TIM10_S +#define TIM10_BASE TIM10_BASE_S + +#define TIM11 TIM11_S +#define TIM11_BASE TIM11_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define TIM18 TIM18_S +#define TIM18_BASE TIM18_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USB1_OTG_HS USB1_OTG_HS_S +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S + +#define USB2_OTG_HS USB2_OTG_HS_S +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S + +#define USB1_HS_PHYC USB1_HS_PHYC_S +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S + +#define USB2_HS_PHYC USB2_HS_PHYC_S +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S + +#define VENC VENC_S +#define VENC_BASE VENC_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define XSPI1 XSPI1_S + +#define XSPI2 XSPI2_S + +#define XSPI3 XSPI3_S + +#define XSPIM XSPIM_S +#define XSPIM_BASE XSPIM_BASE_S + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_S + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_S + +#else + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS + +#define BSEC BSEC_NS +#define BSEC_BASE BSEC_BASE_NS + +#define CACHEAXI CACHEAXI_NS +#define CACHEAXI_BASE CACHEAXI_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define CRYP CRYP_NS +#define CRYP_BASE CRYP_BASE_NS + +#define CSI CSI_NS +#define CSI_BASE CSI_BASE_NS + +#define DBGMCU DBGMCU_NS +#define DBGMCU_BASE DBGMCU_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define DCMIPP DCMIPP_NS +#define DCMIPP_BASE DCMIPP_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define DTS_Sensor0 DTS_Sensor0_NS +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS + +#define DTS_Sensor1 DTS_Sensor1_NS +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS + +#define ETH1 ETH1_NS +#define ETH1_BASE ETH1_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define FDCAN3 FDCAN3_NS +#define FDCAN3_BASE FDCAN3_BASE_NS + +#define FDCAN_CCU FDCAN_CCU_NS +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS + +#define FMC_R_BASE FMC_R_BASE_NS +#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define FMC_Common_R FMC_Common_R_NS +#define FMC_Common_R_BASE FMC_Common_R_BASE_NS + +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPION GPION_NS +#define GPION_BASE GPION_BASE_NS + +#define GPIOO GPIOO_NS +#define GPIOO_BASE GPIOO_BASE_NS + +#define GPIOP GPIOP_NS +#define GPIOP_BASE GPIOP_BASE_NS + +#define GPIOQ GPIOQ_NS +#define GPIOQ_BASE GPIOQ_BASE_NS + +#define GPU2D GPU2D_BASE_NS +#define GPU2D_BASE GPU2D_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define HPDMA1 HPDMA1_NS +#define HPDMA1_BASE HPDMA1_BASE_NS + +#define HPDMA1_Channel0 HPDMA1_Channel0_NS +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS + +#define HPDMA1_Channel1 HPDMA1_Channel1_NS +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS + +#define HPDMA1_Channel2 HPDMA1_Channel2_NS +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS + +#define HPDMA1_Channel3 HPDMA1_Channel3_NS +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS + +#define HPDMA1_Channel4 HPDMA1_Channel4_NS +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS + +#define HPDMA1_Channel5 HPDMA1_Channel5_NS +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS + +#define HPDMA1_Channel6 HPDMA1_Channel6_NS +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS + +#define HPDMA1_Channel7 HPDMA1_Channel7_NS +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS + +#define HPDMA1_Channel8 HPDMA1_Channel8_NS +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS + +#define HPDMA1_Channel9 HPDMA1_Channel9_NS +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS + +#define HPDMA1_Channel10 HPDMA1_Channel10_NS +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS + +#define HPDMA1_Channel11 HPDMA1_Channel11_NS +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS + +#define HPDMA1_Channel12 HPDMA1_Channel12_NS +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS + +#define HPDMA1_Channel13 HPDMA1_Channel13_NS +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS + +#define HPDMA1_Channel14 HPDMA1_Channel14_NS +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS + +#define HPDMA1_Channel15 HPDMA1_Channel15_NS +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define MCE1 MCE1_NS +#define MCE1_BASE MCE1_BASE_NS + +#define MCE1_REGION1 MCE1_REGION1_NS +#define MCE1_REGION1_BASE MCE1_REGION1_BASE_NS + +#define MCE1_REGION2 MCE1_REGION2_NS +#define MCE1_REGION2_BASE MCE1_REGION2_BASE_NS + +#define MCE1_REGION3 MCE1_REGION3_NS +#define MCE1_REGION3_BASE MCE1_REGION3_BASE_NS + +#define MCE1_REGION4 MCE1_REGION4_NS +#define MCE1_REGION4_BASE MCE1_REGION4_BASE_NS + +#define MCE1_CONTEXT1 MCE1_CONTEXT1_NS +#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_NS + +#define MCE1_CONTEXT2 MCE1_CONTEXT2_NS +#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_NS + +#define MCE2 MCE2_NS +#define MCE2_BASE MCE2_BASE_NS + +#define MCE2_REGION1 MCE2_REGION1_NS +#define MCE2_REGION1_BASE MCE2_REGION1_BASE_NS + +#define MCE2_REGION2 MCE2_REGION2_NS +#define MCE2_REGION2_BASE MCE2_REGION2_BASE_NS + +#define MCE2_REGION3 MCE2_REGION3_NS +#define MCE2_REGION3_BASE MCE2_REGION3_BASE_NS + +#define MCE2_REGION4 MCE2_REGION4_NS +#define MCE2_REGION4_BASE MCE2_REGION4_BASE_NS + +#define MCE2_CONTEXT1 MCE2_CONTEXT1_NS +#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_NS + +#define MCE2_CONTEXT2 MCE2_CONTEXT2_NS +#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_NS + +#define MCE3 MCE3_NS +#define MCE3_BASE MCE3_BASE_NS + +#define MCE3_REGION1 MCE3_REGION1_NS +#define MCE3_REGION1_BASE MCE3_REGION1_BASE_NS + +#define MCE3_REGION2 MCE3_REGION2_NS +#define MCE3_REGION2_BASE MCE3_REGION2_BASE_NS + +#define MCE3_REGION3 MCE3_REGION3_NS +#define MCE3_REGION3_BASE MCE3_REGION3_BASE_NS + +#define MCE3_REGION4 MCE3_REGION4_NS +#define MCE3_REGION4_BASE MCE3_REGION4_BASE_NS + +#define MCE3_CONTEXT1 MCE3_CONTEXT1_NS +#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_NS + +#define MCE3_CONTEXT2 MCE3_CONTEXT2_NS +#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_NS + +#define MCE4 MCE4_NS +#define MCE4_BASE MCE4_BASE_NS + +#define MCE4_REGION1 MCE4_REGION1_NS +#define MCE4_REGION1_BASE MCE4_REGION1_BASE_NS + +#define MCE4_REGION2 MCE4_REGION2_NS +#define MCE4_REGION2_BASE MCE4_REGION2_BASE_NS + +#define MCE4_REGION3 MCE4_REGION3_NS +#define MCE4_REGION3_BASE MCE4_REGION3_BASE_NS + +#define MCE4_REGION4 MCE4_REGION4_NS +#define MCE4_REGION4_BASE MCE4_REGION4_BASE_NS + +#define MCE4_CONTEXT1 MCE4_CONTEXT1_NS +#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_NS + +#define MCE4_CONTEXT2 MCE4_CONTEXT2_NS +#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define MDIOS MDIOS_NS +#define MDIOS_BASE MDIOS_BASE_NS + +#define NPU_PRESENT +#define NPU_BASE NPU_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG RAMCFG_NS +#define RAMCFG_BASE RAMCFG_BASE_NS + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define RIFSC RIFSC_NS +#define RIFSC_BASE RIFSC_BASE_NS + +#define RISAF1 RISAF1_NS +#define RISAF1_BASE RISAF1_BASE_NS + +#define RISAF2 RISAF2_NS +#define RISAF2_BASE RISAF2_BASE_NS + +#define RISAF3 RISAF3_NS +#define RISAF3_BASE RISAF3_BASE_NS + +#define RISAF4 RISAF4_NS +#define RISAF4_BASE RISAF4_BASE_NS + +#define RISAF5 RISAF5_NS +#define RISAF5_BASE RISAF5_BASE_NS + +#define RISAF6 RISAF6_NS +#define RISAF6_BASE RISAF6_BASE_NS + +#define RISAF7 RISAF7_NS +#define RISAF7_BASE RISAF7_BASE_NS + +#define RISAF8 RISAF8_NS +#define RISAF8_BASE RISAF8_BASE_NS + +#define RISAF9 RISAF9_NS +#define RISAF9_BASE RISAF9_BASE_NS + +#define RISAF11 RISAF11_NS +#define RISAF11_BASE RISAF11_BASE_NS + +#define RISAF12 RISAF12_NS +#define RISAF12_BASE RISAF12_BASE_NS + +#define RISAF13 RISAF13_NS +#define RISAF13_BASE RISAF13_BASE_NS + +#define RISAF14 RISAF14_NS +#define RISAF14_BASE RISAF14_BASE_NS + +#define RISAF15 RISAF15_NS +#define RISAF15_BASE RISAF15_BASE_NS + +#define RISAF21 RISAF21_NS +#define RISAF21_BASE RISAF21_BASE_NS + +#define RISAF22 RISAF22_NS +#define RISAF22_BASE RISAF22_BASE_NS + +#define RISAF23 RISAF23_NS +#define RISAF23_BASE RISAF23_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define SPDIFRX SPDIFRX_NS +#define SPDIFRX_BASE SPDIFRX_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM9 TIM9_NS +#define TIM9_BASE TIM9_BASE_NS + +#define TIM10 TIM10_NS +#define TIM10_BASE TIM10_BASE_NS + +#define TIM11 TIM11_NS +#define TIM11_BASE TIM11_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define TIM18 TIM18_NS +#define TIM18_BASE TIM18_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USB1_OTG_HS USB1_OTG_HS_NS +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS + +#define USB2_OTG_HS USB2_OTG_HS_NS +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS + +#define USB1_HS_PHYC USB1_HS_PHYC_NS +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS + +#define USB2_HS_PHYC USB2_HS_PHYC_NS +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS + +#define VENC VENC_NS +#define VENC_BASE VENC_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define XSPI1 XSPI1_NS + +#define XSPI2 XSPI2_NS + +#define XSPI3 XSPI3_NS + +#define XSPIM XSPIM_NS +#define XSPIM_BASE XSPIM_BASE_NS + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_NS + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_NS + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_declaration */ + +/** @addtogroup STM32N6xx_Peripheral_Timing_Definition + * @{ + */ + +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ + +/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30UL) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0UL) +#define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16UL) +#define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ + +#define ADC_CALFACT_CALADDOS_Pos (31UL) +#define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */ +#define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */ + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_OP0_Pos (0UL) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */ + +#define ADC_OR_OP1_Pos (1UL) +#define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */ + +#define ADC_OR_OP2_Pos (2UL) +#define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */ +#define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */ + + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* BSEC unit (Boot and Security) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for BSEC_FVRw register *******************/ +#define BSEC_FVRw_FV_Pos (0UL) +#define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */ + +/***************** Bit definition for BSEC_SPLOCKx register *****************/ +#define BSEC_SPLOCKx_SPLOCK0_Pos (0UL) +#define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */ +#define BSEC_SPLOCKx_SPLOCK1_Pos (1UL) +#define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */ +#define BSEC_SPLOCKx_SPLOCK2_Pos (2UL) +#define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */ +#define BSEC_SPLOCKx_SPLOCK3_Pos (3UL) +#define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */ +#define BSEC_SPLOCKx_SPLOCK4_Pos (4UL) +#define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */ +#define BSEC_SPLOCKx_SPLOCK5_Pos (5UL) +#define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */ +#define BSEC_SPLOCKx_SPLOCK6_Pos (6UL) +#define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */ +#define BSEC_SPLOCKx_SPLOCK7_Pos (7UL) +#define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */ +#define BSEC_SPLOCKx_SPLOCK8_Pos (8UL) +#define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */ +#define BSEC_SPLOCKx_SPLOCK9_Pos (9UL) +#define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */ +#define BSEC_SPLOCKx_SPLOCK10_Pos (10UL) +#define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */ +#define BSEC_SPLOCKx_SPLOCK11_Pos (11UL) +#define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */ +#define BSEC_SPLOCKx_SPLOCK12_Pos (12UL) +#define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */ +#define BSEC_SPLOCKx_SPLOCK13_Pos (13UL) +#define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */ +#define BSEC_SPLOCKx_SPLOCK14_Pos (14UL) +#define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */ +#define BSEC_SPLOCKx_SPLOCK15_Pos (15UL) +#define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */ +#define BSEC_SPLOCKx_SPLOCK16_Pos (16UL) +#define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */ +#define BSEC_SPLOCKx_SPLOCK17_Pos (17UL) +#define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */ +#define BSEC_SPLOCKx_SPLOCK18_Pos (18UL) +#define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */ +#define BSEC_SPLOCKx_SPLOCK19_Pos (19UL) +#define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */ +#define BSEC_SPLOCKx_SPLOCK20_Pos (20UL) +#define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */ +#define BSEC_SPLOCKx_SPLOCK21_Pos (21UL) +#define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */ +#define BSEC_SPLOCKx_SPLOCK22_Pos (22UL) +#define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */ +#define BSEC_SPLOCKx_SPLOCK23_Pos (23UL) +#define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */ +#define BSEC_SPLOCKx_SPLOCK24_Pos (24UL) +#define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */ +#define BSEC_SPLOCKx_SPLOCK25_Pos (25UL) +#define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */ +#define BSEC_SPLOCKx_SPLOCK26_Pos (26UL) +#define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */ +#define BSEC_SPLOCKx_SPLOCK27_Pos (27UL) +#define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */ +#define BSEC_SPLOCKx_SPLOCK28_Pos (28UL) +#define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */ +#define BSEC_SPLOCKx_SPLOCK29_Pos (29UL) +#define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */ +#define BSEC_SPLOCKx_SPLOCK30_Pos (30UL) +#define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */ +#define BSEC_SPLOCKx_SPLOCK31_Pos (31UL) +#define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */ + +/***************** Bit definition for BSEC_SWLOCKx register *****************/ +#define BSEC_SWLOCKx_SWLOCK0_Pos (0UL) +#define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */ +#define BSEC_SWLOCKx_SWLOCK1_Pos (1UL) +#define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */ +#define BSEC_SWLOCKx_SWLOCK2_Pos (2UL) +#define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */ +#define BSEC_SWLOCKx_SWLOCK3_Pos (3UL) +#define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */ +#define BSEC_SWLOCKx_SWLOCK4_Pos (4UL) +#define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */ +#define BSEC_SWLOCKx_SWLOCK5_Pos (5UL) +#define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */ +#define BSEC_SWLOCKx_SWLOCK6_Pos (6UL) +#define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */ +#define BSEC_SWLOCKx_SWLOCK7_Pos (7UL) +#define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */ +#define BSEC_SWLOCKx_SWLOCK8_Pos (8UL) +#define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */ +#define BSEC_SWLOCKx_SWLOCK9_Pos (9UL) +#define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */ +#define BSEC_SWLOCKx_SWLOCK10_Pos (10UL) +#define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */ +#define BSEC_SWLOCKx_SWLOCK11_Pos (11UL) +#define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */ +#define BSEC_SWLOCKx_SWLOCK12_Pos (12UL) +#define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */ +#define BSEC_SWLOCKx_SWLOCK13_Pos (13UL) +#define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */ +#define BSEC_SWLOCKx_SWLOCK14_Pos (14UL) +#define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */ +#define BSEC_SWLOCKx_SWLOCK15_Pos (15UL) +#define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */ +#define BSEC_SWLOCKx_SWLOCK16_Pos (16UL) +#define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */ +#define BSEC_SWLOCKx_SWLOCK17_Pos (17UL) +#define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */ +#define BSEC_SWLOCKx_SWLOCK18_Pos (18UL) +#define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */ +#define BSEC_SWLOCKx_SWLOCK19_Pos (19UL) +#define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */ +#define BSEC_SWLOCKx_SWLOCK20_Pos (20UL) +#define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */ +#define BSEC_SWLOCKx_SWLOCK21_Pos (21UL) +#define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */ +#define BSEC_SWLOCKx_SWLOCK22_Pos (22UL) +#define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */ +#define BSEC_SWLOCKx_SWLOCK23_Pos (23UL) +#define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */ +#define BSEC_SWLOCKx_SWLOCK24_Pos (24UL) +#define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */ +#define BSEC_SWLOCKx_SWLOCK25_Pos (25UL) +#define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */ +#define BSEC_SWLOCKx_SWLOCK26_Pos (26UL) +#define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */ +#define BSEC_SWLOCKx_SWLOCK27_Pos (27UL) +#define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */ +#define BSEC_SWLOCKx_SWLOCK28_Pos (28UL) +#define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */ +#define BSEC_SWLOCKx_SWLOCK29_Pos (29UL) +#define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */ +#define BSEC_SWLOCKx_SWLOCK30_Pos (30UL) +#define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */ +#define BSEC_SWLOCKx_SWLOCK31_Pos (31UL) +#define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */ + +/***************** Bit definition for BSEC_SRLOCKx register *****************/ +#define BSEC_SRLOCKx_SRLOCK0_Pos (0UL) +#define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */ +#define BSEC_SRLOCKx_SRLOCK1_Pos (1UL) +#define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */ +#define BSEC_SRLOCKx_SRLOCK2_Pos (2UL) +#define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */ +#define BSEC_SRLOCKx_SRLOCK3_Pos (3UL) +#define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */ +#define BSEC_SRLOCKx_SRLOCK4_Pos (4UL) +#define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */ +#define BSEC_SRLOCKx_SRLOCK5_Pos (5UL) +#define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */ +#define BSEC_SRLOCKx_SRLOCK6_Pos (6UL) +#define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */ +#define BSEC_SRLOCKx_SRLOCK7_Pos (7UL) +#define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */ +#define BSEC_SRLOCKx_SRLOCK8_Pos (8UL) +#define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */ +#define BSEC_SRLOCKx_SRLOCK9_Pos (9UL) +#define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */ +#define BSEC_SRLOCKx_SRLOCK10_Pos (10UL) +#define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */ +#define BSEC_SRLOCKx_SRLOCK11_Pos (11UL) +#define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */ +#define BSEC_SRLOCKx_SRLOCK12_Pos (12UL) +#define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */ +#define BSEC_SRLOCKx_SRLOCK13_Pos (13UL) +#define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */ +#define BSEC_SRLOCKx_SRLOCK14_Pos (14UL) +#define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */ +#define BSEC_SRLOCKx_SRLOCK15_Pos (15UL) +#define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */ +#define BSEC_SRLOCKx_SRLOCK16_Pos (16UL) +#define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */ +#define BSEC_SRLOCKx_SRLOCK17_Pos (17UL) +#define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */ +#define BSEC_SRLOCKx_SRLOCK18_Pos (18UL) +#define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */ +#define BSEC_SRLOCKx_SRLOCK19_Pos (19UL) +#define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */ +#define BSEC_SRLOCKx_SRLOCK20_Pos (20UL) +#define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */ +#define BSEC_SRLOCKx_SRLOCK21_Pos (21UL) +#define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */ +#define BSEC_SRLOCKx_SRLOCK22_Pos (22UL) +#define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */ +#define BSEC_SRLOCKx_SRLOCK23_Pos (23UL) +#define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */ +#define BSEC_SRLOCKx_SRLOCK24_Pos (24UL) +#define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */ +#define BSEC_SRLOCKx_SRLOCK25_Pos (25UL) +#define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */ +#define BSEC_SRLOCKx_SRLOCK26_Pos (26UL) +#define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */ +#define BSEC_SRLOCKx_SRLOCK27_Pos (27UL) +#define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */ +#define BSEC_SRLOCKx_SRLOCK28_Pos (28UL) +#define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */ +#define BSEC_SRLOCKx_SRLOCK29_Pos (29UL) +#define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */ +#define BSEC_SRLOCKx_SRLOCK30_Pos (30UL) +#define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */ +#define BSEC_SRLOCKx_SRLOCK31_Pos (31UL) +#define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */ + +/**************** Bit definition for BSEC_OTPVLDRx register *****************/ +#define BSEC_OTPVLDRx_VLDF0_Pos (0UL) +#define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */ +#define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */ +#define BSEC_OTPVLDRx_VLDF1_Pos (1UL) +#define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */ +#define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */ +#define BSEC_OTPVLDRx_VLDF2_Pos (2UL) +#define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */ +#define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */ +#define BSEC_OTPVLDRx_VLDF3_Pos (3UL) +#define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */ +#define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */ +#define BSEC_OTPVLDRx_VLDF4_Pos (4UL) +#define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */ +#define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */ +#define BSEC_OTPVLDRx_VLDF5_Pos (5UL) +#define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */ +#define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */ +#define BSEC_OTPVLDRx_VLDF6_Pos (6UL) +#define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */ +#define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */ +#define BSEC_OTPVLDRx_VLDF7_Pos (7UL) +#define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */ +#define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */ +#define BSEC_OTPVLDRx_VLDF8_Pos (8UL) +#define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */ +#define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */ +#define BSEC_OTPVLDRx_VLDF9_Pos (9UL) +#define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */ +#define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */ +#define BSEC_OTPVLDRx_VLDF10_Pos (10UL) +#define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */ +#define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */ +#define BSEC_OTPVLDRx_VLDF11_Pos (11UL) +#define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */ +#define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */ +#define BSEC_OTPVLDRx_VLDF12_Pos (12UL) +#define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */ +#define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */ +#define BSEC_OTPVLDRx_VLDF13_Pos (13UL) +#define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */ +#define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */ +#define BSEC_OTPVLDRx_VLDF14_Pos (14UL) +#define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */ +#define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */ +#define BSEC_OTPVLDRx_VLDF15_Pos (15UL) +#define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */ +#define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */ +#define BSEC_OTPVLDRx_VLDF16_Pos (16UL) +#define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */ +#define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */ +#define BSEC_OTPVLDRx_VLDF17_Pos (17UL) +#define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */ +#define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */ +#define BSEC_OTPVLDRx_VLDF18_Pos (18UL) +#define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */ +#define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */ +#define BSEC_OTPVLDRx_VLDF19_Pos (19UL) +#define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */ +#define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */ +#define BSEC_OTPVLDRx_VLDF20_Pos (20UL) +#define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */ +#define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */ +#define BSEC_OTPVLDRx_VLDF21_Pos (21UL) +#define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */ +#define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */ +#define BSEC_OTPVLDRx_VLDF22_Pos (22UL) +#define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */ +#define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */ +#define BSEC_OTPVLDRx_VLDF23_Pos (23UL) +#define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */ +#define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */ +#define BSEC_OTPVLDRx_VLDF24_Pos (24UL) +#define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */ +#define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */ +#define BSEC_OTPVLDRx_VLDF25_Pos (25UL) +#define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */ +#define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */ +#define BSEC_OTPVLDRx_VLDF26_Pos (26UL) +#define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */ +#define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */ +#define BSEC_OTPVLDRx_VLDF27_Pos (27UL) +#define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */ +#define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */ +#define BSEC_OTPVLDRx_VLDF28_Pos (28UL) +#define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */ +#define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */ +#define BSEC_OTPVLDRx_VLDF29_Pos (29UL) +#define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */ +#define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */ +#define BSEC_OTPVLDRx_VLDF30_Pos (30UL) +#define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */ +#define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */ +#define BSEC_OTPVLDRx_VLDF31_Pos (31UL) +#define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */ +#define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */ + +/****************** Bit definition for BSEC_SFSRx register ******************/ +#define BSEC_SFSRx_SFW0_Pos (0UL) +#define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */ +#define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */ +#define BSEC_SFSRx_SFW1_Pos (1UL) +#define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */ +#define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */ +#define BSEC_SFSRx_SFW2_Pos (2UL) +#define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */ +#define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */ +#define BSEC_SFSRx_SFW3_Pos (3UL) +#define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */ +#define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */ +#define BSEC_SFSRx_SFW4_Pos (4UL) +#define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */ +#define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */ +#define BSEC_SFSRx_SFW5_Pos (5UL) +#define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */ +#define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */ +#define BSEC_SFSRx_SFW6_Pos (6UL) +#define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */ +#define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */ +#define BSEC_SFSRx_SFW7_Pos (7UL) +#define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */ +#define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */ +#define BSEC_SFSRx_SFW8_Pos (8UL) +#define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */ +#define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */ +#define BSEC_SFSRx_SFW9_Pos (9UL) +#define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */ +#define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */ +#define BSEC_SFSRx_SFW10_Pos (10UL) +#define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */ +#define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */ +#define BSEC_SFSRx_SFW11_Pos (11UL) +#define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */ +#define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */ +#define BSEC_SFSRx_SFW12_Pos (12UL) +#define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */ +#define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */ +#define BSEC_SFSRx_SFW13_Pos (13UL) +#define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */ +#define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */ +#define BSEC_SFSRx_SFW14_Pos (14UL) +#define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */ +#define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */ +#define BSEC_SFSRx_SFW15_Pos (15UL) +#define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */ +#define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */ +#define BSEC_SFSRx_SFW16_Pos (16UL) +#define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */ +#define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */ +#define BSEC_SFSRx_SFW17_Pos (17UL) +#define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */ +#define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */ +#define BSEC_SFSRx_SFW18_Pos (18UL) +#define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */ +#define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */ +#define BSEC_SFSRx_SFW19_Pos (19UL) +#define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */ +#define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */ +#define BSEC_SFSRx_SFW20_Pos (20UL) +#define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */ +#define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */ +#define BSEC_SFSRx_SFW21_Pos (21UL) +#define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */ +#define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */ +#define BSEC_SFSRx_SFW22_Pos (22UL) +#define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */ +#define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */ +#define BSEC_SFSRx_SFW23_Pos (23UL) +#define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */ +#define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */ +#define BSEC_SFSRx_SFW24_Pos (24UL) +#define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */ +#define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */ +#define BSEC_SFSRx_SFW25_Pos (25UL) +#define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */ +#define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */ +#define BSEC_SFSRx_SFW26_Pos (26UL) +#define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */ +#define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */ +#define BSEC_SFSRx_SFW27_Pos (27UL) +#define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */ +#define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */ +#define BSEC_SFSRx_SFW28_Pos (28UL) +#define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */ +#define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */ +#define BSEC_SFSRx_SFW29_Pos (29UL) +#define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */ +#define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */ +#define BSEC_SFSRx_SFW30_Pos (30UL) +#define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */ +#define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */ +#define BSEC_SFSRx_SFW31_Pos (31UL) +#define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */ +#define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */ + +/****************** Bit definition for BSEC_OTPCR register ******************/ +#define BSEC_OTPCR_ADDR_Pos (0UL) +#define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */ +#define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */ +#define BSEC_OTPCR_PROG_Pos (13UL) +#define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */ +#define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */ +#define BSEC_OTPCR_PPLOCK_Pos (14UL) +#define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */ +#define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */ +#define BSEC_OTPCR_LASTCID_Pos (19UL) +#define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */ +#define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */ + +/******************* Bit definition for BSEC_WDR register *******************/ +#define BSEC_WDR_WRDATA_Pos (0UL) +#define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */ + +/**************** Bit definition for BSEC_SCRATCHRx register ****************/ +#define BSEC_SCRATCHRx_SDATA_Pos (0UL) +#define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */ + +/****************** Bit definition for BSEC_LOCKR register ******************/ +#define BSEC_LOCKR_GWLOCK_Pos (0UL) +#define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */ +#define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */ +#define BSEC_LOCKR_HKLOCK_Pos (2UL) +#define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */ +#define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */ + +/***************** Bit definition for BSEC_JTAGINR register *****************/ +#define BSEC_JTAGINR_JDATAIN_Pos (0UL) +#define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */ + +/**************** Bit definition for BSEC_JTAGOUTR register *****************/ +#define BSEC_JTAGOUTR_JDATAOUT_Pos (0UL) +#define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */ + +/***************** Bit definition for BSEC_UNMAPR register ******************/ +#define BSEC_UNMAPR_UNMAP_Pos (0UL) +#define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */ + +/******************* Bit definition for BSEC_SR register ********************/ +#define BSEC_SR_HVALID_Pos (1UL) +#define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */ +#define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */ +#define BSEC_SR_DBGREQ_Pos (16UL) +#define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */ +#define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */ +#define BSEC_SR_NVSTATE_Pos (26UL) +#define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */ +#define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */ + +/****************** Bit definition for BSEC_OTPSR register ******************/ +#define BSEC_OTPSR_BUSY_Pos (0UL) +#define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */ +#define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */ +#define BSEC_OTPSR_INIT_DONE_Pos (1UL) +#define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */ +#define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */ +#define BSEC_OTPSR_HIDEUP_Pos (2UL) +#define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */ +#define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */ +#define BSEC_OTPSR_OTPNVIR_Pos (4UL) +#define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */ +#define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */ +#define BSEC_OTPSR_OTPERR_Pos (5UL) +#define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */ +#define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */ +#define BSEC_OTPSR_OTPSEC_Pos (6UL) +#define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */ +#define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */ +#define BSEC_OTPSR_PROGFAIL_Pos (16UL) +#define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */ +#define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */ +#define BSEC_OTPSR_DISTURBF_Pos (17UL) +#define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */ +#define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */ +#define BSEC_OTPSR_DEDF_Pos (18UL) +#define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */ +#define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */ +#define BSEC_OTPSR_SECF_Pos (19UL) +#define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */ +#define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */ +#define BSEC_OTPSR_PPLF_Pos (20UL) +#define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */ +#define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */ +#define BSEC_OTPSR_PPLMF_Pos (21UL) +#define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */ +#define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */ +#define BSEC_OTPSR_AMEF_Pos (22UL) +#define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */ +#define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */ + +/***************** Bit definition for BSEC_EPOCHRx register *****************/ +#define BSEC_EPOCHRx_EPOCH_Pos (0UL) +#define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */ + +/**************** Bit definition for BSEC_EPOCHSELR register ****************/ +#define BSEC_EPOCHSELR_EPSEL_Pos (0UL) +#define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */ +#define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */ + +/****************** Bit definition for BSEC_DBGCR register ******************/ +#define BSEC_DBGCR_UNLOCK_Pos (8UL) +#define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */ +#define BSEC_DBGCR_AUTH_HDPL_Pos (16UL) +#define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */ +#define BSEC_DBGCR_AUTH_SEC_Pos (24UL) +#define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */ + +/*************** Bit definition for BSEC_AP_UNLOCK register *****************/ +#define BSEC_AP_UNLOCK_UNLOCK_Pos (0UL) +#define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */ +#define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */ + +/***************** Bit definition for BSEC_HDPLSR register ******************/ +#define BSEC_HDPLSR_HDPL_Pos (0UL) +#define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */ + +/***************** Bit definition for BSEC_HDPLCR register ******************/ +#define BSEC_HDPLCR_INCR_HDPL_Pos (0UL) +#define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */ + +/***************** Bit definition for BSEC_NEXTLR register ******************/ +#define BSEC_NEXTLR_INCR_Pos (0UL) +#define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */ +#define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */ + +/***************** Bit definition for BSEC_WOSCRx register ******************/ +#define BSEC_WOSCRx_WOSDATA_Pos (0UL) +#define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */ + +/****************** Bit definition for BSEC_HRCR register *******************/ +#define BSEC_HRCR_HRC_Pos (0UL) +#define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */ + +/****************** Bit definition for BSEC_WRCR register *******************/ +#define BSEC_WRCR_WRC_Pos (0UL) +#define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */ + + +/******************************************************************************/ +/* */ +/* CACHEAXI */ +/* */ +/******************************************************************************/ +/**************** Bit definition for CACHEAXI_CR1 register ******************/ +#define CACHEAXI_CR1_EN_Pos (0UL) +#define CACHEAXI_CR1_EN_Msk (0x1UL << CACHEAXI_CR1_EN_Pos) /*!< 0x00000001 */ +#define CACHEAXI_CR1_EN CACHEAXI_CR1_EN_Msk /*!< Enable */ +#define CACHEAXI_CR1_CACHEINV_Pos (1UL) +#define CACHEAXI_CR1_CACHEINV_Msk (0x1UL << CACHEAXI_CR1_CACHEINV_Pos) /*!< 0x00000002 */ +#define CACHEAXI_CR1_CACHEINV CACHEAXI_CR1_CACHEINV_Msk /*!< Cache invalidation */ +#define CACHEAXI_CR1_RHITMEN_Pos (16UL) +#define CACHEAXI_CR1_RHITMEN_Msk (0x1UL << CACHEAXI_CR1_RHITMEN_Pos) /*!< 0x00010000 */ +#define CACHEAXI_CR1_RHITMEN CACHEAXI_CR1_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define CACHEAXI_CR1_RMISSMEN_Pos (17UL) +#define CACHEAXI_CR1_RMISSMEN_Msk (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos) /*!< 0x00020000 */ +#define CACHEAXI_CR1_RMISSMEN CACHEAXI_CR1_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define CACHEAXI_CR1_RHITMRST_Pos (18UL) +#define CACHEAXI_CR1_RHITMRST_Msk (0x1UL << CACHEAXI_CR1_RHITMRST_Pos) /*!< 0x00040000 */ +#define CACHEAXI_CR1_RHITMRST CACHEAXI_CR1_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define CACHEAXI_CR1_RMISSMRST_Pos (19UL) +#define CACHEAXI_CR1_RMISSMRST_Msk (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos) /*!< 0x00080000 */ +#define CACHEAXI_CR1_RMISSMRST CACHEAXI_CR1_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define CACHEAXI_CR1_WHITMEN_Pos (20UL) +#define CACHEAXI_CR1_WHITMEN_Msk (0x1UL << CACHEAXI_CR1_WHITMEN_Pos) /*!< 0x00100000 */ +#define CACHEAXI_CR1_WHITMEN CACHEAXI_CR1_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define CACHEAXI_CR1_WMISSMEN_Pos (21UL) +#define CACHEAXI_CR1_WMISSMEN_Msk (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos) /*!< 0x00200000 */ +#define CACHEAXI_CR1_WMISSMEN CACHEAXI_CR1_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define CACHEAXI_CR1_WHITMRST_Pos (22UL) +#define CACHEAXI_CR1_WHITMRST_Msk (0x1UL << CACHEAXI_CR1_WHITMRST_Pos) /*!< 0x00400000 */ +#define CACHEAXI_CR1_WHITMRST CACHEAXI_CR1_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define CACHEAXI_CR1_WMISSMRST_Pos (23UL) +#define CACHEAXI_CR1_WMISSMRST_Msk (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos) /*!< 0x00800000 */ +#define CACHEAXI_CR1_WMISSMRST CACHEAXI_CR1_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define CACHEAXI_CR1_RAMMEN_Pos (24UL) +#define CACHEAXI_CR1_RAMMEN_Msk (0x1UL << CACHEAXI_CR1_RAMMEN_Pos) /*!< 0x01000000 */ +#define CACHEAXI_CR1_RAMMEN CACHEAXI_CR1_RAMMEN_Msk /*!< Read-allocate miss monitor enable */ +#define CACHEAXI_CR1_WAMMEN_Pos (25UL) +#define CACHEAXI_CR1_WAMMEN_Msk (0x1UL << CACHEAXI_CR1_WAMMEN_Pos) /*!< 0x02000000 */ +#define CACHEAXI_CR1_WAMMEN CACHEAXI_CR1_WAMMEN_Msk /*!< Write-allocate miss monitor enable */ +#define CACHEAXI_CR1_RAMMRST_Pos (26UL) +#define CACHEAXI_CR1_RAMMRST_Msk (0x1UL << CACHEAXI_CR1_RAMMRST_Pos) /*!< 0x04000000 */ +#define CACHEAXI_CR1_RAMMRST CACHEAXI_CR1_RAMMRST_Msk /*!< Read-allocate miss monitor reset */ +#define CACHEAXI_CR1_WAMMRST_Pos (27UL) +#define CACHEAXI_CR1_WAMMRST_Msk (0x1UL << CACHEAXI_CR1_WAMMRST_Pos) /*!< 0x08000000 */ +#define CACHEAXI_CR1_WAMMRST CACHEAXI_CR1_WAMMRST_Msk /*!< Write-allocate miss monitor reset */ +#define CACHEAXI_CR1_WTMEN_Pos (28UL) +#define CACHEAXI_CR1_WTMEN_Msk (0x1UL << CACHEAXI_CR1_WTMEN_Pos) /*!< 0x10000000 */ +#define CACHEAXI_CR1_WTMEN CACHEAXI_CR1_WTMEN_Msk /*!< Write-through monitor enable */ +#define CACHEAXI_CR1_EVIMEN_Pos (29UL) +#define CACHEAXI_CR1_EVIMEN_Msk (0x1UL << CACHEAXI_CR1_EVIMEN_Pos) /*!< 0x20000000 */ +#define CACHEAXI_CR1_EVIMEN CACHEAXI_CR1_EVIMEN_Msk /*!< Eviction monitor enable */ +#define CACHEAXI_CR1_WTMRST_Pos (30UL) +#define CACHEAXI_CR1_WTMRST_Msk (0x1UL << CACHEAXI_CR1_WTMRST_Pos) /*!< 0x40000000 */ +#define CACHEAXI_CR1_WTMRST CACHEAXI_CR1_WTMRST_Msk /*!< Write-through monitor reset */ +#define CACHEAXI_CR1_EVIMRST_Pos (31UL) +#define CACHEAXI_CR1_EVIMRST_Msk (0x1UL << CACHEAXI_CR1_EVIMRST_Pos) /*!< 0x80000000 */ +#define CACHEAXI_CR1_EVIMRST CACHEAXI_CR1_EVIMRST_Msk /*!< Eviction monitor reset */ + +/****************** Bit definition for CACHEAXI_SR register *******************/ +#define CACHEAXI_SR_BUSYF_Pos (0UL) +#define CACHEAXI_SR_BUSYF_Msk (0x1UL << CACHEAXI_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define CACHEAXI_SR_BUSYF CACHEAXI_SR_BUSYF_Msk /*!< Busy flag */ +#define CACHEAXI_SR_BSYENDF_Pos (1UL) +#define CACHEAXI_SR_BSYENDF_Msk (0x1UL << CACHEAXI_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define CACHEAXI_SR_BSYENDF CACHEAXI_SR_BSYENDF_Msk /*!< Busy end flag */ +#define CACHEAXI_SR_ERRF_Pos (2UL) +#define CACHEAXI_SR_ERRF_Msk (0x1UL << CACHEAXI_SR_ERRF_Pos) /*!< 0x00000004 */ +#define CACHEAXI_SR_ERRF CACHEAXI_SR_ERRF_Msk /*!< Cache error flag */ +#define CACHEAXI_SR_BUSYCMDF_Pos (3UL) +#define CACHEAXI_SR_BUSYCMDF_Msk (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define CACHEAXI_SR_BUSYCMDF CACHEAXI_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define CACHEAXI_SR_CMDENDF_Pos (4UL) +#define CACHEAXI_SR_CMDENDF_Msk (0x1UL << CACHEAXI_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define CACHEAXI_SR_CMDENDF CACHEAXI_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for CACHEAXI_IER register ******************/ +#define CACHEAXI_IER_BSYENDIE_Pos (1UL) +#define CACHEAXI_IER_BSYENDIE_Msk (0x1UL << CACHEAXI_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define CACHEAXI_IER_BSYENDIE CACHEAXI_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define CACHEAXI_IER_ERRIE_Pos (2UL) +#define CACHEAXI_IER_ERRIE_Msk (0x1UL << CACHEAXI_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define CACHEAXI_IER_ERRIE CACHEAXI_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define CACHEAXI_IER_CMDENDIE_Pos (4UL) +#define CACHEAXI_IER_CMDENDIE_Msk (0x1UL << CACHEAXI_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define CACHEAXI_IER_CMDENDIE CACHEAXI_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for CACHEAXI_FCR register ******************/ +#define CACHEAXI_FCR_CBSYENDF_Pos (1UL) +#define CACHEAXI_FCR_CBSYENDF_Msk (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define CACHEAXI_FCR_CBSYENDF CACHEAXI_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define CACHEAXI_FCR_CERRF_Pos (2UL) +#define CACHEAXI_FCR_CERRF_Msk (0x1UL << CACHEAXI_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define CACHEAXI_FCR_CERRF CACHEAXI_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define CACHEAXI_FCR_CCMDENDF_Pos (4UL) +#define CACHEAXI_FCR_CCMDENDF_Msk (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define CACHEAXI_FCR_CCMDENDF CACHEAXI_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for CACHEAXI_RHMONR register ****************/ +#define CACHEAXI_RHMONR_RHITMON_Pos (0UL) +#define CACHEAXI_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RHMONR_RHITMON CACHEAXI_RHMONR_RHITMON_Msk /*!< Cache read hit monitor register */ + +/****************** Bit definition for CACHEAXI_RMMONR register ****************/ +#define CACHEAXI_RMMONR_RMISSMON_Pos (0UL) +#define CACHEAXI_RMMONR_RMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RMMONR_RMISSMON CACHEAXI_RMMONR_RMISSMON_Msk /*!< Cache read miss monitor register */ + +/****************** Bit definition for CACHEAXI_RAMMONR register ****************/ +#define CACHEAXI_RAMMONR_RAMMON_Pos (0UL) +#define CACHEAXI_RAMMONR_RAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RAMMONR_RAMMON CACHEAXI_RAMMONR_RAMMON_Msk /*!< Cache read-allocate miss monitor counter */ + +/****************** Bit definition for CACHEAXI_EVIMONR register ****************/ +#define CACHEAXI_EVIMONR_EVIMON_Pos (0UL) +#define CACHEAXI_EVIMONR_EVIMON_Msk (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_EVIMONR_EVIMON CACHEAXI_EVIMONR_EVIMON_Msk /*!< Cache eviction monitor counter */ + +/****************** Bit definition for CACHEAXI_WHMONR register ****************/ +#define CACHEAXI_WHMONR_WHITMON_Pos (0UL) +#define CACHEAXI_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WHMONR_WHITMON CACHEAXI_WHMONR_WHITMON_Msk /*!< Cache write hit monitor register */ + +/****************** Bit definition for CACHEAXI_WMMONR register ****************/ +#define CACHEAXI_WMMONR_WMISSMON_Pos (0UL) +#define CACHEAXI_WMMONR_WMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WMMONR_WMISSMON CACHEAXI_WMMONR_WMISSMON_Msk /*!< Cache write miss monitor register */ + +/****************** Bit definition for CACHEAXI_WAMMONR register ****************/ +#define CACHEAXI_WAMMONR_WAMMON_Pos (0UL) +#define CACHEAXI_WAMMONR_WAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WAMMONR_WAMMON CACHEAXI_WAMMONR_WAMMON_Msk /*!< Cache write-allocate miss monitor register */ + +/****************** Bit definition for CACHEAXI_WTMONR register ****************/ +#define CACHEAXI_WTMONR_WTMON_Pos (0UL) +#define CACHEAXI_WTMONR_WTMON_Msk (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WTMONR_WTMON CACHEAXI_WTMONR_WTMON_Msk /*!< Cache write-through monitor register */ + +/**************** Bit definition for CACHEAXI_CR2 register ******************/ +#define CACHEAXI_CR2_STARTCMD_Pos (0UL) +#define CACHEAXI_CR2_STARTCMD_Msk (0x1UL << CACHEAXI_CR2_STARTCMD_Pos) /*!< 0x00000001 */ +#define CACHEAXI_CR2_STARTCMD CACHEAXI_CR2_STARTCMD_Msk /*!< Starts maintenance range command */ +#define CACHEAXI_CR2_CACHECMD_Pos (1UL) +#define CACHEAXI_CR2_CACHECMD_Msk (0x3UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000006 */ +#define CACHEAXI_CR2_CACHECMD CACHEAXI_CR2_CACHECMD_Msk /*!< Cache command maintenance operation */ +#define CACHEAXI_CR2_CACHECMD_0 (0x1UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000002 */ +#define CACHEAXI_CR2_CACHECMD_1 (0x2UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000004 */ + +/****************** Bit definition for CACHEAXI_CMDRSADDRR register ****************/ +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos (0UL) +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */ +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for CACHEAXI_CMDREADDRR register ****************/ +#define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos (0UL) +#define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFC0 */ +#define CACHEAXI_CMDREADDRR_CMDENDADDR CACHEAXI_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Cryp Processor */ +/* */ +/******************************************************************************/ +/******************* Bits definition for CRYP_CR register ********************/ +#define CRYP_CR_ALGODIR_Pos (2UL) +#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */ +#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk /*!< Algorithm direction (Encrypt/Decrypt) */ + +#define CRYP_CR_ALGOMODE_Pos (3UL) +#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */ +#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk /*!< Algorithm mode */ +#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ +#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ +#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ +#define CRYP_CR_ALGOMODE_3 (0x10000UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080000 */ +#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5UL) +#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */ +#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk +#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */ +#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk +#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4UL) +#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */ +#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk +#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */ +#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk +#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19UL) +#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */ +#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk +#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */ +#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk + +#define CRYP_CR_DATATYPE_Pos (6UL) +#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */ +#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk /*!< Data Type selection */ +#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */ +#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */ +#define CRYP_CR_KEYSIZE_Pos (8UL) +#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */ +#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk /*!< Key Size selection */ +#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */ +#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */ +#define CRYP_CR_FFLUSH_Pos (14UL) +#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */ +#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk /*!< CRYP FIFO Flush */ +#define CRYP_CR_CRYPEN_Pos (15UL) +#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */ +#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk /*!< CRYP processor enable */ + +#define CRYP_CR_GCM_CCMPH_Pos (16UL) +#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */ +#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk /*!< GCM or CCM Phase selection */ +#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ +#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ + +#define CRYP_CR_NPBLB_Pos (20UL) +#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk /*!< Number of Padding Bytes in Last Block of payload */ + +#define CRYP_CR_KMOD_Pos (24UL) +#define CRYP_CR_KMOD_Msk (0x3UL << CRYP_CR_KMOD_Pos) /*!< 0x03000000 */ +#define CRYP_CR_KMOD CRYP_CR_KMOD_Msk /*!< Key mode selection */ +#define CRYP_CR_KMOD_0 (0x1UL << CRYP_CR_KMOD_Pos) /*!< 0x01000000 */ +#define CRYP_CR_KMOD_1 (0x2UL << CRYP_CR_KMOD_Pos) /*!< 0x02000000 */ + +#define CRYP_CR_IPRST_Pos (31UL) +#define CRYP_CR_IPRST_Msk (0x1UL << CRYP_CR_IPRST_Pos) /*!< 0x80000000 */ +#define CRYP_CR_IPRST CRYP_CR_IPRST_Msk /*!< CRYP peripheral software reset */ + +/****************** Bits definition for CRYP_SR register *********************/ +#define CRYP_SR_IFEM_Pos (0UL) +#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */ +#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk /*!< Input FIFO empty flag */ +#define CRYP_SR_IFNF_Pos (1UL) +#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */ +#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk /*!< Input FIFO not full flag */ +#define CRYP_SR_OFNE_Pos (2UL) +#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */ +#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk /*!< Output FIFO not empty flag */ +#define CRYP_SR_OFFU_Pos (3UL) +#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */ +#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk /*!< Output FIFO full flag */ +#define CRYP_SR_BUSY_Pos (4UL) +#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */ +#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk /*!< Busy bit */ +#define CRYP_SR_KERF_Pos (6UL) +#define CRYP_SR_KERF_Msk (0x1UL << CRYP_SR_KERF_Pos) /*!< 0x00000040 */ +#define CRYP_SR_KERF CRYP_SR_KERF_Msk /*!< Key error flag */ +#define CRYP_SR_KEYVALID_Pos (7UL) +#define CRYP_SR_KEYVALID_Msk (0x1UL << CRYP_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define CRYP_SR_KEYVALID CRYP_SR_KEYVALID_Msk /*!< Key valid flag */ + +/******************* Bit definition for CRYP_DIN register *******************/ +#define CRYP_DIN_DATAIN_Pos (0UL) +#define CRYP_DIN_DATAIN_Msk (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_DIN_DATAIN CRYP_DIN_DATAIN_Msk /*!< CRYP Data Input */ + +/******************* Bit definition for CRYP_DIN register *******************/ +#define CRYP_DOUT_DATAOUT_Pos (0UL) +#define CRYP_DOUT_DATAOUT_Msk (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_DOUT_DATAOUT CRYP_DOUT_DATAOUT_Msk /*!< CRYP Data Output */ + +/****************** Bits definition for CRYP_DMACR register ******************/ +#define CRYP_DMACR_DIEN_Pos (0UL) +#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */ +#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk /*!< DMA Input Enable */ +#define CRYP_DMACR_DOEN_Pos (1UL) +#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */ +#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk /*!< DMA Output Enable */ + +/***************** Bits definition for CRYP_IMSCR register ******************/ +#define CRYP_IMSCR_INIM_Pos (0UL) +#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */ +#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk /*!< Input FIFO service interrupt mask */ +#define CRYP_IMSCR_OUTIM_Pos (1UL) +#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */ +#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk /*!< Output FIFO service interrupt mask */ + +/****************** Bits definition for CRYP_RISR register *******************/ +#define CRYP_RISR_INRIS_Pos (0UL) +#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */ +#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk /*!< Input FIFO service raw interrupt status */ +#define CRYP_RISR_OUTRIS_Pos (1UL) +#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */ +#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk /*!< Output FIFO service raw interrupt mask */ + +/****************** Bits definition for CRYP_MISR register *******************/ +#define CRYP_MISR_INMIS_Pos (0UL) +#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */ +#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk /*!< Input FIFO service masked interrupt status */ +#define CRYP_MISR_OUTMIS_Pos (1UL) +#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */ +#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk /*!< Output FIFO service masked interrupt status */ + +/******************* Bit definition for CRYP_K0LR register ******************/ +#define CRYP_K0LR_K_Pos (0UL) +#define CRYP_K0LR_K_Msk (0xFFFFFFFFUL << CRYP_K0LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K0LR_K CRYP_K0LR_K_Msk /*!< AES key bit x (x= 224 to 255) */ + +/******************* Bit definition for CRYP_K0RR register ******************/ +#define CRYP_K0RR_K_Pos (0UL) +#define CRYP_K0RR_K_Msk (0xFFFFFFFFUL << CRYP_K0RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K0RR_K CRYP_K0RR_K_Msk /*!< AES key bit x (x= 192 to 223) */ + +/******************* Bit definition for CRYP_IV1LR register ******************/ +#define CRYP_IV1LR_K_Pos (0UL) +#define CRYP_IV1LR_K_Msk (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1LR_K CRYP_IV1LR_K_Msk /*!< AES key bit x (x= 160 to 291) */ + +/******************* Bit definition for CRYP_IV1RR register ******************/ +#define CRYP_IV1RR_K_Pos (0UL) +#define CRYP_IV1RR_K_Msk (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1RR_K CRYP_IV1RR_K_Msk /*!< AES key bit x (x= 128 to 159) */ + +/******************* Bit definition for CRYP_K2LR register ******************/ +#define CRYP_K2LR_K_Pos (0UL) +#define CRYP_K2LR_K_Msk (0xFFFFFFFFUL << CRYP_K2LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K2LR_K CRYP_K2LR_K_Msk /*!< AES key bit x (x= 96 to 127) */ + +/******************* Bit definition for CRYP_K2RR register ******************/ +#define CRYP_K2RR_K_Pos (0UL) +#define CRYP_K2RR_K_Msk (0xFFFFFFFFUL << CRYP_K2RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K2RR_K CRYP_K2RR_K_Msk /*!< AES key bit x (x= 64 to 95) */ + +/******************* Bit definition for CRYP_K3LR register ******************/ +#define CRYP_K3LR_K_Pos (0UL) +#define CRYP_K3LR_K_Msk (0xFFFFFFFFUL << CRYP_K3LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K3LR_K CRYP_K3LR_K_Msk /*!< AES key bit x (x= 32 to 63) */ + +/******************* Bit definition for CRYP_K3RR register ******************/ +#define CRYP_K3RR_K_Pos (0UL) +#define CRYP_K3RR_K_Msk (0xFFFFFFFFUL << CRYP_K3RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K3RR_K CRYP_K3RR_K_Msk /*!< AES key bit x (x= 0 to 31) */ + +/******************* Bit definition for CRYP_IV0LR register ******************/ +#define CRYP_IV0LR_IV_Pos (0UL) +#define CRYP_IV0LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV0LR_IV CRYP_IV0LR_IV_Msk /*!< Initialization vector bit x (x= 0 to 31) */ + +/******************* Bit definition for CRYP_IV0RR register ******************/ +#define CRYP_IV0RR_IV_Pos (0UL) +#define CRYP_IV0RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV0RR_IV CRYP_IV0RR_IV_Msk /*!< Initialization vector bit x (x= 32 to 63) */ + +/******************* Bit definition for CRYP_IV1LR register ******************/ +#define CRYP_IV1LR_IV_Pos (0UL) +#define CRYP_IV1LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1LR_IV CRYP_IV1LR_IV_Msk /*!< Initialization vector bit x (x= 64 to 95) */ + +/******************* Bit definition for CRYP_IV1RR register ******************/ +#define CRYP_IV1RR_IV_Pos (0UL) +#define CRYP_IV1RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1RR_IV CRYP_IV1RR_IV_Msk /*!< Initialization vector bit x (x= 96 to 127) */ + +/******************* Bit definition for CRYP_CSGCMCCM0R register ******************/ +#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos (0UL) +#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM0R_CSGCMCCM0 CRYP_CSGCMCCM0R_CSGCMCCM0_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM1R register ******************/ +#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos (0UL) +#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM1R_CSGCMCCM1 CRYP_CSGCMCCM1R_CSGCMCCM1_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM2R register ******************/ +#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos (0UL) +#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM2R_CSGCMCCM2 CRYP_CSGCMCCM2R_CSGCMCCM2_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM3R register ******************/ +#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos (0UL) +#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM3R_CSGCMCCM3 CRYP_CSGCMCCM3R_CSGCMCCM3_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM4R register ******************/ +#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos (0UL) +#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM4R_CSGCMCCM4 CRYP_CSGCMCCM4R_CSGCMCCM4_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM5R register ******************/ +#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos (0UL) +#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM5R_CSGCMCCM5 CRYP_CSGCMCCM5R_CSGCMCCM5_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM6R register ******************/ +#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos (0UL) +#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM6R_CSGCMCCM6 CRYP_CSGCMCCM6R_CSGCMCCM6_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM7R register ******************/ +#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos (0UL) +#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM7R_CSGCMCCM7 CRYP_CSGCMCCM7R_CSGCMCCM7_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCM0R register ******************/ +#define CRYP_CSGCM0R_CSGCM0_Pos (0UL) +#define CRYP_CSGCM0R_CSGCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM0R_CSGCM0 CRYP_CSGCM0R_CSGCM0_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM1R register ******************/ +#define CRYP_CSGCM1R_CSGCM1_Pos (0UL) +#define CRYP_CSGCM1R_CSGCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM1R_CSGCM1 CRYP_CSGCM1R_CSGCM1_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM2R register ******************/ +#define CRYP_CSGCM2R_CSGCM2_Pos (0UL) +#define CRYP_CSGCM2R_CSGCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM2R_CSGCM2 CRYP_CSGCM2R_CSGCM2_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM3R register ******************/ +#define CRYP_CSGCM3R_CSGCM3_Pos (0UL) +#define CRYP_CSGCM3R_CSGCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM3R_CSGCM3 CRYP_CSGCM3R_CSGCM3_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM4R register ******************/ +#define CRYP_CSGCM4R_CSGCM4_Pos (0UL) +#define CRYP_CSGCM4R_CSGCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM4R_CSGCM4 CRYP_CSGCM4R_CSGCM4_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM5R register ******************/ +#define CRYP_CSGCM5R_CSGCM5_Pos (0UL) +#define CRYP_CSGCM5R_CSGCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM5R_CSGCM5 CRYP_CSGCM5R_CSGCM5_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM6R register ******************/ +#define CRYP_CSGCM6R_CSGCM6_Pos (0UL) +#define CRYP_CSGCM6R_CSGCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM6R_CSGCM6 CRYP_CSGCM6R_CSGCM6_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM7R register ******************/ +#define CRYP_CSGCM7R_CSGCM7_Pos (0UL) +#define CRYP_CSGCM7R_CSGCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM7R_CSGCM7 CRYP_CSGCM7R_CSGCM7_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + + +/******************************************************************************/ +/* */ +/* (CSI) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CSI_CR register ********************/ +#define CSI_CR_CSIEN_Pos (0UL) +#define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */ +#define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */ +#define CSI_CR_VC0START_Pos (2UL) +#define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */ +#define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */ +#define CSI_CR_VC0STOP_Pos (3UL) +#define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */ +#define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */ +#define CSI_CR_VC1START_Pos (6UL) +#define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */ +#define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */ +#define CSI_CR_VC1STOP_Pos (7UL) +#define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */ +#define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */ +#define CSI_CR_VC2START_Pos (10UL) +#define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */ +#define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */ +#define CSI_CR_VC2STOP_Pos (11UL) +#define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */ +#define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */ +#define CSI_CR_VC3START_Pos (14UL) +#define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */ +#define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */ +#define CSI_CR_VC3STOP_Pos (15UL) +#define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */ +#define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */ + +/******************* Bit definition for CSI_PCR register ********************/ +#define CSI_PCR_PWRDOWN_Pos (0UL) +#define CSI_PCR_PWRDOWN_Msk (0x1UL << CSI_PCR_PWRDOWN_Pos) /*!< 0x00000001 */ +#define CSI_PCR_PWRDOWN CSI_PCR_PWRDOWN_Msk /*!< Virtual channel 3 start */ +#define CSI_PCR_CLEN_Pos (1UL) +#define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */ +#define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */ +#define CSI_PCR_DL0EN_Pos (2UL) +#define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */ +#define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */ +#define CSI_PCR_DL1EN_Pos (3UL) +#define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */ +#define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */ + +/***************** Bit definition for CSI_VC0CFGR1 register *****************/ +#define CSI_VC0CFGR1_ALLDT_Pos (0UL) +#define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC0CFGR1_DT0EN_Pos (1UL) +#define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC0CFGR1_DT1EN_Pos (2UL) +#define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC0CFGR1_DT2EN_Pos (3UL) +#define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC0CFGR1_DT3EN_Pos (4UL) +#define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC0CFGR1_DT4EN_Pos (5UL) +#define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC0CFGR1_DT5EN_Pos (6UL) +#define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC0CFGR1_DT6EN_Pos (7UL) +#define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC0CFGR1_CDTFT_Pos (8UL) +#define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC0CFGR1_DT0_Pos (16UL) +#define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC0CFGR1_DT0FT_Pos (24UL) +#define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC0CFGR2 register *****************/ +#define CSI_VC0CFGR2_DT1_Pos (0UL) +#define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT1FT_Pos (8UL) +#define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC0CFGR2_DT2_Pos (16UL) +#define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT2FT_Pos (24UL) +#define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC0CFGR3 register *****************/ +#define CSI_VC0CFGR3_DT3_Pos (0UL) +#define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT3FT_Pos (8UL) +#define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC0CFGR3_DT4_Pos (16UL) +#define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT4FT_Pos (24UL) +#define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC0CFGR4 register *****************/ +#define CSI_VC0CFGR4_DT5_Pos (0UL) +#define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT5FT_Pos (8UL) +#define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC0CFGR4_DT6_Pos (16UL) +#define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT6FT_Pos (24UL) +#define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC1CFGR1 register *****************/ +#define CSI_VC1CFGR1_ALLDT_Pos (0UL) +#define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC1CFGR1_DT0EN_Pos (1UL) +#define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC1CFGR1_DT1EN_Pos (2UL) +#define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC1CFGR1_DT2EN_Pos (3UL) +#define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC1CFGR1_DT3EN_Pos (4UL) +#define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC1CFGR1_DT4EN_Pos (5UL) +#define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC1CFGR1_DT5EN_Pos (6UL) +#define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC1CFGR1_DT6EN_Pos (7UL) +#define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC1CFGR1_CDTFT_Pos (8UL) +#define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC1CFGR1_DT0_Pos (16UL) +#define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC1CFGR1_DT0FT_Pos (24UL) +#define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC1CFGR2 register *****************/ +#define CSI_VC1CFGR2_DT1_Pos (0UL) +#define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT1FT_Pos (8UL) +#define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC1CFGR2_DT2_Pos (16UL) +#define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT2FT_Pos (24UL) +#define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC1CFGR3 register *****************/ +#define CSI_VC1CFGR3_DT3_Pos (0UL) +#define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT3FT_Pos (8UL) +#define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC1CFGR3_DT4_Pos (16UL) +#define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT4FT_Pos (24UL) +#define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC1CFGR4 register *****************/ +#define CSI_VC1CFGR4_DT5_Pos (0UL) +#define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT5FT_Pos (8UL) +#define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC1CFGR4_DT6_Pos (16UL) +#define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT6FT_Pos (24UL) +#define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC2CFGR1 register *****************/ +#define CSI_VC2CFGR1_ALLDT_Pos (0UL) +#define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC2CFGR1_DT0EN_Pos (1UL) +#define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC2CFGR1_DT1EN_Pos (2UL) +#define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC2CFGR1_DT2EN_Pos (3UL) +#define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC2CFGR1_DT3EN_Pos (4UL) +#define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC2CFGR1_DT4EN_Pos (5UL) +#define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC2CFGR1_DT5EN_Pos (6UL) +#define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC2CFGR1_DT6EN_Pos (7UL) +#define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC2CFGR1_CDTFT_Pos (8UL) +#define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC2CFGR1_DT0_Pos (16UL) +#define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC2CFGR1_DT0FT_Pos (24UL) +#define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC2CFGR2 register *****************/ +#define CSI_VC2CFGR2_DT1_Pos (0UL) +#define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT1FT_Pos (8UL) +#define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC2CFGR2_DT2_Pos (16UL) +#define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT2FT_Pos (24UL) +#define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC2CFGR3 register *****************/ +#define CSI_VC2CFGR3_DT3_Pos (0UL) +#define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT3FT_Pos (8UL) +#define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC2CFGR3_DT4_Pos (16UL) +#define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT4FT_Pos (24UL) +#define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC2CFGR4 register *****************/ +#define CSI_VC2CFGR4_DT5_Pos (0UL) +#define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT5FT_Pos (8UL) +#define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC2CFGR4_DT6_Pos (16UL) +#define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT6FT_Pos (24UL) +#define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC3CFGR1 register *****************/ +#define CSI_VC3CFGR1_ALLDT_Pos (0UL) +#define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC3CFGR1_DT0EN_Pos (1UL) +#define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC3CFGR1_DT1EN_Pos (2UL) +#define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC3CFGR1_DT2EN_Pos (3UL) +#define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC3CFGR1_DT3EN_Pos (4UL) +#define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC3CFGR1_DT4EN_Pos (5UL) +#define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC3CFGR1_DT5EN_Pos (6UL) +#define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC3CFGR1_DT6EN_Pos (7UL) +#define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC3CFGR1_CDTFT_Pos (8UL) +#define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC3CFGR1_DT0_Pos (16UL) +#define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC3CFGR1_DT0FT_Pos (24UL) +#define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC3CFGR2 register *****************/ +#define CSI_VC3CFGR2_DT1_Pos (0UL) +#define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT1FT_Pos (8UL) +#define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC3CFGR2_DT2_Pos (16UL) +#define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT2FT_Pos (24UL) +#define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC3CFGR3 register *****************/ +#define CSI_VC3CFGR3_DT3_Pos (0UL) +#define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT3FT_Pos (8UL) +#define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC3CFGR3_DT4_Pos (16UL) +#define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT4FT_Pos (24UL) +#define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC3CFGR4 register *****************/ +#define CSI_VC3CFGR4_DT5_Pos (0UL) +#define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT5FT_Pos (8UL) +#define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC3CFGR4_DT6_Pos (16UL) +#define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT6FT_Pos (24UL) +#define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_LB0CFGR register ******************/ +#define CSI_LB0CFGR_BYTECNT_Pos (0UL) +#define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB0CFGR_LINECNT_Pos (16UL) +#define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB1CFGR register ******************/ +#define CSI_LB1CFGR_BYTECNT_Pos (0UL) +#define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB1CFGR_LINECNT_Pos (16UL) +#define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB2CFGR register ******************/ +#define CSI_LB2CFGR_BYTECNT_Pos (0UL) +#define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB2CFGR_LINECNT_Pos (16UL) +#define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB3CFGR register ******************/ +#define CSI_LB3CFGR_BYTECNT_Pos (0UL) +#define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB3CFGR_LINECNT_Pos (16UL) +#define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_TIM0CFGR register *****************/ +#define CSI_TIM0CFGR_COUNT_Pos (0UL) +#define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM1CFGR register *****************/ +#define CSI_TIM1CFGR_COUNT_Pos (0UL) +#define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM2CFGR register *****************/ +#define CSI_TIM2CFGR_COUNT_Pos (0UL) +#define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM3CFGR register *****************/ +#define CSI_TIM3CFGR_COUNT_Pos (0UL) +#define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/****************** Bit definition for CSI_LMCFGR register ******************/ +#define CSI_LMCFGR_LANENB_Pos (8UL) +#define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */ +#define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */ +#define CSI_LMCFGR_DL0MAP_Pos (16UL) +#define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */ +#define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */ +#define CSI_LMCFGR_DL1MAP_Pos (20UL) +#define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */ +#define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */ + +/****************** Bit definition for CSI_PRGITR register ******************/ +#define CSI_PRGITR_LB0VC_Pos (0UL) +#define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */ +#define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */ +#define CSI_PRGITR_LB0EN_Pos (3UL) +#define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */ +#define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */ +#define CSI_PRGITR_LB1VC_Pos (4UL) +#define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */ +#define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */ +#define CSI_PRGITR_LB1EN_Pos (7UL) +#define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */ +#define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */ +#define CSI_PRGITR_LB2VC_Pos (8UL) +#define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */ +#define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */ +#define CSI_PRGITR_LB2EN_Pos (11UL) +#define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */ +#define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */ +#define CSI_PRGITR_LB3VC_Pos (12UL) +#define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */ +#define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */ +#define CSI_PRGITR_LB3EN_Pos (15UL) +#define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */ +#define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */ +#define CSI_PRGITR_TIM0VC_Pos (16UL) +#define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */ +#define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM0EOF_Pos (18UL) +#define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */ +#define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */ +#define CSI_PRGITR_TIM0EN_Pos (19UL) +#define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */ +#define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */ +#define CSI_PRGITR_TIM1VC_Pos (20UL) +#define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */ +#define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM1EOF_Pos (22UL) +#define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */ +#define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */ +#define CSI_PRGITR_TIM1EN_Pos (23UL) +#define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */ +#define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */ +#define CSI_PRGITR_TIM2VC_Pos (24UL) +#define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */ +#define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM2EOF_Pos (26UL) +#define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */ +#define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */ +#define CSI_PRGITR_TIM2EN_Pos (27UL) +#define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */ +#define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */ +#define CSI_PRGITR_TIM3VC_Pos (28UL) +#define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */ +#define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM3EOF_Pos (30UL) +#define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */ +#define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */ +#define CSI_PRGITR_TIM3EN_Pos (31UL) +#define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */ +#define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */ + +/******************* Bit definition for CSI_WDR register ********************/ +#define CSI_WDR_CNT_Pos (0UL) +#define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */ +#define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */ + +/******************* Bit definition for CSI_IER0 register *******************/ +#define CSI_IER0_LB0IE_Pos (0UL) +#define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */ +#define CSI_IER0_LB1IE_Pos (1UL) +#define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */ +#define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */ +#define CSI_IER0_LB2IE_Pos (2UL) +#define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */ +#define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */ +#define CSI_IER0_LB3IE_Pos (3UL) +#define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */ +#define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */ +#define CSI_IER0_TIM0IE_Pos (4UL) +#define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */ +#define CSI_IER0_TIM1IE_Pos (5UL) +#define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */ +#define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */ +#define CSI_IER0_TIM2IE_Pos (6UL) +#define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */ +#define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */ +#define CSI_IER0_TIM3IE_Pos (7UL) +#define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */ +#define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */ +#define CSI_IER0_SOF0IE_Pos (8UL) +#define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */ +#define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_SOF1IE_Pos (9UL) +#define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_SOF2IE_Pos (10UL) +#define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */ +#define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_SOF3IE_Pos (11UL) +#define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */ +#define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_EOF0IE_Pos (12UL) +#define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */ +#define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_EOF1IE_Pos (13UL) +#define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */ +#define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_EOF2IE_Pos (14UL) +#define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */ +#define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_EOF3IE_Pos (15UL) +#define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */ +#define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_SPKTIE_Pos (16UL) +#define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */ +#define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */ +#define CSI_IER0_CCFIFOFIE_Pos (21UL) +#define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */ +#define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */ +#define CSI_IER0_CRCERRIE_Pos (24UL) +#define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */ +#define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */ +#define CSI_IER0_ECCERRIE_Pos (25UL) +#define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */ +#define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */ +#define CSI_IER0_CECCERRIE_Pos (26UL) +#define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */ +#define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */ +#define CSI_IER0_IDERRIE_Pos (27UL) +#define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */ +#define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */ +#define CSI_IER0_SPKTERRIE_Pos (28UL) +#define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */ +#define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */ +#define CSI_IER0_WDERRIE_Pos (29UL) +#define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */ +#define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */ +#define CSI_IER0_SYNCERRIE_Pos (30UL) +#define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */ +#define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */ + +/******************* Bit definition for CSI_IER1 register *******************/ +#define CSI_IER1_ESOTDL0IE_Pos (0UL) +#define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */ +#define CSI_IER1_ESOTSYNCDL0IE_Pos (1UL) +#define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */ +#define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */ +#define CSI_IER1_EESCDL0IE_Pos (2UL) +#define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */ +#define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL0IE_Pos (3UL) +#define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */ +#define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL0IE_Pos (4UL) +#define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */ +#define CSI_IER1_ESOTDL1IE_Pos (8UL) +#define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */ +#define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */ +#define CSI_IER1_ESOTSYNCDL1IE_Pos (9UL) +#define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */ +#define CSI_IER1_EESCDL1IE_Pos (10UL) +#define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */ +#define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL1IE_Pos (11UL) +#define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */ +#define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL1IE_Pos (12UL) +#define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */ +#define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */ + +/******************* Bit definition for CSI_SR0 register ********************/ +#define CSI_SR0_LB0F_Pos (0UL) +#define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */ +#define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */ +#define CSI_SR0_LB1F_Pos (1UL) +#define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */ +#define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */ +#define CSI_SR0_LB2F_Pos (2UL) +#define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */ +#define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */ +#define CSI_SR0_LB3F_Pos (3UL) +#define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */ +#define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */ +#define CSI_SR0_TIM0F_Pos (4UL) +#define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */ +#define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */ +#define CSI_SR0_TIM1F_Pos (5UL) +#define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */ +#define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */ +#define CSI_SR0_TIM2F_Pos (6UL) +#define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */ +#define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */ +#define CSI_SR0_TIM3F_Pos (7UL) +#define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */ +#define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */ +#define CSI_SR0_SOF0F_Pos (8UL) +#define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */ +#define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */ +#define CSI_SR0_SOF1F_Pos (9UL) +#define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */ +#define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */ +#define CSI_SR0_SOF2F_Pos (10UL) +#define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */ +#define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */ +#define CSI_SR0_SOF3F_Pos (11UL) +#define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */ +#define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */ +#define CSI_SR0_EOF0F_Pos (12UL) +#define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */ +#define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */ +#define CSI_SR0_EOF1F_Pos (13UL) +#define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */ +#define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */ +#define CSI_SR0_EOF2F_Pos (14UL) +#define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */ +#define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */ +#define CSI_SR0_EOF3F_Pos (15UL) +#define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */ +#define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */ +#define CSI_SR0_SPKTF_Pos (16UL) +#define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */ +#define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */ +#define CSI_SR0_VC0STATEF_Pos (17UL) +#define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */ +#define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */ +#define CSI_SR0_VC1STATEF_Pos (18UL) +#define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */ +#define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */ +#define CSI_SR0_VC2STATEF_Pos (19UL) +#define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */ +#define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */ +#define CSI_SR0_VC3STATEF_Pos (20UL) +#define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */ +#define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */ +#define CSI_SR0_CCFIFOFF_Pos (21UL) +#define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */ +#define CSI_SR0_CRCERRF_Pos (24UL) +#define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */ +#define CSI_SR0_ECCERRF_Pos (25UL) +#define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */ +#define CSI_SR0_CECCERRF_Pos (26UL) +#define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */ +#define CSI_SR0_IDERRF_Pos (27UL) +#define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */ +#define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */ +#define CSI_SR0_SPKTERRF_Pos (28UL) +#define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */ +#define CSI_SR0_WDERRF_Pos (29UL) +#define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */ +#define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */ +#define CSI_SR0_SYNCERRF_Pos (30UL) +#define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */ + +/******************* Bit definition for CSI_SR1 register ********************/ +#define CSI_SR1_ESOTDL0F_Pos (0UL) +#define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */ +#define CSI_SR1_ESOTSYNCDL0F_Pos (1UL) +#define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */ +#define CSI_SR1_EESCDL0F_Pos (2UL) +#define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL0F_Pos (3UL) +#define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL0F_Pos (4UL) +#define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */ +#define CSI_SR1_ESOTDL1F_Pos (8UL) +#define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */ +#define CSI_SR1_ESOTSYNCDL1F_Pos (9UL) +#define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */ +#define CSI_SR1_EESCDL1F_Pos (10UL) +#define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL1F_Pos (11UL) +#define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL1F_Pos (12UL) +#define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */ +#define CSI_SR1_ACTDL0F_Pos (16UL) +#define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */ +#define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */ +#define CSI_SR1_SYNCDL0F_Pos (17UL) +#define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */ +#define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */ +#define CSI_SR1_SKCALDL0F_Pos (18UL) +#define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */ +#define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */ +#define CSI_SR1_STOPDL0F_Pos (19UL) +#define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */ +#define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */ +#define CSI_SR1_ULPNDL0F_Pos (20UL) +#define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */ +#define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */ +#define CSI_SR1_ACTDL1F_Pos (22UL) +#define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */ +#define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */ +#define CSI_SR1_SYNCDL1F_Pos (23UL) +#define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */ +#define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */ +#define CSI_SR1_SKCALDL1F_Pos (24UL) +#define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */ +#define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */ +#define CSI_SR1_STOPDL1F_Pos (25UL) +#define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */ +#define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */ +#define CSI_SR1_ULPNDL1F_Pos (26UL) +#define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */ +#define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */ +#define CSI_SR1_STOPCLF_Pos (28UL) +#define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */ +#define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */ +#define CSI_SR1_ULPNACTF_Pos (29UL) +#define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */ +#define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */ +#define CSI_SR1_ULPNCLF_Pos (30UL) +#define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */ +#define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */ +#define CSI_SR1_ACTCLF_Pos (31UL) +#define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */ +#define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */ + +/******************* Bit definition for CSI_FCR0 register *******************/ +#define CSI_FCR0_CLB0F_Pos (0UL) +#define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */ +#define CSI_FCR0_CLB1F_Pos (1UL) +#define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */ +#define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */ +#define CSI_FCR0_CLB2F_Pos (2UL) +#define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */ +#define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */ +#define CSI_FCR0_CLB3F_Pos (3UL) +#define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */ +#define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */ +#define CSI_FCR0_CTIM0F_Pos (4UL) +#define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */ +#define CSI_FCR0_CTIM1F_Pos (5UL) +#define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */ +#define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */ +#define CSI_FCR0_CTIM2F_Pos (6UL) +#define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */ +#define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */ +#define CSI_FCR0_CTIM3F_Pos (7UL) +#define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */ +#define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */ +#define CSI_FCR0_CSOF0F_Pos (8UL) +#define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */ +#define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */ +#define CSI_FCR0_CSOF1F_Pos (9UL) +#define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */ +#define CSI_FCR0_CSOF2F_Pos (10UL) +#define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */ +#define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */ +#define CSI_FCR0_CSOF3F_Pos (11UL) +#define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */ +#define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */ +#define CSI_FCR0_CEOF0F_Pos (12UL) +#define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */ +#define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */ +#define CSI_FCR0_CEOF1F_Pos (13UL) +#define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */ +#define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */ +#define CSI_FCR0_CEOF2F_Pos (14UL) +#define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */ +#define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */ +#define CSI_FCR0_CEOF3F_Pos (15UL) +#define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */ +#define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */ +#define CSI_FCR0_CSPKTF_Pos (16UL) +#define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */ +#define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */ +#define CSI_FCR0_CCCFIFOFF_Pos (21UL) +#define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */ +#define CSI_FCR0_CCRCERRF_Pos (24UL) +#define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */ +#define CSI_FCR0_CECCERRF_Pos (25UL) +#define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */ +#define CSI_FCR0_CCECCERRF_Pos (26UL) +#define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */ +#define CSI_FCR0_CIDERRF_Pos (27UL) +#define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */ +#define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */ +#define CSI_FCR0_CSPKTERRF_Pos (28UL) +#define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */ +#define CSI_FCR0_CWDERRF_Pos (29UL) +#define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */ +#define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */ +#define CSI_FCR0_CSYNCERRF_Pos (30UL) +#define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */ + +/******************* Bit definition for CSI_FCR1 register *******************/ +#define CSI_FCR1_CESOTDL0F_Pos (0UL) +#define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */ +#define CSI_FCR1_CESOTSYNCDL0F_Pos (1UL) +#define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */ +#define CSI_FCR1_CEESCDL0F_Pos (2UL) +#define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL0F_Pos (3UL) +#define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL0F_Pos (4UL) +#define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */ +#define CSI_FCR1_CESOTDL1F_Pos (8UL) +#define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */ +#define CSI_FCR1_CESOTSYNCDL1F_Pos (9UL) +#define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */ +#define CSI_FCR1_CEESCDL1F_Pos (10UL) +#define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL1F_Pos (11UL) +#define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL1F_Pos (12UL) +#define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */ + +/****************** Bit definition for CSI_SPDFR register *******************/ +#define CSI_SPDFR_DATAFIELD_Pos (0UL) +#define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */ +#define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */ +#define CSI_SPDFR_DATATYPE_Pos (16UL) +#define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */ +#define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */ +#define CSI_SPDFR_VCHANNEL_Pos (22UL) +#define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */ +#define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */ + +/******************* Bit definition for CSI_ERR1 register *******************/ +#define CSI_ERR1_CRCDTERR_Pos (0UL) +#define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */ +#define CSI_ERR1_CRCVCERR_Pos (6UL) +#define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */ +#define CSI_ERR1_CECCDTERR_Pos (8UL) +#define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */ +#define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */ +#define CSI_ERR1_CECCVCERR_Pos (14UL) +#define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */ +#define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */ +#define CSI_ERR1_IDDTERR_Pos (16UL) +#define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */ +#define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */ +#define CSI_ERR1_IDVCERR_Pos (22UL) +#define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */ +#define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */ + +/******************* Bit definition for CSI_ERR2 register *******************/ +#define CSI_ERR2_SPKTDTERR_Pos (0UL) +#define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */ +#define CSI_ERR2_SPKTVCERR_Pos (6UL) +#define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */ +#define CSI_ERR2_WDVCERR_Pos (16UL) +#define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */ +#define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */ +#define CSI_ERR2_SYNCVCERR_Pos (18UL) +#define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */ +#define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */ + +/******************* Bit definition for CSI_PRCR register *******************/ +#define CSI_PRCR_PEN_Pos (1UL) +#define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */ +#define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */ + +/******************* Bit definition for CSI_PMCR register *******************/ +#define CSI_PMCR_FRXMDL0_Pos (0UL) +#define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */ +#define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */ +#define CSI_PMCR_FRXMDL1_Pos (1UL) +#define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */ +#define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */ +#define CSI_PMCR_FTXSMDL0_Pos (2UL) +#define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */ +#define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */ +#define CSI_PMCR_DTDL_Pos (4UL) +#define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */ +#define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */ +#define CSI_PMCR_RTDL0_Pos (8UL) +#define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */ +#define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */ +#define CSI_PMCR_TUESDL0_Pos (12UL) +#define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */ +#define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */ +#define CSI_PMCR_TUEXDL0_Pos (16UL) +#define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */ +#define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */ + +/******************* Bit definition for CSI_PFCR register *******************/ +#define CSI_PFCR_CCFR_Pos (0UL) +#define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */ +#define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */ +#define CSI_PFCR_HSFR_Pos (8UL) +#define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */ +#define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */ +#define CSI_PFCR_DLD_Pos (16UL) +#define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */ +#define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */ + +/****************** Bit definition for CSI_PTCR0 register *******************/ +#define CSI_PTCR0_TCKEN_Pos (0UL) +#define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */ +#define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */ +#define CSI_PTCR0_TRSEN_Pos (1UL) +#define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */ +#define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */ + +/****************** Bit definition for CSI_PTCR1 register *******************/ +#define CSI_PTCR1_TDI_Pos (0UL) +#define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */ +#define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */ +#define CSI_PTCR1_TWM_Pos (16UL) +#define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */ +#define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */ + +/******************* Bit definition for CSI_PTSR register *******************/ +#define CSI_PTSR_TDO_Pos (0UL) +#define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */ +#define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */ + + +/*********************************************************************************/ +/* */ +/* DBGMCU */ +/* */ +/*********************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register ****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */ +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */ + +/******************** Bit definition for DBGMCU_CR register ********************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0UL) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1UL) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2UL) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */ +#define DBGMCU_CR_DBGCLKEN_Pos (20UL) +#define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */ +#define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */ +#define DBGMCU_CR_TRACECLKEN_Pos (21UL) +#define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */ +#define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */ +#define DBGMCU_CR_DBTRGOEN_Pos (28UL) +#define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */ +#define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */ +#define DBGMCU_CR_HLT_TSGEN_EN_Pos (31UL) +#define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */ +#define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */ + +/******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0UL) +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1UL) +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2UL) +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3UL) +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4UL) +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5UL) +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6UL) +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7UL) +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8UL) +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9UL) +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11UL) +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12UL) +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13UL) +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21UL) +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22UL) +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23UL) +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24UL) +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25UL) +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */ + +/******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8UL) +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */ + +/******************** Bit definition for DBGMCU_APB2FZ1 register ***************/ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0UL) +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1UL) +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15UL) +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16UL) +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17UL) +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18UL) +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19UL) +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */ + +/******************** Bit definition for DBGMCU_APB4FZ1 register ***************/ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8UL) +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16UL) +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18UL) +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */ + +/******************** Bit definition for DBGMCU_APB5FZ1 register ***************/ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4UL) +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */ + +/******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */ +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos (16UL) +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk /*!< NPU stop in debug mode */ + +/******************** Bit definition for DBGMCU_SR register ***************/ +#define DBGMCU_SR_AP0_PRESENT_Pos (0UL) +#define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */ +#define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */ +#define DBGMCU_SR_AP1_PRESENT_Pos (1UL) +#define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */ +#define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */ +#define DBGMCU_SR_AP0_ENABLE_Pos (16UL) +#define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */ +#define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */ +#define DBGMCU_SR_AP1_ENABLE_Pos (17UL) +#define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */ +#define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */ + +/******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0UL) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1UL) +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */ + + +/******************************************************************************/ +/* */ +/* DCMI */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DCMI_CR register ******************/ +#define DCMI_CR_CAPTURE_Pos (0UL) +#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ +#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk +#define DCMI_CR_CM_Pos (1UL) +#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ +#define DCMI_CR_CM DCMI_CR_CM_Msk +#define DCMI_CR_CROP_Pos (2UL) +#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ +#define DCMI_CR_CROP DCMI_CR_CROP_Msk +#define DCMI_CR_JPEG_Pos (3UL) +#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ +#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk +#define DCMI_CR_ESS_Pos (4UL) +#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ +#define DCMI_CR_ESS DCMI_CR_ESS_Msk +#define DCMI_CR_PCKPOL_Pos (5UL) +#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk +#define DCMI_CR_HSPOL_Pos (6UL) +#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk +#define DCMI_CR_VSPOL_Pos (7UL) +#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk +#define DCMI_CR_FCRC_Pos (8UL) +#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ +#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ +#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ +#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ +#define DCMI_CR_EDM_Pos (10UL) +#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ +#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ +#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ +#define DCMI_CR_ENABLE_Pos (14UL) +#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk +#define DCMI_CR_BSM_Pos (16UL) +#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ +#define DCMI_CR_BSM DCMI_CR_BSM_Msk +#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ +#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ +#define DCMI_CR_OEBS_Pos (18UL) +#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ +#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk +#define DCMI_CR_LSM_Pos (19UL) +#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ +#define DCMI_CR_LSM DCMI_CR_LSM_Msk +#define DCMI_CR_OELS_Pos (20UL) +#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ +#define DCMI_CR_OELS DCMI_CR_OELS_Msk +#define DCMI_CR_PSDM_Pos (31UL) +#define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */ +#define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ + +/******************** Bits definition for DCMI_SR register ******************/ +#define DCMI_SR_HSYNC_Pos (0UL) +#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ +#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk +#define DCMI_SR_VSYNC_Pos (1UL) +#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ +#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk +#define DCMI_SR_FNE_Pos (2UL) +#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ +#define DCMI_SR_FNE DCMI_SR_FNE_Msk + +/******************** Bits definition for DCMI_RIS register ****************/ +#define DCMI_RIS_FRAME_RIS_Pos (0UL) +#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ +#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk +#define DCMI_RIS_OVR_RIS_Pos (1UL) +#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk +#define DCMI_RIS_ERR_RIS_Pos (2UL) +#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ +#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk +#define DCMI_RIS_VSYNC_RIS_Pos (3UL) +#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ +#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk +#define DCMI_RIS_LINE_RIS_Pos (4UL) +#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ +#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk + +/******************** Bits definition for DCMI_IER register *****************/ +#define DCMI_IER_FRAME_IE_Pos (0UL) +#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ +#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk +#define DCMI_IER_OVR_IE_Pos (1UL) +#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk +#define DCMI_IER_ERR_IE_Pos (2UL) +#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ +#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk +#define DCMI_IER_VSYNC_IE_Pos (3UL) +#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ +#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk +#define DCMI_IER_LINE_IE_Pos (4UL) +#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ +#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk + +/******************** Bits definition for DCMI_MIS register *****************/ +#define DCMI_MIS_FRAME_MIS_Pos (0UL) +#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ +#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk +#define DCMI_MIS_OVR_MIS_Pos (1UL) +#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk +#define DCMI_MIS_ERR_MIS_Pos (2UL) +#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ +#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk +#define DCMI_MIS_VSYNC_MIS_Pos (3UL) +#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ +#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk +#define DCMI_MIS_LINE_MIS_Pos (4UL) +#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ +#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk + +/******************** Bits definition for DCMI_ICR register *****************/ +#define DCMI_ICR_FRAME_ISC_Pos (0UL) +#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ +#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk +#define DCMI_ICR_OVR_ISC_Pos (1UL) +#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk +#define DCMI_ICR_ERR_ISC_Pos (2UL) +#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ +#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk +#define DCMI_ICR_VSYNC_ISC_Pos (3UL) +#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ +#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk +#define DCMI_ICR_LINE_ISC_Pos (4UL) +#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ +#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk + +/******************** Bits definition for DCMI_ESCR register ******************/ +#define DCMI_ESCR_FSC_Pos (0UL) +#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk +#define DCMI_ESCR_LSC_Pos (8UL) +#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk +#define DCMI_ESCR_LEC_Pos (16UL) +#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk +#define DCMI_ESCR_FEC_Pos (24UL) +#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk + +/******************** Bits definition for DCMI_ESUR register ******************/ +#define DCMI_ESUR_FSU_Pos (0UL) +#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk +#define DCMI_ESUR_LSU_Pos (8UL) +#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk +#define DCMI_ESUR_LEU_Pos (16UL) +#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk +#define DCMI_ESUR_FEU_Pos (24UL) +#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk + +/******************** Bits definition for DCMI_CWSTRT register ******************/ +#define DCMI_CWSTRT_HOFFCNT_Pos (0UL) +#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk +#define DCMI_CWSTRT_VST_Pos (16UL) +#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ +#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk + +/******************** Bits definition for DCMI_CWSIZE register ******************/ +#define DCMI_CWSIZE_CAPCNT_Pos (0UL) +#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk +#define DCMI_CWSIZE_VLINE_Pos (16UL) +#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ +#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk + +/******************** Bits definition for DCMI_DR register ******************/ +#define DCMI_DR_BYTE0_Pos (0UL) +#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ +#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk +#define DCMI_DR_BYTE1_Pos (8UL) +#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ +#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk +#define DCMI_DR_BYTE2_Pos (16UL) +#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ +#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk +#define DCMI_DR_BYTE3_Pos (24UL) +#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ +#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk + + +/******************************************************************************/ +/* */ +/* DCMIPP */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DCMIPP_IPGR1 register *****************/ +#define DCMIPP_IPGR1_MEMORYPAGE_Pos (0UL) +#define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */ +#define DCMIPP_IPGR1_QOS_MODE_Pos (24UL) +#define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */ +#define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */ + +/***************** Bit definition for DCMIPP_IPGR2 register *****************/ +#define DCMIPP_IPGR2_PSTART_Pos (0UL) +#define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */ + +/***************** Bit definition for DCMIPP_IPGR3 register *****************/ +#define DCMIPP_IPGR3_IDLE_Pos (0UL) +#define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */ + +/***************** Bit definition for DCMIPP_IPGR8 register *****************/ +#define DCMIPP_IPGR8_DID_Pos (0UL) +#define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */ +#define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */ +#define DCMIPP_IPGR8_REVID_Pos (8UL) +#define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */ +#define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */ +#define DCMIPP_IPGR8_ARCHIID_Pos (16UL) +#define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */ +#define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */ +#define DCMIPP_IPGR8_IPPID_Pos (24UL) +#define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */ +#define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */ + +/**************** Bit definition for DCMIPP_IPC1R1 register *****************/ +#define DCMIPP_IPC1R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC1R1_OTR_Pos (8UL) +#define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC1R2 register *****************/ +#define DCMIPP_IPC1R2_WLRU_Pos (16UL) +#define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC1R3 register *****************/ +#define DCMIPP_IPC1R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC1R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC2R1 register *****************/ +#define DCMIPP_IPC2R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC2R1_OTR_Pos (8UL) +#define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC2R2 register *****************/ +#define DCMIPP_IPC2R2_WLRU_Pos (16UL) +#define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC2R3 register *****************/ +#define DCMIPP_IPC2R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC2R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC3R1 register *****************/ +#define DCMIPP_IPC3R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC3R1_OTR_Pos (8UL) +#define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC3R2 register *****************/ +#define DCMIPP_IPC3R2_WLRU_Pos (16UL) +#define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC3R3 register *****************/ +#define DCMIPP_IPC3R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC3R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC4R1 register *****************/ +#define DCMIPP_IPC4R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC4R1_OTR_Pos (8UL) +#define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC4R2 register *****************/ +#define DCMIPP_IPC4R2_WLRU_Pos (16UL) +#define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC4R3 register *****************/ +#define DCMIPP_IPC4R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC4R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC5R1 register *****************/ +#define DCMIPP_IPC5R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC5R1_OTR_Pos (8UL) +#define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC5R2 register *****************/ +#define DCMIPP_IPC5R2_WLRU_Pos (16UL) +#define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC5R3 register *****************/ +#define DCMIPP_IPC5R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC5R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/*************** Bit definition for DCMIPP_PRHWCFGR register ****************/ + +/***************** Bit definition for DCMIPP_PRCR register ******************/ +#define DCMIPP_PRCR_ESS_Pos (4UL) +#define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */ +#define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */ +#define DCMIPP_PRCR_PCKPOL_Pos (5UL) +#define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */ +#define DCMIPP_PRCR_HSPOL_Pos (6UL) +#define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */ +#define DCMIPP_PRCR_VSPOL_Pos (7UL) +#define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */ +#define DCMIPP_PRCR_EDM_Pos (10UL) +#define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */ +#define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */ +#define DCMIPP_PRCR_ENABLE_Pos (14UL) +#define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */ +#define DCMIPP_PRCR_FORMAT_Pos (16UL) +#define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */ +#define DCMIPP_PRCR_SWAPCYCLES_Pos (25UL) +#define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */ +#define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */ +#define DCMIPP_PRCR_SWAPBITS_Pos (26UL) +#define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */ +#define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */ + +/**************** Bit definition for DCMIPP_PRESCR register *****************/ +#define DCMIPP_PRESCR_FSC_Pos (0UL) +#define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */ +#define DCMIPP_PRESCR_LSC_Pos (8UL) +#define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */ +#define DCMIPP_PRESCR_LEC_Pos (16UL) +#define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */ +#define DCMIPP_PRESCR_FEC_Pos (24UL) +#define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */ + +/**************** Bit definition for DCMIPP_PRESUR register *****************/ +#define DCMIPP_PRESUR_FSU_Pos (0UL) +#define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */ +#define DCMIPP_PRESUR_LSU_Pos (8UL) +#define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */ +#define DCMIPP_PRESUR_LEU_Pos (16UL) +#define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */ +#define DCMIPP_PRESUR_FEU_Pos (24UL) +#define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */ + +/***************** Bit definition for DCMIPP_PRIER register *****************/ +#define DCMIPP_PRIER_ERRIE_Pos (6UL) +#define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */ + +/***************** Bit definition for DCMIPP_PRSR register ******************/ +#define DCMIPP_PRSR_ERRF_Pos (6UL) +#define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */ +#define DCMIPP_PRSR_HSYNC_Pos (16UL) +#define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */ +#define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */ +#define DCMIPP_PRSR_VSYNC_Pos (17UL) +#define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */ +#define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */ + +/***************** Bit definition for DCMIPP_PRFCR register *****************/ +#define DCMIPP_PRFCR_CERRF_Pos (6UL) +#define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */ + +/***************** Bit definition for DCMIPP_CMCR register ******************/ +#define DCMIPP_CMCR_INSEL_Pos (0UL) +#define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */ +#define DCMIPP_CMCR_PSFC_Pos (1UL) +#define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */ +#define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */ +#define DCMIPP_CMCR_CFC_Pos (4UL) +#define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */ +#define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */ +#define DCMIPP_CMCR_SWAPRB_Pos (7UL) +#define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */ +#define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */ + +/**************** Bit definition for DCMIPP_CMFRCR register *****************/ +#define DCMIPP_CMFRCR_FRMCNT_Pos (0UL) +#define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */ + +/***************** Bit definition for DCMIPP_CMIER register *****************/ +#define DCMIPP_CMIER_ATXERRIE_Pos (5UL) +#define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */ +#define DCMIPP_CMIER_PRERRIE_Pos (6UL) +#define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */ +#define DCMIPP_CMIER_P0LINEIE_Pos (8UL) +#define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0FRAMEIE_Pos (9UL) +#define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0VSYNCIE_Pos (10UL) +#define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0LIMITIE_Pos (14UL) +#define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0OVRIE_Pos (15UL) +#define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P1LINEIE_Pos (16UL) +#define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */ +#define DCMIPP_CMIER_P1FRAMEIE_Pos (17UL) +#define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1VSYNCIE_Pos (18UL) +#define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1OVRIE_Pos (23UL) +#define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P2LINEIE_Pos (24UL) +#define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2FRAMEIE_Pos (25UL) +#define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2VSYNCIE_Pos (26UL) +#define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2OVRIE_Pos (31UL) +#define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR1 register *****************/ +#define DCMIPP_CMSR1_PRHSYNC_Pos (0UL) +#define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_PRVSYNC_Pos (1UL) +#define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */ +#define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_P0LSTLINE_Pos (8UL) +#define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0LSTFRM_Pos (9UL) +#define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0CPTACT_Pos (15UL) +#define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */ +#define DCMIPP_CMSR1_P1LSTLINE_Pos (16UL) +#define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1LSTFRM_Pos (17UL) +#define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1CPTACT_Pos (23UL) +#define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */ +#define DCMIPP_CMSR1_P2LSTLINE_Pos (24UL) +#define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2LSTFRM_Pos (25UL) +#define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2CPTACT_Pos (31UL) +#define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR2 register *****************/ +#define DCMIPP_CMSR2_ATXERRF_Pos (5UL) +#define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */ +#define DCMIPP_CMSR2_PRERRF_Pos (6UL) +#define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */ +#define DCMIPP_CMSR2_P0LINEF_Pos (8UL) +#define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0FRAMEF_Pos (9UL) +#define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0VSYNCF_Pos (10UL) +#define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0LIMITF_Pos (14UL) +#define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0OVRF_Pos (15UL) +#define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P1LINEF_Pos (16UL) +#define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1FRAMEF_Pos (17UL) +#define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1VSYNCF_Pos (18UL) +#define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1OVRF_Pos (23UL) +#define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P2LINEF_Pos (24UL) +#define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2FRAMEF_Pos (25UL) +#define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2VSYNCF_Pos (26UL) +#define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2OVRF_Pos (31UL) +#define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMFCR register *****************/ +#define DCMIPP_CMFCR_CATXERRF_Pos (5UL) +#define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */ +#define DCMIPP_CMFCR_CPRERRF_Pos (6UL) +#define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */ +#define DCMIPP_CMFCR_CP0LINEF_Pos (8UL) +#define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0FRAMEF_Pos (9UL) +#define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0VSYNCF_Pos (10UL) +#define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP0LIMITF_Pos (14UL) +#define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_CMFCR_CP0OVRF_Pos (15UL) +#define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP1LINEF_Pos (16UL) +#define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1FRAMEF_Pos (17UL) +#define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1VSYNCF_Pos (18UL) +#define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP1OVRF_Pos (23UL) +#define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP2LINEF_Pos (24UL) +#define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2FRAMEF_Pos (25UL) +#define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2VSYNCF_Pos (26UL) +#define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP2OVRF_Pos (31UL) +#define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0FSCR register *****************/ +#define DCMIPP_P0FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */ +#define DCMIPP_P0FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */ +#define DCMIPP_P0FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_VC_Pos (19UL) +#define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P0FCTCR register ****************/ +#define DCMIPP_P0FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P0SCSTR register ****************/ +#define DCMIPP_P0SCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0SCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P0SCSZR register ****************/ +#define DCMIPP_P0SCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0SCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0SCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */ +#define DCMIPP_P0SCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */ + +/*************** Bit definition for DCMIPP_P0DCCNTR register ****************/ +#define DCMIPP_P0DCCNTR_CNT_Pos (0UL) +#define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */ +#define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */ + +/*************** Bit definition for DCMIPP_P0DCLMTR register ****************/ +#define DCMIPP_P0DCLMTR_LIMIT_Pos (0UL) +#define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */ +#define DCMIPP_P0DCLMTR_ENABLE_Pos (31UL) +#define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P0PPCR register *****************/ +#define DCMIPP_P0PPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0PPCR_PAD_Pos (5UL) +#define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0PPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */ +#define DCMIPP_P0PPCR_BSM_Pos (7UL) +#define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */ +#define DCMIPP_P0PPCR_OEBS_Pos (9UL) +#define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */ +#define DCMIPP_P0PPCR_LSM_Pos (10UL) +#define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */ +#define DCMIPP_P0PPCR_OELS_Pos (11UL) +#define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */ +#define DCMIPP_P0PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0PPCR_DBM_Pos (16UL) +#define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */ + +/*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/ +#define DCMIPP_P0PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/ +#define DCMIPP_P0PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */ + +/***************** Bit definition for DCMIPP_P0IER register *****************/ +#define DCMIPP_P0IER_LINEIE_Pos (0UL) +#define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P0IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P0IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P0IER_LIMITIE_Pos (6UL) +#define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */ +#define DCMIPP_P0IER_OVRIE_Pos (7UL) +#define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P0SR register ******************/ +#define DCMIPP_P0SR_LINEF_Pos (0UL) +#define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P0SR_FRAMEF_Pos (1UL) +#define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P0SR_VSYNCF_Pos (2UL) +#define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P0SR_LIMITF_Pos (6UL) +#define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */ +#define DCMIPP_P0SR_OVRF_Pos (7UL) +#define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P0SR_LSTLINE_Pos (16UL) +#define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_LSTFRM_Pos (17UL) +#define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_CPTACT_Pos (23UL) +#define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P0FCR register *****************/ +#define DCMIPP_P0FCR_CLINEF_Pos (0UL) +#define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P0FCR_CLIMITF_Pos (6UL) +#define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_P0FCR_COVRF_Pos (7UL) +#define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0CFSCR register ****************/ +#define DCMIPP_P0CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */ +#define DCMIPP_P0CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */ +#define DCMIPP_P0CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0CFSCR_VC_Pos (19UL) +#define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P0CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P0CFCTCR register ****************/ +#define DCMIPP_P0CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P0CSCSTR register ****************/ +#define DCMIPP_P0CSCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0CSCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P0CSCSZR register ****************/ +#define DCMIPP_P0CSCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0CSCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0CSCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */ +#define DCMIPP_P0CSCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */ + +/**************** Bit definition for DCMIPP_P0CPPCR register ****************/ +#define DCMIPP_P0CPPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0CPPCR_PAD_Pos (5UL) +#define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0CPPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */ +#define DCMIPP_P0CPPCR_BSM_Pos (7UL) +#define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */ +#define DCMIPP_P0CPPCR_OEBS_Pos (9UL) +#define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */ +#define DCMIPP_P0CPPCR_LSM_Pos (10UL) +#define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */ +#define DCMIPP_P0CPPCR_OELS_Pos (11UL) +#define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */ +#define DCMIPP_P0CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0CPPCR_DBM_Pos (16UL) +#define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */ + +/************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/ +#define DCMIPP_P0CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/**************** Bit definition for DCMIPP_P1FSCR register *****************/ +#define DCMIPP_P1FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */ +#define DCMIPP_P1FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */ +#define DCMIPP_P1FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */ +#define DCMIPP_P1FSCR_VC_Pos (19UL) +#define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_FDTF_Pos (24UL) +#define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P1FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P1FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P1SRCR register *****************/ +#define DCMIPP_P1SRCR_LASTLINE_Pos (0UL) +#define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12UL) +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */ +#define DCMIPP_P1SRCR_CROPEN_Pos (15UL) +#define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */ +#define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */ + +/**************** Bit definition for DCMIPP_P1BPRCR register ****************/ +#define DCMIPP_P1BPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */ +#define DCMIPP_P1BPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */ + +/**************** Bit definition for DCMIPP_P1BPRSR register ****************/ +#define DCMIPP_P1BPRSR_BADCNT_Pos (0UL) +#define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */ + +/**************** Bit definition for DCMIPP_P1DECR register *****************/ +#define DCMIPP_P1DECR_ENABLE_Pos (0UL) +#define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DECR_HDEC_Pos (1UL) +#define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DECR_VDEC_Pos (3UL) +#define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1BLCCR register ****************/ +#define DCMIPP_P1BLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */ +#define DCMIPP_P1BLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */ +#define DCMIPP_P1BLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */ +#define DCMIPP_P1BLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR1 register ****************/ +#define DCMIPP_P1EXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */ +#define DCMIPP_P1EXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */ +#define DCMIPP_P1EXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR2 register ****************/ +#define DCMIPP_P1EXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */ +#define DCMIPP_P1EXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */ +#define DCMIPP_P1EXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */ +#define DCMIPP_P1EXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */ + +/**************** Bit definition for DCMIPP_P1ST1CR register ****************/ +#define DCMIPP_P1ST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST1CR_BINS_Pos (2UL) +#define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST1CR_SRC_Pos (4UL) +#define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST1CR_MODE_Pos (7UL) +#define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST2CR register ****************/ +#define DCMIPP_P1ST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST2CR_BINS_Pos (2UL) +#define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST2CR_SRC_Pos (4UL) +#define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST2CR_MODE_Pos (7UL) +#define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST3CR register ****************/ +#define DCMIPP_P1ST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST3CR_BINS_Pos (2UL) +#define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST3CR_SRC_Pos (4UL) +#define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST3CR_MODE_Pos (7UL) +#define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1STSTR register ****************/ +#define DCMIPP_P1STSTR_HSTART_Pos (0UL) +#define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSTR_VSTART_Pos (16UL) +#define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1STSZR register ****************/ +#define DCMIPP_P1STSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1STSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1ST1SR register ****************/ +#define DCMIPP_P1ST1SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST2SR register ****************/ +#define DCMIPP_P1ST2SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST3SR register ****************/ +#define DCMIPP_P1ST3SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1DMCR register *****************/ +#define DCMIPP_P1DMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DMCR_TYPE_Pos (1UL) +#define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */ +#define DCMIPP_P1DMCR_PEAK_Pos (16UL) +#define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */ +#define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */ +#define DCMIPP_P1DMCR_LINEV_Pos (20UL) +#define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */ +#define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */ +#define DCMIPP_P1DMCR_LINEH_Pos (24UL) +#define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */ +#define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */ +#define DCMIPP_P1DMCR_EDGE_Pos (28UL) +#define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */ + +/**************** Bit definition for DCMIPP_P1CCCR register *****************/ +#define DCMIPP_P1CCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/**************** Bit definition for DCMIPP_P1CCRR1 register ****************/ +#define DCMIPP_P1CCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCRR2 register ****************/ +#define DCMIPP_P1CCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCGR1 register ****************/ +#define DCMIPP_P1CCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCGR2 register ****************/ +#define DCMIPP_P1CCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCBR1 register ****************/ +#define DCMIPP_P1CCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCBR2 register ****************/ +#define DCMIPP_P1CCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CTCR1 register ****************/ +#define DCMIPP_P1CTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */ +#define DCMIPP_P1CTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR2 register ****************/ +#define DCMIPP_P1CTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR3 register ****************/ +#define DCMIPP_P1CTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1FCTCR register ****************/ +#define DCMIPP_P1FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P1CRSTR register ****************/ +#define DCMIPP_P1CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CRSZR register ****************/ +#define DCMIPP_P1CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1DCCR register *****************/ +#define DCMIPP_P1DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1DCCR_HDEC_Pos (1UL) +#define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DCCR_VDEC_Pos (3UL) +#define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1DSCR register *****************/ +#define DCMIPP_P1DSCR_HDIV_Pos (0UL) +#define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_VDIV_Pos (16UL) +#define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */ + +/*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/ +#define DCMIPP_P1DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P1DSSZR register ****************/ +#define DCMIPP_P1DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CMRICR register ***************/ +#define DCMIPP_P1CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P1CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P1CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P1CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P1CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P1CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P1CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P1CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P1CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/ +#define DCMIPP_P1RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P1RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P1RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P1RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P1RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/ +#define DCMIPP_P1RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P1RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P1GMCR register *****************/ +#define DCMIPP_P1GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/ + +/**************** Bit definition for DCMIPP_P1YUVCR register ****************/ +#define DCMIPP_P1YUVCR_ENABLE_Pos (0UL) +#define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1YUVCR_TYPE_Pos (1UL) +#define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */ +#define DCMIPP_P1YUVCR_CLAMP_Pos (2UL) +#define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/ +#define DCMIPP_P1YUVRR1_RR_Pos (0UL) +#define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1YUVRR1_RG_Pos (16UL) +#define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/ +#define DCMIPP_P1YUVRR2_RB_Pos (0UL) +#define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1YUVRR2_RA_Pos (16UL) +#define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/ +#define DCMIPP_P1YUVGR1_GR_Pos (0UL) +#define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1YUVGR1_GG_Pos (16UL) +#define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/ +#define DCMIPP_P1YUVGR2_GB_Pos (0UL) +#define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1YUVGR2_GA_Pos (16UL) +#define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/ +#define DCMIPP_P1YUVBR1_BR_Pos (0UL) +#define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1YUVBR1_BG_Pos (16UL) +#define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/ +#define DCMIPP_P1YUVBR2_BB_Pos (0UL) +#define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1YUVBR2_BA_Pos (16UL) +#define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1PPCR register *****************/ +#define DCMIPP_P1PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P1PPCR_DBM_Pos (16UL) +#define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P1PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P1PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/ +#define DCMIPP_P1PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/ +#define DCMIPP_P1PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */ + +/*************** Bit definition for DCMIPP_P1PPM0PR register ****************/ +#define DCMIPP_P1PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/ +#define DCMIPP_P1PPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/ +#define DCMIPP_P1PPM1AR2_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1PR register ****************/ +#define DCMIPP_P1PPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1STM1AR register ****************/ +#define DCMIPP_P1STM1AR_M1A_Pos (0UL) +#define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */ + +/*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/ +#define DCMIPP_P1PPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/ +#define DCMIPP_P1PPM2AR2_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */ + +/*************** Bit definition for DCMIPP_P1STM2AR register ****************/ +#define DCMIPP_P1STM2AR_M2A_Pos (0UL) +#define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */ + +/***************** Bit definition for DCMIPP_P1IER register *****************/ +#define DCMIPP_P1IER_LINEIE_Pos (0UL) +#define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P1IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P1IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P1IER_OVRIE_Pos (7UL) +#define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P1SR register ******************/ +#define DCMIPP_P1SR_LINEF_Pos (0UL) +#define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P1SR_FRAMEF_Pos (1UL) +#define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P1SR_VSYNCF_Pos (2UL) +#define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P1SR_OVRF_Pos (7UL) +#define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P1SR_LSTLINE_Pos (16UL) +#define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_LSTFRM_Pos (17UL) +#define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_CPTACT_Pos (23UL) +#define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P1FCR register *****************/ +#define DCMIPP_P1FCR_CLINEF_Pos (0UL) +#define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P1FCR_COVRF_Pos (7UL) +#define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P1CFSCR register ****************/ +#define DCMIPP_P1CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */ +#define DCMIPP_P1CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */ +#define DCMIPP_P1CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */ +#define DCMIPP_P1CFSCR_VC_Pos (19UL) +#define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P1CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P1CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P1CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P1CBPRCR register ****************/ +#define DCMIPP_P1CBPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */ +#define DCMIPP_P1CBPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */ + +/*************** Bit definition for DCMIPP_P1CBLCCR register ****************/ +#define DCMIPP_P1CBLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */ +#define DCMIPP_P1CBLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */ +#define DCMIPP_P1CBLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */ +#define DCMIPP_P1CBLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/ +#define DCMIPP_P1CEXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */ +#define DCMIPP_P1CEXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */ +#define DCMIPP_P1CEXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/ +#define DCMIPP_P1CEXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */ +#define DCMIPP_P1CEXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */ +#define DCMIPP_P1CEXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */ +#define DCMIPP_P1CEXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */ + +/*************** Bit definition for DCMIPP_P1CST1CR register ****************/ +#define DCMIPP_P1CST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */ +#define DCMIPP_P1CST1CR_BINS_Pos (2UL) +#define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */ +#define DCMIPP_P1CST1CR_SRC_Pos (4UL) +#define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */ +#define DCMIPP_P1CST1CR_MODE_Pos (7UL) +#define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */ +#define DCMIPP_P1CST1CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST2CR register ****************/ +#define DCMIPP_P1CST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST2CR_BINS_Pos (2UL) +#define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST2CR_SRC_Pos (4UL) +#define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */ +#define DCMIPP_P1CST2CR_MODE_Pos (7UL) +#define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */ +#define DCMIPP_P1CST2CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST3CR register ****************/ +#define DCMIPP_P1CST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST3CR_BINS_Pos (2UL) +#define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST3CR_SRC_Pos (4UL) +#define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1CST3CR_MODE_Pos (7UL) +#define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */ +#define DCMIPP_P1CST3CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CSTSTR register ****************/ +#define DCMIPP_P1CSTSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CSTSZR register ****************/ +#define DCMIPP_P1CSTSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CSTSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */ + +/**************** Bit definition for DCMIPP_P1CCCCR register ****************/ +#define DCMIPP_P1CCCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */ +#define DCMIPP_P1CCCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/ +#define DCMIPP_P1CCCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/ +#define DCMIPP_P1CCCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/ +#define DCMIPP_P1CCCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/ +#define DCMIPP_P1CCCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/ +#define DCMIPP_P1CCCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/ +#define DCMIPP_P1CCCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/ +#define DCMIPP_P1CCTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */ +#define DCMIPP_P1CCTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/ +#define DCMIPP_P1CCTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/ +#define DCMIPP_P1CCTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CFCTCR register ****************/ +#define DCMIPP_P1CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P1CCRSTR register ****************/ +#define DCMIPP_P1CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CCRSZR register ****************/ +#define DCMIPP_P1CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P1CDCCR register *****************/ +#define DCMIPP_P1CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1CDSCR register ****************/ +#define DCMIPP_P1CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/ +#define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P1CDSSZR register ****************/ +#define DCMIPP_P1CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CPPCR register ****************/ +#define DCMIPP_P1CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ + +/************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/ +#define DCMIPP_P1CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/ +#define DCMIPP_P1CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/ +#define DCMIPP_P1CPPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/ +#define DCMIPP_P1CPPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/ +#define DCMIPP_P1CPPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */ + +/**************** Bit definition for DCMIPP_P2FSCR register *****************/ +#define DCMIPP_P2FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */ +#define DCMIPP_P2FSCR_VC_Pos (19UL) +#define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P2FSCR_FDTF_Pos (24UL) +#define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P2FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P2FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P2FCTCR register ****************/ +#define DCMIPP_P2FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P2CRSTR register ****************/ +#define DCMIPP_P2CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CRSZR register ****************/ +#define DCMIPP_P2CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P2DCCR register *****************/ +#define DCMIPP_P2DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2DCCR_HDEC_Pos (1UL) +#define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2DCCR_VDEC_Pos (3UL) +#define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2DSCR register *****************/ +#define DCMIPP_P2DSCR_HDIV_Pos (0UL) +#define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_VDIV_Pos (16UL) +#define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/ +#define DCMIPP_P2DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P2DSSZR register ****************/ +#define DCMIPP_P2DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2GMCR register *****************/ +#define DCMIPP_P2GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2CMRICR register ***************/ +#define DCMIPP_P2CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P2CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P2CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P2CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P2CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P2CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P2CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P2CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P2CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/ +#define DCMIPP_P2RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P2RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P2RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P2RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P2RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/ +#define DCMIPP_P2RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P2RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P2PPCR register *****************/ +#define DCMIPP_P2PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2PPCR_DBM_Pos (16UL) +#define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/ +#define DCMIPP_P2PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */ + +/*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/ +#define DCMIPP_P2PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2STM0AR_Pos (0UL) +#define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */ + +/***************** Bit definition for DCMIPP_P2IER register *****************/ +#define DCMIPP_P2IER_LINEIE_Pos (0UL) +#define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P2IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P2IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P2IER_OVRIE_Pos (7UL) +#define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P2SR register ******************/ +#define DCMIPP_P2SR_LINEF_Pos (0UL) +#define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P2SR_FRAMEF_Pos (1UL) +#define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P2SR_VSYNCF_Pos (2UL) +#define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P2SR_OVRF_Pos (7UL) +#define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P2SR_LSTLINE_Pos (16UL) +#define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_LSTFRM_Pos (17UL) +#define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_CPTACT_Pos (23UL) +#define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P2FCR register *****************/ +#define DCMIPP_P2FCR_CLINEF_Pos (0UL) +#define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P2FCR_COVRF_Pos (7UL) +#define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P2CFSCR register ****************/ +#define DCMIPP_P2CFSCR_DTID_Pos (0UL) +#define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */ +#define DCMIPP_P2CFSCR_VC_Pos (19UL) +#define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P2CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P2CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P2CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P2CFCTCR register ****************/ +#define DCMIPP_P2CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P2CCRSTR register ****************/ +#define DCMIPP_P2CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P2CCRSZR register ****************/ +#define DCMIPP_P2CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P2CDCCR register *****************/ +#define DCMIPP_P2CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2CDSCR register ****************/ +#define DCMIPP_P2CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/ +#define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P2CDSSZR register ****************/ +#define DCMIPP_P2CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CPPCR register ****************/ +#define DCMIPP_P2CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2CPPCR_DBM_Pos (16UL) +#define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2CPPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2CPPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/ +#define DCMIPP_P2CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/ +#define DCMIPP_P2CPPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */ + +/*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/ +#define DCMIPP_P2CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/**************** Bit definition for DCMIPP_HWCFGR2 register ****************/ +#define DCMIPP_HWCFGR2_VPFT_Pos (0UL) +#define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */ +#define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */ +#define DCMIPP_HWCFGR2_DBMFT_Pos (4UL) +#define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */ +#define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */ +#define DCMIPP_HWCFGR2_PROCCLK_Pos (8UL) +#define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */ +#define DCMIPP_HWCFGR2_ADDMOD_Pos (12UL) +#define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */ +#define DCMIPP_HWCFGR2_DEC1_Pos (16UL) +#define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */ +#define DCMIPP_HWCFGR2_DEC2_Pos (17UL) +#define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */ +#define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */ +#define DCMIPP_HWCFGR2_MCU_Pos (20UL) +#define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */ +#define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */ +#define DCMIPP_HWCFGR2_TPG_Pos (24UL) +#define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */ +#define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */ +#define DCMIPP_HWCFGR2_STV_Pos (28UL) +#define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */ +#define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */ + +/**************** Bit definition for DCMIPP_HWCFGR1 register ****************/ +#define DCMIPP_HWCFGR1_CSIFT_Pos (0UL) +#define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */ +#define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */ +#define DCMIPP_HWCFGR1_PIPENB_Pos (4UL) +#define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */ +#define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */ +#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8UL) +#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */ +#define DCMIPP_HWCFGR1_DSP1FT_Pos (12UL) +#define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */ +#define DCMIPP_HWCFGR1_DSP2FT_Pos (13UL) +#define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */ +#define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */ +#define DCMIPP_HWCFGR1_RB2RGB_Pos (16UL) +#define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */ +#define DCMIPP_HWCFGR1_PLANARFT_Pos (20UL) +#define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */ +#define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI1NB_Pos (24UL) +#define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */ +#define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI2NB_Pos (28UL) +#define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */ +#define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */ + +/***************** Bit definition for DCMIPP_VERR register ******************/ +#define DCMIPP_VERR_MINREV_Pos (0UL) +#define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */ +#define DCMIPP_VERR_MAJREV_Pos (4UL) +#define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */ + +/***************** Bit definition for DCMIPP_IPIDR register *****************/ +#define DCMIPP_IPIDR_IDR_Pos (0UL) +#define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */ + +/***************** Bit definition for DCMIPP_SIDR register ******************/ +#define DCMIPP_SIDR_SID_Pos (0UL) +#define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */ + +/******************************************************************************/ +/* */ +/* Delay Block Interface (DLYBSD) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DLYBSD_CFGR register ********************/ +#define DLYB_CFGR_SDMMC_DLL_EN_Pos (0UL) +#define DLYB_CFGR_SDMMC_DLL_EN_Msk (0x1UL << DLYB_CFGR_SDMMC_DLL_EN_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SDMMC_DLL_EN DLYB_CFGR_SDMMC_DLL_EN_Msk /*!= AAW[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWHPCR_WHSPPOS_Pos (16UL) +#define LTDC_LxWHPCR_WHSPPOS_Msk (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos) +#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxWVPCR register */ +#define LTDC_LxWVPCR_WVSTPOS_Pos (0UL) +#define LTDC_LxWVPCR_WVSTPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos) +#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWVPCR_WVSPPOS_Pos (16UL) +#define LTDC_LxWVPCR_WVSPPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos) +#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxCKCR register */ +#define LTDC_LxCKCR_CKBLUE_Pos (0UL) +#define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos) +#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */ +#define LTDC_LxCKCR_CKGREEN_Pos (8UL) +#define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos) +#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */ +#define LTDC_LxCKCR_CKRED_Pos (16UL) +#define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos) +#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */ + +/* Bit fields for LTDC_LxPFCR register */ +#define LTDC_LxPFCR_PF_Pos (0UL) +#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) +#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */ + +/* Bit fields for LTDC_LxCACR register */ +#define LTDC_LxCACR_CONSTA_Pos (0UL) +#define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos) +#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */ + +/* Bit fields for LTDC_LxDCCR register */ +#define LTDC_LxDCCR_DCBLUE_Pos (0UL) +#define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos) +#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */ +#define LTDC_LxDCCR_DCGREEN_Pos (8UL) +#define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos) +#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */ +#define LTDC_LxDCCR_DCRED_Pos (16UL) +#define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos) +#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */ +#define LTDC_LxDCCR_DCALPHA_Pos (24UL) +#define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos) +#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */ + +/* Bit fields for LTDC_LxBFCR register */ +#define LTDC_LxBFCR_BF2_Pos (0UL) +#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) +#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */ +#define LTDC_LxBFCR_BF1_Pos (8UL) +#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) +#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */ +#define LTDC_LxBFCR_BOR_Pos (16UL) +#define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos) +#define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */ + +/* Bit fields for LTDC_LxBLCR register */ +#define LTDC_LxBLCR_BL_Pos (0UL) +#define LTDC_LxBLCR_BL_Msk (0x1fUL << LTDC_LxBLCR_BL_Pos) +#define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */ + +/* Bit fields for LTDC_LxPCR register */ +#define LTDC_LxPCR_YCEN_Pos (3UL) +#define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos) +#define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */ +#define LTDC_LxPCR_YCM_Pos (4UL) +#define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos) +#define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */ +#define LTDC_LxPCR_YF_Pos (6UL) +#define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos) +#define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */ +#define LTDC_LxPCR_CBF_Pos (7UL) +#define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos) +#define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */ +#define LTDC_LxPCR_OF_Pos (8UL) +#define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos) +#define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */ +#define LTDC_LxPCR_YREN_Pos (9UL) +#define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos) +#define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */ + +/* Bit fields for LTDC_LxCFBAR register */ +#define LTDC_LxCFBAR_CFBADD_Pos (0UL) +#define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos) +#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxCFBLR register */ +#define LTDC_LxCFBLR_CFBLL_Pos (0UL) +#define LTDC_LxCFBLR_CFBLL_Msk (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos) +#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_LxCFBLR_CFBP_Pos (16UL) +#define LTDC_LxCFBLR_CFBP_Msk (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos) +#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxCFBLNR register */ +#define LTDC_LxCFBLNR_CFBLNBR_Pos (0UL) +#define LTDC_LxCFBLNR_CFBLNBR_Msk (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos) +#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_L1AFBA0R register */ +#define LTDC_L1AFBA0R_AFBADD0_Pos (0UL) +#define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos) +#define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBA1R register */ +#define LTDC_L1AFBA1R_AFBADD1_Pos (0UL) +#define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos) +#define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBLR register */ +#define LTDC_L1AFBLR_AFBLL_Pos (0UL) +#define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos) +#define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_L1AFBLR_AFBP_Pos (16UL) +#define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos) +#define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxAFBLNR register */ +#define LTDC_L1AFBLNR_AFBLNBR_Pos (0UL) +#define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos) +#define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_LxCLUTWR register */ +#define LTDC_LxCLUTWR_BLUE_Pos (0UL) +#define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos) +#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */ +#define LTDC_LxCLUTWR_GREEN_Pos (8UL) +#define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos) +#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */ +#define LTDC_LxCLUTWR_RED_Pos (16UL) +#define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos) +#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */ +#define LTDC_LxCLUTWR_CLUTADD_Pos (24UL) +#define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos) +#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */ + +/* Bit fields for LTDC_LxCYR0R register */ +#define LTDC_LxCYR0R_CR2R_Pos (0UL) +#define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos) +#define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR0R_CB2B_Pos (16UL) +#define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos) +#define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxCYR1R register */ +#define LTDC_LxCYR1R_CR2G_Pos (0UL) +#define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos) +#define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR1R_CB2G_Pos (16UL) +#define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos) +#define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxFPF0R register */ +#define LTDC_LxFPF0R_APOS_Pos (0UL) +#define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos) +#define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_ALEN_Pos (5UL) +#define LTDC_LxFPF0R_ALEN_Msk (0xfUL << LTDC_LxFPF0R_ALEN_Pos) +#define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF0R_RPOS_Pos (9UL) +#define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos) +#define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_RLEN_Pos (14UL) +#define LTDC_LxFPF0R_RLEN_Msk (0xfUL << LTDC_LxFPF0R_RLEN_Pos) +#define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */ + +/* Bit fields for LTDC_LxFPF1R register */ +#define LTDC_LxFPF1R_GPOS_Pos (0UL) +#define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos) +#define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_GLEN_Pos (5UL) +#define LTDC_LxFPF1R_GLEN_Msk (0xfUL << LTDC_LxFPF1R_GLEN_Pos) +#define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF1R_BPOS_Pos (9UL) +#define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos) +#define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_BLEN_Pos (14UL) +#define LTDC_LxFPF1R_BLEN_Msk (0xfUL << LTDC_LxFPF1R_BLEN_Pos) +#define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */ + +#define LTDC_LxFPF1R_PSIZE_Pos (18UL) +#define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos) +#define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */ + + +/******************************************************************************/ +/* */ +/* Memory Cipher Engine (MCE) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for MCE_CR register ********************/ +#define MCE_CR_GLOCK_Pos (0UL) +#define MCE_CR_GLOCK_Msk (0x1UL << MCE_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define MCE_CR_GLOCK MCE_CR_GLOCK_Msk /*!< MCE global lock */ +#define MCE_CR_MKLOCK_Pos (1UL) +#define MCE_CR_MKLOCK_Msk (0x1UL << MCE_CR_MKLOCK_Pos) /*!< 0x00000002 */ +#define MCE_CR_MKLOCK MCE_CR_MKLOCK_Msk /*!< MCE master and fast master keys lock */ +#define MCE_CR_CIPHERSEL_Pos (4UL) +#define MCE_CR_CIPHERSEL_Msk (0x3UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000030 */ +#define MCE_CR_CIPHERSEL MCE_CR_CIPHERSEL_Msk /*!< MCE Cipher selection */ +#define MCE_CR_CIPHERSEL_0 (0x1UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000010 */ +#define MCE_CR_CIPHERSEL_1 (0x2UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000020 */ + +/******************** Bit definition for MCE_SR register ********************/ +#define MCE_SR_MKVALID_Pos (0UL) +#define MCE_SR_MKVALID_Msk (0x1UL << MCE_SR_MKVALID_Pos) /*!< 0x00000001 */ +#define MCE_SR_MKVALID MCE_SR_MKVALID_Msk /*!< MCE master key valid flag */ +#define MCE_SR_FMKVALID_Pos (2UL) +#define MCE_SR_FMKVALID_Msk (0x1UL << MCE_SR_FMKVALID_Pos) /*!< 0x00000004 */ +#define MCE_SR_FMKVALID MCE_SR_FMKVALID_Msk /*!< MCE fast master key valid flag */ +#define MCE_SR_ENCDIS_Pos (4UL) +#define MCE_SR_ENCDIS_Msk (0x1UL << MCE_SR_ENCDIS_Pos) /*!< 0x00000010 */ +#define MCE_SR_ENCDIS MCE_SR_ENCDIS_Msk /*!< MCE encryption disabled flag */ + +/******************** Bit definition for MCE_IASR register ******************/ +#define MCE_IASR_IAEF_Pos (1UL) +#define MCE_IASR_IAEF_Msk (0x1UL << MCE_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define MCE_IASR_IAEF MCE_IASR_IAEF_Msk /*!< MCE illegal access error flag */ + +/******************** Bit definition for MCE_IACR register ******************/ +#define MCE_IACR_IAEF_Pos (1UL) +#define MCE_IACR_IAEF_Msk (0x1UL << MCE_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define MCE_IACR_IAEF MCE_IACR_IAEF_Msk /*!< MCE illegal access error clear bit */ + +/******************** Bit definition for MCE_IAIER register *****************/ +#define MCE_IAIER_IAEIE_Pos (1UL) +#define MCE_IAIER_IAEIE_Msk (0x1UL << MCE_IAIER_IAEIE_Pos) /*!< 0x00000002 */ +#define MCE_IAIER_IAEIE MCE_IAIER_IAEIE_Msk /*!< MCE illegal access error interrupt enable */ + +/******************** Bit definition for MCE_IADDR register *****************/ +#define MCE_IADDR_IADD_Pos (0UL) +#define MCE_IADDR_IADD_Msk (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define MCE_IADDR_IADD MCE_IADDR_IADD_Msk /*!< MCE illegal access */ + +/******************** Bit definition for MCE_REGCR register *****************/ +#define MCE_REGCR_BREN_Pos (0UL) +#define MCE_REGCR_BREN_Msk (0x1UL << MCE_REGCR_BREN_Pos) /*!< 0x00000001 */ +#define MCE_REGCR_BREN MCE_REGCR_BREN_Msk /*!< MCE base region enable */ +#define MCE_REGCR_CTXID_Pos (9UL) +#define MCE_REGCR_CTXID_Msk (0x3UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000600 */ +#define MCE_REGCR_CTXID MCE_REGCR_CTXID_Msk /*!< MCE context ID */ +#define MCE_REGCR_CTXID_0 (0x1UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000200 */ +#define MCE_REGCR_CTXID_1 (0x2UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000400 */ +#define MCE_REGCR_ENC_Pos (14UL) +#define MCE_REGCR_ENC_Msk (0x3UL << MCE_REGCR_ENC_Pos) /*!< 0x0000C000 */ +#define MCE_REGCR_ENC MCE_REGCR_ENC_Msk /*!< MCE encrypted region */ +#define MCE_REGCR_ENC_0 (0x1UL << MCE_REGCR_ENC_Pos) /*!< 0x00004000 */ +#define MCE_REGCR_ENC_1 (0x2UL << MCE_REGCR_ENC_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for MCE_SADDR register *****************/ +#define MCE_SADDR_BADDSTART_Pos (12UL) +#define MCE_SADDR_BADDSTART_Msk (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos) /*!< 0xFFFFF000 */ +#define MCE_SADDR_BADDSTART MCE_SADDR_BADDSTART_Msk /*!< MCE region address start */ + +/******************** Bit definition for MCE_EADDR register *****************/ +#define MCE_EADDR_BADDEND_Pos (12UL) +#define MCE_EADDR_BADDEND_Msk (0xFFFFFUL << MCE_EADDR_BADDEND_Pos) /*!< 0xFFFFF000 */ +#define MCE_EADDR_BADDEND MCE_EADDR_BADDEND_Msk /*!< MCE region address end */ + +/******************** Bit definition for MCE_MKEYR0 register ****************/ +#define MCE_MKEYR0_MKEY_Pos (0UL) +#define MCE_MKEYR0_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR0_MKEY MCE_MKEYR0_MKEY_Msk /*!< MCE master key, bits [31:0] */ + +/******************** Bit definition for MCE_MKEYR1 register ****************/ +#define MCE_MKEYR1_MKEY_Pos (0UL) +#define MCE_MKEYR1_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR1_MKEY MCE_MKEYR1_MKEY_Msk /*!< MCE master key, bits [63:32] */ + +/******************** Bit definition for MCE_MKEYR2 register ****************/ +#define MCE_MKEYR2_MKEY_Pos (0UL) +#define MCE_MKEYR2_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR2_MKEY MCE_MKEYR2_MKEY_Msk /*!< MCE master key, bits [95:64] */ + +/******************** Bit definition for MCE_MKEYR3 register ****************/ +#define MCE_MKEYR3_MKEY_Pos (0UL) +#define MCE_MKEYR3_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR3_MKEY MCE_MKEYR3_MKEY_Msk /*!< MCE master key, bits [127:96] */ + +/******************** Bit definition for MCE_MKEYR4 register ****************/ +#define MCE_MKEYR4_MKEY_Pos (0UL) +#define MCE_MKEYR4_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR4_MKEY MCE_MKEYR4_MKEY_Msk /*!< MCE master key, bits [159:128] */ + +/******************** Bit definition for MCE_MKEYR5 register ****************/ +#define MCE_MKEYR5_MKEY_Pos (0UL) +#define MCE_MKEYR5_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR5_MKEY MCE_MKEYR5_MKEY_Msk /*!< MCE master key, bits [191:160] */ + +/******************** Bit definition for MCE_MKEYR6 register ****************/ +#define MCE_MKEYR6_MKEY_Pos (0UL) +#define MCE_MKEYR6_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR6_MKEY MCE_MKEYR6_MKEY_Msk /*!< MCE master key, bits [223:192] */ + +/******************** Bit definition for MCE_MKEYR7 register ****************/ +#define MCE_MKEYR7_MKEY_Pos (0UL) +#define MCE_MKEYR7_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR7_MKEY MCE_MKEYR7_MKEY_Msk /*!< MCE master key, bits [255:224] */ + +/******************** Bit definition for MCE_FMKEYR0 register ***************/ +#define MCE_FMKEYR0_FMKEY_Pos (0UL) +#define MCE_FMKEYR0_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR0_FMKEY MCE_FMKEYR0_FMKEY_Msk /*!< MCE fast master key, bits [31:0] */ + +/******************** Bit definition for MCE_FMKEYR1 register ***************/ +#define MCE_FMKEYR1_FMKEY_Pos (0UL) +#define MCE_FMKEYR1_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR1_FMKEY MCE_FMKEYR1_FMKEY_Msk /*!< MCE fast master key, bits [63:32] */ + +/******************** Bit definition for MCE_FMKEYR2 register ***************/ +#define MCE_FMKEYR2_FMKEY_Pos (0UL) +#define MCE_FMKEYR2_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR2_FMKEY MCE_FMKEYR2_FMKEY_Msk /*!< MCE fast master key, bits [95:64] */ + +/******************** Bit definition for MCE_FMKEYR3 register ***************/ +#define MCE_FMKEYR3_FMKEY_Pos (0UL) +#define MCE_FMKEYR3_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR3_FMKEY MCE_FMKEYR3_FMKEY_Msk /*!< MCE fast master key, bits [127:96] */ + +/******************** Bit definition for MCE_FMKEYR4 register ****************/ +#define MCE_FMKEYR4_FMKEY_Pos (0UL) +#define MCE_FMKEYR4_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR4_FMKEY MCE_FMKEYR4_FMKEY_Msk /*!< MCE fast master key, bits [159:128] */ + +/******************** Bit definition for MCE_FMKEYR5 register ****************/ +#define MCE_FMKEYR5_FMKEY_Pos (0UL) +#define MCE_FMKEYR5_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR5_FMKEY MCE_FMKEYR5_FMKEY_Msk /*!< MCE fast master key, bits [191:160] */ + +/******************** Bit definition for MCE_FMKEYR6 register ****************/ +#define MCE_FMKEYR6_FMKEY_Pos (0UL) +#define MCE_FMKEYR6_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR6_FMKEY MCE_FMKEYR6_FMKEY_Msk /*!< MCE fast master key, bits [223:192] */ + +/******************** Bit definition for MCE_FMKEYR7 register ****************/ +#define MCE_FMKEYR7_FMKEY_Pos (0UL) +#define MCE_FMKEYR7_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR7_FMKEY MCE_FMKEYR7_FMKEY_Msk /*!< MCE fast master key, bits [255:224] */ + +/******************** Bit definition for MCE_CCCFGR register ****************/ +#define MCE_CCCFGR_CCEN_Pos (0UL) +#define MCE_CCCFGR_CCEN_Msk (0x1UL << MCE_CCCFGR_CCEN_Pos) /*!< 0x00000001 */ +#define MCE_CCCFGR_CCEN MCE_CCCFGR_CCEN_Msk /*!< MCE cipher context enable */ +#define MCE_CCCFGR_CCLOCK_Pos (1UL) +#define MCE_CCCFGR_CCLOCK_Msk (0x1UL << MCE_CCCFGR_CCLOCK_Pos) /*!< 0x00000002 */ +#define MCE_CCCFGR_CCLOCK MCE_CCCFGR_CCLOCK_Msk /*!< MCE cipher context lock */ +#define MCE_CCCFGR_KEYLOCK_Pos (2UL) +#define MCE_CCCFGR_KEYLOCK_Msk (0x1UL << MCE_CCCFGR_KEYLOCK_Pos) /*!< 0x00000004 */ +#define MCE_CCCFGR_KEYLOCK MCE_CCCFGR_KEYLOCK_Msk /*!< MCE cipher context key lock */ +#define MCE_CCCFGR_MODE_Pos (4UL) +#define MCE_CCCFGR_MODE_Msk (0x3UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000030 */ +#define MCE_CCCFGR_MODE MCE_CCCFGR_MODE_Msk /*!< MCE authorized cipher mode */ +#define MCE_CCCFGR_MODE_0 (0x1UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000010 */ +#define MCE_CCCFGR_MODE_1 (0x2UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000020 */ +#define MCE_CCCFGR_KEYCRC_Pos (8UL) +#define MCE_CCCFGR_KEYCRC_Msk (0xFFUL << MCE_CCCFGR_KEYCRC_Pos) /*!< 0x0000FF00 */ +#define MCE_CCCFGR_KEYCRC MCE_CCCFGR_KEYCRC_Msk /*!< MCE cipher context key CRC */ +#define MCE_CCCFGR_VERSION_Pos (16UL) +#define MCE_CCCFGR_VERSION_Msk (0xFFFFUL << MCE_CCCFGR_VERSION_Pos) /*!< 0xFFFF0000 */ +#define MCE_CCCFGR_VERSION MCE_CCCFGR_VERSION_Msk /*!< MCE cipher context version */ + +/******************** Bit definition for MCE_CCNR0 register *****************/ +#define MCE_CCNR0_SCNONCE_Pos (0UL) +#define MCE_CCNR0_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCNR0_SCNONCE MCE_CCNR0_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [31:0] */ + +/******************** Bit definition for MCE_CCNR1 register ****************/ +#define MCE_CCNR1_SCNONCE_Pos (0UL) +#define MCE_CCNR1_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCNR1_SCNONCE MCE_CCNR1_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [63:32] */ + +/******************** Bit definition for MCE_CCKEYR0 register ***************/ +#define MCE_CCKEYR0_KEY_Pos (0UL) +#define MCE_CCKEYR0_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR0_KEY MCE_CCKEYR0_KEY_Msk /*!< MCE cipher context key, bits [31:0] */ + +/******************** Bit definition for MCE_CCKEYR1 register ***************/ +#define MCE_CCKEYR1_KEY_Pos (0UL) +#define MCE_CCKEYR1_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR1_KEY MCE_CCKEYR1_KEY_Msk /*!< MCE fast master key, bits [63:32] */ + +/******************** Bit definition for MCE_CCKEYR2 register ***************/ +#define MCE_CCKEYR2_KEY_Pos (0UL) +#define MCE_CCKEYR2_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR2_KEY MCE_CCKEYR2_KEY_Msk /*!< MCE fast master key, bits [95:64] */ + +/******************** Bit definition for MCE_CCKEYR3 register ***************/ +#define MCE_CCKEYR3_KEY_Pos (0UL) +#define MCE_CCKEYR3_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR3_KEY MCE_CCKEYR3_KEY_Msk /*!< MCE fast master key, bits [127:96] */ + + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ****************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */ +#define MDF_GCR_ILVNB_Pos (4UL) +#define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */ +#define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */ + +/******************* Bit definition for MDF/ADF_CKGCR register ********************/ +#define MDF_CKGCR_CKDEN_Pos (0UL) +#define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */ +#define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5UL) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6UL) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8UL) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10UL) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14UL) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18UL) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29UL) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30UL) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31UL) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2UL) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3UL) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register *******************/ +#define PSSI_RIS_OVR_RIS_Pos (1UL) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register *******************/ +#define PSSI_IER_OVR_IE_Pos (1UL) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register *******************/ +#define PSSI_MIS_OVR_MIS_Pos (1UL) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register *******************/ +#define PSSI_ICR_OVR_ISC_Pos (1UL) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0UL) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************* Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_SDEN_Pos (2UL) +#define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */ +#define PWR_CR1_MODE_PDN_Pos (4UL) +#define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */ +#define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */ +#define PWR_CR1_LPDS08V_Pos (5UL) +#define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */ +#define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */ +#define PWR_CR1_VDD18SMPSVMEN_Pos (8UL) +#define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */ +#define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */ +#define PWR_CR1_VDD18SMPSRDY_Pos (15UL) +#define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */ +#define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */ +#define PWR_CR1_POPL_Pos (16UL) +#define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */ +#define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */ +#define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */ +#define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */ +#define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */ +#define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */ +#define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */ + +/******************* Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDEN_Pos (0UL) +#define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */ +#define PWR_CR2_PVDO_Pos (8UL) +#define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */ +#define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +/******************* Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_VCOREMONEN_Pos (0UL) +#define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */ +#define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */ +#define PWR_CR3_VCORELLS_Pos (4UL) +#define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */ +#define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */ +#define PWR_CR3_VCOREL_Pos (8UL) +#define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */ +#define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */ +#define PWR_CR3_VCOREH_Pos (9UL) +#define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */ +#define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */ + +/******************* Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_TCMRBSEN_Pos (0UL) +#define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */ +#define PWR_CR4_TCMFLXRBSEN_Pos (4UL) +#define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */ +#define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */ + +/****************** Bit definition for PWR_VOSCR register *******************/ +#define PWR_VOSCR_VOS_Pos (0UL) +#define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */ +#define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */ +#define PWR_VOSCR_VOSRDY_Pos (1UL) +#define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSCR_ACTVOS_Pos (16UL) +#define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ +#define PWR_VOSCR_ACTVOSRDY_Pos (17UL) +#define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */ +#define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */ + +/****************** Bit definition for PWR_BDCR1 register *******************/ +#define PWR_BDCR1_MONEN_Pos (0UL) +#define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ +#define PWR_BDCR1_VBATL_Pos (16UL) +#define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */ +#define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */ +#define PWR_BDCR1_VBATH_Pos (17UL) +#define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */ +#define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */ +#define PWR_BDCR1_TEMPL_Pos (18UL) +#define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */ +#define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */ +#define PWR_BDCR1_TEMPH_Pos (19UL) +#define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */ +#define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */ + +/****************** Bit definition for PWR_BDCR2 register *******************/ +#define PWR_BDCR2_BKPRBSEN_Pos (0UL) +#define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */ + +/****************** Bit definition for PWR_DBPCR register *******************/ +#define PWR_DBPCR_DBP_Pos (0UL) +#define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */ + +/****************** Bit definition for PWR_CPUCR register *******************/ +#define PWR_CPUCR_PDDS_Pos (0UL) +#define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */ +#define PWR_CPUCR_CSSF_Pos (1UL) +#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */ +#define PWR_CPUCR_STOPF_Pos (8UL) +#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */ +#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */ +#define PWR_CPUCR_SBF_Pos (9UL) +#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */ +#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */ +#define PWR_CPUCR_SVOS_Pos (16UL) +#define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */ +#define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */ + +/****************** Bit definition for PWR_SVMCR1 register ******************/ +#define PWR_SVMCR1_VDDIO4VMEN_Pos (0UL) +#define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */ +#define PWR_SVMCR1_VDDIO4SV_Pos (8UL) +#define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */ +#define PWR_SVMCR1_VDDIO4RDY_Pos (16UL) +#define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */ +#define PWR_SVMCR1_VDDIO4VRSEL_Pos (24UL) +#define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */ +#define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25UL) +#define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR2 register ******************/ +#define PWR_SVMCR2_VDDIO5VMEN_Pos (0UL) +#define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */ +#define PWR_SVMCR2_VDDIO5SV_Pos (8UL) +#define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */ +#define PWR_SVMCR2_VDDIO5RDY_Pos (16UL) +#define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */ +#define PWR_SVMCR2_VDDIO5VRSEL_Pos (24UL) +#define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */ +#define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25UL) +#define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR3 register ******************/ +#define PWR_SVMCR3_VDDIO2VMEN_Pos (0UL) +#define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */ +#define PWR_SVMCR3_VDDIO3VMEN_Pos (1UL) +#define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */ +#define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */ +#define PWR_SVMCR3_USB33VMEN_Pos (2UL) +#define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */ +#define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */ +#define PWR_SVMCR3_AVMEN_Pos (4UL) +#define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */ +#define PWR_SVMCR3_VDDIO2SV_Pos (8UL) +#define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */ +#define PWR_SVMCR3_VDDIO3SV_Pos (9UL) +#define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */ +#define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */ +#define PWR_SVMCR3_USB33SV_Pos (10UL) +#define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */ +#define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */ +#define PWR_SVMCR3_ASV_Pos (12UL) +#define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */ +#define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */ +#define PWR_SVMCR3_VDDIO2RDY_Pos (16UL) +#define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */ +#define PWR_SVMCR3_VDDIO3RDY_Pos (17UL) +#define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */ +#define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */ +#define PWR_SVMCR3_USB33RDY_Pos (18UL) +#define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */ +#define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */ +#define PWR_SVMCR3_ARDY_Pos (20UL) +#define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */ +#define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */ +#define PWR_SVMCR3_VDDIOVRSEL_Pos (24UL) +#define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */ +#define PWR_SVMCR3_VDDIO2VRSEL_Pos (25UL) +#define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */ +#define PWR_SVMCR3_VDDIO3VRSEL_Pos (26UL) +#define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */ + +/***************** Bit definition for PWR_WKUPCR register *******************/ +#define PWR_WKUPCR_WKUPC1_Pos (0UL) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPCR_WKUPC2_Pos (1UL) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPCR_WKUPC3_Pos (2UL) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPCR_WKUPC4_Pos (3UL) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */ +#define PWR_WKUPCR_WKUPC_Pos (0UL) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */ + +/***************** Bit definition for PWR_WKUPSR register *******************/ +#define PWR_WKUPSR_WKUPF1_Pos (0UL) +#define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPSR_WKUPF2_Pos (1UL) +#define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPSR_WKUPF3_Pos (2UL) +#define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPSR_WKUPF4_Pos (3UL) +#define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */ + +/***************** Bit definition for PWR_WKUPEPR register *******************/ +#define PWR_WKUPEPR_WKUPEN1_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1UL) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2UL) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3UL) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8UL) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPP2_Pos (9UL) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPP3_Pos (10UL) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPP4_Pos (11UL) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPP_Pos (8UL) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16UL) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18UL) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20UL) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22UL) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WKUPEPR_WKUPEN_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ + +/***************** Bit definition for PWR_SECCFGR register ******************/ +#define PWR_SECCFGR_SEC0_Pos (0UL) +#define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */ +#define PWR_SECCFGR_SEC1_Pos (1UL) +#define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */ +#define PWR_SECCFGR_SEC2_Pos (2UL) +#define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */ +#define PWR_SECCFGR_SEC3_Pos (3UL) +#define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */ +#define PWR_SECCFGR_SEC4_Pos (4UL) +#define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */ +#define PWR_SECCFGR_SEC5_Pos (5UL) +#define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */ +#define PWR_SECCFGR_SEC6_Pos (6UL) +#define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */ +#define PWR_SECCFGR_SEC7_Pos (7UL) +#define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */ +#define PWR_SECCFGR_WKUPSEC1_Pos (16UL) +#define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */ +#define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */ +#define PWR_SECCFGR_WKUPSEC2_Pos (17UL) +#define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */ +#define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */ +#define PWR_SECCFGR_WKUPSEC3_Pos (18UL) +#define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */ +#define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */ +#define PWR_SECCFGR_WKUPSEC4_Pos (19UL) +#define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */ +#define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */ + +/***************** Bit definition for PWR_PRIVCFGR register *****************/ +#define PWR_PRIVCFGR_PRIV0_Pos (0UL) +#define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */ +#define PWR_PRIVCFGR_PRIV1_Pos (1UL) +#define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */ +#define PWR_PRIVCFGR_PRIV2_Pos (2UL) +#define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */ +#define PWR_PRIVCFGR_PRIV3_Pos (3UL) +#define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */ +#define PWR_PRIVCFGR_PRIV4_Pos (4UL) +#define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */ +#define PWR_PRIVCFGR_PRIV5_Pos (5UL) +#define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */ +#define PWR_PRIVCFGR_PRIV6_Pos (6UL) +#define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */ +#define PWR_PRIVCFGR_PRIV7_Pos (7UL) +#define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV1_Pos (16UL) +#define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */ +#define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV2_Pos (17UL) +#define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */ +#define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV3_Pos (18UL) +#define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */ +#define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV4_Pos (19UL) +#define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */ +#define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */ + + +/******************************************************************************/ +/* */ +/* RAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_CR register ******************/ +#define RAMCFG_CR_ECCE_Pos (0UL) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */ +#define RAMCFG_CR_ALE_Pos (4UL) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8UL) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_SRAMHWERDIS_Pos (12UL) +#define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */ +#define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */ +#define RAMCFG_CR_ITCMCFG_Pos (16UL) +#define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */ +#define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ +#define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_SRAMSD_Pos (20UL) +#define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */ +#define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */ +#define RAMCFG_CR_DTCMCFG_Pos (24UL) +#define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */ +#define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ + +/******************* Bit definition for RAMCFG_IER register *****************/ +#define RAMCFG_IER_SEIE_Pos (0UL) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */ +#define RAMCFG_IER_DEIE_Pos (1UL) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */ + +/******************* Bit definition for RAMCFG_ISR register *****************/ +#define RAMCFG_ISR_SEDC_Pos (0UL) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */ +#define RAMCFG_ISR_DED_Pos (1UL) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8UL) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */ + +/******************* Bit definition for RAMCFG_ESEAR register ****************/ +#define RAMCFG_ESEAR_ESEA_Pos (0UL) +#define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */ + +/******************* Bit definition for RAMCFG_EDEAR register ****************/ +#define RAMCFG_EDEAR_EDEA_Pos (0UL) +#define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */ + +/******************* Bit definition for RAMCFG_ICR register *****************/ +#define RAMCFG_ICR_CSEDC_Pos (0UL) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */ +#define RAMCFG_ICR_CDED_Pos (1UL) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/ + +/***************** Bit definition for RAMCFG_ECCKEYR register ***************/ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0UL) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */ + +/***************** Bit definition for RAMCFG_ERKEYR register ****************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0UL) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */ + + +/******************************************************************************/ +/* */ +/* (RCC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_LSION_Pos (0UL) +#define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_CR_LSEON_Pos (1UL) +#define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */ +#define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */ +#define RCC_CR_MSION_Pos (2UL) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */ +#define RCC_CR_HSION_Pos (3UL) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */ +#define RCC_CR_HSEON_Pos (4UL) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */ +#define RCC_CR_PLL1ON_Pos (8UL) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */ +#define RCC_CR_PLL2ON_Pos (9UL) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ +#define RCC_CR_PLL3ON_Pos (10UL) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ +#define RCC_CR_PLL4ON_Pos (11UL) +#define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */ +#define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */ + +/******************** Bit definition for RCC_SR register ********************/ +#define RCC_SR_LSIRDY_Pos (0UL) +#define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */ +#define RCC_SR_LSERDY_Pos (1UL) +#define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */ +#define RCC_SR_MSIRDY_Pos (2UL) +#define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */ +#define RCC_SR_HSIRDY_Pos (3UL) +#define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */ +#define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_SR_HSERDY_Pos (4UL) +#define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */ +#define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_SR_PLL1RDY_Pos (8UL) +#define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */ +#define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_SR_PLL2RDY_Pos (9UL) +#define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */ +#define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_SR_PLL3RDY_Pos (10UL) +#define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */ +#define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_SR_PLL4RDY_Pos (11UL) +#define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */ +#define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ + +/****************** Bit definition for RCC_STOPCR register ******************/ +#define RCC_STOPCR_MSISTOPEN_Pos (0UL) +#define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */ +#define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCR_HSISTOPEN_Pos (1UL) +#define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */ +#define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */ + +/****************** Bit definition for RCC_CFGR1 register *******************/ +#define RCC_CFGR1_STOPWUCK_Pos (0UL) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */ +#define RCC_CFGR1_CPUSW_Pos (16UL) +#define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */ +#define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */ +#define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */ +#define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */ +#define RCC_CFGR1_CPUSWS_Pos (20UL) +#define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */ +#define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */ +#define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_SYSSW_Pos (24UL) +#define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */ +#define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */ +#define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_SYSSWS_Pos (28UL) +#define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */ +#define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for RCC_CFGR2 register *******************/ +#define RCC_CFGR2_PPRE1_Pos (0UL) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE2_Pos (4UL) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE4_Pos (12UL) +#define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */ +#define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_PPRE5_Pos (16UL) +#define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */ +#define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */ +#define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */ +#define RCC_CFGR2_HPRE_Pos (20UL) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_TIMPRE_Pos (24UL) +#define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */ +#define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */ +#define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */ +#define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_VSWRST_Pos (31UL) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */ + +/****************** Bit definition for RCC_HWRSR register *******************/ +#define RCC_HWRSR_RMVF_Pos (16UL) +#define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_HWRSR_LCKRSTF_Pos (17UL) +#define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_HWRSR_BORRSTF_Pos (21UL) +#define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_HWRSR_PINRSTF_Pos (22UL) +#define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_HWRSR_PORRSTF_Pos (23UL) +#define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_HWRSR_SFTRSTF_Pos (24UL) +#define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_HWRSR_IWDGRSTF_Pos (26UL) +#define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_HWRSR_WWDGRSTF_Pos (28UL) +#define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_HWRSR_LPWRRSTF_Pos (30UL) +#define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/******************* Bit definition for RCC_RSR register ********************/ +#define RCC_RSR_RMVF_Pos (16UL) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_LCKRSTF_Pos (17UL) +#define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_RSR_BORRSTF_Pos (21UL) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_RSR_PINRSTF_Pos (22UL) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_PORRSTF_Pos (23UL) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (24UL) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_RSR_IWDGRSTF_Pos (26UL) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (28UL) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (30UL) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/***************** Bit definition for RCC_LSECFGR register ******************/ +#define RCC_LSECFGR_LSECSSON_Pos (7UL) +#define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */ +#define RCC_LSECFGR_LSECSSRA_Pos (8UL) +#define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */ +#define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */ +#define RCC_LSECFGR_LSECSSD_Pos (9UL) +#define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */ +#define RCC_LSECFGR_LSEBYP_Pos (15UL) +#define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */ +#define RCC_LSECFGR_LSEEXT_Pos (16UL) +#define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */ +#define RCC_LSECFGR_LSEGFON_Pos (17UL) +#define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */ +#define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */ +#define RCC_LSECFGR_LSEDRV_Pos (18UL) +#define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */ +#define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */ +#define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for RCC_MSICFGR register ******************/ +#define RCC_MSICFGR_MSIFREQSEL_Pos (9UL) +#define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */ +#define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */ +#define RCC_MSICFGR_MSITRIM_Pos (16UL) +#define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */ +#define RCC_MSICFGR_MSICAL_Pos (23UL) +#define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */ +#define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (7UL) +#define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_Pos (16UL) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSICAL_Pos (23UL) +#define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ + +/****************** Bit definition for RCC_HSIMCR register ******************/ +#define RCC_HSIMCR_HSIREF_Pos (0UL) +#define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */ +#define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */ +#define RCC_HSIMCR_HSIDEV_Pos (16UL) +#define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */ +#define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */ +#define RCC_HSIMCR_HSIMONEN_Pos (31UL) +#define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */ +#define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */ + +/****************** Bit definition for RCC_HSIMSR register ******************/ +#define RCC_HSIMSR_HSIVAL_Pos (0UL) +#define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */ +#define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */ + +/***************** Bit definition for RCC_HSECFGR register ******************/ +#define RCC_HSECFGR_HSEDIV2SEL_Pos (6UL) +#define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */ +#define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */ +#define RCC_HSECFGR_HSECSSON_Pos (7UL) +#define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */ +#define RCC_HSECFGR_HSECSSD_Pos (9UL) +#define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */ +#define RCC_HSECFGR_HSECSSBYP_Pos (10UL) +#define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */ +#define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */ +#define RCC_HSECFGR_HSECSSBPRE_Pos (11UL) +#define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */ +#define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */ +#define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */ +#define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */ +#define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */ +#define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */ +#define RCC_HSECFGR_HSEBYP_Pos (15UL) +#define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_HSECFGR_HSEEXT_Pos (16UL) +#define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_PLL1DIVN_Pos (8UL) +#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */ +#define RCC_PLL1CFGR1_PLL1DIVM_Pos (20UL) +#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */ +#define RCC_PLL1CFGR1_PLL1BYP_Pos (27UL) +#define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */ +#define RCC_PLL1CFGR1_PLL1SEL_Pos (28UL) +#define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */ +#define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0UL) +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL1CFGR3 register *****************/ +#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0UL) +#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */ +#define RCC_PLL1CFGR3_PLL1DACEN_Pos (1UL) +#define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2UL) +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */ +#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3UL) +#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4UL) +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */ +#define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8UL) +#define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */ +#define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16UL) +#define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */ +#define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24UL) +#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */ +#define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27UL) +#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30UL) +#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_PLL2DIVN_Pos (8UL) +#define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */ +#define RCC_PLL2CFGR1_PLL2DIVM_Pos (20UL) +#define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */ +#define RCC_PLL2CFGR1_PLL2BYP_Pos (27UL) +#define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */ +#define RCC_PLL2CFGR1_PLL2SEL_Pos (28UL) +#define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */ +#define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0UL) +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL2CFGR3 register *****************/ +#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0UL) +#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */ +#define RCC_PLL2CFGR3_PLL2DACEN_Pos (1UL) +#define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2UL) +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */ +#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3UL) +#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4UL) +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */ +#define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8UL) +#define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */ +#define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16UL) +#define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */ +#define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24UL) +#define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */ +#define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27UL) +#define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30UL) +#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_PLL3DIVN_Pos (8UL) +#define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */ +#define RCC_PLL3CFGR1_PLL3DIVM_Pos (20UL) +#define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */ +#define RCC_PLL3CFGR1_PLL3BYP_Pos (27UL) +#define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */ +#define RCC_PLL3CFGR1_PLL3SEL_Pos (28UL) +#define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */ +#define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0UL) +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL3CFGR3 register *****************/ +#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0UL) +#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */ +#define RCC_PLL3CFGR3_PLL3DACEN_Pos (1UL) +#define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2UL) +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */ +#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3UL) +#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4UL) +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */ +#define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8UL) +#define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */ +#define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16UL) +#define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */ +#define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24UL) +#define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */ +#define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27UL) +#define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30UL) +#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_PLL4DIVN_Pos (8UL) +#define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */ +#define RCC_PLL4CFGR1_PLL4DIVM_Pos (20UL) +#define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */ +#define RCC_PLL4CFGR1_PLL4BYP_Pos (27UL) +#define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */ +#define RCC_PLL4CFGR1_PLL4SEL_Pos (28UL) +#define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */ +#define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0UL) +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL4CFGR3 register *****************/ +#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0UL) +#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */ +#define RCC_PLL4CFGR3_PLL4DACEN_Pos (1UL) +#define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2UL) +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */ +#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3UL) +#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4UL) +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */ +#define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8UL) +#define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */ +#define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16UL) +#define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */ +#define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24UL) +#define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */ +#define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27UL) +#define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30UL) +#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/***************** Bit definition for RCC_IC1CFGR register ******************/ +#define RCC_IC1CFGR_IC1INT_Pos (16UL) +#define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */ +#define RCC_IC1CFGR_IC1SEL_Pos (28UL) +#define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */ +#define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC2CFGR register ******************/ +#define RCC_IC2CFGR_IC2INT_Pos (16UL) +#define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */ +#define RCC_IC2CFGR_IC2SEL_Pos (28UL) +#define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */ +#define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC3CFGR register ******************/ +#define RCC_IC3CFGR_IC3INT_Pos (16UL) +#define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */ +#define RCC_IC3CFGR_IC3SEL_Pos (28UL) +#define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */ +#define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC4CFGR register ******************/ +#define RCC_IC4CFGR_IC4INT_Pos (16UL) +#define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */ +#define RCC_IC4CFGR_IC4SEL_Pos (28UL) +#define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */ +#define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC5CFGR register ******************/ +#define RCC_IC5CFGR_IC5INT_Pos (16UL) +#define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */ +#define RCC_IC5CFGR_IC5SEL_Pos (28UL) +#define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */ +#define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC6CFGR register ******************/ +#define RCC_IC6CFGR_IC6INT_Pos (16UL) +#define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */ +#define RCC_IC6CFGR_IC6SEL_Pos (28UL) +#define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */ +#define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC7CFGR register ******************/ +#define RCC_IC7CFGR_IC7INT_Pos (16UL) +#define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */ +#define RCC_IC7CFGR_IC7SEL_Pos (28UL) +#define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */ +#define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC8CFGR register ******************/ +#define RCC_IC8CFGR_IC8INT_Pos (16UL) +#define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */ +#define RCC_IC8CFGR_IC8SEL_Pos (28UL) +#define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */ +#define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC9CFGR register ******************/ +#define RCC_IC9CFGR_IC9INT_Pos (16UL) +#define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */ +#define RCC_IC9CFGR_IC9SEL_Pos (28UL) +#define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */ +#define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC10CFGR register *****************/ +#define RCC_IC10CFGR_IC10INT_Pos (16UL) +#define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */ +#define RCC_IC10CFGR_IC10SEL_Pos (28UL) +#define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */ +#define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC11CFGR register *****************/ +#define RCC_IC11CFGR_IC11INT_Pos (16UL) +#define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */ +#define RCC_IC11CFGR_IC11SEL_Pos (28UL) +#define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */ +#define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC12CFGR register *****************/ +#define RCC_IC12CFGR_IC12INT_Pos (16UL) +#define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */ +#define RCC_IC12CFGR_IC12SEL_Pos (28UL) +#define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */ +#define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC13CFGR register *****************/ +#define RCC_IC13CFGR_IC13INT_Pos (16UL) +#define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */ +#define RCC_IC13CFGR_IC13SEL_Pos (28UL) +#define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */ +#define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC14CFGR register *****************/ +#define RCC_IC14CFGR_IC14INT_Pos (16UL) +#define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */ +#define RCC_IC14CFGR_IC14SEL_Pos (28UL) +#define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */ +#define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC15CFGR register *****************/ +#define RCC_IC15CFGR_IC15INT_Pos (16UL) +#define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */ +#define RCC_IC15CFGR_IC15SEL_Pos (28UL) +#define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */ +#define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC16CFGR register *****************/ +#define RCC_IC16CFGR_IC16INT_Pos (16UL) +#define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */ +#define RCC_IC16CFGR_IC16SEL_Pos (28UL) +#define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */ +#define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC17CFGR register *****************/ +#define RCC_IC17CFGR_IC17INT_Pos (16UL) +#define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */ +#define RCC_IC17CFGR_IC17SEL_Pos (28UL) +#define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */ +#define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC18CFGR register *****************/ +#define RCC_IC18CFGR_IC18INT_Pos (16UL) +#define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */ +#define RCC_IC18CFGR_IC18SEL_Pos (28UL) +#define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */ +#define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC19CFGR register *****************/ +#define RCC_IC19CFGR_IC19INT_Pos (16UL) +#define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */ +#define RCC_IC19CFGR_IC19SEL_Pos (28UL) +#define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */ +#define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC20CFGR register *****************/ +#define RCC_IC20CFGR_IC20INT_Pos (16UL) +#define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */ +#define RCC_IC20CFGR_IC20SEL_Pos (28UL) +#define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */ +#define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for RCC_CIER register *******************/ +#define RCC_CIER_LSIRDYIE_Pos (0UL) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1UL) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_MSIRDYIE_Pos (2UL) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */ +#define RCC_CIER_HSIRDYIE_Pos (3UL) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (4UL) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ +#define RCC_CIER_PLL1RDYIE_Pos (8UL) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */ +#define RCC_CIER_PLL2RDYIE_Pos (9UL) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */ +#define RCC_CIER_PLL3RDYIE_Pos (10UL) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */ +#define RCC_CIER_PLL4RDYIE_Pos (11UL) +#define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */ +#define RCC_CIER_LSECSSIE_Pos (16UL) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */ +#define RCC_CIER_HSECSSIE_Pos (17UL) +#define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */ +#define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */ +#define RCC_CIER_WKUPIE_Pos (24UL) +#define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */ +#define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */ + +/******************* Bit definition for RCC_CIFR register *******************/ +#define RCC_CIFR_LSIRDYF_Pos (0UL) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1UL) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (2UL) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (3UL) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (4UL) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_PLL1RDYF_Pos (8UL) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */ +#define RCC_CIFR_PLL2RDYF_Pos (9UL) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */ +#define RCC_CIFR_PLL3RDYF_Pos (10UL) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */ +#define RCC_CIFR_PLL4RDYF_Pos (11UL) +#define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (16UL) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (17UL) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_WKUPF_Pos (24UL) +#define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */ +#define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */ + +/******************* Bit definition for RCC_CICR register *******************/ +#define RCC_CICR_LSIRDYC_Pos (0UL) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1UL) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_MSIRDYC_Pos (2UL) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */ +#define RCC_CICR_HSIRDYC_Pos (3UL) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (4UL) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_PLL1RDYC_Pos (8UL) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */ +#define RCC_CICR_PLL2RDYC_Pos (9UL) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */ +#define RCC_CICR_PLL3RDYC_Pos (10UL) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */ +#define RCC_CICR_PLL4RDYC_Pos (11UL) +#define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (16UL) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (17UL) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_WKUPFC_Pos (24UL) +#define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */ +#define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */ + +/****************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_ADF1SEL_Pos (0UL) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */ +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_ADC12SEL_Pos (4UL) +#define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */ +#define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_ADCPRE_Pos (8UL) +#define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */ +#define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */ +#define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_DCMIPPSEL_Pos (20UL) +#define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */ +#define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_ETH1PTPSEL_Pos (0UL) +#define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_ETH1PTPDIV_Pos (4UL) +#define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */ +#define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8UL) +#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1CLKSEL_Pos (12UL) +#define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ETH1SEL_Pos (16UL) +#define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20UL) +#define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24UL) +#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR3 register ******************/ +#define RCC_CCIPR3_FDCANSEL_Pos (0UL) +#define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */ +#define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_FMCSEL_Pos (4UL) +#define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */ +#define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_DFTSEL_Pos (8UL) +#define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */ + +/****************** Bit definition for RCC_CCIPR4 register ******************/ +#define RCC_CCIPR4_I2C1SEL_Pos (0UL) +#define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */ +#define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR4_I2C2SEL_Pos (4UL) +#define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */ +#define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR4_I2C3SEL_Pos (8UL) +#define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */ +#define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR4_I2C4SEL_Pos (12UL) +#define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */ +#define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR4_I3C1SEL_Pos (16UL) +#define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */ +#define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR4_I3C2SEL_Pos (20UL) +#define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */ +#define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR4_LTDCSEL_Pos (24UL) +#define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */ +#define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */ + +/****************** Bit definition for RCC_CCIPR5 register ******************/ +#define RCC_CCIPR5_MCO1SEL_Pos (0UL) +#define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */ +#define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR5_MCO1PRE_Pos (4UL) +#define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */ +#define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR5_MCO2SEL_Pos (8UL) +#define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */ +#define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR5_MCO2PRE_Pos (12UL) +#define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */ +#define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */ +#define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR5_MDF1SEL_Pos (16UL) +#define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */ +#define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for RCC_CCIPR6 register ******************/ +#define RCC_CCIPR6_XSPI1SEL_Pos (0UL) +#define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */ +#define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR6_XSPI2SEL_Pos (4UL) +#define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */ +#define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR6_XSPI3SEL_Pos (8UL) +#define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */ +#define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR6_OTGPHY1SEL_Pos (12UL) +#define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */ +#define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16UL) +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR6_OTGPHY2SEL_Pos (20UL) +#define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */ +#define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24UL) +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR7 register ******************/ +#define RCC_CCIPR7_PERSEL_Pos (0UL) +#define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */ +#define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR7_PSSISEL_Pos (4UL) +#define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */ +#define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR7_RTCSEL_Pos (8UL) +#define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */ +#define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR7_RTCPRE_Pos (12UL) +#define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */ +#define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */ +#define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR7_SAI1SEL_Pos (20UL) +#define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */ +#define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR7_SAI2SEL_Pos (24UL) +#define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */ +#define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */ + +/****************** Bit definition for RCC_CCIPR8 register ******************/ +#define RCC_CCIPR8_SDMMC1SEL_Pos (0UL) +#define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */ +#define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR8_SDMMC2SEL_Pos (4UL) +#define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */ +#define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */ + +/****************** Bit definition for RCC_CCIPR9 register ******************/ +#define RCC_CCIPR9_SPDIFRX1SEL_Pos (0UL) +#define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */ +#define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR9_SPI1SEL_Pos (4UL) +#define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */ +#define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR9_SPI2SEL_Pos (8UL) +#define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */ +#define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR9_SPI3SEL_Pos (12UL) +#define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */ +#define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR9_SPI4SEL_Pos (16UL) +#define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */ +#define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR9_SPI5SEL_Pos (20UL) +#define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */ +#define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR9_SPI6SEL_Pos (24UL) +#define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */ +#define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR12 register ******************/ +#define RCC_CCIPR12_LPTIM1SEL_Pos (8UL) +#define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */ +#define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR12_LPTIM2SEL_Pos (12UL) +#define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */ +#define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR12_LPTIM3SEL_Pos (16UL) +#define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */ +#define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR12_LPTIM4SEL_Pos (20UL) +#define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */ +#define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR12_LPTIM5SEL_Pos (24UL) +#define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */ +#define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR13 register ******************/ +#define RCC_CCIPR13_USART1SEL_Pos (0UL) +#define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */ +#define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR13_USART2SEL_Pos (4UL) +#define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */ +#define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR13_USART3SEL_Pos (8UL) +#define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */ +#define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR13_UART4SEL_Pos (12UL) +#define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */ +#define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR13_UART5SEL_Pos (16UL) +#define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */ +#define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR13_USART6SEL_Pos (20UL) +#define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */ +#define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR13_UART7SEL_Pos (24UL) +#define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */ +#define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR13_UART8SEL_Pos (28UL) +#define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */ +#define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */ +#define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */ + +/***************** Bit definition for RCC_CCIPR14 register ******************/ +#define RCC_CCIPR14_UART9SEL_Pos (0UL) +#define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */ +#define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR14_USART10SEL_Pos (4UL) +#define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */ +#define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR14_LPUART1SEL_Pos (8UL) +#define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */ +#define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */ + +/***************** Bit definition for RCC_MISCRSTR register *****************/ +#define RCC_MISCRSTR_DBGRST_Pos (0UL) +#define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */ +#define RCC_MISCRSTR_XSPIPHY1RST_Pos (4UL) +#define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTR_XSPIPHY2RST_Pos (5UL) +#define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7UL) +#define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8UL) +#define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTR register ******************/ +#define RCC_MEMRSTR_AXISRAM3RST_Pos (0UL) +#define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */ +#define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTR_AXISRAM4RST_Pos (1UL) +#define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */ +#define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTR_AXISRAM5RST_Pos (2UL) +#define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */ +#define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTR_AXISRAM6RST_Pos (3UL) +#define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */ +#define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTR_AHBSRAM1RST_Pos (4UL) +#define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */ +#define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTR_AHBSRAM2RST_Pos (5UL) +#define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */ +#define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTR_AXISRAM1RST_Pos (7UL) +#define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */ +#define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTR_AXISRAM2RST_Pos (8UL) +#define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */ +#define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTR_FLEXRAMRST_Pos (9UL) +#define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTR_CACHEAXIRAMRST_Pos (10UL) +#define RCC_MEMRSTR_CACHEAXIRAMRST_Msk (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTR_CACHEAXIRAMRST RCC_MEMRSTR_CACHEAXIRAMRST_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTR_VENCRAMRST_Pos (11UL) +#define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTR_BOOTROMRST_Pos (12UL) +#define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */ + +/***************** Bit definition for RCC_AHB1RSTR register *****************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4UL) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTR_ADC12RST_Pos (5UL) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */ + +/***************** Bit definition for RCC_AHB2RSTR register *****************/ +#define RCC_AHB2RSTR_RAMCFGRST_Pos (12UL) +#define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTR_MDF1RST_Pos (16UL) +#define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTR_ADF1RST_Pos (17UL) +#define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */ + +/***************** Bit definition for RCC_AHB3RSTR register *****************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0UL) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */ +#define RCC_AHB3RSTR_HASHRST_Pos (1UL) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB3RSTR_CRYPRST_Pos (2UL) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTR_SAESRST_Pos (4UL) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk /*!< SAES reset */ +#define RCC_AHB3RSTR_PKARST_Pos (8UL) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */ +#define RCC_AHB3RSTR_IACRST_Pos (10UL) +#define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */ + +/***************** Bit definition for RCC_AHB4RSTR register *****************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0UL) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTR_GPIOBRST_Pos (1UL) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTR_GPIOCRST_Pos (2UL) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTR_GPIODRST_Pos (3UL) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTR_GPIOERST_Pos (4UL) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTR_GPIOFRST_Pos (5UL) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTR_GPIOGRST_Pos (6UL) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTR_GPIOHRST_Pos (7UL) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTR_GPIONRST_Pos (13UL) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTR_GPIOORST_Pos (14UL) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTR_GPIOPRST_Pos (15UL) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTR_GPIOQRST_Pos (16UL) +#define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTR_PWRRST_Pos (18UL) +#define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */ +#define RCC_AHB4RSTR_CRCRST_Pos (19UL) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */ + +/***************** Bit definition for RCC_AHB5RSTR register *****************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0UL) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTR_DMA2DRST_Pos (1UL) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTR_JPEGRST_Pos (3UL) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTR_FMCRST_Pos (4UL) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */ +#define RCC_AHB5RSTR_XSPI1RST_Pos (5UL) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTR_PSSIRST_Pos (6UL) +#define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTR_SDMMC2RST_Pos (7UL) +#define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8UL) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTR_XSPI2RST_Pos (12UL) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTR_XSPIMRST_Pos (13UL) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTR_XSPI3RST_Pos (17UL) +#define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTR_GFXMMURST_Pos (19UL) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTR_GPU2DRST_Pos (20UL) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23UL) +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24UL) +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTR_ETH1RST_Pos (25UL) +#define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTR_OTG1RST_Pos (26UL) +#define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTR_OTGPHY1RST_Pos (27UL) +#define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */ +#define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTR_OTGPHY2RST_Pos (28UL) +#define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */ +#define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTR_OTG2RST_Pos (29UL) +#define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTR_CACHEAXIRST_Pos (30UL) +#define RCC_AHB5RSTR_CACHEAXIRST_Msk (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTR_CACHEAXIRST RCC_AHB5RSTR_CACHEAXIRST_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTR_NPURST_Pos (31UL) +#define RCC_AHB5RSTR_NPURST_Msk (0x1UL << RCC_AHB5RSTR_NPURST_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTR_NPURST RCC_AHB5RSTR_NPURST_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTR1 register *****************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0UL) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTR1_TIM3RST_Pos (1UL) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTR1_TIM4RST_Pos (2UL) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTR1_TIM5RST_Pos (3UL) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTR1_TIM6RST_Pos (4UL) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTR1_TIM7RST_Pos (5UL) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTR1_TIM12RST_Pos (6UL) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTR1_TIM13RST_Pos (7UL) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTR1_TIM14RST_Pos (8UL) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9UL) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTR1_WWDGRST_Pos (11UL) +#define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */ +#define RCC_APB1RSTR1_TIM10RST_Pos (12UL) +#define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTR1_TIM11RST_Pos (13UL) +#define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTR1_SPI2RST_Pos (14UL) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTR1_SPI3RST_Pos (15UL) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16UL) +#define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTR1_USART2RST_Pos (17UL) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1RSTR1_USART3RST_Pos (18UL) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1RSTR1_UART4RST_Pos (19UL) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1RSTR1_UART5RST_Pos (20UL) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1RSTR1_I2C1RST_Pos (21UL) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTR1_I2C2RST_Pos (22UL) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTR1_I2C3RST_Pos (23UL) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTR1_I3C1RST_Pos (24UL) +#define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTR1_I3C2RST_Pos (25UL) +#define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTR1_UART7RST_Pos (30UL) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */ +#define RCC_APB1RSTR1_UART8RST_Pos (31UL) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTR2 register *****************/ +#define RCC_APB1RSTR2_MDIOSRST_Pos (5UL) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTR2_FDCANRST_Pos (8UL) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTR2_UCPD1RST_Pos (18UL) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0UL) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (1UL) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (4UL) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_USART6RST_Pos (5UL) +#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ +#define RCC_APB2RSTR_UART9RST_Pos (6UL) +#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */ +#define RCC_APB2RSTR_USART10RST_Pos (7UL) +#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */ +#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12UL) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST_Pos (13UL) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTR_TIM18RST_Pos (15UL) +#define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */ +#define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16UL) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17UL) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18UL) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_TIM9RST_Pos (19UL) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTR_SPI5RST_Pos (20UL) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTR_SAI1RST_Pos (21UL) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST_Pos (22UL) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTR1 register *****************/ +#define RCC_APB4RSTR1_HDPRST_Pos (2UL) +#define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */ +#define RCC_APB4RSTR1_LPUART1RST_Pos (3UL) +#define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTR1_SPI6RST_Pos (5UL) +#define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTR1_I2C4RST_Pos (7UL) +#define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */ +#define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTR1_LPTIM2RST_Pos (9UL) +#define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */ +#define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTR1_LPTIM3RST_Pos (10UL) +#define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */ +#define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTR1_LPTIM4RST_Pos (11UL) +#define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */ +#define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTR1_LPTIM5RST_Pos (12UL) +#define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */ +#define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTR1_VREFBUFRST_Pos (15UL) +#define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTR1_RTCRST_Pos (16UL) +#define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTR2 register *****************/ +#define RCC_APB4RSTR2_SYSCFGRST_Pos (0UL) +#define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */ +#define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTR2_DTSRST_Pos (2UL) +#define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */ + +/***************** Bit definition for RCC_APB5RSTR register *****************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1UL) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2UL) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTR_GFXTIMRST_Pos (4UL) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTR_VENCRST_Pos (5UL) +#define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */ +#define RCC_APB5RSTR_CSIRST_Pos (6UL) +#define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */ + +/****************** Bit definition for RCC_DIVENR register ******************/ +#define RCC_DIVENR_IC1EN_Pos (0UL) +#define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */ +#define RCC_DIVENR_IC2EN_Pos (1UL) +#define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */ +#define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */ +#define RCC_DIVENR_IC3EN_Pos (2UL) +#define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */ +#define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */ +#define RCC_DIVENR_IC4EN_Pos (3UL) +#define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */ +#define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */ +#define RCC_DIVENR_IC5EN_Pos (4UL) +#define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */ +#define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */ +#define RCC_DIVENR_IC6EN_Pos (5UL) +#define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */ +#define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */ +#define RCC_DIVENR_IC7EN_Pos (6UL) +#define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */ +#define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */ +#define RCC_DIVENR_IC8EN_Pos (7UL) +#define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */ +#define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */ +#define RCC_DIVENR_IC9EN_Pos (8UL) +#define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */ +#define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */ +#define RCC_DIVENR_IC10EN_Pos (9UL) +#define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */ +#define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */ +#define RCC_DIVENR_IC11EN_Pos (10UL) +#define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */ +#define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */ +#define RCC_DIVENR_IC12EN_Pos (11UL) +#define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */ +#define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */ +#define RCC_DIVENR_IC13EN_Pos (12UL) +#define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */ +#define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */ +#define RCC_DIVENR_IC14EN_Pos (13UL) +#define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */ +#define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */ +#define RCC_DIVENR_IC15EN_Pos (14UL) +#define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */ +#define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */ +#define RCC_DIVENR_IC16EN_Pos (15UL) +#define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */ +#define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */ +#define RCC_DIVENR_IC17EN_Pos (16UL) +#define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */ +#define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */ +#define RCC_DIVENR_IC18EN_Pos (17UL) +#define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */ +#define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */ +#define RCC_DIVENR_IC19EN_Pos (18UL) +#define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */ +#define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */ +#define RCC_DIVENR_IC20EN_Pos (19UL) +#define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */ +#define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */ + +/****************** Bit definition for RCC_BUSENR register ******************/ +#define RCC_BUSENR_ACLKNEN_Pos (0UL) +#define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */ +#define RCC_BUSENR_ACLKNCEN_Pos (1UL) +#define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */ +#define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */ +#define RCC_BUSENR_AHBMEN_Pos (2UL) +#define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */ +#define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */ +#define RCC_BUSENR_AHB1EN_Pos (3UL) +#define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */ +#define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */ +#define RCC_BUSENR_AHB2EN_Pos (4UL) +#define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */ +#define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */ +#define RCC_BUSENR_AHB3EN_Pos (5UL) +#define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */ +#define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */ +#define RCC_BUSENR_AHB4EN_Pos (6UL) +#define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */ +#define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */ +#define RCC_BUSENR_AHB5EN_Pos (7UL) +#define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */ +#define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */ +#define RCC_BUSENR_APB1EN_Pos (8UL) +#define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */ +#define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */ +#define RCC_BUSENR_APB2EN_Pos (9UL) +#define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */ +#define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */ +#define RCC_BUSENR_APB3EN_Pos (10UL) +#define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */ +#define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */ +#define RCC_BUSENR_APB4EN_Pos (11UL) +#define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */ +#define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */ +#define RCC_BUSENR_APB5EN_Pos (12UL) +#define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */ +#define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENR register ******************/ +#define RCC_MISCENR_DBGEN_Pos (0UL) +#define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */ +#define RCC_MISCENR_MCO1EN_Pos (1UL) +#define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */ +#define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */ +#define RCC_MISCENR_MCO2EN_Pos (2UL) +#define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */ +#define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */ +#define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3UL) +#define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENR_PEREN_Pos (6UL) +#define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */ +#define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */ + +/****************** Bit definition for RCC_MEMENR register ******************/ +#define RCC_MEMENR_AXISRAM3EN_Pos (0UL) +#define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */ +#define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENR_AXISRAM4EN_Pos (1UL) +#define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */ +#define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENR_AXISRAM5EN_Pos (2UL) +#define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */ +#define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENR_AXISRAM6EN_Pos (3UL) +#define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */ +#define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENR_AHBSRAM1EN_Pos (4UL) +#define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */ +#define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENR_AHBSRAM2EN_Pos (5UL) +#define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */ +#define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENR_BKPSRAMEN_Pos (6UL) +#define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENR_AXISRAM1EN_Pos (7UL) +#define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */ +#define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENR_AXISRAM2EN_Pos (8UL) +#define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */ +#define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENR_FLEXRAMEN_Pos (9UL) +#define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENR_CACHEAXIRAMEN_Pos (10UL) +#define RCC_MEMENR_CACHEAXIRAMEN_Msk (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */ +#define RCC_MEMENR_CACHEAXIRAMEN RCC_MEMENR_CACHEAXIRAMEN_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENR_VENCRAMEN_Pos (11UL) +#define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMENR_BOOTROMEN_Pos (12UL) +#define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENR register ******************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4UL) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENR_ADC12EN_Pos (5UL) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENR register ******************/ +#define RCC_AHB2ENR_RAMCFGEN_Pos (12UL) +#define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENR_MDF1EN_Pos (16UL) +#define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENR_ADF1EN_Pos (17UL) +#define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENR register ******************/ +#define RCC_AHB3ENR_RNGEN_Pos (0UL) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */ +#define RCC_AHB3ENR_HASHEN_Pos (1UL) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */ +#define RCC_AHB3ENR_CRYPEN_Pos (2UL) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk /*!< CRYP enable */ +#define RCC_AHB3ENR_SAESEN_Pos (4UL) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk /*!< SAES enable */ +#define RCC_AHB3ENR_PKAEN_Pos (8UL) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */ +#define RCC_AHB3ENR_RIFSCEN_Pos (9UL) +#define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENR_IACEN_Pos (10UL) +#define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */ +#define RCC_AHB3ENR_RISAFEN_Pos (14UL) +#define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENR register ******************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0UL) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENR_GPIOBEN_Pos (1UL) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENR_GPIOCEN_Pos (2UL) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENR_GPIODEN_Pos (3UL) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENR_GPIOEEN_Pos (4UL) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENR_GPIOFEN_Pos (5UL) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENR_GPIOGEN_Pos (6UL) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENR_GPIOHEN_Pos (7UL) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENR_GPIONEN_Pos (13UL) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENR_GPIOOEN_Pos (14UL) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENR_GPIOPEN_Pos (15UL) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENR_GPIOQEN_Pos (16UL) +#define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENR_PWREN_Pos (18UL) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */ +#define RCC_AHB4ENR_CRCEN_Pos (19UL) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENR register ******************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0UL) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENR_DMA2DEN_Pos (1UL) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENR_JPEGEN_Pos (3UL) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */ +#define RCC_AHB5ENR_FMCEN_Pos (4UL) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */ +#define RCC_AHB5ENR_XSPI1EN_Pos (5UL) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENR_PSSIEN_Pos (6UL) +#define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */ +#define RCC_AHB5ENR_SDMMC2EN_Pos (7UL) +#define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENR_SDMMC1EN_Pos (8UL) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENR_XSPI2EN_Pos (12UL) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENR_XSPIMEN_Pos (13UL) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENR_MCE1EN_Pos (14UL) +#define RCC_AHB5ENR_MCE1EN_Msk (0x1UL << RCC_AHB5ENR_MCE1EN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_MCE1EN RCC_AHB5ENR_MCE1EN_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENR_MCE2EN_Pos (15UL) +#define RCC_AHB5ENR_MCE2EN_Msk (0x1UL << RCC_AHB5ENR_MCE2EN_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENR_MCE2EN RCC_AHB5ENR_MCE2EN_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENR_MCE3EN_Pos (16UL) +#define RCC_AHB5ENR_MCE3EN_Msk (0x1UL << RCC_AHB5ENR_MCE3EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENR_MCE3EN RCC_AHB5ENR_MCE3EN_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENR_XSPI3EN_Pos (17UL) +#define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENR_MCE4EN_Pos (18UL) +#define RCC_AHB5ENR_MCE4EN_Msk (0x1UL << RCC_AHB5ENR_MCE4EN_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENR_MCE4EN RCC_AHB5ENR_MCE4EN_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENR_GFXMMUEN_Pos (19UL) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENR_GPU2DEN_Pos (20UL) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENR_ETH1MACEN_Pos (22UL) +#define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENR_ETH1TXEN_Pos (23UL) +#define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENR_ETH1RXEN_Pos (24UL) +#define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENR_ETH1EN_Pos (25UL) +#define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENR_OTG1EN_Pos (26UL) +#define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENR_OTGPHY1EN_Pos (27UL) +#define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENR_OTGPHY2EN_Pos (28UL) +#define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENR_OTG2EN_Pos (29UL) +#define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENR_CACHEAXIEN_Pos (30UL) +#define RCC_AHB5ENR_CACHEAXIEN_Msk (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENR_CACHEAXIEN RCC_AHB5ENR_CACHEAXIEN_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENR_NPUEN_Pos (31UL) +#define RCC_AHB5ENR_NPUEN_Msk (0x1UL << RCC_AHB5ENR_NPUEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENR_NPUEN RCC_AHB5ENR_NPUEN_Msk /*!< NPU enable */ + +/***************** Bit definition for RCC_APB1ENR1 register *****************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0UL) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */ +#define RCC_APB1ENR1_TIM3EN_Pos (1UL) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */ +#define RCC_APB1ENR1_TIM4EN_Pos (2UL) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */ +#define RCC_APB1ENR1_TIM5EN_Pos (3UL) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */ +#define RCC_APB1ENR1_TIM6EN_Pos (4UL) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */ +#define RCC_APB1ENR1_TIM7EN_Pos (5UL) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */ +#define RCC_APB1ENR1_TIM12EN_Pos (6UL) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */ +#define RCC_APB1ENR1_TIM13EN_Pos (7UL) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */ +#define RCC_APB1ENR1_TIM14EN_Pos (8UL) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */ +#define RCC_APB1ENR1_LPTIM1EN_Pos (9UL) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENR1_WWDGEN_Pos (11UL) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */ +#define RCC_APB1ENR1_TIM10EN_Pos (12UL) +#define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */ +#define RCC_APB1ENR1_TIM11EN_Pos (13UL) +#define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */ +#define RCC_APB1ENR1_SPI2EN_Pos (14UL) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */ +#define RCC_APB1ENR1_SPI3EN_Pos (15UL) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */ +#define RCC_APB1ENR1_SPDIFRX1EN_Pos (16UL) +#define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENR1_USART2EN_Pos (17UL) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */ +#define RCC_APB1ENR1_USART3EN_Pos (18UL) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */ +#define RCC_APB1ENR1_UART4EN_Pos (19UL) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */ +#define RCC_APB1ENR1_UART5EN_Pos (20UL) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */ +#define RCC_APB1ENR1_I2C1EN_Pos (21UL) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */ +#define RCC_APB1ENR1_I2C2EN_Pos (22UL) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */ +#define RCC_APB1ENR1_I2C3EN_Pos (23UL) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */ +#define RCC_APB1ENR1_I3C1EN_Pos (24UL) +#define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */ +#define RCC_APB1ENR1_I3C2EN_Pos (25UL) +#define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */ +#define RCC_APB1ENR1_UART7EN_Pos (30UL) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */ +#define RCC_APB1ENR1_UART8EN_Pos (31UL) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */ + +/***************** Bit definition for RCC_APB1ENR2 register *****************/ +#define RCC_APB1ENR2_MDIOSEN_Pos (5UL) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */ +#define RCC_APB1ENR2_FDCANEN_Pos (8UL) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */ +#define RCC_APB1ENR2_UCPD1EN_Pos (18UL) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENR register ******************/ +#define RCC_APB2ENR_TIM1EN_Pos (0UL) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */ +#define RCC_APB2ENR_TIM8EN_Pos (1UL) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */ +#define RCC_APB2ENR_USART1EN_Pos (4UL) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */ +#define RCC_APB2ENR_USART6EN_Pos (5UL) +#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */ +#define RCC_APB2ENR_UART9EN_Pos (6UL) +#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */ +#define RCC_APB2ENR_USART10EN_Pos (7UL) +#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12UL) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */ +#define RCC_APB2ENR_SPI4EN_Pos (13UL) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */ +#define RCC_APB2ENR_TIM18EN_Pos (15UL) +#define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16UL) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17UL) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18UL) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */ +#define RCC_APB2ENR_TIM9EN_Pos (19UL) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */ +#define RCC_APB2ENR_SPI5EN_Pos (20UL) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */ +#define RCC_APB2ENR_SAI1EN_Pos (21UL) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */ +#define RCC_APB2ENR_SAI2EN_Pos (22UL) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENR register ******************/ +#define RCC_APB3ENR_DFTEN_Pos (2UL) +#define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */ + +/***************** Bit definition for RCC_APB4ENR1 register *****************/ +#define RCC_APB4ENR1_HDPEN_Pos (2UL) +#define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */ +#define RCC_APB4ENR1_LPUART1EN_Pos (3UL) +#define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENR1_SPI6EN_Pos (5UL) +#define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */ +#define RCC_APB4ENR1_I2C4EN_Pos (7UL) +#define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */ +#define RCC_APB4ENR1_LPTIM2EN_Pos (9UL) +#define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENR1_LPTIM3EN_Pos (10UL) +#define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENR1_LPTIM4EN_Pos (11UL) +#define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENR1_LPTIM5EN_Pos (12UL) +#define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENR1_VREFBUFEN_Pos (15UL) +#define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENR1_RTCEN_Pos (16UL) +#define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */ +#define RCC_APB4ENR1_RTCAPBEN_Pos (17UL) +#define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */ + +/***************** Bit definition for RCC_APB4ENR2 register *****************/ +#define RCC_APB4ENR2_SYSCFGEN_Pos (0UL) +#define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENR2_BSECEN_Pos (1UL) +#define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */ +#define RCC_APB4ENR2_DTSEN_Pos (2UL) +#define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENR register ******************/ +#define RCC_APB5ENR_LTDCEN_Pos (1UL) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */ +#define RCC_APB5ENR_DCMIPPEN_Pos (2UL) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENR_GFXTIMEN_Pos (4UL) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENR_VENCEN_Pos (5UL) +#define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */ +#define RCC_APB5ENR_CSIEN_Pos (6UL) +#define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */ + +/***************** Bit definition for RCC_BUSLPENR register *****************/ +#define RCC_BUSLPENR_ACLKNLPEN_Pos (0UL) +#define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENR_ACLKNCLPEN_Pos (1UL) +#define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */ +#define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENR register *****************/ +#define RCC_MISCLPENR_DBGLPEN_Pos (0UL) +#define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3UL) +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENR_PERLPEN_Pos (6UL) +#define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMLPENR register *****************/ +#define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0UL) +#define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1UL) +#define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2UL) +#define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3UL) +#define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4UL) +#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5UL) +#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6UL) +#define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7UL) +#define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8UL) +#define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9UL) +#define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos (10UL) +#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENR_CACHEAXIRAMLPEN RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMLPENR_VENCRAMLPEN_Pos (11UL) +#define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENR_BOOTROMLPEN_Pos (12UL) +#define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENR register *****************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4UL) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5UL) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENR register *****************/ +#define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12UL) +#define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENR_MDF1LPEN_Pos (16UL) +#define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENR_ADF1LPEN_Pos (17UL) +#define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENR register *****************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0UL) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */ +#define RCC_AHB3LPENR_HASHLPEN_Pos (1UL) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */ +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2UL) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk /*!< CRYP enable */ +#define RCC_AHB3LPENR_SAESLPEN_Pos (4UL) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk /*!< SAES enable */ +#define RCC_AHB3LPENR_PKALPEN_Pos (8UL) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */ +#define RCC_AHB3LPENR_RIFSCLPEN_Pos (9UL) +#define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */ +#define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENR_IACLPEN_Pos (10UL) +#define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */ +#define RCC_AHB3LPENR_RISAFLPEN_Pos (14UL) +#define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENR register *****************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0UL) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1UL) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2UL) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3UL) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4UL) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5UL) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6UL) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7UL) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13UL) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14UL) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15UL) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENR_GPIOQLPEN_Pos (16UL) +#define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */ +#define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENR_PWRLPEN_Pos (18UL) +#define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */ +#define RCC_AHB4LPENR_CRCLPEN_Pos (19UL) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENR register *****************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0UL) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1UL) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3UL) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENR_FMCLPEN_Pos (4UL) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */ +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5UL) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENR_PSSILPEN_Pos (6UL) +#define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7UL) +#define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8UL) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12UL) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (13UL) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENR_MCE1LPEN_Pos (14UL) +#define RCC_AHB5LPENR_MCE1LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_MCE1LPEN RCC_AHB5LPENR_MCE1LPEN_Msk /*!< MCE1 enable */ +#define RCC_AHB5LPENR_MCE2LPEN_Pos (15UL) +#define RCC_AHB5LPENR_MCE2LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENR_MCE2LPEN RCC_AHB5LPENR_MCE2LPEN_Msk /*!< MCE2 enable */ +#define RCC_AHB5LPENR_MCE3LPEN_Pos (16UL) +#define RCC_AHB5LPENR_MCE3LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENR_MCE3LPEN RCC_AHB5LPENR_MCE3LPEN_Msk /*!< MCE3 enable */ +#define RCC_AHB5LPENR_XSPI3LPEN_Pos (17UL) +#define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENR_MCE4LPEN_Pos (18UL) +#define RCC_AHB5LPENR_MCE4LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENR_MCE4LPEN RCC_AHB5LPENR_MCE4LPEN_Msk /*!< MCE4 enable */ +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19UL) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20UL) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22UL) +#define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23UL) +#define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24UL) +#define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENR_ETH1LPEN_Pos (25UL) +#define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENR_OTG1LPEN_Pos (26UL) +#define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27UL) +#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28UL) +#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENR_OTG2LPEN_Pos (29UL) +#define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */ +#define RCC_AHB5LPENR_CACHEAXILPEN_Pos (30UL) +#define RCC_AHB5LPENR_CACHEAXILPEN_Msk (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_CACHEAXILPEN RCC_AHB5LPENR_CACHEAXILPEN_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5LPENR_NPULPEN_Pos (31UL) +#define RCC_AHB5LPENR_NPULPEN_Msk (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_NPULPEN RCC_AHB5LPENR_NPULPEN_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1LPENR1 register ****************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0UL) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1UL) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2UL) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3UL) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4UL) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5UL) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6UL) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7UL) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8UL) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9UL) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11UL) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */ +#define RCC_APB1LPENR1_TIM10LPEN_Pos (12UL) +#define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENR1_TIM11LPEN_Pos (13UL) +#define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14UL) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15UL) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16UL) +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENR1_USART2LPEN_Pos (17UL) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */ +#define RCC_APB1LPENR1_USART3LPEN_Pos (18UL) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */ +#define RCC_APB1LPENR1_UART4LPEN_Pos (19UL) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */ +#define RCC_APB1LPENR1_UART5LPEN_Pos (20UL) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */ +#define RCC_APB1LPENR1_I2C1LPEN_Pos (21UL) +#define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22UL) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23UL) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENR1_I3C1LPEN_Pos (24UL) +#define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */ +#define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENR1_I3C2LPEN_Pos (25UL) +#define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */ +#define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENR1_UART7LPEN_Pos (30UL) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */ +#define RCC_APB1LPENR1_UART8LPEN_Pos (31UL) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1LPENR2 register ****************/ +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5UL) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */ +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8UL) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */ +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (18UL) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */ + +/**************** Bit definition for RCC_APB2LPENR register *****************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0UL) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (1UL) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENR_USART1LPEN_Pos (4UL) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */ +#define RCC_APB2LPENR_USART6LPEN_Pos (5UL) +#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */ +#define RCC_APB2LPENR_UART9LPEN_Pos (6UL) +#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */ +#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */ +#define RCC_APB2LPENR_USART10LPEN_Pos (7UL) +#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12UL) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENR_SPI4LPEN_Pos (13UL) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENR_TIM18LPEN_Pos (15UL) +#define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16UL) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17UL) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18UL) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENR_TIM9LPEN_Pos (19UL) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENR_SPI5LPEN_Pos (20UL) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENR_SAI1LPEN_Pos (21UL) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENR_SAI2LPEN_Pos (22UL) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENR register *****************/ +#define RCC_APB3LPENR_DFTLPEN_Pos (2UL) +#define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4LPENR1 register ****************/ +#define RCC_APB4LPENR1_HDPLPEN_Pos (2UL) +#define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */ +#define RCC_APB4LPENR1_LPUART1LPEN_Pos (3UL) +#define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENR1_SPI6LPEN_Pos (5UL) +#define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENR1_I2C4LPEN_Pos (7UL) +#define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */ +#define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9UL) +#define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10UL) +#define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11UL) +#define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12UL) +#define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15UL) +#define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENR1_RTCLPEN_Pos (16UL) +#define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */ +#define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17UL) +#define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4LPENR2 register ****************/ +#define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0UL) +#define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENR2_BSECLPEN_Pos (1UL) +#define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */ +#define RCC_APB4LPENR2_DTSLPEN_Pos (2UL) +#define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENR register *****************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1UL) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2UL) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4UL) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENR_VENCLPEN_Pos (5UL) +#define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */ +#define RCC_APB5LPENR_CSILPEN_Pos (6UL) +#define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */ + +/******************* Bit definition for RCC_RDCR register *******************/ +#define RCC_RDCR_MRD_Pos (16UL) +#define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */ + +/***************** Bit definition for RCC_SECCFGR0 register *****************/ +#define RCC_SECCFGR0_LSISEC_Pos (0UL) +#define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */ +#define RCC_SECCFGR0_LSESEC_Pos (1UL) +#define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */ +#define RCC_SECCFGR0_MSISEC_Pos (2UL) +#define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSISEC_Pos (3UL) +#define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSESEC_Pos (4UL) +#define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR0 register *****************/ +#define RCC_PRIVCFGR0_LSIPRIV_Pos (0UL) +#define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_LSEPRIV_Pos (1UL) +#define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */ +#define RCC_PRIVCFGR0_MSIPRIV_Pos (2UL) +#define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSIPRIV_Pos (3UL) +#define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSEPRIV_Pos (4UL) +#define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR0 register *****************/ +#define RCC_LOCKCFGR0_LSILOCK_Pos (0UL) +#define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_LSELOCK_Pos (1UL) +#define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */ +#define RCC_LOCKCFGR0_MSILOCK_Pos (2UL) +#define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSILOCK_Pos (3UL) +#define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSELOCK_Pos (4UL) +#define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR0 register *****************/ +#define RCC_PUBCFGR0_LSIPUB_Pos (0UL) +#define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */ +#define RCC_PUBCFGR0_LSEPUB_Pos (1UL) +#define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */ +#define RCC_PUBCFGR0_MSIPUB_Pos (2UL) +#define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSIPUB_Pos (3UL) +#define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSEPUB_Pos (4UL) +#define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_SECCFGR1 register *****************/ +#define RCC_SECCFGR1_PLL1SEC_Pos (0UL) +#define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */ +#define RCC_SECCFGR1_PLL2SEC_Pos (1UL) +#define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */ +#define RCC_SECCFGR1_PLL3SEC_Pos (2UL) +#define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */ +#define RCC_SECCFGR1_PLL4SEC_Pos (3UL) +#define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR1 register *****************/ +#define RCC_PRIVCFGR1_PLL1PRIV_Pos (0UL) +#define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */ +#define RCC_PRIVCFGR1_PLL2PRIV_Pos (1UL) +#define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */ +#define RCC_PRIVCFGR1_PLL3PRIV_Pos (2UL) +#define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */ +#define RCC_PRIVCFGR1_PLL4PRIV_Pos (3UL) +#define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR1 register *****************/ +#define RCC_LOCKCFGR1_PLL1LOCK_Pos (0UL) +#define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */ +#define RCC_LOCKCFGR1_PLL2LOCK_Pos (1UL) +#define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */ +#define RCC_LOCKCFGR1_PLL3LOCK_Pos (2UL) +#define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */ +#define RCC_LOCKCFGR1_PLL4LOCK_Pos (3UL) +#define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR1 register *****************/ +#define RCC_PUBCFGR1_PLL1PUB_Pos (0UL) +#define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */ +#define RCC_PUBCFGR1_PLL2PUB_Pos (1UL) +#define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */ +#define RCC_PUBCFGR1_PLL3PUB_Pos (2UL) +#define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */ +#define RCC_PUBCFGR1_PLL4PUB_Pos (3UL) +#define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_SECCFGR2 register *****************/ +#define RCC_SECCFGR2_IC1SEC_Pos (0UL) +#define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */ +#define RCC_SECCFGR2_IC2SEC_Pos (1UL) +#define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */ +#define RCC_SECCFGR2_IC3SEC_Pos (2UL) +#define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */ +#define RCC_SECCFGR2_IC4SEC_Pos (3UL) +#define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */ +#define RCC_SECCFGR2_IC5SEC_Pos (4UL) +#define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */ +#define RCC_SECCFGR2_IC6SEC_Pos (5UL) +#define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */ +#define RCC_SECCFGR2_IC7SEC_Pos (6UL) +#define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */ +#define RCC_SECCFGR2_IC8SEC_Pos (7UL) +#define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */ +#define RCC_SECCFGR2_IC9SEC_Pos (8UL) +#define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */ +#define RCC_SECCFGR2_IC10SEC_Pos (9UL) +#define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */ +#define RCC_SECCFGR2_IC11SEC_Pos (10UL) +#define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */ +#define RCC_SECCFGR2_IC12SEC_Pos (11UL) +#define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */ +#define RCC_SECCFGR2_IC13SEC_Pos (12UL) +#define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */ +#define RCC_SECCFGR2_IC14SEC_Pos (13UL) +#define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */ +#define RCC_SECCFGR2_IC15SEC_Pos (14UL) +#define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */ +#define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */ +#define RCC_SECCFGR2_IC16SEC_Pos (15UL) +#define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */ +#define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */ +#define RCC_SECCFGR2_IC17SEC_Pos (16UL) +#define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */ +#define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */ +#define RCC_SECCFGR2_IC18SEC_Pos (17UL) +#define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */ +#define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */ +#define RCC_SECCFGR2_IC19SEC_Pos (18UL) +#define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */ +#define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */ +#define RCC_SECCFGR2_IC20SEC_Pos (19UL) +#define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */ +#define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR2 register *****************/ +#define RCC_PRIVCFGR2_IC1PRIV_Pos (0UL) +#define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */ +#define RCC_PRIVCFGR2_IC2PRIV_Pos (1UL) +#define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */ +#define RCC_PRIVCFGR2_IC3PRIV_Pos (2UL) +#define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */ +#define RCC_PRIVCFGR2_IC4PRIV_Pos (3UL) +#define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */ +#define RCC_PRIVCFGR2_IC5PRIV_Pos (4UL) +#define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */ +#define RCC_PRIVCFGR2_IC6PRIV_Pos (5UL) +#define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */ +#define RCC_PRIVCFGR2_IC7PRIV_Pos (6UL) +#define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */ +#define RCC_PRIVCFGR2_IC8PRIV_Pos (7UL) +#define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */ +#define RCC_PRIVCFGR2_IC9PRIV_Pos (8UL) +#define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */ +#define RCC_PRIVCFGR2_IC10PRIV_Pos (9UL) +#define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */ +#define RCC_PRIVCFGR2_IC11PRIV_Pos (10UL) +#define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */ +#define RCC_PRIVCFGR2_IC12PRIV_Pos (11UL) +#define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */ +#define RCC_PRIVCFGR2_IC13PRIV_Pos (12UL) +#define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */ +#define RCC_PRIVCFGR2_IC14PRIV_Pos (13UL) +#define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */ +#define RCC_PRIVCFGR2_IC15PRIV_Pos (14UL) +#define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */ +#define RCC_PRIVCFGR2_IC16PRIV_Pos (15UL) +#define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */ +#define RCC_PRIVCFGR2_IC17PRIV_Pos (16UL) +#define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */ +#define RCC_PRIVCFGR2_IC18PRIV_Pos (17UL) +#define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */ +#define RCC_PRIVCFGR2_IC19PRIV_Pos (18UL) +#define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */ +#define RCC_PRIVCFGR2_IC20PRIV_Pos (19UL) +#define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR2 register *****************/ +#define RCC_LOCKCFGR2_IC1LOCK_Pos (0UL) +#define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */ +#define RCC_LOCKCFGR2_IC2LOCK_Pos (1UL) +#define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */ +#define RCC_LOCKCFGR2_IC3LOCK_Pos (2UL) +#define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */ +#define RCC_LOCKCFGR2_IC4LOCK_Pos (3UL) +#define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */ +#define RCC_LOCKCFGR2_IC5LOCK_Pos (4UL) +#define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */ +#define RCC_LOCKCFGR2_IC6LOCK_Pos (5UL) +#define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */ +#define RCC_LOCKCFGR2_IC7LOCK_Pos (6UL) +#define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */ +#define RCC_LOCKCFGR2_IC8LOCK_Pos (7UL) +#define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */ +#define RCC_LOCKCFGR2_IC9LOCK_Pos (8UL) +#define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */ +#define RCC_LOCKCFGR2_IC10LOCK_Pos (9UL) +#define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */ +#define RCC_LOCKCFGR2_IC11LOCK_Pos (10UL) +#define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */ +#define RCC_LOCKCFGR2_IC12LOCK_Pos (11UL) +#define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */ +#define RCC_LOCKCFGR2_IC13LOCK_Pos (12UL) +#define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */ +#define RCC_LOCKCFGR2_IC14LOCK_Pos (13UL) +#define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */ +#define RCC_LOCKCFGR2_IC15LOCK_Pos (14UL) +#define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */ +#define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */ +#define RCC_LOCKCFGR2_IC16LOCK_Pos (15UL) +#define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */ +#define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */ +#define RCC_LOCKCFGR2_IC17LOCK_Pos (16UL) +#define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */ +#define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */ +#define RCC_LOCKCFGR2_IC18LOCK_Pos (17UL) +#define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */ +#define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */ +#define RCC_LOCKCFGR2_IC19LOCK_Pos (18UL) +#define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */ +#define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */ +#define RCC_LOCKCFGR2_IC20LOCK_Pos (19UL) +#define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */ +#define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR2 register *****************/ +#define RCC_PUBCFGR2_IC1PUB_Pos (0UL) +#define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */ +#define RCC_PUBCFGR2_IC2PUB_Pos (1UL) +#define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */ +#define RCC_PUBCFGR2_IC3PUB_Pos (2UL) +#define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */ +#define RCC_PUBCFGR2_IC4PUB_Pos (3UL) +#define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */ +#define RCC_PUBCFGR2_IC5PUB_Pos (4UL) +#define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */ +#define RCC_PUBCFGR2_IC6PUB_Pos (5UL) +#define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */ +#define RCC_PUBCFGR2_IC7PUB_Pos (6UL) +#define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */ +#define RCC_PUBCFGR2_IC8PUB_Pos (7UL) +#define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */ +#define RCC_PUBCFGR2_IC9PUB_Pos (8UL) +#define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */ +#define RCC_PUBCFGR2_IC10PUB_Pos (9UL) +#define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */ +#define RCC_PUBCFGR2_IC11PUB_Pos (10UL) +#define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */ +#define RCC_PUBCFGR2_IC12PUB_Pos (11UL) +#define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */ +#define RCC_PUBCFGR2_IC13PUB_Pos (12UL) +#define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */ +#define RCC_PUBCFGR2_IC14PUB_Pos (13UL) +#define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */ +#define RCC_PUBCFGR2_IC15PUB_Pos (14UL) +#define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */ +#define RCC_PUBCFGR2_IC16PUB_Pos (15UL) +#define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */ +#define RCC_PUBCFGR2_IC17PUB_Pos (16UL) +#define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */ +#define RCC_PUBCFGR2_IC18PUB_Pos (17UL) +#define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */ +#define RCC_PUBCFGR2_IC19PUB_Pos (18UL) +#define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */ +#define RCC_PUBCFGR2_IC20PUB_Pos (19UL) +#define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_SECCFGR3 register *****************/ +#define RCC_SECCFGR3_MODSEC_Pos (0UL) +#define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */ +#define RCC_SECCFGR3_SYSSEC_Pos (1UL) +#define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */ +#define RCC_SECCFGR3_BUSSEC_Pos (2UL) +#define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */ +#define RCC_SECCFGR3_PERSEC_Pos (3UL) +#define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */ +#define RCC_SECCFGR3_INTSEC_Pos (4UL) +#define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */ +#define RCC_SECCFGR3_RSTSEC_Pos (5UL) +#define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR3 register *****************/ +#define RCC_PRIVCFGR3_MODPRIV_Pos (0UL) +#define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */ +#define RCC_PRIVCFGR3_SYSPRIV_Pos (1UL) +#define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */ +#define RCC_PRIVCFGR3_BUSPRIV_Pos (2UL) +#define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */ +#define RCC_PRIVCFGR3_PERPRIV_Pos (3UL) +#define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */ +#define RCC_PRIVCFGR3_INTPRIV_Pos (4UL) +#define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */ +#define RCC_PRIVCFGR3_RSTPRIV_Pos (5UL) +#define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR3 register *****************/ +#define RCC_LOCKCFGR3_MODLOCK_Pos (0UL) +#define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */ +#define RCC_LOCKCFGR3_SYSLOCK_Pos (1UL) +#define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */ +#define RCC_LOCKCFGR3_BUSLOCK_Pos (2UL) +#define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */ +#define RCC_LOCKCFGR3_PERLOCK_Pos (3UL) +#define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */ +#define RCC_LOCKCFGR3_INTLOCK_Pos (4UL) +#define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */ +#define RCC_LOCKCFGR3_RSTLOCK_Pos (5UL) +#define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR3 register *****************/ +#define RCC_PUBCFGR3_MODPUB_Pos (0UL) +#define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */ +#define RCC_PUBCFGR3_SYSPUB_Pos (1UL) +#define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */ +#define RCC_PUBCFGR3_BUSPUB_Pos (2UL) +#define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */ +#define RCC_PUBCFGR3_PERPUB_Pos (3UL) +#define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */ +#define RCC_PUBCFGR3_INTPUB_Pos (4UL) +#define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */ +#define RCC_PUBCFGR3_RSTPUB_Pos (5UL) +#define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */ + +/***************** Bit definition for RCC_SECCFGR4 register *****************/ +#define RCC_SECCFGR4_ACLKNSEC_Pos (0UL) +#define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */ +#define RCC_SECCFGR4_ACLKNCSEC_Pos (1UL) +#define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */ +#define RCC_SECCFGR4_AHBMSEC_Pos (2UL) +#define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */ +#define RCC_SECCFGR4_AHB1SEC_Pos (3UL) +#define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */ +#define RCC_SECCFGR4_AHB2SEC_Pos (4UL) +#define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */ +#define RCC_SECCFGR4_AHB3SEC_Pos (5UL) +#define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */ +#define RCC_SECCFGR4_AHB4SEC_Pos (6UL) +#define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */ +#define RCC_SECCFGR4_AHB5SEC_Pos (7UL) +#define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */ +#define RCC_SECCFGR4_APB1SEC_Pos (8UL) +#define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */ +#define RCC_SECCFGR4_APB2SEC_Pos (9UL) +#define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */ +#define RCC_SECCFGR4_APB3SEC_Pos (10UL) +#define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */ +#define RCC_SECCFGR4_APB4SEC_Pos (11UL) +#define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */ +#define RCC_SECCFGR4_APB5SEC_Pos (12UL) +#define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */ +#define RCC_SECCFGR4_NOCSEC_Pos (13UL) +#define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR4 register *****************/ +#define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0UL) +#define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */ +#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1UL) +#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */ +#define RCC_PRIVCFGR4_AHBMPRIV_Pos (2UL) +#define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */ +#define RCC_PRIVCFGR4_AHB1PRIV_Pos (3UL) +#define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB2PRIV_Pos (4UL) +#define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB3PRIV_Pos (5UL) +#define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB4PRIV_Pos (6UL) +#define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB5PRIV_Pos (7UL) +#define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */ +#define RCC_PRIVCFGR4_APB1PRIV_Pos (8UL) +#define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */ +#define RCC_PRIVCFGR4_APB2PRIV_Pos (9UL) +#define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */ +#define RCC_PRIVCFGR4_APB3PRIV_Pos (10UL) +#define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */ +#define RCC_PRIVCFGR4_APB4PRIV_Pos (11UL) +#define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */ +#define RCC_PRIVCFGR4_APB5PRIV_Pos (12UL) +#define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */ +#define RCC_PRIVCFGR4_NOCPRIV_Pos (13UL) +#define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR4 register *****************/ +#define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0UL) +#define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */ +#define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */ +#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1UL) +#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */ +#define RCC_LOCKCFGR4_AHBMLOCK_Pos (2UL) +#define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */ +#define RCC_LOCKCFGR4_AHB1LOCK_Pos (3UL) +#define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB2LOCK_Pos (4UL) +#define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB3LOCK_Pos (5UL) +#define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB4LOCK_Pos (6UL) +#define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB5LOCK_Pos (7UL) +#define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */ +#define RCC_LOCKCFGR4_APB1LOCK_Pos (8UL) +#define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */ +#define RCC_LOCKCFGR4_APB2LOCK_Pos (9UL) +#define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */ +#define RCC_LOCKCFGR4_APB3LOCK_Pos (10UL) +#define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */ +#define RCC_LOCKCFGR4_APB4LOCK_Pos (11UL) +#define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */ +#define RCC_LOCKCFGR4_APB5LOCK_Pos (12UL) +#define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */ +#define RCC_LOCKCFGR4_NOCLOCK_Pos (13UL) +#define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR4 register *****************/ +#define RCC_PUBCFGR4_ACLKNPUB_Pos (0UL) +#define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */ +#define RCC_PUBCFGR4_ACLKNCPUB_Pos (1UL) +#define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */ +#define RCC_PUBCFGR4_AHBMPUB_Pos (2UL) +#define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */ +#define RCC_PUBCFGR4_AHB1PUB_Pos (3UL) +#define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */ +#define RCC_PUBCFGR4_AHB2PUB_Pos (4UL) +#define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */ +#define RCC_PUBCFGR4_AHB3PUB_Pos (5UL) +#define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */ +#define RCC_PUBCFGR4_AHB4PUB_Pos (6UL) +#define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */ +#define RCC_PUBCFGR4_AHB5PUB_Pos (7UL) +#define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */ +#define RCC_PUBCFGR4_APB1PUB_Pos (8UL) +#define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */ +#define RCC_PUBCFGR4_APB2PUB_Pos (9UL) +#define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */ +#define RCC_PUBCFGR4_APB3PUB_Pos (10UL) +#define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */ +#define RCC_PUBCFGR4_APB4PUB_Pos (11UL) +#define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */ +#define RCC_PUBCFGR4_APB5PUB_Pos (12UL) +#define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */ +#define RCC_PUBCFGR4_NOCPUB_Pos (13UL) +#define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR5 register *****************/ +#define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0UL) +#define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1UL) +#define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2UL) +#define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3UL) +#define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4UL) +#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5UL) +#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6UL) +#define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */ +#define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7UL) +#define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8UL) +#define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9UL) +#define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */ +#define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */ +#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos (10UL) +#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR5_CACHEAXIRAMPUB RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk /*!< Public protection of CACHEAXIRAM bus configuration bits */ +#define RCC_PUBCFGR5_VENCRAMPUB_Pos (11UL) +#define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */ +#define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSIONS_Pos (0UL) +#define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */ +#define RCC_CSR_LSEONS_Pos (1UL) +#define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */ +#define RCC_CSR_MSIONS_Pos (2UL) +#define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */ +#define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */ +#define RCC_CSR_HSIONS_Pos (3UL) +#define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */ +#define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */ +#define RCC_CSR_HSEONS_Pos (4UL) +#define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */ +#define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */ +#define RCC_CSR_PLL1ONS_Pos (8UL) +#define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */ +#define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */ +#define RCC_CSR_PLL2ONS_Pos (9UL) +#define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */ +#define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */ +#define RCC_CSR_PLL3ONS_Pos (10UL) +#define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */ +#define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */ +#define RCC_CSR_PLL4ONS_Pos (11UL) +#define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */ +#define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCSR register ******************/ +#define RCC_STOPCSR_MSISTOPENS_Pos (0UL) +#define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */ +#define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCSR_HSISTOPENS_Pos (1UL) +#define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */ +#define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTSR register *****************/ +#define RCC_MISCRSTSR_DBGRSTS_Pos (0UL) +#define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4UL) +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5UL) +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7UL) +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8UL) +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTSR register *****************/ +#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0UL) +#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1UL) +#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2UL) +#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3UL) +#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4UL) +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5UL) +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7UL) +#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8UL) +#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9UL) +#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos (10UL) +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11UL) +#define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12UL) +#define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTSR register *****************/ +#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4UL) +#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTSR_ADC12RSTS_Pos (5UL) +#define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTSR register *****************/ +#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12UL) +#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTSR_MDF1RSTS_Pos (16UL) +#define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTSR_ADF1RSTS_Pos (17UL) +#define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTSR register *****************/ +#define RCC_AHB3RSTSR_RNGRSTS_Pos (0UL) +#define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */ +#define RCC_AHB3RSTSR_HASHRSTS_Pos (1UL) +#define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */ +#define RCC_AHB3RSTSR_CRYPRSTS_Pos (2UL) +#define RCC_AHB3RSTSR_CRYPRSTS_Msk (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTSR_CRYPRSTS RCC_AHB3RSTSR_CRYPRSTS_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTSR_SAESRSTS_Pos (4UL) +#define RCC_AHB3RSTSR_SAESRSTS_Msk (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSR_SAESRSTS RCC_AHB3RSTSR_SAESRSTS_Msk /*!< SAES reset */ +#define RCC_AHB3RSTSR_PKARSTS_Pos (8UL) +#define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */ +#define RCC_AHB3RSTSR_IACRSTS_Pos (10UL) +#define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTSR register *****************/ +#define RCC_AHB4RSTSR_GPIOARSTS_Pos (0UL) +#define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1UL) +#define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2UL) +#define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTSR_GPIODRSTS_Pos (3UL) +#define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTSR_GPIOERSTS_Pos (4UL) +#define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5UL) +#define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6UL) +#define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7UL) +#define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTSR_GPIONRSTS_Pos (13UL) +#define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTSR_GPIOORSTS_Pos (14UL) +#define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15UL) +#define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16UL) +#define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTSR_PWRRSTS_Pos (18UL) +#define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */ +#define RCC_AHB4RSTSR_CRCRSTS_Pos (19UL) +#define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTSR register *****************/ +#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0UL) +#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1UL) +#define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTSR_JPEGRSTS_Pos (3UL) +#define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTSR_FMCRSTS_Pos (4UL) +#define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */ +#define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5UL) +#define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTSR_PSSIRSTS_Pos (6UL) +#define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7UL) +#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8UL) +#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12UL) +#define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13UL) +#define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17UL) +#define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19UL) +#define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20UL) +#define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23UL) +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24UL) +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTSR_ETH1RSTS_Pos (25UL) +#define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTSR_OTG1RSTS_Pos (26UL) +#define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27UL) +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28UL) +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTSR_OTG2RSTS_Pos (29UL) +#define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos (30UL) +#define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTSR_CACHEAXIRSTS RCC_AHB5RSTSR_CACHEAXIRSTS_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTSR_NPURSTS_Pos (31UL) +#define RCC_AHB5RSTSR_NPURSTS_Msk (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTSR_NPURSTS RCC_AHB5RSTSR_NPURSTS_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTSR1 register ****************/ +#define RCC_APB1RSTSR1_TIM2RSTS_Pos (0UL) +#define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTSR1_TIM3RSTS_Pos (1UL) +#define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTSR1_TIM4RSTS_Pos (2UL) +#define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTSR1_TIM5RSTS_Pos (3UL) +#define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTSR1_TIM6RSTS_Pos (4UL) +#define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTSR1_TIM7RSTS_Pos (5UL) +#define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTSR1_TIM12RSTS_Pos (6UL) +#define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTSR1_TIM13RSTS_Pos (7UL) +#define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTSR1_TIM14RSTS_Pos (8UL) +#define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9UL) +#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTSR1_WWDGRSTS_Pos (11UL) +#define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */ +#define RCC_APB1RSTSR1_TIM10RSTS_Pos (12UL) +#define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTSR1_TIM11RSTS_Pos (13UL) +#define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTSR1_SPI2RSTS_Pos (14UL) +#define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTSR1_SPI3RSTS_Pos (15UL) +#define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16UL) +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTSR1_USART2RSTS_Pos (17UL) +#define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */ +#define RCC_APB1RSTSR1_USART3RSTS_Pos (18UL) +#define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */ +#define RCC_APB1RSTSR1_UART4RSTS_Pos (19UL) +#define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */ +#define RCC_APB1RSTSR1_UART5RSTS_Pos (20UL) +#define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */ +#define RCC_APB1RSTSR1_I2C1RSTS_Pos (21UL) +#define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTSR1_I2C2RSTS_Pos (22UL) +#define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTSR1_I2C3RSTS_Pos (23UL) +#define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTSR1_I3C1RSTS_Pos (24UL) +#define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTSR1_I3C2RSTS_Pos (25UL) +#define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTSR1_UART7RSTS_Pos (30UL) +#define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */ +#define RCC_APB1RSTSR1_UART8RSTS_Pos (31UL) +#define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTSR2 register ****************/ +#define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5UL) +#define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTSR2_FDCANRSTS_Pos (8UL) +#define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18UL) +#define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTSR register *****************/ +#define RCC_APB2RSTSR_TIM1RSTS_Pos (0UL) +#define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTSR_TIM8RSTS_Pos (1UL) +#define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTSR_USART1RSTS_Pos (4UL) +#define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */ +#define RCC_APB2RSTSR_USART6RSTS_Pos (5UL) +#define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */ +#define RCC_APB2RSTSR_UART9RSTS_Pos (6UL) +#define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */ +#define RCC_APB2RSTSR_USART10RSTS_Pos (7UL) +#define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */ +#define RCC_APB2RSTSR_SPI1RSTS_Pos (12UL) +#define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTSR_SPI4RSTS_Pos (13UL) +#define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTSR_TIM18RSTS_Pos (15UL) +#define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTSR_TIM15RSTS_Pos (16UL) +#define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTSR_TIM16RSTS_Pos (17UL) +#define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTSR_TIM17RSTS_Pos (18UL) +#define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTSR_TIM9RSTS_Pos (19UL) +#define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTSR_SPI5RSTS_Pos (20UL) +#define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTSR_SAI1RSTS_Pos (21UL) +#define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTSR_SAI2RSTS_Pos (22UL) +#define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTSR1 register ****************/ +#define RCC_APB4RSTSR1_HDPRSTS_Pos (2UL) +#define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */ +#define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3UL) +#define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTSR1_SPI6RSTS_Pos (5UL) +#define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTSR1_I2C4RSTS_Pos (7UL) +#define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9UL) +#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10UL) +#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11UL) +#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12UL) +#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15UL) +#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTSR1_RTCRSTS_Pos (16UL) +#define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTSR2 register ****************/ +#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0UL) +#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTSR2_DTSRSTS_Pos (2UL) +#define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTSR register *****************/ +#define RCC_APB5RSTSR_LTDCRSTS_Pos (1UL) +#define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */ +#define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2UL) +#define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4UL) +#define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTSR_VENCRSTS_Pos (5UL) +#define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */ +#define RCC_APB5RSTSR_CSIRSTS_Pos (6UL) +#define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENSR register ******************/ +#define RCC_DIVENSR_IC1ENS_Pos (0UL) +#define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */ +#define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */ +#define RCC_DIVENSR_IC2ENS_Pos (1UL) +#define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */ +#define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */ +#define RCC_DIVENSR_IC3ENS_Pos (2UL) +#define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */ +#define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */ +#define RCC_DIVENSR_IC4ENS_Pos (3UL) +#define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */ +#define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */ +#define RCC_DIVENSR_IC5ENS_Pos (4UL) +#define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */ +#define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */ +#define RCC_DIVENSR_IC6ENS_Pos (5UL) +#define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */ +#define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */ +#define RCC_DIVENSR_IC7ENS_Pos (6UL) +#define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */ +#define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */ +#define RCC_DIVENSR_IC8ENS_Pos (7UL) +#define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */ +#define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */ +#define RCC_DIVENSR_IC9ENS_Pos (8UL) +#define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */ +#define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */ +#define RCC_DIVENSR_IC10ENS_Pos (9UL) +#define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */ +#define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */ +#define RCC_DIVENSR_IC11ENS_Pos (10UL) +#define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */ +#define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */ +#define RCC_DIVENSR_IC12ENS_Pos (11UL) +#define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */ +#define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */ +#define RCC_DIVENSR_IC13ENS_Pos (12UL) +#define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */ +#define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */ +#define RCC_DIVENSR_IC14ENS_Pos (13UL) +#define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */ +#define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */ +#define RCC_DIVENSR_IC15ENS_Pos (14UL) +#define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */ +#define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */ +#define RCC_DIVENSR_IC16ENS_Pos (15UL) +#define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */ +#define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */ +#define RCC_DIVENSR_IC17ENS_Pos (16UL) +#define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */ +#define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */ +#define RCC_DIVENSR_IC18ENS_Pos (17UL) +#define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */ +#define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */ +#define RCC_DIVENSR_IC19ENS_Pos (18UL) +#define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */ +#define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */ +#define RCC_DIVENSR_IC20ENS_Pos (19UL) +#define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */ +#define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENSR register ******************/ +#define RCC_BUSENSR_ACLKNENS_Pos (0UL) +#define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */ +#define RCC_BUSENSR_ACLKNCENS_Pos (1UL) +#define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */ +#define RCC_BUSENSR_AHBMENS_Pos (2UL) +#define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */ +#define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */ +#define RCC_BUSENSR_AHB1ENS_Pos (3UL) +#define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */ +#define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */ +#define RCC_BUSENSR_AHB2ENS_Pos (4UL) +#define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */ +#define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */ +#define RCC_BUSENSR_AHB3ENS_Pos (5UL) +#define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */ +#define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */ +#define RCC_BUSENSR_AHB4ENS_Pos (6UL) +#define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */ +#define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */ +#define RCC_BUSENSR_AHB5ENS_Pos (7UL) +#define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */ +#define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */ +#define RCC_BUSENSR_APB1ENS_Pos (8UL) +#define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */ +#define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */ +#define RCC_BUSENSR_APB2ENS_Pos (9UL) +#define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */ +#define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */ +#define RCC_BUSENSR_APB3ENS_Pos (10UL) +#define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */ +#define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */ +#define RCC_BUSENSR_APB4ENS_Pos (11UL) +#define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */ +#define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */ +#define RCC_BUSENSR_APB5ENS_Pos (12UL) +#define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */ +#define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENSR register *****************/ +#define RCC_MISCENSR_DBGENS_Pos (0UL) +#define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */ +#define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */ +#define RCC_MISCENSR_MCO1ENS_Pos (1UL) +#define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */ +#define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */ +#define RCC_MISCENSR_MCO2ENS_Pos (2UL) +#define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */ +#define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */ +#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3UL) +#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENSR_PERENS_Pos (6UL) +#define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */ +#define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENSR register ******************/ +#define RCC_MEMENSR_AXISRAM3ENS_Pos (0UL) +#define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */ +#define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENSR_AXISRAM4ENS_Pos (1UL) +#define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */ +#define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENSR_AXISRAM5ENS_Pos (2UL) +#define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */ +#define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENSR_AXISRAM6ENS_Pos (3UL) +#define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */ +#define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENSR_AHBSRAM1ENS_Pos (4UL) +#define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */ +#define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENSR_AHBSRAM2ENS_Pos (5UL) +#define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */ +#define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENSR_BKPSRAMENS_Pos (6UL) +#define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENSR_AXISRAM1ENS_Pos (7UL) +#define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */ +#define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENSR_AXISRAM2ENS_Pos (8UL) +#define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */ +#define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENSR_FLEXRAMENS_Pos (9UL) +#define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENSR_CACHEAXIRAMENS_Pos (10UL) +#define RCC_MEMENSR_CACHEAXIRAMENS_Msk (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos) /*!< 0x00000400 */ +#define RCC_MEMENSR_CACHEAXIRAMENS RCC_MEMENSR_CACHEAXIRAMENS_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENSR_VENCRAMENS_Pos (11UL) +#define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMENSR_BOOTROMENS_Pos (12UL) +#define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENSR register *****************/ +#define RCC_AHB1ENSR_GPDMA1ENS_Pos (4UL) +#define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENSR_ADC12ENS_Pos (5UL) +#define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENSR register *****************/ +#define RCC_AHB2ENSR_RAMCFGENS_Pos (12UL) +#define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENSR_MDF1ENS_Pos (16UL) +#define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENSR_ADF1ENS_Pos (17UL) +#define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENSR register *****************/ +#define RCC_AHB3ENSR_RNGENS_Pos (0UL) +#define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */ +#define RCC_AHB3ENSR_HASHENS_Pos (1UL) +#define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */ +#define RCC_AHB3ENSR_CRYPENS_Pos (2UL) +#define RCC_AHB3ENSR_CRYPENS_Msk (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENSR_CRYPENS RCC_AHB3ENSR_CRYPENS_Msk /*!< CRYP enable */ +#define RCC_AHB3ENSR_SAESENS_Pos (4UL) +#define RCC_AHB3ENSR_SAESENS_Msk (0x1UL << RCC_AHB3ENSR_SAESENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENSR_SAESENS RCC_AHB3ENSR_SAESENS_Msk /*!< SAES enable */ +#define RCC_AHB3ENSR_PKAENS_Pos (8UL) +#define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */ +#define RCC_AHB3ENSR_RIFSCENS_Pos (9UL) +#define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENSR_IACENS_Pos (10UL) +#define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */ +#define RCC_AHB3ENSR_RISAFENS_Pos (14UL) +#define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENSR register *****************/ +#define RCC_AHB4ENSR_GPIOAENS_Pos (0UL) +#define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENSR_GPIOBENS_Pos (1UL) +#define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENSR_GPIOCENS_Pos (2UL) +#define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENSR_GPIODENS_Pos (3UL) +#define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENSR_GPIOEENS_Pos (4UL) +#define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENSR_GPIOFENS_Pos (5UL) +#define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENSR_GPIOGENS_Pos (6UL) +#define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENSR_GPIOHENS_Pos (7UL) +#define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENSR_GPIONENS_Pos (13UL) +#define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENSR_GPIOOENS_Pos (14UL) +#define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENSR_GPIOPENS_Pos (15UL) +#define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENSR_GPIOQENS_Pos (16UL) +#define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENSR_PWRENS_Pos (18UL) +#define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */ +#define RCC_AHB4ENSR_CRCENS_Pos (19UL) +#define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENSR register *****************/ +#define RCC_AHB5ENSR_HPDMA1ENS_Pos (0UL) +#define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENSR_DMA2DENS_Pos (1UL) +#define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENSR_JPEGENS_Pos (3UL) +#define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */ +#define RCC_AHB5ENSR_FMCENS_Pos (4UL) +#define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */ +#define RCC_AHB5ENSR_XSPI1ENS_Pos (5UL) +#define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENSR_PSSIENS_Pos (6UL) +#define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */ +#define RCC_AHB5ENSR_SDMMC2ENS_Pos (7UL) +#define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENSR_SDMMC1ENS_Pos (8UL) +#define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENSR_XSPI2ENS_Pos (12UL) +#define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENSR_XSPIMENS_Pos (13UL) +#define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENSR_MCE1ENS_Pos (14UL) +#define RCC_AHB5ENSR_MCE1ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENSR_MCE1ENS RCC_AHB5ENSR_MCE1ENS_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENSR_MCE2ENS_Pos (15UL) +#define RCC_AHB5ENSR_MCE2ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENSR_MCE2ENS RCC_AHB5ENSR_MCE2ENS_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENSR_MCE3ENS_Pos (16UL) +#define RCC_AHB5ENSR_MCE3ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENSR_MCE3ENS RCC_AHB5ENSR_MCE3ENS_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENSR_XSPI3ENS_Pos (17UL) +#define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENSR_MCE4ENS_Pos (18UL) +#define RCC_AHB5ENSR_MCE4ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENSR_MCE4ENS RCC_AHB5ENSR_MCE4ENS_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENSR_GFXMMUENS_Pos (19UL) +#define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENSR_GPU2DENS_Pos (20UL) +#define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENSR_ETH1MACENS_Pos (22UL) +#define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENSR_ETH1TXENS_Pos (23UL) +#define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENSR_ETH1RXENS_Pos (24UL) +#define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENSR_ETH1ENS_Pos (25UL) +#define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENSR_OTG1ENS_Pos (26UL) +#define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27UL) +#define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28UL) +#define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENSR_OTG2ENS_Pos (29UL) +#define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENSR_CACHEAXIENS_Pos (30UL) +#define RCC_AHB5ENSR_CACHEAXIENS_Msk (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENSR_CACHEAXIENS RCC_AHB5ENSR_CACHEAXIENS_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENSR_NPUENS_Pos (31UL) +#define RCC_AHB5ENSR_NPUENS_Msk (0x1UL << RCC_AHB5ENSR_NPUENS_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENSR_NPUENS RCC_AHB5ENSR_NPUENS_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1ENSR1 register *****************/ +#define RCC_APB1ENSR1_TIM2ENS_Pos (0UL) +#define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */ +#define RCC_APB1ENSR1_TIM3ENS_Pos (1UL) +#define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */ +#define RCC_APB1ENSR1_TIM4ENS_Pos (2UL) +#define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */ +#define RCC_APB1ENSR1_TIM5ENS_Pos (3UL) +#define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */ +#define RCC_APB1ENSR1_TIM6ENS_Pos (4UL) +#define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */ +#define RCC_APB1ENSR1_TIM7ENS_Pos (5UL) +#define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */ +#define RCC_APB1ENSR1_TIM12ENS_Pos (6UL) +#define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */ +#define RCC_APB1ENSR1_TIM13ENS_Pos (7UL) +#define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */ +#define RCC_APB1ENSR1_TIM14ENS_Pos (8UL) +#define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */ +#define RCC_APB1ENSR1_LPTIM1ENS_Pos (9UL) +#define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENSR1_WWDGENS_Pos (11UL) +#define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */ +#define RCC_APB1ENSR1_TIM10ENS_Pos (12UL) +#define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */ +#define RCC_APB1ENSR1_TIM11ENS_Pos (13UL) +#define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */ +#define RCC_APB1ENSR1_SPI2ENS_Pos (14UL) +#define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */ +#define RCC_APB1ENSR1_SPI3ENS_Pos (15UL) +#define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */ +#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16UL) +#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENSR1_USART2ENS_Pos (17UL) +#define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */ +#define RCC_APB1ENSR1_USART3ENS_Pos (18UL) +#define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */ +#define RCC_APB1ENSR1_UART4ENS_Pos (19UL) +#define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */ +#define RCC_APB1ENSR1_UART5ENS_Pos (20UL) +#define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */ +#define RCC_APB1ENSR1_I2C1ENS_Pos (21UL) +#define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */ +#define RCC_APB1ENSR1_I2C2ENS_Pos (22UL) +#define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */ +#define RCC_APB1ENSR1_I2C3ENS_Pos (23UL) +#define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */ +#define RCC_APB1ENSR1_I3C1ENS_Pos (24UL) +#define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */ +#define RCC_APB1ENSR1_I3C2ENS_Pos (25UL) +#define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */ +#define RCC_APB1ENSR1_UART7ENS_Pos (30UL) +#define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */ +#define RCC_APB1ENSR1_UART8ENS_Pos (31UL) +#define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENSR2 register *****************/ +#define RCC_APB1ENSR2_MDIOSENS_Pos (5UL) +#define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */ +#define RCC_APB1ENSR2_FDCANENS_Pos (8UL) +#define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */ +#define RCC_APB1ENSR2_UCPD1ENS_Pos (18UL) +#define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENSR register *****************/ +#define RCC_APB2ENSR_TIM1ENS_Pos (0UL) +#define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */ +#define RCC_APB2ENSR_TIM8ENS_Pos (1UL) +#define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */ +#define RCC_APB2ENSR_USART1ENS_Pos (4UL) +#define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */ +#define RCC_APB2ENSR_USART6ENS_Pos (5UL) +#define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */ +#define RCC_APB2ENSR_UART9ENS_Pos (6UL) +#define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */ +#define RCC_APB2ENSR_USART10ENS_Pos (7UL) +#define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */ +#define RCC_APB2ENSR_SPI1ENS_Pos (12UL) +#define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */ +#define RCC_APB2ENSR_SPI4ENS_Pos (13UL) +#define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */ +#define RCC_APB2ENSR_TIM18ENS_Pos (15UL) +#define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */ +#define RCC_APB2ENSR_TIM15ENS_Pos (16UL) +#define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */ +#define RCC_APB2ENSR_TIM16ENS_Pos (17UL) +#define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */ +#define RCC_APB2ENSR_TIM17ENS_Pos (18UL) +#define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */ +#define RCC_APB2ENSR_TIM9ENS_Pos (19UL) +#define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */ +#define RCC_APB2ENSR_SPI5ENS_Pos (20UL) +#define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */ +#define RCC_APB2ENSR_SAI1ENS_Pos (21UL) +#define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */ +#define RCC_APB2ENSR_SAI2ENS_Pos (22UL) +#define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENSR register *****************/ +#define RCC_APB3ENSR_DFTENS_Pos (2UL) +#define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENSR1 register *****************/ +#define RCC_APB4ENSR1_HDPENS_Pos (2UL) +#define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */ +#define RCC_APB4ENSR1_LPUART1ENS_Pos (3UL) +#define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENSR1_SPI6ENS_Pos (5UL) +#define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */ +#define RCC_APB4ENSR1_I2C4ENS_Pos (7UL) +#define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */ +#define RCC_APB4ENSR1_LPTIM2ENS_Pos (9UL) +#define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENSR1_LPTIM3ENS_Pos (10UL) +#define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENSR1_LPTIM4ENS_Pos (11UL) +#define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENSR1_LPTIM5ENS_Pos (12UL) +#define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENSR1_VREFBUFENS_Pos (15UL) +#define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENSR1_RTCENS_Pos (16UL) +#define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */ +#define RCC_APB4ENSR1_RTCAPBENS_Pos (17UL) +#define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENSR2 register *****************/ +#define RCC_APB4ENSR2_SYSCFGENS_Pos (0UL) +#define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENSR2_BSECENS_Pos (1UL) +#define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */ +#define RCC_APB4ENSR2_DTSENS_Pos (2UL) +#define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENSR register *****************/ +#define RCC_APB5ENSR_LTDCENS_Pos (1UL) +#define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */ +#define RCC_APB5ENSR_DCMIPPENS_Pos (2UL) +#define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENSR_GFXTIMENS_Pos (4UL) +#define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENSR_VENCENS_Pos (5UL) +#define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */ +#define RCC_APB5ENSR_CSIENS_Pos (6UL) +#define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENSR register *****************/ +#define RCC_BUSLPENSR_ACLKNLPENS_Pos (0UL) +#define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1UL) +#define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENSR register ****************/ +#define RCC_MISCLPENSR_DBGLPENS_Pos (0UL) +#define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3UL) +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENSR_PERLPENS_Pos (6UL) +#define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */ + +/**************** Bit definition for RCC_MEMLPENSR register *****************/ +#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0UL) +#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1UL) +#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2UL) +#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3UL) +#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4UL) +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5UL) +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6UL) +#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7UL) +#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8UL) +#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9UL) +#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos (10UL) +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11UL) +#define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12UL) +#define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENSR register ****************/ +#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4UL) +#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENSR_ADC12LPENS_Pos (5UL) +#define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENSR register ****************/ +#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12UL) +#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENSR_MDF1LPENS_Pos (16UL) +#define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENSR_ADF1LPENS_Pos (17UL) +#define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENSR register ****************/ +#define RCC_AHB3LPENSR_RNGLPENS_Pos (0UL) +#define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */ +#define RCC_AHB3LPENSR_HASHLPENS_Pos (1UL) +#define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */ +#define RCC_AHB3LPENSR_CRYPLPENS_Pos (2UL) +#define RCC_AHB3LPENSR_CRYPLPENS_Msk (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENSR_CRYPLPENS RCC_AHB3LPENSR_CRYPLPENS_Msk /*!< CRYP enable */ +#define RCC_AHB3LPENSR_SAESLPENS_Pos (4UL) +#define RCC_AHB3LPENSR_SAESLPENS_Msk (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENSR_SAESLPENS RCC_AHB3LPENSR_SAESLPENS_Msk /*!< SAES enable */ +#define RCC_AHB3LPENSR_PKALPENS_Pos (8UL) +#define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */ +#define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9UL) +#define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENSR_IACLPENS_Pos (10UL) +#define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENSR_RISAFLPENS_Pos (14UL) +#define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENSR register ****************/ +#define RCC_AHB4LPENSR_GPIOALPENS_Pos (0UL) +#define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1UL) +#define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2UL) +#define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENSR_GPIODLPENS_Pos (3UL) +#define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENSR_GPIOELPENS_Pos (4UL) +#define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5UL) +#define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6UL) +#define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7UL) +#define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENSR_GPIONLPENS_Pos (13UL) +#define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14UL) +#define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15UL) +#define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16UL) +#define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENSR_PWRLPENS_Pos (18UL) +#define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */ +#define RCC_AHB4LPENSR_CRCLPENS_Pos (19UL) +#define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENSR register ****************/ +#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0UL) +#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1UL) +#define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENSR_JPEGLPENS_Pos (3UL) +#define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENSR_FMCLPENS_Pos (4UL) +#define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */ +#define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5UL) +#define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENSR_PSSILPENS_Pos (6UL) +#define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7UL) +#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8UL) +#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12UL) +#define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13UL) +#define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENSR_MCE1LPENS_Pos (14UL) +#define RCC_AHB5LPENSR_MCE1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENSR_MCE1LPENS RCC_AHB5LPENSR_MCE1LPENS_Msk /*!< MCE1 enable */ +#define RCC_AHB5LPENSR_MCE2LPENS_Pos (15UL) +#define RCC_AHB5LPENSR_MCE2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENSR_MCE2LPENS RCC_AHB5LPENSR_MCE2LPENS_Msk /*!< MCE2 enable */ +#define RCC_AHB5LPENSR_MCE3LPENS_Pos (16UL) +#define RCC_AHB5LPENSR_MCE3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENSR_MCE3LPENS RCC_AHB5LPENSR_MCE3LPENS_Msk /*!< MCE3 enable */ +#define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17UL) +#define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENSR_MCE4LPENS_Pos (18UL) +#define RCC_AHB5LPENSR_MCE4LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENSR_MCE4LPENS RCC_AHB5LPENSR_MCE4LPENS_Msk /*!< MCE4 enable */ +#define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19UL) +#define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20UL) +#define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22UL) +#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23UL) +#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24UL) +#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENSR_ETH1LPENS_Pos (25UL) +#define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENSR_OTG1LPENS_Pos (26UL) +#define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27UL) +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28UL) +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENSR_OTG2LPENS_Pos (29UL) +#define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */ +#define RCC_AHB5LPENSR_CACHEAXILPENS_Pos (30UL) +#define RCC_AHB5LPENSR_CACHEAXILPENS_Msk (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENSR_CACHEAXILPENS RCC_AHB5LPENSR_CACHEAXILPENS_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5LPENSR_NPULPENS_Pos (31UL) +#define RCC_AHB5LPENSR_NPULPENS_Msk (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */ +#define RCC_AHB5LPENSR_NPULPENS RCC_AHB5LPENSR_NPULPENS_Msk /*!< NPU enable */ + +/*************** Bit definition for RCC_APB1LPENSR1 register ****************/ +#define RCC_APB1LPENSR1_TIM2LPENS_Pos (0UL) +#define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENSR1_TIM3LPENS_Pos (1UL) +#define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENSR1_TIM4LPENS_Pos (2UL) +#define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENSR1_TIM5LPENS_Pos (3UL) +#define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENSR1_TIM6LPENS_Pos (4UL) +#define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENSR1_TIM7LPENS_Pos (5UL) +#define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENSR1_TIM12LPENS_Pos (6UL) +#define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENSR1_TIM13LPENS_Pos (7UL) +#define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENSR1_TIM14LPENS_Pos (8UL) +#define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9UL) +#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENSR1_WWDGLPENS_Pos (11UL) +#define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */ +#define RCC_APB1LPENSR1_TIM10LPENS_Pos (12UL) +#define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENSR1_TIM11LPENS_Pos (13UL) +#define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENSR1_SPI2LPENS_Pos (14UL) +#define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENSR1_SPI3LPENS_Pos (15UL) +#define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16UL) +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENSR1_USART2LPENS_Pos (17UL) +#define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */ +#define RCC_APB1LPENSR1_USART3LPENS_Pos (18UL) +#define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */ +#define RCC_APB1LPENSR1_UART4LPENS_Pos (19UL) +#define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */ +#define RCC_APB1LPENSR1_UART5LPENS_Pos (20UL) +#define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */ +#define RCC_APB1LPENSR1_I2C1LPENS_Pos (21UL) +#define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENSR1_I2C2LPENS_Pos (22UL) +#define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENSR1_I2C3LPENS_Pos (23UL) +#define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENSR1_I3C1LPENS_Pos (24UL) +#define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENSR1_I3C2LPENS_Pos (25UL) +#define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENSR1_UART7LPENS_Pos (30UL) +#define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */ +#define RCC_APB1LPENSR1_UART8LPENS_Pos (31UL) +#define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENSR2 register ****************/ +#define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5UL) +#define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENSR2_FDCANLPENS_Pos (8UL) +#define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18UL) +#define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENSR register ****************/ +#define RCC_APB2LPENSR_TIM1LPENS_Pos (0UL) +#define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENSR_TIM8LPENS_Pos (1UL) +#define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENSR_USART1LPENS_Pos (4UL) +#define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */ +#define RCC_APB2LPENSR_USART6LPENS_Pos (5UL) +#define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */ +#define RCC_APB2LPENSR_UART9LPENS_Pos (6UL) +#define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */ +#define RCC_APB2LPENSR_USART10LPENS_Pos (7UL) +#define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */ +#define RCC_APB2LPENSR_SPI1LPENS_Pos (12UL) +#define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENSR_SPI4LPENS_Pos (13UL) +#define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENSR_TIM18LPENS_Pos (15UL) +#define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENSR_TIM15LPENS_Pos (16UL) +#define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENSR_TIM16LPENS_Pos (17UL) +#define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENSR_TIM17LPENS_Pos (18UL) +#define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENSR_TIM9LPENS_Pos (19UL) +#define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENSR_SPI5LPENS_Pos (20UL) +#define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENSR_SAI1LPENS_Pos (21UL) +#define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENSR_SAI2LPENS_Pos (22UL) +#define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENSR register ****************/ +#define RCC_APB3LPENSR_DFTLPENS_Pos (2UL) +#define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENSR1 register ****************/ +#define RCC_APB4LPENSR1_HDPLPENS_Pos (2UL) +#define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */ +#define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3UL) +#define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENSR1_SPI6LPENS_Pos (5UL) +#define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENSR1_I2C4LPENS_Pos (7UL) +#define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9UL) +#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10UL) +#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11UL) +#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12UL) +#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15UL) +#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENSR1_RTCLPENS_Pos (16UL) +#define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */ +#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17UL) +#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENSR2 register ****************/ +#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0UL) +#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENSR2_BSECLPENS_Pos (1UL) +#define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */ +#define RCC_APB4LPENSR2_DTSLPENS_Pos (2UL) +#define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENSR register ****************/ +#define RCC_APB5LPENSR_LTDCLPENS_Pos (1UL) +#define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */ +#define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2UL) +#define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4UL) +#define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENSR_VENCLPENS_Pos (5UL) +#define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */ +#define RCC_APB5LPENSR_CSILPENS_Pos (6UL) +#define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_PRIVCFGSR0 register ****************/ +#define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR0 register *****************/ +#define RCC_PUBCFGSR0_LSIPUBS_Pos (0UL) +#define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_LSEPUBS_Pos (1UL) +#define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_MSIPUBS_Pos (2UL) +#define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSIPUBS_Pos (3UL) +#define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSEPUBS_Pos (4UL) +#define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR1 register ****************/ +#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR1 register *****************/ +#define RCC_PUBCFGSR1_PLL1PUBS_Pos (0UL) +#define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL2PUBS_Pos (1UL) +#define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL3PUBS_Pos (2UL) +#define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL4PUBS_Pos (3UL) +#define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR2 register ****************/ +#define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13UL) +#define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14UL) +#define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15UL) +#define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16UL) +#define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17UL) +#define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18UL) +#define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19UL) +#define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR2 register *****************/ +#define RCC_PUBCFGSR2_IC1PUBS_Pos (0UL) +#define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC2PUBS_Pos (1UL) +#define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC3PUBS_Pos (2UL) +#define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC4PUBS_Pos (3UL) +#define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC5PUBS_Pos (4UL) +#define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC6PUBS_Pos (5UL) +#define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC7PUBS_Pos (6UL) +#define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC8PUBS_Pos (7UL) +#define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC9PUBS_Pos (8UL) +#define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC10PUBS_Pos (9UL) +#define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC11PUBS_Pos (10UL) +#define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC12PUBS_Pos (11UL) +#define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC13PUBS_Pos (12UL) +#define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC14PUBS_Pos (13UL) +#define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC15PUBS_Pos (14UL) +#define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC16PUBS_Pos (15UL) +#define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */ +#define RCC_PUBCFGSR2_IC17PUBS_Pos (16UL) +#define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC18PUBS_Pos (17UL) +#define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC19PUBS_Pos (18UL) +#define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC20PUBS_Pos (19UL) +#define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR3 register ****************/ +#define RCC_PRIVCFGSR3_MODPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_PERPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_INTPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5UL) +#define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR3 register *****************/ +#define RCC_PUBCFGSR3_MODPUBS_Pos (0UL) +#define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_SYSPUBS_Pos (1UL) +#define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_BUSPUBS_Pos (2UL) +#define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_PERPUBS_Pos (3UL) +#define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_INTPUBS_Pos (4UL) +#define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_RSTPUBS_Pos (5UL) +#define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR4 register ****************/ +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13UL) +#define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR4 register *****************/ +#define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0UL) +#define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1UL) +#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHBMPUBS_Pos (2UL) +#define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB1PUBS_Pos (3UL) +#define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB2PUBS_Pos (4UL) +#define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB3PUBS_Pos (5UL) +#define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB4PUBS_Pos (6UL) +#define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB5PUBS_Pos (7UL) +#define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB1PUBS_Pos (8UL) +#define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB2PUBS_Pos (9UL) +#define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB3PUBS_Pos (10UL) +#define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB4PUBS_Pos (11UL) +#define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB5PUBS_Pos (12UL) +#define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_NOCPUBS_Pos (13UL) +#define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR5 register *****************/ +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0UL) +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1UL) +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2UL) +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3UL) +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4UL) +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5UL) +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6UL) +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7UL) +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8UL) +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9UL) +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos (10UL) +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11UL) +#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + +/******************* Bit definition for RCC_CCR register ********************/ +#define RCC_CCR_LSIONC_Pos (0UL) +#define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */ +#define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */ +#define RCC_CCR_LSEONC_Pos (1UL) +#define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */ +#define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */ +#define RCC_CCR_MSIONC_Pos (2UL) +#define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */ +#define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */ +#define RCC_CCR_HSIONC_Pos (3UL) +#define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */ +#define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */ +#define RCC_CCR_HSEONC_Pos (4UL) +#define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */ +#define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */ +#define RCC_CCR_PLL1ONC_Pos (8UL) +#define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */ +#define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */ +#define RCC_CCR_PLL2ONC_Pos (9UL) +#define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */ +#define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */ +#define RCC_CCR_PLL3ONC_Pos (10UL) +#define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */ +#define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */ +#define RCC_CCR_PLL4ONC_Pos (11UL) +#define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */ +#define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCCR register ******************/ +#define RCC_STOPCCR_MSISTOPENC_Pos (0UL) +#define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */ +#define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCCR_HSISTOPENC_Pos (1UL) +#define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */ +#define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTCR register *****************/ +#define RCC_MISCRSTCR_DBGRSTC_Pos (0UL) +#define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4UL) +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5UL) +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7UL) +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8UL) +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTCR register *****************/ +#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0UL) +#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1UL) +#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2UL) +#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3UL) +#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4UL) +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5UL) +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7UL) +#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8UL) +#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9UL) +#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos (10UL) +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11UL) +#define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12UL) +#define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTCR register *****************/ +#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4UL) +#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTCR_ADC12RSTC_Pos (5UL) +#define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTCR register *****************/ +#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12UL) +#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTCR_MDF1RSTC_Pos (16UL) +#define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTCR_ADF1RSTC_Pos (17UL) +#define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTCR register *****************/ +#define RCC_AHB3RSTCR_RNGRSTC_Pos (0UL) +#define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */ +#define RCC_AHB3RSTCR_HASHRSTC_Pos (1UL) +#define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */ +#define RCC_AHB3RSTCR_CRYPRSTC_Pos (2UL) +#define RCC_AHB3RSTCR_CRYPRSTC_Msk (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTCR_CRYPRSTC RCC_AHB3RSTCR_CRYPRSTC_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTCR_SAESRSTC_Pos (4UL) +#define RCC_AHB3RSTCR_SAESRSTC_Msk (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCR_SAESRSTC RCC_AHB3RSTCR_SAESRSTC_Msk /*!< SAES reset */ +#define RCC_AHB3RSTCR_PKARSTC_Pos (8UL) +#define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */ +#define RCC_AHB3RSTCR_IACRSTC_Pos (10UL) +#define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTCR register *****************/ +#define RCC_AHB4RSTCR_GPIOARSTC_Pos (0UL) +#define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1UL) +#define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2UL) +#define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTCR_GPIODRSTC_Pos (3UL) +#define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTCR_GPIOERSTC_Pos (4UL) +#define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5UL) +#define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6UL) +#define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7UL) +#define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTCR_GPIONRSTC_Pos (13UL) +#define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTCR_GPIOORSTC_Pos (14UL) +#define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15UL) +#define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16UL) +#define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTCR_PWRRSTC_Pos (18UL) +#define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */ +#define RCC_AHB4RSTCR_CRCRSTC_Pos (19UL) +#define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTCR register *****************/ +#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0UL) +#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1UL) +#define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTCR_JPEGRSTC_Pos (3UL) +#define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTCR_FMCRSTC_Pos (4UL) +#define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */ +#define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5UL) +#define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTCR_PSSIRSTC_Pos (6UL) +#define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7UL) +#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8UL) +#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12UL) +#define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13UL) +#define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17UL) +#define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19UL) +#define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20UL) +#define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23UL) +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24UL) +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTCR_ETH1RSTC_Pos (25UL) +#define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTCR_OTG1RSTC_Pos (26UL) +#define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27UL) +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28UL) +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTCR_OTG2RSTC_Pos (29UL) +#define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos (30UL) +#define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTCR_CACHEAXIRSTC RCC_AHB5RSTCR_CACHEAXIRSTC_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTCR_NPURSTC_Pos (31UL) +#define RCC_AHB5RSTCR_NPURSTC_Msk (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTCR_NPURSTC RCC_AHB5RSTCR_NPURSTC_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTCR1 register ****************/ +#define RCC_APB1RSTCR1_TIM2RSTC_Pos (0UL) +#define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTCR1_TIM3RSTC_Pos (1UL) +#define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTCR1_TIM4RSTC_Pos (2UL) +#define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTCR1_TIM5RSTC_Pos (3UL) +#define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTCR1_TIM6RSTC_Pos (4UL) +#define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTCR1_TIM7RSTC_Pos (5UL) +#define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTCR1_TIM12RSTC_Pos (6UL) +#define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTCR1_TIM13RSTC_Pos (7UL) +#define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTCR1_TIM14RSTC_Pos (8UL) +#define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9UL) +#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTCR1_WWDGRSTC_Pos (11UL) +#define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */ +#define RCC_APB1RSTCR1_TIM10RSTC_Pos (12UL) +#define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTCR1_TIM11RSTC_Pos (13UL) +#define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTCR1_SPI2RSTC_Pos (14UL) +#define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTCR1_SPI3RSTC_Pos (15UL) +#define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16UL) +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTCR1_USART2RSTC_Pos (17UL) +#define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */ +#define RCC_APB1RSTCR1_USART3RSTC_Pos (18UL) +#define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */ +#define RCC_APB1RSTCR1_UART4RSTC_Pos (19UL) +#define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */ +#define RCC_APB1RSTCR1_UART5RSTC_Pos (20UL) +#define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */ +#define RCC_APB1RSTCR1_I2C1RSTC_Pos (21UL) +#define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTCR1_I2C2RSTC_Pos (22UL) +#define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTCR1_I2C3RSTC_Pos (23UL) +#define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTCR1_I3C1RSTC_Pos (24UL) +#define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTCR1_I3C2RSTC_Pos (25UL) +#define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTCR1_UART7RSTC_Pos (30UL) +#define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */ +#define RCC_APB1RSTCR1_UART8RSTC_Pos (31UL) +#define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTCR2 register ****************/ +#define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5UL) +#define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTCR2_FDCANRSTC_Pos (8UL) +#define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18UL) +#define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTCR register *****************/ +#define RCC_APB2RSTCR_TIM1RSTC_Pos (0UL) +#define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTCR_TIM8RSTC_Pos (1UL) +#define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTCR_USART1RSTC_Pos (4UL) +#define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */ +#define RCC_APB2RSTCR_USART6RSTC_Pos (5UL) +#define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */ +#define RCC_APB2RSTCR_UART9RSTC_Pos (6UL) +#define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */ +#define RCC_APB2RSTCR_USART10RSTC_Pos (7UL) +#define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */ +#define RCC_APB2RSTCR_SPI1RSTC_Pos (12UL) +#define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTCR_SPI4RSTC_Pos (13UL) +#define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTCR_TIM18RSTC_Pos (15UL) +#define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTCR_TIM15RSTC_Pos (16UL) +#define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTCR_TIM16RSTC_Pos (17UL) +#define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTCR_TIM17RSTC_Pos (18UL) +#define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTCR_TIM9RSTC_Pos (19UL) +#define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTCR_SPI5RSTC_Pos (20UL) +#define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTCR_SAI1RSTC_Pos (21UL) +#define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTCR_SAI2RSTC_Pos (22UL) +#define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTCR1 register ****************/ +#define RCC_APB4RSTCR1_HDPRSTC_Pos (2UL) +#define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */ +#define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3UL) +#define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTCR1_SPI6RSTC_Pos (5UL) +#define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTCR1_I2C4RSTC_Pos (7UL) +#define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9UL) +#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10UL) +#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11UL) +#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12UL) +#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15UL) +#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTCR1_RTCRSTC_Pos (16UL) +#define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTCR2 register ****************/ +#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0UL) +#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTCR2_DTSRSTC_Pos (2UL) +#define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTCR register *****************/ +#define RCC_APB5RSTCR_LTDCRSTC_Pos (1UL) +#define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */ +#define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2UL) +#define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4UL) +#define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTCR_VENCRSTC_Pos (5UL) +#define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */ +#define RCC_APB5RSTCR_CSIRSTC_Pos (6UL) +#define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENCR register ******************/ +#define RCC_DIVENCR_IC1ENC_Pos (0UL) +#define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */ +#define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */ +#define RCC_DIVENCR_IC2ENC_Pos (1UL) +#define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */ +#define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */ +#define RCC_DIVENCR_IC3ENC_Pos (2UL) +#define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */ +#define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */ +#define RCC_DIVENCR_IC4ENC_Pos (3UL) +#define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */ +#define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */ +#define RCC_DIVENCR_IC5ENC_Pos (4UL) +#define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */ +#define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */ +#define RCC_DIVENCR_IC6ENC_Pos (5UL) +#define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */ +#define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */ +#define RCC_DIVENCR_IC7ENC_Pos (6UL) +#define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */ +#define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */ +#define RCC_DIVENCR_IC8ENC_Pos (7UL) +#define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */ +#define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */ +#define RCC_DIVENCR_IC9ENC_Pos (8UL) +#define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */ +#define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */ +#define RCC_DIVENCR_IC10ENC_Pos (9UL) +#define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */ +#define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */ +#define RCC_DIVENCR_IC11ENC_Pos (10UL) +#define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */ +#define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */ +#define RCC_DIVENCR_IC12ENC_Pos (11UL) +#define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */ +#define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */ +#define RCC_DIVENCR_IC13ENC_Pos (12UL) +#define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */ +#define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */ +#define RCC_DIVENCR_IC14ENC_Pos (13UL) +#define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */ +#define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */ +#define RCC_DIVENCR_IC15ENC_Pos (14UL) +#define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */ +#define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */ +#define RCC_DIVENCR_IC16ENC_Pos (15UL) +#define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */ +#define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */ +#define RCC_DIVENCR_IC17ENC_Pos (16UL) +#define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */ +#define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */ +#define RCC_DIVENCR_IC18ENC_Pos (17UL) +#define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */ +#define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */ +#define RCC_DIVENCR_IC19ENC_Pos (18UL) +#define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */ +#define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */ +#define RCC_DIVENCR_IC20ENC_Pos (19UL) +#define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */ +#define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENCR register ******************/ +#define RCC_BUSENCR_ACLKNENC_Pos (0UL) +#define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */ +#define RCC_BUSENCR_ACLKNCENC_Pos (1UL) +#define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */ +#define RCC_BUSENCR_AHBMENC_Pos (2UL) +#define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */ +#define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */ +#define RCC_BUSENCR_AHB1ENC_Pos (3UL) +#define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */ +#define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */ +#define RCC_BUSENCR_AHB2ENC_Pos (4UL) +#define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */ +#define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */ +#define RCC_BUSENCR_AHB3ENC_Pos (5UL) +#define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */ +#define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */ +#define RCC_BUSENCR_AHB4ENC_Pos (6UL) +#define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */ +#define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */ +#define RCC_BUSENCR_AHB5ENC_Pos (7UL) +#define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */ +#define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */ +#define RCC_BUSENCR_APB1ENC_Pos (8UL) +#define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */ +#define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */ +#define RCC_BUSENCR_APB2ENC_Pos (9UL) +#define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */ +#define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */ +#define RCC_BUSENCR_APB3ENC_Pos (10UL) +#define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */ +#define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */ +#define RCC_BUSENCR_APB4ENC_Pos (11UL) +#define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */ +#define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */ +#define RCC_BUSENCR_APB5ENC_Pos (12UL) +#define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */ +#define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENCR register *****************/ +#define RCC_MISCENCR_DBGENC_Pos (0UL) +#define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */ +#define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */ +#define RCC_MISCENCR_MCO1ENC_Pos (1UL) +#define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */ +#define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */ +#define RCC_MISCENCR_MCO2ENC_Pos (2UL) +#define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */ +#define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */ +#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3UL) +#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENCR_PERENC_Pos (6UL) +#define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */ +#define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENCR register ******************/ +#define RCC_MEMENCR_AXISRAM3ENC_Pos (0UL) +#define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */ +#define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENCR_AXISRAM4ENC_Pos (1UL) +#define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */ +#define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENCR_AXISRAM5ENC_Pos (2UL) +#define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */ +#define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENCR_AXISRAM6ENC_Pos (3UL) +#define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */ +#define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENCR_AHBSRAM1ENC_Pos (4UL) +#define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */ +#define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENCR_AHBSRAM2ENC_Pos (5UL) +#define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */ +#define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENCR_BKPSRAMENC_Pos (6UL) +#define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENCR_AXISRAM1ENC_Pos (7UL) +#define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */ +#define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENCR_AXISRAM2ENC_Pos (8UL) +#define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */ +#define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENCR_FLEXRAMENC_Pos (9UL) +#define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENCR_CACHEAXIRAMENC_Pos (10UL) +#define RCC_MEMENCR_CACHEAXIRAMENC_Msk (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos) /*!< 0x00000400 */ +#define RCC_MEMENCR_CACHEAXIRAMENC RCC_MEMENCR_CACHEAXIRAMENC_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENCR_VENCRAMENC_Pos (11UL) +#define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */ +#define RCC_MEMENCR_BOOTROMENC_Pos (12UL) +#define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENCR register *****************/ +#define RCC_AHB1ENCR_GPDMA1ENC_Pos (4UL) +#define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENCR_ADC12ENC_Pos (5UL) +#define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENCR register *****************/ +#define RCC_AHB2ENCR_RAMCFGENC_Pos (12UL) +#define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENCR_MDF1ENC_Pos (16UL) +#define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENCR_ADF1ENC_Pos (17UL) +#define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENCR register *****************/ +#define RCC_AHB3ENCR_RNGENC_Pos (0UL) +#define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */ +#define RCC_AHB3ENCR_HASHENC_Pos (1UL) +#define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */ +#define RCC_AHB3ENCR_CRYPENC_Pos (2UL) +#define RCC_AHB3ENCR_CRYPENC_Msk (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENCR_CRYPENC RCC_AHB3ENCR_CRYPENC_Msk /*!< CRYP enable */ +#define RCC_AHB3ENCR_SAESENC_Pos (4UL) +#define RCC_AHB3ENCR_SAESENC_Msk (0x1UL << RCC_AHB3ENCR_SAESENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENCR_SAESENC RCC_AHB3ENCR_SAESENC_Msk /*!< SAES enable */ +#define RCC_AHB3ENCR_PKAENC_Pos (8UL) +#define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */ +#define RCC_AHB3ENCR_RIFSCENC_Pos (9UL) +#define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENCR_IACENC_Pos (10UL) +#define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */ +#define RCC_AHB3ENCR_RISAFENC_Pos (14UL) +#define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENCR register *****************/ +#define RCC_AHB4ENCR_GPIOAENC_Pos (0UL) +#define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENCR_GPIOBENC_Pos (1UL) +#define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENCR_GPIOCENC_Pos (2UL) +#define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENCR_GPIODENC_Pos (3UL) +#define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENCR_GPIOEENC_Pos (4UL) +#define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENCR_GPIOFENC_Pos (5UL) +#define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENCR_GPIOGENC_Pos (6UL) +#define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENCR_GPIOHENC_Pos (7UL) +#define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENCR_GPIONENC_Pos (13UL) +#define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENCR_GPIOOENC_Pos (14UL) +#define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENCR_GPIOPENC_Pos (15UL) +#define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENCR_GPIOQENC_Pos (16UL) +#define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENCR_PWRENC_Pos (18UL) +#define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */ +#define RCC_AHB4ENCR_CRCENC_Pos (19UL) +#define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENCR register *****************/ +#define RCC_AHB5ENCR_HPDMA1ENC_Pos (0UL) +#define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENCR_DMA2DENC_Pos (1UL) +#define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENCR_JPEGENC_Pos (3UL) +#define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */ +#define RCC_AHB5ENCR_FMCENC_Pos (4UL) +#define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */ +#define RCC_AHB5ENCR_XSPI1ENC_Pos (5UL) +#define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENCR_PSSIENC_Pos (6UL) +#define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */ +#define RCC_AHB5ENCR_SDMMC2ENC_Pos (7UL) +#define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENCR_SDMMC1ENC_Pos (8UL) +#define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENCR_XSPI2ENC_Pos (12UL) +#define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENCR_XSPIMENC_Pos (13UL) +#define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENCR_MCE1ENC_Pos (14UL) +#define RCC_AHB5ENCR_MCE1ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENCR_MCE1ENC RCC_AHB5ENCR_MCE1ENC_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENCR_MCE2ENC_Pos (15UL) +#define RCC_AHB5ENCR_MCE2ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENCR_MCE2ENC RCC_AHB5ENCR_MCE2ENC_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENCR_MCE3ENC_Pos (16UL) +#define RCC_AHB5ENCR_MCE3ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENCR_MCE3ENC RCC_AHB5ENCR_MCE3ENC_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENCR_XSPI3ENC_Pos (17UL) +#define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENCR_MCE4ENC_Pos (18UL) +#define RCC_AHB5ENCR_MCE4ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENCR_MCE4ENC RCC_AHB5ENCR_MCE4ENC_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENCR_GFXMMUENC_Pos (19UL) +#define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENCR_GPU2DENC_Pos (20UL) +#define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENCR_ETH1MACENC_Pos (22UL) +#define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENCR_ETH1TXENC_Pos (23UL) +#define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENCR_ETH1RXENC_Pos (24UL) +#define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENCR_ETH1ENC_Pos (25UL) +#define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENCR_OTG1ENC_Pos (26UL) +#define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27UL) +#define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28UL) +#define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENCR_OTG2ENC_Pos (29UL) +#define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENCR_CACHEAXIENC_Pos (30UL) +#define RCC_AHB5ENCR_CACHEAXIENC_Msk (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENCR_CACHEAXIENC RCC_AHB5ENCR_CACHEAXIENC_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENCR_NPUENC_Pos (31UL) +#define RCC_AHB5ENCR_NPUENC_Msk (0x1UL << RCC_AHB5ENCR_NPUENC_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENCR_NPUENC RCC_AHB5ENCR_NPUENC_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1ENCR1 register *****************/ +#define RCC_APB1ENCR1_TIM2ENC_Pos (0UL) +#define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */ +#define RCC_APB1ENCR1_TIM3ENC_Pos (1UL) +#define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */ +#define RCC_APB1ENCR1_TIM4ENC_Pos (2UL) +#define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */ +#define RCC_APB1ENCR1_TIM5ENC_Pos (3UL) +#define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */ +#define RCC_APB1ENCR1_TIM6ENC_Pos (4UL) +#define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */ +#define RCC_APB1ENCR1_TIM7ENC_Pos (5UL) +#define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */ +#define RCC_APB1ENCR1_TIM12ENC_Pos (6UL) +#define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */ +#define RCC_APB1ENCR1_TIM13ENC_Pos (7UL) +#define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */ +#define RCC_APB1ENCR1_TIM14ENC_Pos (8UL) +#define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */ +#define RCC_APB1ENCR1_LPTIM1ENC_Pos (9UL) +#define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENCR1_TIM10ENC_Pos (12UL) +#define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */ +#define RCC_APB1ENCR1_TIM11ENC_Pos (13UL) +#define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */ +#define RCC_APB1ENCR1_SPI2ENC_Pos (14UL) +#define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */ +#define RCC_APB1ENCR1_SPI3ENC_Pos (15UL) +#define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */ +#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16UL) +#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENCR1_USART2ENC_Pos (17UL) +#define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */ +#define RCC_APB1ENCR1_USART3ENC_Pos (18UL) +#define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */ +#define RCC_APB1ENCR1_UART4ENC_Pos (19UL) +#define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */ +#define RCC_APB1ENCR1_UART5ENC_Pos (20UL) +#define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */ +#define RCC_APB1ENCR1_I2C1ENC_Pos (21UL) +#define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */ +#define RCC_APB1ENCR1_I2C2ENC_Pos (22UL) +#define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */ +#define RCC_APB1ENCR1_I2C3ENC_Pos (23UL) +#define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */ +#define RCC_APB1ENCR1_I3C1ENC_Pos (24UL) +#define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */ +#define RCC_APB1ENCR1_I3C2ENC_Pos (25UL) +#define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */ +#define RCC_APB1ENCR1_UART7ENC_Pos (30UL) +#define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */ +#define RCC_APB1ENCR1_UART8ENC_Pos (31UL) +#define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENCR2 register *****************/ +#define RCC_APB1ENCR2_MDIOSENC_Pos (5UL) +#define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */ +#define RCC_APB1ENCR2_FDCANENC_Pos (8UL) +#define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */ +#define RCC_APB1ENCR2_UCPD1ENC_Pos (18UL) +#define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENCR register *****************/ +#define RCC_APB2ENCR_TIM1ENC_Pos (0UL) +#define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */ +#define RCC_APB2ENCR_TIM8ENC_Pos (1UL) +#define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */ +#define RCC_APB2ENCR_USART1ENC_Pos (4UL) +#define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */ +#define RCC_APB2ENCR_USART6ENC_Pos (5UL) +#define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */ +#define RCC_APB2ENCR_UART9ENC_Pos (6UL) +#define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */ +#define RCC_APB2ENCR_USART10ENC_Pos (7UL) +#define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */ +#define RCC_APB2ENCR_SPI1ENC_Pos (12UL) +#define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */ +#define RCC_APB2ENCR_SPI4ENC_Pos (13UL) +#define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */ +#define RCC_APB2ENCR_TIM18ENC_Pos (15UL) +#define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */ +#define RCC_APB2ENCR_TIM15ENC_Pos (16UL) +#define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */ +#define RCC_APB2ENCR_TIM16ENC_Pos (17UL) +#define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */ +#define RCC_APB2ENCR_TIM17ENC_Pos (18UL) +#define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */ +#define RCC_APB2ENCR_TIM9ENC_Pos (19UL) +#define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */ +#define RCC_APB2ENCR_SPI5ENC_Pos (20UL) +#define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */ +#define RCC_APB2ENCR_SAI1ENC_Pos (21UL) +#define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */ +#define RCC_APB2ENCR_SAI2ENC_Pos (22UL) +#define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENCR register *****************/ +#define RCC_APB3ENCR_DFTENC_Pos (2UL) +#define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENCR1 register *****************/ +#define RCC_APB4ENCR1_HDPENC_Pos (2UL) +#define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */ +#define RCC_APB4ENCR1_LPUART1ENC_Pos (3UL) +#define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENCR1_SPI6ENC_Pos (5UL) +#define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */ +#define RCC_APB4ENCR1_I2C4ENC_Pos (7UL) +#define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */ +#define RCC_APB4ENCR1_LPTIM2ENC_Pos (9UL) +#define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENCR1_LPTIM3ENC_Pos (10UL) +#define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENCR1_LPTIM4ENC_Pos (11UL) +#define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENCR1_LPTIM5ENC_Pos (12UL) +#define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENCR1_VREFBUFENC_Pos (15UL) +#define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENCR1_RTCENC_Pos (16UL) +#define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */ +#define RCC_APB4ENCR1_RTCAPBENC_Pos (17UL) +#define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENCR2 register *****************/ +#define RCC_APB4ENCR2_SYSCFGENC_Pos (0UL) +#define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENCR2_BSECENC_Pos (1UL) +#define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */ +#define RCC_APB4ENCR2_DTSENC_Pos (2UL) +#define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENCR register *****************/ +#define RCC_APB5ENCR_LTDCENC_Pos (1UL) +#define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */ +#define RCC_APB5ENCR_DCMIPPENC_Pos (2UL) +#define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENCR_GFXTIMENC_Pos (4UL) +#define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENCR_VENCENC_Pos (5UL) +#define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */ +#define RCC_APB5ENCR_CSIENC_Pos (6UL) +#define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENCR register *****************/ +#define RCC_BUSLPENCR_ACLKNLPENC_Pos (0UL) +#define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */ +#define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1UL) +#define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */ + +/**************** Bit definition for RCC_MISCLPENCR register ****************/ +#define RCC_MISCLPENCR_DBGLPENC_Pos (0UL) +#define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3UL) +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */ +#define RCC_MISCLPENCR_PERLPENC_Pos (6UL) +#define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */ + +/**************** Bit definition for RCC_MEMLPENCR register *****************/ +#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0UL) +#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1UL) +#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2UL) +#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3UL) +#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4UL) +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5UL) +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6UL) +#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7UL) +#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8UL) +#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9UL) +#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos (10UL) +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk /*!< CACHEAXIRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11UL) +#define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12UL) +#define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB1LPENCR register ****************/ +#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4UL) +#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */ +#define RCC_AHB1LPENCR_ADC12LPENC_Pos (5UL) +#define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB2LPENCR register ****************/ +#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12UL) +#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */ +#define RCC_AHB2LPENCR_MDF1LPENC_Pos (16UL) +#define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */ +#define RCC_AHB2LPENCR_ADF1LPENC_Pos (17UL) +#define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB3LPENCR register ****************/ +#define RCC_AHB3LPENCR_RNGLPENC_Pos (0UL) +#define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */ +#define RCC_AHB3LPENCR_HASHLPENC_Pos (1UL) +#define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */ +#define RCC_AHB3LPENCR_CRYPLPENC_Pos (2UL) +#define RCC_AHB3LPENCR_CRYPLPENC_Msk (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENCR_CRYPLPENC RCC_AHB3LPENCR_CRYPLPENC_Msk /*!< CRYP enable in Sleep mode */ +#define RCC_AHB3LPENCR_SAESLPENC_Pos (4UL) +#define RCC_AHB3LPENCR_SAESLPENC_Msk (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENCR_SAESLPENC RCC_AHB3LPENCR_SAESLPENC_Msk /*!< SAES enable in Sleep mode */ +#define RCC_AHB3LPENCR_PKALPENC_Pos (8UL) +#define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */ +#define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9UL) +#define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */ +#define RCC_AHB3LPENCR_IACLPENC_Pos (10UL) +#define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENCR_RISAFLPENC_Pos (14UL) +#define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB4LPENCR register ****************/ +#define RCC_AHB4LPENCR_GPIOALPENC_Pos (0UL) +#define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1UL) +#define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2UL) +#define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIODLPENC_Pos (3UL) +#define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOELPENC_Pos (4UL) +#define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5UL) +#define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6UL) +#define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7UL) +#define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIONLPENC_Pos (13UL) +#define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14UL) +#define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15UL) +#define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16UL) +#define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */ +#define RCC_AHB4LPENCR_PWRLPENC_Pos (18UL) +#define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */ +#define RCC_AHB4LPENCR_CRCLPENC_Pos (19UL) +#define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB5LPENCR register ****************/ +#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0UL) +#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1UL) +#define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_JPEGLPENC_Pos (3UL) +#define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */ +#define RCC_AHB5LPENCR_FMCLPENC_Pos (4UL) +#define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5UL) +#define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_PSSILPENC_Pos (6UL) +#define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7UL) +#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8UL) +#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12UL) +#define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13UL) +#define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE1LPENC_Pos (14UL) +#define RCC_AHB5LPENCR_MCE1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENCR_MCE1LPENC RCC_AHB5LPENCR_MCE1LPENC_Msk /*!< MCE1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE2LPENC_Pos (15UL) +#define RCC_AHB5LPENCR_MCE2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENCR_MCE2LPENC RCC_AHB5LPENCR_MCE2LPENC_Msk /*!< MCE2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE3LPENC_Pos (16UL) +#define RCC_AHB5LPENCR_MCE3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENCR_MCE3LPENC RCC_AHB5LPENCR_MCE3LPENC_Msk /*!< MCE3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17UL) +#define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE4LPENC_Pos (18UL) +#define RCC_AHB5LPENCR_MCE4LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENCR_MCE4LPENC RCC_AHB5LPENCR_MCE4LPENC_Msk /*!< MCE4 enable in Sleep mode */ +#define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19UL) +#define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */ +#define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20UL) +#define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22UL) +#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23UL) +#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24UL) +#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1LPENC_Pos (25UL) +#define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG1LPENC_Pos (26UL) +#define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27UL) +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28UL) +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG2LPENC_Pos (29UL) +#define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_CACHEAXILPENC_Pos (30UL) +#define RCC_AHB5LPENCR_CACHEAXILPENC_Msk (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENCR_CACHEAXILPENC RCC_AHB5LPENCR_CACHEAXILPENC_Msk /*!< CACHEAXI enable in Sleep mode */ +#define RCC_AHB5LPENCR_NPULPENC_Pos (31UL) +#define RCC_AHB5LPENCR_NPULPENC_Msk (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */ +#define RCC_AHB5LPENCR_NPULPENC RCC_AHB5LPENCR_NPULPENC_Msk /*!< NPU enable in Sleep mode */ + +/*************** Bit definition for RCC_APB1LPENCR1 register ****************/ +#define RCC_APB1LPENCR1_TIM2LPENC_Pos (0UL) +#define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENCR1_TIM3LPENC_Pos (1UL) +#define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENCR1_TIM4LPENC_Pos (2UL) +#define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENCR1_TIM5LPENC_Pos (3UL) +#define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENCR1_TIM6LPENC_Pos (4UL) +#define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENCR1_TIM7LPENC_Pos (5UL) +#define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENCR1_TIM12LPENC_Pos (6UL) +#define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENCR1_TIM13LPENC_Pos (7UL) +#define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENCR1_TIM14LPENC_Pos (8UL) +#define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9UL) +#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENCR1_WWDGLPENC_Pos (11UL) +#define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */ +#define RCC_APB1LPENCR1_TIM10LPENC_Pos (12UL) +#define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENCR1_TIM11LPENC_Pos (13UL) +#define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENCR1_SPI2LPENC_Pos (14UL) +#define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENCR1_SPI3LPENC_Pos (15UL) +#define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16UL) +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENCR1_USART2LPENC_Pos (17UL) +#define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */ +#define RCC_APB1LPENCR1_USART3LPENC_Pos (18UL) +#define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */ +#define RCC_APB1LPENCR1_UART4LPENC_Pos (19UL) +#define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */ +#define RCC_APB1LPENCR1_UART5LPENC_Pos (20UL) +#define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */ +#define RCC_APB1LPENCR1_I2C1LPENC_Pos (21UL) +#define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENCR1_I2C2LPENC_Pos (22UL) +#define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENCR1_I2C3LPENC_Pos (23UL) +#define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENCR1_I3C1LPENC_Pos (24UL) +#define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENCR1_I3C2LPENC_Pos (25UL) +#define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENCR1_UART7LPENC_Pos (30UL) +#define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */ +#define RCC_APB1LPENCR1_UART8LPENC_Pos (31UL) +#define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENCR2 register ****************/ +#define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5UL) +#define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENCR2_FDCANLPENC_Pos (8UL) +#define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18UL) +#define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENCR register ****************/ +#define RCC_APB2LPENCR_TIM1LPENC_Pos (0UL) +#define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENCR_TIM8LPENC_Pos (1UL) +#define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENCR_USART1LPENC_Pos (4UL) +#define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */ +#define RCC_APB2LPENCR_USART6LPENC_Pos (5UL) +#define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */ +#define RCC_APB2LPENCR_UART9LPENC_Pos (6UL) +#define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */ +#define RCC_APB2LPENCR_USART10LPENC_Pos (7UL) +#define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */ +#define RCC_APB2LPENCR_SPI1LPENC_Pos (12UL) +#define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENCR_SPI4LPENC_Pos (13UL) +#define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENCR_TIM18LPENC_Pos (15UL) +#define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENCR_TIM15LPENC_Pos (16UL) +#define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENCR_TIM16LPENC_Pos (17UL) +#define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENCR_TIM17LPENC_Pos (18UL) +#define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENCR_TIM9LPENC_Pos (19UL) +#define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENCR_SPI5LPENC_Pos (20UL) +#define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENCR_SAI1LPENC_Pos (21UL) +#define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENCR_SAI2LPENC_Pos (22UL) +#define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENCR register ****************/ +#define RCC_APB3LPENCR_DFTLPENC_Pos (2UL) +#define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENCR1 register ****************/ +#define RCC_APB4LPENCR1_HDPLPENC_Pos (2UL) +#define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */ +#define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3UL) +#define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENCR1_SPI6LPENC_Pos (5UL) +#define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENCR1_I2C4LPENC_Pos (7UL) +#define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9UL) +#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10UL) +#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11UL) +#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12UL) +#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15UL) +#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENCR1_RTCLPENC_Pos (16UL) +#define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */ +#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17UL) +#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENCR2 register ****************/ +#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0UL) +#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENCR2_BSECLPENC_Pos (1UL) +#define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */ +#define RCC_APB4LPENCR2_DTSLPENC_Pos (2UL) +#define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENCR register ****************/ +#define RCC_APB5LPENCR_LTDCLPENC_Pos (1UL) +#define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */ +#define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2UL) +#define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */ +#define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4UL) +#define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */ +#define RCC_APB5LPENCR_VENCLPENC_Pos (5UL) +#define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */ +#define RCC_APB5LPENCR_CSILPENC_Pos (6UL) +#define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */ + +/**************** Bit definition for RCC_PRIVCFGCR0 register ****************/ +#define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR0 register *****************/ +#define RCC_PUBCFGCR0_LSIPUBC_Pos (0UL) +#define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_LSEPUBC_Pos (1UL) +#define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_MSIPUBC_Pos (2UL) +#define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSIPUBC_Pos (3UL) +#define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSEPUBC_Pos (4UL) +#define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR1 register ****************/ +#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR1 register *****************/ +#define RCC_PUBCFGCR1_PLL1PUBC_Pos (0UL) +#define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL2PUBC_Pos (1UL) +#define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL3PUBC_Pos (2UL) +#define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL4PUBC_Pos (3UL) +#define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR2 register ****************/ +#define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13UL) +#define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14UL) +#define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15UL) +#define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16UL) +#define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17UL) +#define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18UL) +#define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19UL) +#define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR2 register *****************/ +#define RCC_PUBCFGCR2_IC1PUBC_Pos (0UL) +#define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC2PUBC_Pos (1UL) +#define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC3PUBC_Pos (2UL) +#define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC4PUBC_Pos (3UL) +#define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC5PUBC_Pos (4UL) +#define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC6PUBC_Pos (5UL) +#define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC7PUBC_Pos (6UL) +#define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC8PUBC_Pos (7UL) +#define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC9PUBC_Pos (8UL) +#define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC10PUBC_Pos (9UL) +#define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC11PUBC_Pos (10UL) +#define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC12PUBC_Pos (11UL) +#define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC13PUBC_Pos (12UL) +#define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC14PUBC_Pos (13UL) +#define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC15PUBC_Pos (14UL) +#define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC16PUBC_Pos (15UL) +#define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC17PUBC_Pos (16UL) +#define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC18PUBC_Pos (17UL) +#define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC19PUBC_Pos (18UL) +#define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC20PUBC_Pos (19UL) +#define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR3 register ****************/ +#define RCC_PRIVCFGCR3_MODPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_PERPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_INTPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5UL) +#define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR3 register *****************/ +#define RCC_PUBCFGCR3_MODPUBC_Pos (0UL) +#define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_SYSPUBC_Pos (1UL) +#define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_BUSPUBC_Pos (2UL) +#define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_PERPUBC_Pos (3UL) +#define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_INTPUBC_Pos (4UL) +#define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_RSTPUBC_Pos (5UL) +#define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR4 register ****************/ +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13UL) +#define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR4 register *****************/ +#define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0UL) +#define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1UL) +#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHBMPUBC_Pos (2UL) +#define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB1PUBC_Pos (3UL) +#define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB2PUBC_Pos (4UL) +#define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB3PUBC_Pos (5UL) +#define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB4PUBC_Pos (6UL) +#define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB5PUBC_Pos (7UL) +#define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB1PUBC_Pos (8UL) +#define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB2PUBC_Pos (9UL) +#define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB3PUBC_Pos (10UL) +#define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB4PUBC_Pos (11UL) +#define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB5PUBC_Pos (12UL) +#define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_NOCPUBC_Pos (13UL) +#define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR5 register *****************/ +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0UL) +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1UL) +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2UL) +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3UL) +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4UL) +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5UL) +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6UL) +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7UL) +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8UL) +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9UL) +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos (10UL) +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk /*!< Public protection of CACHEAXIRAM configuration bits */ +#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11UL) +#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + + +/******************************************************************************/ +/* */ +/* Resource Isolation Framework Security Controller (RIFSC) */ +/* */ +/******************************************************************************/ +/**************** Bit definition for RIFSC_RISC_CR register *****************/ +#define RIFSC_RISC_CR_GLOCK_Pos (0UL) +#define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */ + +/************* Bit definition for RIFSC_RISC_SECCFGRx register **************/ +#define RIFSC_RISC_SECCFGRx_SEC0_Pos (0UL) +#define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */ +#define RIFSC_RISC_SECCFGRx_SEC1_Pos (1UL) +#define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */ +#define RIFSC_RISC_SECCFGRx_SEC2_Pos (2UL) +#define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */ +#define RIFSC_RISC_SECCFGRx_SEC3_Pos (3UL) +#define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */ +#define RIFSC_RISC_SECCFGRx_SEC4_Pos (4UL) +#define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */ +#define RIFSC_RISC_SECCFGRx_SEC5_Pos (5UL) +#define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */ +#define RIFSC_RISC_SECCFGRx_SEC6_Pos (6UL) +#define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */ +#define RIFSC_RISC_SECCFGRx_SEC7_Pos (7UL) +#define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */ +#define RIFSC_RISC_SECCFGRx_SEC8_Pos (8UL) +#define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */ +#define RIFSC_RISC_SECCFGRx_SEC9_Pos (9UL) +#define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */ +#define RIFSC_RISC_SECCFGRx_SEC10_Pos (10UL) +#define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */ +#define RIFSC_RISC_SECCFGRx_SEC11_Pos (11UL) +#define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */ +#define RIFSC_RISC_SECCFGRx_SEC12_Pos (12UL) +#define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */ +#define RIFSC_RISC_SECCFGRx_SEC13_Pos (13UL) +#define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */ +#define RIFSC_RISC_SECCFGRx_SEC14_Pos (14UL) +#define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */ +#define RIFSC_RISC_SECCFGRx_SEC15_Pos (15UL) +#define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */ +#define RIFSC_RISC_SECCFGRx_SEC16_Pos (16UL) +#define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */ +#define RIFSC_RISC_SECCFGRx_SEC17_Pos (17UL) +#define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */ +#define RIFSC_RISC_SECCFGRx_SEC18_Pos (18UL) +#define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */ +#define RIFSC_RISC_SECCFGRx_SEC19_Pos (19UL) +#define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */ +#define RIFSC_RISC_SECCFGRx_SEC20_Pos (20UL) +#define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */ +#define RIFSC_RISC_SECCFGRx_SEC21_Pos (21UL) +#define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */ +#define RIFSC_RISC_SECCFGRx_SEC22_Pos (22UL) +#define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */ +#define RIFSC_RISC_SECCFGRx_SEC23_Pos (23UL) +#define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */ +#define RIFSC_RISC_SECCFGRx_SEC24_Pos (24UL) +#define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */ +#define RIFSC_RISC_SECCFGRx_SEC25_Pos (25UL) +#define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */ +#define RIFSC_RISC_SECCFGRx_SEC26_Pos (26UL) +#define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */ +#define RIFSC_RISC_SECCFGRx_SEC27_Pos (27UL) +#define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */ +#define RIFSC_RISC_SECCFGRx_SEC28_Pos (28UL) +#define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */ +#define RIFSC_RISC_SECCFGRx_SEC29_Pos (29UL) +#define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */ +#define RIFSC_RISC_SECCFGRx_SEC30_Pos (30UL) +#define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */ +#define RIFSC_RISC_SECCFGRx_SEC31_Pos (31UL) +#define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/ +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */ + +/**************** Bit definition for RIFSC_RIMC_CR register *****************/ +#define RIFSC_RIMC_CR_GLOCK_Pos (0UL) +#define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */ +#define RIFSC_RIMC_CR_DAPCID_Pos (8UL) +#define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */ +#define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */ +#define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */ + +/*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/ +#define RIFSC_RIMC_ATTRx_MCID_Pos (4UL) +#define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */ +#define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */ +#define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */ +#define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */ +#define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */ +#define RIFSC_RIMC_ATTRx_MSEC_Pos (8UL) +#define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */ +#define RIFSC_RIMC_ATTRx_MPRIV_Pos (9UL) +#define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */ + +/******************************************************************************/ +/* */ +/* Resource Isolation Slave unit for Address space protection (RISAF) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RISAF_CR register *******************/ +#define RISAF_CR_GLOCK_Pos (0UL) +#define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */ + +/****************** Bit definition for RISAF_IASR register ******************/ +#define RISAF_IASR_CAEF_Pos (0UL) +#define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IASR_IAEF_Pos (1UL) +#define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */ + +/****************** Bit definition for RISAF_IACR register ******************/ +#define RISAF_IACR_CAEF_Pos (0UL) +#define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IACR_IAEF_Pos (1UL) +#define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */ + +/***************** Bit definition for RISAF_IAESR register *****************/ +#define RISAF_IAESR_IACID_Pos (0UL) +#define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */ +#define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */ +#define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */ +#define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */ +#define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */ +#define RISAF_IAESR_IAPRIV_Pos (4UL) +#define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */ +#define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */ +#define RISAF_IAESR_IASEC_Pos (5UL) +#define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */ +#define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */ +#define RISAF_IAESR_IANRW_Pos (7UL) +#define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */ +#define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */ + +/***************** Bit definition for RISAF_IADDR register *****************/ +#define RISAF_IADDR_IADD_Pos (0UL) +#define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */ +#define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */ +#define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */ +#define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */ +#define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */ +#define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */ +#define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */ +#define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */ +#define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */ +#define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */ +#define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */ +#define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */ +#define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */ +#define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */ +#define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */ +#define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */ +#define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */ +#define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */ +#define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */ +#define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */ +#define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */ +#define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */ +#define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */ +#define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */ +#define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */ +#define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */ +#define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */ +#define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */ +#define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */ +#define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */ +#define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */ +#define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */ +#define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_CFGR register ****************/ +#define RISAF_REGx_CFGR_BREN_Pos (0UL) +#define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */ +#define RISAF_REGx_CFGR_SEC_Pos (8UL) +#define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */ +#define RISAF_REGx_CFGR_PRIVC0_Pos (16UL) +#define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */ +#define RISAF_REGx_CFGR_PRIVC1_Pos (17UL) +#define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */ +#define RISAF_REGx_CFGR_PRIVC2_Pos (18UL) +#define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */ +#define RISAF_REGx_CFGR_PRIVC3_Pos (19UL) +#define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */ +#define RISAF_REGx_CFGR_PRIVC4_Pos (20UL) +#define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */ +#define RISAF_REGx_CFGR_PRIVC5_Pos (21UL) +#define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */ +#define RISAF_REGx_CFGR_PRIVC6_Pos (22UL) +#define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */ +#define RISAF_REGx_CFGR_PRIVC7_Pos (23UL) +#define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */ + +/************** Bit definition for RISAF_REGx_STARTR register ***************/ +#define RISAF_REGx_STARTR_BADDSTART_Pos (0UL) +#define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */ +#define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_ENDR register ****************/ +#define RISAF_REGx_ENDR_BADDEND_Pos (0UL) +#define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */ +#define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_CIDCFGR register **************/ +#define RISAF_REGx_CIDCFGR_RDENC0_Pos (0UL) +#define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_RDENC1_Pos (1UL) +#define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_RDENC2_Pos (2UL) +#define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_RDENC3_Pos (3UL) +#define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_RDENC4_Pos (4UL) +#define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_RDENC5_Pos (5UL) +#define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_RDENC6_Pos (6UL) +#define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_RDENC7_Pos (7UL) +#define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */ +#define RISAF_REGx_CIDCFGR_WRENC0_Pos (16UL) +#define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_WRENC1_Pos (17UL) +#define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_WRENC2_Pos (18UL) +#define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_WRENC3_Pos (19UL) +#define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_WRENC4_Pos (20UL) +#define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_WRENC5_Pos (21UL) +#define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_WRENC6_Pos (22UL) +#define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_WRENC7_Pos (23UL) +#define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */ + +/*************** Bit definition for RISAF_REGx_zCFGR register ***************/ +#define RISAF_REGx_zCFGR_SREN_Pos (0UL) +#define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */ +#define RISAF_REGx_zCFGR_RLOCK_Pos (1UL) +#define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */ +#define RISAF_REGx_zCFGR_SRCID_Pos (4UL) +#define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */ +#define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zCFGR_SEC_Pos (8UL) +#define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */ +#define RISAF_REGx_zCFGR_PRIV_Pos (9UL) +#define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */ +#define RISAF_REGx_zCFGR_RDEN_Pos (12UL) +#define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */ +#define RISAF_REGx_zCFGR_WREN_Pos (13UL) +#define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */ + +/************** Bit definition for RISAF_REGx_zSTARTR register **************/ +#define RISAF_REGx_zSTARTR_SADDSTART_Pos (0UL) +#define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */ +#define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_zENDR register ***************/ +#define RISAF_REGx_zENDR_SADDEND_Pos (0UL) +#define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */ +#define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_zNESTR register ***************/ +#define RISAF_REGx_zNESTR_DCEN_Pos (2UL) +#define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */ +#define RISAF_REGx_zNESTR_DCCID_Pos (4UL) +#define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */ +#define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */ + +/******************************************************************************/ +/* */ +/* (IAC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IAC_IER0 register *******************/ +#define IAC_IERx_IAIE0_Pos (0UL) +#define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */ +#define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_IERx_IAIE1_Pos (1UL) +#define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */ +#define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_IERx_IAIE2_Pos (2UL) +#define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */ +#define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_IERx_IAIE3_Pos (3UL) +#define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */ +#define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_IERx_IAIE4_Pos (4UL) +#define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */ +#define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_IERx_IAIE5_Pos (5UL) +#define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */ +#define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_IERx_IAIE6_Pos (6UL) +#define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */ +#define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_IERx_IAIE7_Pos (7UL) +#define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */ +#define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_IERx_IAIE8_Pos (8UL) +#define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */ +#define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_IERx_IAIE9_Pos (9UL) +#define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */ +#define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_IERx_IAIE10_Pos (10UL) +#define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */ +#define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_IERx_IAIE11_Pos (11UL) +#define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */ +#define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_IERx_IAIE12_Pos (12UL) +#define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */ +#define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_IERx_IAIE13_Pos (13UL) +#define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */ +#define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_IERx_IAIE14_Pos (14UL) +#define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */ +#define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_IERx_IAIE15_Pos (15UL) +#define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */ +#define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_IERx_IAIE16_Pos (16UL) +#define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */ +#define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_IERx_IAIE17_Pos (17UL) +#define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */ +#define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_IERx_IAIE18_Pos (18UL) +#define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */ +#define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_IERx_IAIE19_Pos (19UL) +#define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */ +#define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_IERx_IAIE20_Pos (20UL) +#define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */ +#define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_IERx_IAIE21_Pos (21UL) +#define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */ +#define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_IERx_IAIE22_Pos (22UL) +#define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */ +#define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_IERx_IAIE23_Pos (23UL) +#define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */ +#define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_IERx_IAIE24_Pos (24UL) +#define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */ +#define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_IERx_IAIE25_Pos (25UL) +#define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */ +#define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_IERx_IAIE26_Pos (26UL) +#define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */ +#define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_IERx_IAIE27_Pos (27UL) +#define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */ +#define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_IERx_IAIE28_Pos (28UL) +#define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */ +#define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_IERx_IAIE29_Pos (29UL) +#define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */ +#define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_IERx_IAIE30_Pos (30UL) +#define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */ +#define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_IERx_IAIE31_Pos (31UL) +#define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */ +#define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ISRx register *******************/ +#define IAC_ISRx_IAF0_Pos (0UL) +#define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_ISRx_IAF1_Pos (1UL) +#define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_ISRx_IAF2_Pos (2UL) +#define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_ISRx_IAF3_Pos (3UL) +#define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_ISRx_IAF4_Pos (4UL) +#define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_ISRx_IAF5_Pos (5UL) +#define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_ISRx_IAF6_Pos (6UL) +#define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_ISRx_IAF7_Pos (7UL) +#define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_ISRx_IAF8_Pos (8UL) +#define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_ISRx_IAF9_Pos (9UL) +#define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_ISRx_IAF10_Pos (10UL) +#define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_ISRx_IAF11_Pos (11UL) +#define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_ISRx_IAF12_Pos (12UL) +#define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_ISRx_IAF13_Pos (13UL) +#define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_ISRx_IAF14_Pos (14UL) +#define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_ISRx_IAF15_Pos (15UL) +#define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_ISRx_IAF16_Pos (16UL) +#define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_ISRx_IAF17_Pos (17UL) +#define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_ISRx_IAF18_Pos (18UL) +#define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_ISRx_IAF19_Pos (19UL) +#define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_ISRx_IAF20_Pos (20UL) +#define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_ISRx_IAF21_Pos (21UL) +#define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_ISRx_IAF22_Pos (22UL) +#define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_ISRx_IAF23_Pos (23UL) +#define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_ISRx_IAF24_Pos (24UL) +#define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_ISRx_IAF25_Pos (25UL) +#define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_ISRx_IAF26_Pos (26UL) +#define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_ISRx_IAF27_Pos (27UL) +#define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_ISRx_IAF28_Pos (28UL) +#define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_ISRx_IAF29_Pos (29UL) +#define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_ISRx_IAF30_Pos (30UL) +#define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_ISRx_IAF31_Pos (31UL) +#define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ICRx register *******************/ +#define IAC_ICRx_IAF0_Pos (0UL) +#define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */ +#define IAC_ICRx_IAF1_Pos (1UL) +#define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */ +#define IAC_ICRx_IAF2_Pos (2UL) +#define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */ +#define IAC_ICRx_IAF3_Pos (3UL) +#define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */ +#define IAC_ICRx_IAF4_Pos (4UL) +#define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */ +#define IAC_ICRx_IAF5_Pos (5UL) +#define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */ +#define IAC_ICRx_IAF6_Pos (6UL) +#define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */ +#define IAC_ICRx_IAF7_Pos (7UL) +#define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */ +#define IAC_ICRx_IAF8_Pos (8UL) +#define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */ +#define IAC_ICRx_IAF9_Pos (9UL) +#define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */ +#define IAC_ICRx_IAF10_Pos (10UL) +#define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */ +#define IAC_ICRx_IAF11_Pos (11UL) +#define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */ +#define IAC_ICRx_IAF12_Pos (12UL) +#define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */ +#define IAC_ICRx_IAF13_Pos (13UL) +#define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */ +#define IAC_ICRx_IAF14_Pos (14UL) +#define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */ +#define IAC_ICRx_IAF15_Pos (15UL) +#define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */ +#define IAC_ICRx_IAF16_Pos (16UL) +#define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */ +#define IAC_ICRx_IAF17_Pos (17UL) +#define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */ +#define IAC_ICRx_IAF18_Pos (18UL) +#define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */ +#define IAC_ICRx_IAF19_Pos (19UL) +#define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */ +#define IAC_ICRx_IAF20_Pos (20UL) +#define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */ +#define IAC_ICRx_IAF21_Pos (21UL) +#define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */ +#define IAC_ICRx_IAF22_Pos (22UL) +#define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */ +#define IAC_ICRx_IAF23_Pos (23UL) +#define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */ +#define IAC_ICRx_IAF24_Pos (24UL) +#define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */ +#define IAC_ICRx_IAF25_Pos (25UL) +#define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */ +#define IAC_ICRx_IAF26_Pos (26UL) +#define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */ +#define IAC_ICRx_IAF27_Pos (27UL) +#define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */ +#define IAC_ICRx_IAF28_Pos (28UL) +#define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */ +#define IAC_ICRx_IAF29_Pos (29UL) +#define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */ +#define IAC_ICRx_IAF30_Pos (30UL) +#define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */ +#define IAC_ICRx_IAF31_Pos (31UL) +#define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */ + +/****************** Bit definition for IAC_IISRx register *******************/ +#define IAC_IISRx_ILACIN0_Pos (0UL) +#define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */ +#define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN1_Pos (1UL) +#define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */ +#define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN2_Pos (2UL) +#define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */ +#define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN3_Pos (3UL) +#define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */ +#define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN4_Pos (4UL) +#define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */ +#define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN5_Pos (5UL) +#define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */ +#define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN6_Pos (6UL) +#define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */ +#define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN7_Pos (7UL) +#define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */ +#define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN8_Pos (8UL) +#define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */ +#define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN9_Pos (9UL) +#define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */ +#define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN10_Pos (10UL) +#define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */ +#define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN11_Pos (11UL) +#define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */ +#define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN12_Pos (12UL) +#define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */ +#define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN13_Pos (13UL) +#define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */ +#define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN14_Pos (14UL) +#define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */ +#define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN15_Pos (15UL) +#define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */ +#define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN16_Pos (16UL) +#define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */ +#define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN17_Pos (17UL) +#define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */ +#define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN18_Pos (18UL) +#define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */ +#define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN19_Pos (19UL) +#define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */ +#define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN20_Pos (20UL) +#define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */ +#define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN21_Pos (21UL) +#define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */ +#define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN22_Pos (22UL) +#define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */ +#define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN23_Pos (23UL) +#define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */ +#define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN24_Pos (24UL) +#define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */ +#define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN25_Pos (25UL) +#define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */ +#define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN26_Pos (26UL) +#define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */ +#define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN27_Pos (27UL) +#define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */ +#define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN28_Pos (28UL) +#define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */ +#define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN29_Pos (29UL) +#define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */ +#define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN30_Pos (30UL) +#define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */ +#define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN31_Pos (31UL) +#define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */ +#define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0UL) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4UL) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8UL) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12UL) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16UL) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20UL) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22UL) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0UL) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4UL) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8UL) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12UL) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13UL) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16UL) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20UL) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0UL) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2UL) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3UL) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4UL) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5UL) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6UL) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7UL) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8UL) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10UL) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16UL) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0UL) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16UL) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0UL) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16UL) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0UL) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3UL) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4UL) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5UL) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6UL) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7UL) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8UL) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9UL) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10UL) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11UL) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12UL) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13UL) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14UL) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15UL) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16UL) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17UL) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18UL) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19UL) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20UL) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21UL) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23UL) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24UL) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0UL) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1UL) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3UL) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5UL) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x1UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020*/ +#define SAES_CR_CHMOD_1 (0x2UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11UL) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12UL) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13UL) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x0006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM or CCM phase selection */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00020000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE_Pos (18UL) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_KEYPROT_Pos (19UL) +#define SAES_CR_KEYPROT_Msk (0x1UL << SAES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define SAES_CR_KEYPROT SAES_CR_KEYPROT_Msk /*!< Key protection */ +#define SAES_CR_NPBLB_Pos (20UL) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24UL) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26UL) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KSHAREID_0 (0x1UL << SAES_CR_KSHAREID_Pos) /*!< 0x04000000 */ +#define SAES_CR_KSHAREID_1 (0x2UL << SAES_CR_KSHAREID_Pos) /*!< 0x08000000 */ +#define SAES_CR_KEYSEL_Pos (28UL) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define SAES_CR_IPRST_Pos (31UL) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0UL) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1UL) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2UL) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3UL) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7UL) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< Key valid Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0UL) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0UL) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0UL) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES cryptographic key, bits [31:0] */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0UL) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES cryptographic key, bits [63:32] */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0UL) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES cryptographic key, bits [95:64] */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0UL) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0UL) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0UL) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0UL) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0UL) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0UL) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES initialization vector input, bits [31:0] */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0UL) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES initialization vector input, bits [63:32] */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0UL) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES initialization vector input, bits [95:64] */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0UL) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES initialization vector input, bits [127:96] */ + +/******************* Bits definition for SAES_DPACFGR register ******************/ +#define SAES_DPACFGR_REDCFG_Pos (0UL) +#define SAES_DPACFGR_REDCFG_Msk (0x3UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000003 */ +#define SAES_DPACFGR_REDCFG SAES_DPACFGR_REDCFG_Msk /*!< Redundancy configuration*/ +#define SAES_DPACFGR_REDCFG_0 (0x1UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000001 */ +#define SAES_DPACFGR_REDCFG_1 (0x2UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000002 */ +#define SAES_DPACFGR_RESEED_Pos (2UL) +#define SAES_DPACFGR_RESEED_Msk (0x1UL << SAES_DPACFGR_RESEED_Pos) /*!< 0x00000004 */ +#define SAES_DPACFGR_RESEED SAES_DPACFGR_RESEED_Msk /*!< Automatic reseed enable */ +#define SAES_DPACFGR_TRIMCFG_Pos (3UL) +#define SAES_DPACFGR_TRIMCFG_Msk (0x3UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000018 */ +#define SAES_DPACFGR_TRIMCFG SAES_DPACFGR_TRIMCFG_Msk /*!< Clock trimming */ +#define SAES_DPACFGR_TRIMCFG_0 (0x1UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000008 */ +#define SAES_DPACFGR_TRIMCFG_1 (0x2UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000010 */ +#define SAES_DPACFGR_CONFIGLOCK_Pos (31UL) +#define SAES_DPACFGR_CONFIGLOCK_Msk (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define SAES_DPACFGR_CONFIGLOCK SAES_DPACFGR_CONFIGLOCK_Msk /*!< DPA configuration lock */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0UL) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1UL) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2UL) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3UL) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< RNG error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0UL) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1UL) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2UL) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3UL) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< RNG error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0UL) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1UL) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2UL) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3UL) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< RNG error interrupt flag clear */ + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0UL) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Exported_Functions + * @{ + */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + \brief Update SystemCoreClock variable from secure application and return its value + when security is implemented in the system (Non-secure callable function). + + Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SYSTEM_STM32N6XX_H */ + +/** + * @} + */ + +/** + * @} + */ + Index: trunk/firmware/FSBL/SES/STM32N6xx/Device/Source/system_stm32n6xx_s.c =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Device/Source/system_stm32n6xx_s.c (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Device/Source/system_stm32n6xx_s.c (revision 16) @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file system_stm32n6xx_s.c + * @author MCD Application Team + * @brief CMSIS Cortex-M55 Device Peripheral Access Layer System Source File + * to be used in secure application. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32n6xx.s" file. + * + * - SystemCoreClock variable: Contains the CPU core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update + * the variable SystemCoreClock and return + * its value to the non-secure calling + * application. It must be called whenever + * the core clock is changed during program + * execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32n6xx.s" file, to + * configure the system before to branch to main program. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32N6xx_System + * @{ + */ + +/** @addtogroup STM32N6xx_System_Private_Includes + * @{ + */ + +#include "stm32n6xx.h" +#include "partition_stm32n6xx.h" /* Trustzone-M core secure attributes */ +#include + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_TypesDefinitions + * @{ + */ + +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the High-Speed External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000UL /*!< Minimum value of the Low-power Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +#if !defined (EXTERNAL_I2S_CLOCK_VALUE) + #define EXTERNAL_I2S_CLOCK_VALUE 12288000UL /*!< Value of the External clock for I2S_CKIN in Hz */ +#endif /* EXTERNAL_I2S_CLOCK_VALUE */ + + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in memory, else the vector table is kept at the automatic + selected boot address */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS SRAM1_AXI_BASE_S /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Functions + * @{ + */ + +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)&__vector_table) +#elif defined(__ARMCC_VERSION) +extern void *__Vectors; +#define INTVECT_START ((uint32_t)&__Vectors) +#elif defined(__GNUC__) +extern void *g_pfnVectors; +#define INTVECT_START ((uint32_t)&g_pfnVectors) +#endif + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#else + SCB->VTOR = INTVECT_START; +#endif /* USER_VECT_TAB_ADDRESS */ + + /* System configuration setup */ + RCC->APB4ENSR2 = RCC_APB4ENSR2_SYSCFGENS; + /* Delay after an RCC peripheral clock enabling */ + (void)RCC->APB4ENR2; + + /* Set default Vector Table location after system reset or return from Standby */ + SYSCFG->INITSVTORCR = SCB->VTOR; + /* Read back the value to make sure it is written before deactivating SYSCFG */ + (void) SYSCFG->INITSVTORCR; + /* Deactivate SYSCFG clock */ + RCC->APB4ENCR2 = RCC_APB4ENCR2_SYSCFGENC; + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + + SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif /* __FPU_PRESENT && __FPU_USED */ + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Depending on secure or non-secure compilation, the adequate RCC peripheral + * memory are is accessed thanks to RCC alias defined in stm32n6xxxx.h device file + * so either from RCC_S peripheral register mapped memory in secure or from + * RCC_NS peripheral register mapped memory in non-secure. + * + * @note Each time the CPU core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If CPUCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If CPUCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(**) + * + * - If CPUCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If CPUCLK source is IC1, SystemCoreClock will contain the HSI_VALUE(*) + * or MSI_VALUE(**) or HSE_VALUE(***) or EXTERNAL_I2S_CLOCK_VALUE (****) + * multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE default value is 64 MHz. + * With the HAL, HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file + * but the real value may vary depending on the variations in voltage and temperature. + * + * (**) MSI_VALUE default value is 4 MHz. + * With the HAL, MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file + * but the real value may vary depending on the variations in voltage and temperature. + * + * (***) HSE_VALUE default value is 30 MHz. + * With the HAL, HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file. + * User has to ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * (****) EXTERNAL_I2S_CLOCK_VALUE default value is 12.288 MHz. + * With the HAL, EXTERNAL_I2S_CLOCK_VALUE is a constant defined in stm32n6xx_hal_conf.h file. + * User has to ensure that EXTERNAL_I2S_CLOCK_VALUE is same as the real I2S_CKIN + * pin frequency. Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysclk = 0; + uint32_t pllm = 0; + uint32_t plln = 0; + uint32_t pllfracn = 0; + uint32_t pllp1 = 0; + uint32_t pllp2 = 0; + uint32_t pllcfgr, pllsource, pllbypass, ic_divider; + float_t pllvco; + + /* Get CPUCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_CPUSWS) + { + case 0: /* HSI used as system clock source (default after reset) */ + sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos); + break; + + case RCC_CFGR1_CPUSWS_0: /* MSI used as system clock source */ + if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) + { + sysclk = MSI_VALUE; + } + else + { + sysclk = 16000000UL; + } + break; + + case RCC_CFGR1_CPUSWS_1: /* HSE used as system clock source */ + sysclk = HSE_VALUE; + break; + + case (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0): /* IC1 used as system clock source */ + /* Get IC1 clock source parameters */ + switch (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL)) + { + case 0: /* PLL1 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL1CFGR1); + pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL; + pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; + plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL1CFGR3); + pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; + } + break; + case RCC_IC1CFGR_IC1SEL_0: /* PLL2 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL2CFGR1); + pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL; + pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos; + plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL2CFGR3); + pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos; + } + break; + + case RCC_IC1CFGR_IC1SEL_1: /* PLL3 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL3CFGR1); + pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL; + pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos; + plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL3CFGR3); + pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos; + } + break; + + default: /* RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0 */ /* PLL4 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL4CFGR1); + pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL; + pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; + plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL4CFGR3); + pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos; + } + break; + } + + /* Get oscillator frequency used as PLL clock source */ + switch (pllsource) + { + case 0: /* HSI selected as PLL clock source */ + sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos); + break; + case RCC_PLL1CFGR1_PLL1SEL_0: /* MSI selected as PLL clock source */ + if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) + { + sysclk = MSI_VALUE; + } + else + { + sysclk = 16000000UL; + } + break; + case RCC_PLL1CFGR1_PLL1SEL_1: /* HSE selected as PLL clock source */ + sysclk = HSE_VALUE; + break; + case (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0): /* I2S_CKIN selected as PLL clock source */ + sysclk = EXTERNAL_I2S_CLOCK_VALUE; + break; + default: + /* Nothing to do, should not occur */ + break; + } + + /* Check whether PLL is in bypass mode or not */ + if (pllbypass == 0U) + { + /* Compte PLL output frequency (Integer and fractional modes) */ + /* PLLVCO = (Freq * (DIVN + (FRACN / 0x1000000) / DIVM) / (DIVP1 * DIVP2)) */ + pllvco = ((float_t)sysclk * ((float_t)plln + ((float_t)pllfracn/(float_t)0x1000000UL))) / (float_t)pllm; + sysclk = (uint32_t)((float_t)(pllvco/(((float_t)pllp1) * ((float_t)pllp2)))); + } + /* Apply IC1 divider */ + ic_divider = (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL; + sysclk = sysclk / ic_divider; + break; + default: + /* Nothing to do, should not occur */ + break; + } + + /* Return system clock frequency (CPU frequency) */ + SystemCoreClock = sysclk; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the CPU core clock, it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + SystemCoreClockUpdate(); + + return SystemCoreClock; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/SES/STM32N6xx/Scripts/STM32N6xx_Target.js =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Scripts/STM32N6xx_Target.js (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Scripts/STM32N6xx_Target.js (revision 16) @@ -0,0 +1,44 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2026 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + Index: trunk/firmware/FSBL/SES/STM32N6xx/Source/STM32N6xx_Startup.s =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Source/STM32N6xx_Startup.s (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Source/STM32N6xx_Startup.s (revision 16) @@ -0,0 +1,299 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2026 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32N6xx_Startup.s +Purpose : Startup and exception handlers for STM32N6xx devices. + +Additional information: + Preprocessor Definitions + __NO_SYSTEM_INIT + If defined, + SystemInit is not called. + If not defined, + SystemInit is called. + SystemInit is usually supplied by the CMSIS files. + This file declares a weak implementation as fallback. + + __NO_SYSTEM_CLK_UPDATE + If defined, + SystemCoreClockUpdate is not automatically called. + Should be defined if SystemCoreClockUpdate must not be called before main(). + If not defined, + SystemCoreClockUpdate is called before the application entry point. + + __MEMORY_INIT + If defined, + MemoryInit is called after SystemInit. + void MemoryInit(void) can be implemented to enable external + memory controllers. + + __VECTORS_IN_RAM + If defined, + the vector table will be copied from Flash to RAM, + and the vector table offset register is adjusted. + + __VTOR_CONFIG + If defined, + the vector table offset register is set to point to the + application's vector table. + + __NO_FPU_ENABLE + If defined, the FPU is explicitly not enabled, + even if the compiler could use floating point operations. + + __SOFTFP__ + Defined by the build system. + If not defined, the FPU is enabled for floating point operations. +*/ + + .syntax unified + + +#ifndef __STACK_LIMIT_MSP + #define __STACK_LIMIT_MSP __stack_start__ +#endif +#ifndef __STACK_LIMIT_PSP + #define __STACK_LIMIT_PSP 0x0 +#endif + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* Reset_Handler +* +* Function description +* Exception handler for reset. +* Generic bringup of a Cortex-M system. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .global reset_handler + .global Reset_Handler + .equ reset_handler, Reset_Handler + .section .init.Reset_Handler, "ax" + .balign 2 + .thumb_func +Reset_Handler: +#ifdef __SET_STACK_LIMITS + ldr r1, =__STACK_LIMIT_MSP + msr msplim, r1 + ldr r1, =__STACK_LIMIT_PSP + msr psplim, r1 +#endif +#ifdef __SEGGER_STOP + .extern __SEGGER_STOP_Limit_MSP + // + // Initialize main stack limit to 0 to disable stack checks before runtime init + // + movs R0, #0 + ldr R1, =__SEGGER_STOP_Limit_MSP + str R0, [R1] +#endif +#ifndef __NO_SYSTEM_INIT + // + // Call SystemInit + // + bl SystemInit +#endif +#ifdef __MEMORY_INIT + // + // Call MemoryInit + // + bl MemoryInit +#endif +#ifdef __VECTORS_IN_RAM + // + // Copy vector table (from Flash) to RAM + // + ldr R0, =__vectors_start__ + ldr R1, =__vectors_end__ + ldr R2, =__vectors_ram_start__ +1: + cmp R0, R1 + beq 2f + ldr R3, [R0] + str R3, [R2] + adds R0, R0, #4 + adds R2, R2, #4 + b 1b +2: +#endif + +#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM) + // + // Configure vector table offset register + // +#ifdef __ARM_ARCH_6M__ + ldr R0, =0xE000ED08 // VTOR_REG +#else + movw R0, 0xED08 // VTOR_REG + movt R0, 0xE000 +#endif +#ifdef __VECTORS_IN_RAM + ldr R1, =_vectors_ram +#else + ldr R1, =_vectors +#endif + str R1, [R0] +#endif +#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE) + // + // Enable CP11 and CP10 with CPACR |= (0xf<<20) + // + movw R0, 0xED88 // CPACR + movt R0, 0xE000 + ldr R1, [R0] + orrs R1, R1, #(0xf << 20) + str R1, [R0] +#endif + + // Open the debug access port to the Cortex-M55 by writing 0xB4 to BSEC_AP_UNLOCK + //ldr r0, = 0x56009E90 + //mov r1, #0xB4 + //str r1, [r0] + + // Enable the non-secure/secure debug by writing 0xB451B400 to BSEC_DBGCR + //ldr r0, = 0x56009E8C + //ldr r1, = 0xB451B400 + //str r1, [r0] + + // + // Call runtime initialization, which calls main(). + // + bl _start + + // + // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, + // when there is no strong definition of SystemInit. + // + .weak SystemInit + // + // Place SystemCoreClockUpdate in .init_array + // to be called after runtime initialization + // +#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE) + .section .init_array, "aw" + .balign 4 + .word SystemCoreClockUpdate +#endif + +/********************************************************************* +* +* HardFault_Handler +* +* Function description +* Simple exception handler for HardFault. +* In case of a HardFault caused by BKPT instruction without +* debugger attached, return execution, otherwise stay in loop. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + +#undef L +#define L(label) .LHardFault_Handler_##label + + .weak HardFault_Handler + .section .init.HardFault_Handler, "ax" + .balign 2 + .thumb_func +HardFault_Handler: + // + // Check if HardFault is caused by BKPT instruction + // + ldr R1, =0xE000ED2C // Load NVIC_HFSR + ldr R2, [R1] + cmp R2, #0 // Check NVIC_HFSR[31] + +L(hfLoop): + bmi L(hfLoop) // Not set? Stay in HardFault Handler. + // + // Continue execution after BKPT instruction + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R0, #4 + mov R1, LR + tst R0, R1 // Check EXC_RETURN in Link register bit 2. + bne L(Uses_PSP) + mrs R0, MSP // Stacking was using MSP. + b L(Pass_StackPtr) +L(Uses_PSP): + mrs R0, PSP // Stacking was using PSP. +L(Pass_StackPtr): +#else + tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack + ite eq + mrseq R0, MSP // Frame stored on MSP + mrsne R0, PSP // Frame stored on PSP +#endif + // + // Reset HardFault Status + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R3, #1 + lsls R3, R3, #31 + orrs R2, R3 + str R2, [R1] +#else + orr R2, R2, #0x80000000 + str R2, [R1] +#endif + // + // Adjust return address + // + ldr R1, [R0, #24] // Get stored PC from stack + adds R1, #2 // Adjust PC by 2 to skip current BKPT + str R1, [R0, #24] // Write back adjusted PC to stack + // + bx LR // Return + +/*************************** End of file ****************************/ Index: trunk/firmware/FSBL/SES/STM32N6xx/Source/stm32n657xx_Vectors.s =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx/Source/stm32n657xx_Vectors.s (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx/Source/stm32n657xx_Vectors.s (revision 16) @@ -0,0 +1,430 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2026 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : stm32n657xx_Vectors.s +Purpose : Exception and interrupt vectors for stm32n657xx devices. + +Additional information: + Preprocessor Definitions + __NO_EXTERNAL_INTERRUPTS + If defined, + the vector table will contain only the internal exceptions + and interrupts. + __VECTORS_IN_RAM + If defined, + an area of RAM, large enough to store the vector table, + will be reserved. + + __OPTIMIZATION_SMALL + If defined, + all weak definitions of interrupt handlers will share the + same implementation. + If not defined, + all weak definitions of interrupt handlers will be defined + with their own implementation. +*/ + .syntax unified + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ + +// +// Directly place a vector (word) in the vector table +// +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// +// Declare an exception handler with a weak definition +// +.macro EXC_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// +// Declare an interrupt handler with a weak definition +// +.macro ISR_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern __stack_end__ + .extern Reset_Handler + .extern HardFault_Handler + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* Setup of the vector table and weak definition of interrupt handlers +* +*/ + .section .vectors, "ax" + .code 16 + .balign 1024 + .global _vectors + .global g_pfnVectors +_vectors: +g_pfnVectors: + // + // Internal exceptions and interrupts + // + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + VECTOR HardFault_Handler +#ifdef __ARM_ARCH_6M__ + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED +#else + EXC_HANDLER MemManage_Handler + EXC_HANDLER BusFault_Handler + EXC_HANDLER UsageFault_Handler +#endif + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER SVC_Handler +#ifdef __ARM_ARCH_6M__ + ISR_RESERVED +#else + EXC_HANDLER DebugMon_Handler +#endif + ISR_RESERVED + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + // + // External interrupts + // +#ifndef __NO_EXTERNAL_INTERRUPTS + ISR_HANDLER PVD_PVM_IRQHandler + ISR_RESERVED + ISR_HANDLER DTS_IRQHandler + ISR_HANDLER RCC_IRQHandler + ISR_HANDLER LOCKUP_IRQHandler + ISR_HANDLER CACHE_ECC_IRQHandler + ISR_HANDLER TCM_ECC_IRQHandler + ISR_HANDLER BCK_ECC_IRQHandler + ISR_HANDLER FPU_IRQHandler + ISR_RESERVED + ISR_HANDLER RTC_S_IRQHandler + ISR_HANDLER TAMP_IRQHandler + ISR_HANDLER RIFSC_TAMPER_IRQHandler + ISR_HANDLER IAC_IRQHandler + ISR_HANDLER RCC_S_IRQHandler + ISR_RESERVED + ISR_HANDLER RTC_IRQHandler + ISR_RESERVED + ISR_HANDLER IWDG_IRQHandler + ISR_HANDLER WWDG_IRQHandler + ISR_HANDLER EXTI0_IRQHandler + ISR_HANDLER EXTI1_IRQHandler + ISR_HANDLER EXTI2_IRQHandler + ISR_HANDLER EXTI3_IRQHandler + ISR_HANDLER EXTI4_IRQHandler + ISR_HANDLER EXTI5_IRQHandler + ISR_HANDLER EXTI6_IRQHandler + ISR_HANDLER EXTI7_IRQHandler + ISR_HANDLER EXTI8_IRQHandler + ISR_HANDLER EXTI9_IRQHandler + ISR_HANDLER EXTI10_IRQHandler + ISR_HANDLER EXTI11_IRQHandler + ISR_HANDLER EXTI12_IRQHandler + ISR_HANDLER EXTI13_IRQHandler + ISR_HANDLER EXTI14_IRQHandler + ISR_HANDLER EXTI15_IRQHandler + ISR_HANDLER SAES_IRQHandler + ISR_HANDLER CRYP_IRQHandler + ISR_HANDLER PKA_IRQHandler + ISR_HANDLER HASH_IRQHandler + ISR_HANDLER RNG_IRQHandler + ISR_RESERVED + ISR_HANDLER MCE1_IRQHandler + ISR_HANDLER MCE2_IRQHandler + ISR_HANDLER MCE3_IRQHandler + ISR_HANDLER MCE4_IRQHandler + ISR_HANDLER ADC1_2_IRQHandler + ISR_HANDLER CSI_IRQHandler + ISR_HANDLER DCMIPP_IRQHandler + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_HANDLER PAHB_ERR_IRQHandler + ISR_HANDLER NPU0_IRQHandler + ISR_HANDLER NPU1_IRQHandler + ISR_HANDLER NPU2_IRQHandler + ISR_HANDLER NPU3_IRQHandler + ISR_HANDLER CACHEAXI_IRQHandler + ISR_HANDLER LTDC_LO_IRQHandler + ISR_HANDLER LTDC_LO_ERR_IRQHandler + ISR_HANDLER DMA2D_IRQHandler + ISR_HANDLER JPEG_IRQHandler + ISR_HANDLER VENC_IRQHandler + ISR_HANDLER GFXMMU_IRQHandler + ISR_HANDLER GFXTIM_IRQHandler + ISR_HANDLER GPU2D_IRQHandler + ISR_HANDLER GPU2D_ER_IRQHandler + ISR_HANDLER ICACHE_IRQHandler + ISR_HANDLER HPDMA1_Channel0_IRQHandler + ISR_HANDLER HPDMA1_Channel1_IRQHandler + ISR_HANDLER HPDMA1_Channel2_IRQHandler + ISR_HANDLER HPDMA1_Channel3_IRQHandler + ISR_HANDLER HPDMA1_Channel4_IRQHandler + ISR_HANDLER HPDMA1_Channel5_IRQHandler + ISR_HANDLER HPDMA1_Channel6_IRQHandler + ISR_HANDLER HPDMA1_Channel7_IRQHandler + ISR_HANDLER HPDMA1_Channel8_IRQHandler + ISR_HANDLER HPDMA1_Channel9_IRQHandler + ISR_HANDLER HPDMA1_Channel10_IRQHandler + ISR_HANDLER HPDMA1_Channel11_IRQHandler + ISR_HANDLER HPDMA1_Channel12_IRQHandler + ISR_HANDLER HPDMA1_Channel13_IRQHandler + ISR_HANDLER HPDMA1_Channel14_IRQHandler + ISR_HANDLER HPDMA1_Channel15_IRQHandler + ISR_HANDLER GPDMA1_Channel0_IRQHandler + ISR_HANDLER GPDMA1_Channel1_IRQHandler + ISR_HANDLER GPDMA1_Channel2_IRQHandler + ISR_HANDLER GPDMA1_Channel3_IRQHandler + ISR_HANDLER GPDMA1_Channel4_IRQHandler + ISR_HANDLER GPDMA1_Channel5_IRQHandler + ISR_HANDLER GPDMA1_Channel6_IRQHandler + ISR_HANDLER GPDMA1_Channel7_IRQHandler + ISR_HANDLER GPDMA1_Channel8_IRQHandler + ISR_HANDLER GPDMA1_Channel9_IRQHandler + ISR_HANDLER GPDMA1_Channel10_IRQHandler + ISR_HANDLER GPDMA1_Channel11_IRQHandler + ISR_HANDLER GPDMA1_Channel12_IRQHandler + ISR_HANDLER GPDMA1_Channel13_IRQHandler + ISR_HANDLER GPDMA1_Channel14_IRQHandler + ISR_HANDLER GPDMA1_Channel15_IRQHandler + ISR_HANDLER I2C1_EV_IRQHandler + ISR_HANDLER I2C1_ER_IRQHandler + ISR_HANDLER I2C2_EV_IRQHandler + ISR_HANDLER I2C2_ER_IRQHandler + ISR_HANDLER I2C3_EV_IRQHandler + ISR_HANDLER I2C3_ER_IRQHandler + ISR_HANDLER I2C4_EV_IRQHandler + ISR_HANDLER I2C4_ER_IRQHandler + ISR_HANDLER I3C1_EV_IRQHandler + ISR_HANDLER I3C1_ER_IRQHandler + ISR_HANDLER I3C2_EV_IRQHandler + ISR_HANDLER I3C2_ER_IRQHandler + ISR_HANDLER TIM1_BRK_IRQHandler + ISR_HANDLER TIM1_UP_IRQHandler + ISR_HANDLER TIM1_TRG_CCU_IRQHandler + ISR_HANDLER TIM1_CC_IRQHandler + ISR_HANDLER TIM2_IRQHandler + ISR_HANDLER TIM3_IRQHandler + ISR_HANDLER TIM4_IRQHandler + ISR_HANDLER TIM5_IRQHandler + ISR_HANDLER TIM6_IRQHandler + ISR_HANDLER TIM7_IRQHandler + ISR_HANDLER TIM8_BRK_IRQHandler + ISR_HANDLER TIM8_UP_IRQHandler + ISR_HANDLER TIM8_TRG_CCU_IRQHandler + ISR_HANDLER TIM8_CC_IRQHandler + ISR_HANDLER TIM9_IRQHandler + ISR_HANDLER TIM10_IRQHandler + ISR_HANDLER TIM11_IRQHandler + ISR_HANDLER TIM12_IRQHandler + ISR_HANDLER TIM13_IRQHandler + ISR_HANDLER TIM14_IRQHandler + ISR_HANDLER TIM15_IRQHandler + ISR_HANDLER TIM16_IRQHandler + ISR_HANDLER TIM17_IRQHandler + ISR_HANDLER TIM18_IRQHandler + ISR_HANDLER LPTIM1_IRQHandler + ISR_HANDLER LPTIM2_IRQHandler + ISR_HANDLER LPTIM3_IRQHandler + ISR_HANDLER LPTIM4_IRQHandler + ISR_HANDLER LPTIM5_IRQHandler + ISR_HANDLER ADF1_FLT0_IRQHandler + ISR_HANDLER MDF1_FLT0_IRQHandler + ISR_HANDLER MDF1_FLT1_IRQHandler + ISR_HANDLER MDF1_FLT2_IRQHandler + ISR_HANDLER MDF1_FLT3_IRQHandler + ISR_HANDLER MDF1_FLT4_IRQHandler + ISR_HANDLER MDF1_FLT5_IRQHandler + ISR_HANDLER SAI1_A_IRQHandler + ISR_HANDLER SAI1_B_IRQHandler + ISR_HANDLER SAI2_A_IRQHandler + ISR_HANDLER SAI2_B_IRQHandler + ISR_HANDLER SPDIFRX_IRQHandler + ISR_HANDLER SPI1_IRQHandler + ISR_HANDLER SPI2_IRQHandler + ISR_HANDLER SPI3_IRQHandler + ISR_HANDLER SPI4_IRQHandler + ISR_HANDLER SPI5_IRQHandler + ISR_HANDLER SPI6_IRQHandler + ISR_HANDLER USART1_IRQHandler + ISR_HANDLER USART2_IRQHandler + ISR_HANDLER USART3_IRQHandler + ISR_HANDLER UART4_IRQHandler + ISR_HANDLER UART5_IRQHandler + ISR_HANDLER USART6_IRQHandler + ISR_HANDLER UART7_IRQHandler + ISR_HANDLER UART8_IRQHandler + ISR_HANDLER UART9_IRQHandler + ISR_HANDLER USART10_IRQHandler + ISR_HANDLER LPUART1_IRQHandler + ISR_HANDLER XSPI1_IRQHandler + ISR_HANDLER XSPI2_IRQHandler + ISR_HANDLER XSPI3_IRQHandler + ISR_HANDLER FMC_IRQHandler + ISR_HANDLER SDMMC1_IRQHandler + ISR_HANDLER SDMMC2_IRQHandler + ISR_HANDLER UCPD1_IRQHandler + ISR_HANDLER USB1_OTG_HS_IRQHandler + ISR_HANDLER USB2_OTG_HS_IRQHandler + ISR_HANDLER ETH1_IRQHandler + ISR_HANDLER FDCAN1_IT0_IRQHandler + ISR_HANDLER FDCAN1_IT1_IRQHandler + ISR_HANDLER FDCAN2_IT0_IRQHandler + ISR_HANDLER FDCAN2_IT1_IRQHandler + ISR_HANDLER FDCAN3_IT0_IRQHandler + ISR_HANDLER FDCAN3_IT1_IRQHandler + ISR_HANDLER FDCAN_CU_IRQHandler + ISR_HANDLER MDIOS_IRQHandler + ISR_HANDLER DCMI_PSSI_IRQHandler + ISR_HANDLER WAKEUP_PIN_IRQHandler + ISR_HANDLER CTI_INT0_IRQHandler + ISR_HANDLER CTI_INT1_IRQHandler + ISR_RESERVED + ISR_HANDLER LTDC_UP_IRQHandler + ISR_HANDLER LTDC_UP_ERR_IRQHandler +#endif + // + .section .vectors, "ax" +_vectors_end: + +#ifdef __VECTORS_IN_RAM + // + // Reserve space with the size of the vector table + // in the designated RAM section. + // + .section .vectors_ram, "ax" + .balign 1024 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop + + +/*************************** End of file ****************************/ Index: trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf =================================================================== --- trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf (revision 16) +++ trunk/firmware/FSBL/SES/STM32N6xx_RAM.icf (revision 16) @@ -0,0 +1,133 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2026 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32N6xx_RAM.icf +Purpose : STM32N6xx linker script for application placement in RAM + (to be copied to RAM by bootloader or debugger) + for use with the SEGGER Linker. +Maps : STM32N645A0HxQ, STM32N645B0HxQ, STM32N645I0HxQ, STM32N645L0HxQ, + STM32N645X0HxQ, STM32N645Z0HxQ, STM32N647A0HxQ, STM32N647B0HxQ, + STM32N647I0HxQ, STM32N647L0HxQ, STM32N647X0HxQ, STM32N647Z0HxQ, + STM32N655A0HxQ, STM32N655B0HxQ, STM32N655I0HxQ, STM32N655L0HxQ, + STM32N655X0HxQ, STM32N655Z0HxQ, STM32N657A0HxQ, STM32N657B0HxQ, + STM32N657I0HxQ, STM32N657L0HxQ, STM32N657X0HxQ, STM32N657Z0HxQ +Literature: + [1] SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html) + [2] SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files) +*/ + +define memory with size = 4G; + +// +// Combined regions per memory type +// +define region RAM = AXI_RAM2; + +// +// Block definitions +// +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block exidx { section .ARM.exidx, section .ARM.exidx.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with auto size = __HEAPSIZE__, alignment = 8, readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, readwrite access { }; +define block stack_process with size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +// +// Explicit initialization settings for sections +// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits +// +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .vectors_ram }; +initialize by copy with packing=auto { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by calling __SEGGER_STOP_X_InitLimits { section .data.stop.* }; + +#define USES_ALLOC_FUNC \ + linked symbol malloc || linked symbol aligned_alloc || \ + linked symbol calloc || linked symbol realloc + +initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap }; // Init the heap if one is required +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +//assert with warning "free() linked into application but there are no calls to an allocation function!" { +// linked symbol free => USES_ALLOC_FUNC +//}; + +assert with error "heap is too small!" { USES_ALLOC_FUNC => size of block heap >= 48 }; +assert with error "heap size not a multiple of 8!" { USES_ALLOC_FUNC => size of block heap % 8 == 0 }; +assert with error "heap not correctly aligned!" { USES_ALLOC_FUNC => start of block heap % 8 == 0 }; + +// +// Explicit placement in RAMn +// +place in AHB_RAM1 { section .AHB_RAM1, section .AHB_RAM1.* }; +place in AHB_RAM2 { section .AHB_RAM2, section .AHB_RAM2.* }; +place in AXI_RAM1 { section .AXI_RAM1, section .AXI_RAM1.* }; // This region may be deactivated and not accessible +place in AXI_RAM2 { section .AXI_RAM2, section .AXI_RAM2.* }; // This region may be deactivated and not accessible +place in AXI_RAM3 { section .AXI_RAM3, section .AXI_RAM3.* }; // This region may be deactivated and not accessible +place in AXI_RAM4 { section .AXI_RAM4, section .AXI_RAM4.* }; // This region may be deactivated and not accessible +place in BKP_RAM { section .BKP_RAM, section .BKP_RAM.* }; // This region may be deactivated and not accessible +place in DTCM_RAM { section .DTCM_RAM, section .DTCM_RAM.* }; // This region may be deactivated and not accessible +place in FLEX_RAM { section .FLEX_RAM, section .FLEX_RAM.* }; +place in ITCM_RAM { section .ITCM_RAM, section .ITCM_RAM.* }; // This region may be deactivated and not accessible + +// +// RAM Placement +// +place at start of RAM { section .vectors }; // Vector table section +place in RAM with minimum size order { block tdata_load, // Thread-local-storage load image + block exidx, // ARM exception unwinding block + block ctors, // Constructors block + block dtors, // Destructors block + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; +place in RAM { section .fast, section .fast.* }; // "ramfunc" section +place in RAM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack }; // Stack reserved block at the end Index: trunk/firmware/FSBL/SES/blto2_FSBL.emProject =================================================================== --- trunk/firmware/FSBL/SES/blto2_FSBL.emProject (revision 16) +++ trunk/firmware/FSBL/SES/blto2_FSBL.emProject (revision 16) @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +